RMLV0416EGSB-5S2 [RENESAS]
4Mb Advanced LPSRAM; 4MB先进LPSRAM
| 型号： | RMLV0416EGSB-5S2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4Mb Advanced LPSRAM |
| 文件： | 总15页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RMLV0416E Series
4Mb Advanced LPSRAM (256k word × 16bit)
R10DS0205EJ0001
Rev.0.01
2013.09.10
Description
The RMLV0416E Series is a family of 4-Mbit static RAMs organized 262,144-word × 16-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0416E Series has realized higher density, higher
performance and low power consumption. The RMLV0416E Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 44-pin TSOP II or 48-ball fine pitch ball grid array.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 45/55ns (max.)
Current consumption:
── Standby: 0.4µA (typ.)
Equal access and cycle times
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Access
time
Temperature
Range
Part Name
Package
RMLV0416EGSB-4S2
RMLV0416EGSB-5S2
RMLV0416EGBG-4S2
RMLV0416EGBG-5S2
45 ns
400-mil 44pin plastic TSOP II
55 ns
45 ns
55 ns
-40 ~ +85°C
48-ball f-BGA with 0.75mm ball pitch
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RMLV0416E Series
Preliminary
Pin Arrangement
44pin TSOP II
48-ball f-BGA
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
1
2
1
2
3
4
5
6
A6
A2
A7
3
A
B
C
D
E
F
LB#
OE#
A0
A1
A2
CS2
A1
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
CS2
A8
4
A0
5
I/O8
I/O9
Vss
UB#
I/O10
I/O11
I/O12
I/O13
NC
A3
A5
A4
A6
CS1#
I/O1
I/O3
I/O4
I/O5
WE#
A11
I/O0
I/O2
Vcc
Vss
I/O6
I/O7
NC
CS1#
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE#
A17
A16
A15
A14
A13
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A17
NC
A14
A12
A9
A7
Vcc
A16
A15
A13
A10
I/O14
I/O15
NC
G
H
A9
A10
A11
A12
A8
(Top view)
(Top view)
Pin Description
Pin name
Function
VCC
Power supply
VSS
Ground
A0 to A17
I/O0 to I/O15
CS1#
CS2
Address input
Data input/output
Chip select 1
Chip select 2
Output enable
Write enable
OE#
WE#
LB#
Lower byte select
Upper byte select
No connection
UB#
NC
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RMLV0416E Series
Preliminary
Block Diagram
VCC
A1
A2
VSS
A3
A4
・
・
・
・
・
A6
A8
Memory Matrix
2,048 x 2,048
Row
Decoder
A13
A14
A15
A16
A17
I/O0
・
・
・
Column I/O
・
Column Decoder
Input
Data
Control
I/O15
A0 A5 A7 A9 A10 A11 A12
・
・
CS2
CS1#
LB#
Control logic
UB#
WE#
OE#
Operation Table
UB#
X
LB#
I/O8 to I/O15
High-Z
High-Z
High-Z
Dout
Operation
Standby
CS1#
CS2
X
WE#
X
OE#
I/O0 to I/O7
High-Z
High-Z
High-Z
Dout
H
X
X
L
L
L
L
L
L
L
X
X
X
H
L
L
X
X
X
Standby
X
X
X
H
L
Standby
H
H
H
H
L
L
Read
H
L
H
L
L
Dout
High-Z
Dout
Lower byte read
Upper byte read
Write
H
L
H
L
High-Z
Din
H
X
L
Din
H
L
L
High-Z
Din
Lower byte write
Upper byte write
Output disable
H
L
X
Din
H
X
H
L
X
H
High-Z
High-Z
H
H
X
High-Z
Note 1. H: VIH L:VIL
X: VIH or VIL
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RMLV0416E Series
Preliminary
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Symbol
VCC
Value
-0.5 to +4.6
-0.5*2 to VCC+0.3*3
0.7
unit
V
VT
V
PT
W
°C
°C
°C
Operation temperature
Topr
Tstg
Tbias
-40 to +85
-65 to +150
-40 to +85
Storage temperature range
Storage temperature range under bias
Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum)
3. Maximum voltage is +4.6V.
DC Operating Conditions
Parameter
Symbol
VCC
VSS
VIH
Min.
2.7
0
Typ.
3.0
0
Max.
Unit
V
Note
Supply voltage
3.6
0
V
Input high voltage
Input low voltage
2.2
-0.3
-40
─
VCC+0.3
0.6
V
VIL
─
V
4
Ambient temperature range
Ta
─
+85
°C
Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum)
DC Characteristics
Parameter
Symbol
| ILI |
Min.
Typ. Max. Unit
Test conditions
Vin = VSS to VCC
Input leakage current
Output leakage current
─
─
1
A
CS1# = VIH or CS2 = VIL or OE# = VIH
or WE# = VIL or LB# = UB# = VIH,
VI/O = VSS to VCC
| ILO
|
─
─
1
A
Operating current
CS1# = VIL, CS2 = VIH,
ICC
─
─
─
─
10
20
mA
mA
Others = VIH/VIL, II/O = 0mA
Average operating current
Min. cycle, duty =100%, II/O = 0mA,
CS1# = VIL, CS2 = VIH, Others = VIH/VIL
Cycle =1s, duty =100%, II/O = 0mA,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
ICC1
ICC2
ISB
─
─
2.5
mA
Standby current
Standby current
─
─
0.1*5
0.4*5
0.3
2
mA
CS2 = VIL, Others = VSS to VCC
Vin = VSS to VCC,
~+25°C
A
(1) CS2 ≤ 0.2V
or
─
─
─
─
─
─
3
5
7
A
A
A
~+40°C
(2) CS1# ≥ VCC-0.2V,
ISB1
CS2 ≥ VCC-0.2V
~+70°C
or
(3) LB# = UB# ≥ VCC-0.2V,
~+85°C
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V
Output high voltage
Output low voltage
VOH
2.4
VCC-0.2
─
─
─
─
─
─
─
V
V
V
V
IOH = -1mA
VOH2
VOL
IOH = -0.1mA
IOL = 2mA
0.4
0.2
VOL2
─
IOL = 0.1mA
Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C*2)
Parameter
Input capacitance
Input / output capacitance
Symbol
C in
Min.
─
Typ.
─
Max.
8
Unit
pF
Test conditions
Vin =0V
Note
6
6
C I/O
─
─
10
pF
VI/O =0V
Note 6. This parameter is sampled and not 100% tested.
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RMLV0416E Series
Preliminary
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
1.4V
Input pulse levels: VIL = 0.4V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
RL = 500 ohm
I/O
CL = 30 pF (-4S2)
CL = 50 pF (-5S2)
Read Cycle
RMLV0416EG**-4S2
RMLV0416EG**-5S2
Parameter
Symbol
Unit
Note
Min.
45
─
Max.
Min.
55
─
Max.
─
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
45
45
45
22
─
55
55
55
30
─
tACS1
tACS2
tOE
─
─
Chip select access time
─
─
Output enable to output valid
Output hold from address change
LB#, UB# access time
─
─
tOH
10
─
10
─
tBA
45
─
55
─
tCLZ1
tCLZ2
tBLZ
tOLZ
tCHZ1
tCHZ2
tBHZ
tOHZ
10
10
5
10
10
5
7,8
7,8
Chip select to output in low-Z
─
─
LB#, UB# enable to low-Z
─
─
7,8
Output enable to output in low-Z
5
─
5
─
7,8
0
18
18
18
18
0
20
20
20
20
7,8,9
7,8,9
7,8,9
7,8,9
Chip deselect to output in high-Z
0
0
LB#, UB# disable to high-Z
0
0
Output disable to output in high-Z
0
0
Note 7. This parameter is sampled and not 100% tested.
8. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2
min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
9. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
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RMLV0416E Series
Write Cycle
Preliminary
Note
RMLV0416EG**-4S2
RMLV0416EG**-5S2
Parameter
Symbol
Unit
Min.
45
35
35
35
35
0
Max.
─
Min.
55
50
50
40
50
0
Max.
─
Write cycle time
tWC
tAW
tCW
tWP
tBW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to write end
Chip select to write end
─
─
─
─
Write pulse width
─
─
10
LB#,UB# valid to write end
Address setup time to write start
Write recovery time from write end
Data to write time overlap
Data hold from write end
Output enable from write end
Output disable to output in high-Z
Write to output in high-Z
─
─
─
─
tWR
tDW
tDH
0
─
0
─
25
0
─
25
0
─
─
─
tOW
tOHZ
tWHZ
5
─
5
─
11
0
18
18
0
20
20
11,12
11,12
0
0
Note 10. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
11. This parameter is sampled and not 100% tested.
12. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to
the I/O levels.
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RMLV0416E Series
Preliminary
Timing Waveforms
Read Cycle
tRC
A0~17
Valid address
tAA
tACS1
CS1#
*14,15
*13,14,15
tCLZ1
tCHZ1
CS2
tACS2
*13,14,15
*14,15
tCLZ2
tCHZ2
tBA
LB#,UB#
*13,14,15
*14,15
tBLZ
tBHZ
VIH
WE#
WE# = “H” level
*13,14,15
tOHZ
tOE
OE#
*14,15
tOLZ
tOH
High impedance
I/O0~15
Valid Data
Note 13. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
14. This parameter is sampled and not 100% tested
15. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2
min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
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RMLV0416E Series
Preliminary
Write Cycle (1) (WE# CLOCK, OE#=”H” while writing)
tWC
Valid address
A0~17
tCW
CS1#
CS2
tCW
tBW
LB#,UB#
tAW
tWR
*16
tWP
WE#
tAS
OE#
*17,18
tWHZ
*17,18
tOHZ
tDW
tDH
I/O0~15
Valid Data
*19
Note 16. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
17. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to
the I/O levels.
18. This parameter is sampled and not 100% tested
19. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
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RMLV0416E Series
Preliminary
Write Cycle (2) (WE# CLOCK, OE# Low Fixed)
tWC
Valid address
A0~17
tCW
CS1#
CS2
tCW
tBW
LB#,UB#
tAW
tWR
*20
tWP
WE#
tAS
OE#
VIL
OE# = “L” level
*21,22
tWHZ
tOW
Valid Data
tDH
*23
*23
I/O0~15
tDW
Note 20. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
21. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O
levels.
22. This parameter is sampled and not 100% tested.
23. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
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RMLV0416E Series
Preliminary
Write Cycle (3) (CS1#, CS2 CLOCK)
tWC
Valid address
A0~17
tAW
tAS
tWR
tCW
CS1#
CS2
tAS
tCW
tBW
LB#,UB#
WE#
*24
tWP
OE#
OE# = “H” level
VIH
tDW
tDH
Valid Data
I/O0~15
Note 24. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
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RMLV0416E Series
Preliminary
Write Cycle (4) (LB#, UB# CLOCK)
tWC
Valid address
A0~17
tAW
tCW
CS1#
CS2
tCW
tWR
tBW
tAS
LB#,UB#
WE#
*25
tWP
OE#
OE# = “H” level
VIH
tDH
tDW
Valid Data
I/O0~15
Note 25. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
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RMLV0416E Series
Preliminary
Low VCC Data Retention Characteristics
Parameter
Symbol
Min.
1.5
Typ. Max.
Unit
V
Test conditions*27
Vin ≥ 0V,
(1) CS2 ≤ 0.2V
or
VCC for data retention
VDR
─
─
(2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V
or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V
0.4*26
2
3
5
7
A
A
A
A
~+25°C
VCC = 3.0V, Vin ≥ 0V,
─
─
─
─
(1) CS2 ≤ 0.2V
or
─
~+40°C
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V
Data retention current
ICCDR
or
─
~+70°C
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
─
~+85°C
CS2 ≥ VCC-0.2V
Chip deselect time to data retention
Operation recovery time
tCDR
tR
0
5
─
─
─
─
ns
See retention waveform.
ms
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If
CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The
other inputs levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high-impedance state.
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RMLV0416E Series
Preliminary
Low Vcc Data Retention Timing Waveforms (CS1# controlled)
CS1# Controlled
VCC
2.7V
2.7V
tCDR
tR
tR
tR
VDR
2.2V
2.2V
0.6V
2.2V
CS1# ≥ VCC - 0.2V
CS1#
Low Vcc Data Retention Timing Waveforms (CS2 controlled)
CS2 Controlled
VCC
2.7V
2.7V
tCDR
CS2
VDR
0.6V
CS2 ≤ 0.2V
Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled)
LB#,UB# Controlled
VCC
2.7V
2.7V
tCDR
VDR
2.2V
LB#,UB# ≥ VCC - 0.2V
LB#,UB#
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Revision History
RMLV0416E Series Data Sheet
Description
Summary
Rev.
0.01
Date
Page
2013.09.10
─
Preliminary first Edition issued
All trademarks and registered trademarks are the property of their respective owners.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
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Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
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