RNA51958AFPH0 [RENESAS]
Voltage Detecting, System Resetting IC Series; 电压检测，设备重新启动IC系列
| 型号： | RNA51958AFPH0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Voltage Detecting, System Resetting IC Series |
| 文件： | 总12页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RNA51958A,B
Voltage Detecting, System Resetting IC Series
REJ03D0915-0100
Rev.1.00
Mar 02, 2009
Description
RNA51958A,B are semiconductor integrated circuits for resetting of all types of logic circuits such as CPUs, and
has the feature of setting the detection voltage by adding external resistance.
They include a built-in delay circuit to provide the desired retardation time simply by adding an external capacitor.
They fined extensive applications, including battery checking circuit, level detecting circuit and waveform shaping
circuit.
Features
•
•
•
•
•
Few external parts
Large delay time with a capacitor of small capacitance (td ≈ 100 ms, at 0.33 µF)
Wide supply voltage range: 2 V to 17 V
Wide application range
Ordering Information
Taping Abbreviation
Package
Abbreviation
Surface
Treatment
Part Name
Package Type
Package Code
(Quantity)
RNA51958AFPH0
RNA51958BFPH0
SOP-8 pin
SOP-8 pin
PRSP0008DE-C
PRSP0008DE-C
FP
FP
H (2,500 pcs / Reel)
H (2,500 pcs / Reel)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
Application
•
Reset circuit of Pch, Nch, CMOS, microcomputer, CPU and MCU, Reset of logic circuit, Battery check circuit,
switching circuit back-up voltage, level detecting circuit, waveform shaping circuit, delay waveform generating
circuit, DC/DC converter, over voltage protection circuit
Recommended Operating Condition
•
Supply voltage range: 2 V to 17 V
Outline and Article Indication
• RNA51958A, B
Type No.
Lot No.
R 9 5 8 A
YMWC
CCC
R 9 5 8 B
YMWC
CCC
Y : Year Code
(the last digit of year)
M : Month Code
W : Week Code
C : Control Code
SOP-8
Trace Code
Pin No.1
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 1 of 11
RNA51958A,B
Pin Arrangement
RNA51958AFP/BFP
NC
Input
NC
1
2
3
4
8
7
6
5
NC
Power-supply
Output
GND
Delay capacitor
(Top view)
NC: No Connection
Outline: PRSP0008DE-C
Block Diagram
RNA51958A, B
Power-
A: Built-in Load
B: Open Collector
supply
5µA
Typ
25µA
Typ
Output
–
+
Input
+
1.25V
GND
Delay capacitor
Operating Waveform
RNA51958A, B
1.25V
t
t
H
L
td
td
td ≈ 0.34 × Cd(pF) µs
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 2 of 11
RNA51958A,B
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Symbol
VCC
Ratings
18
Unit
V
Conditions
Supply voltage
Output sink current
Isink
6
mA
VCC
18
Type A (output with constant current load)
Output voltage
VO
Pd
V
Type B (open collector output)
8-pin SOP (PRSP0008DE-C)
Refer to the
Power dissipation
400
mW
Thermal derating
Kθ
4.4
mW/°C thermal derating
curve.
8-pin SOP (PRSP0008DE-C)
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
–0.3 to VCC
–0.3 to +7
°C
°C
VCC ≤ 7 V
Input voltage range
Vin
V
VCC > 7 V
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
•
“H” reset type
Item
Symbol
VS
Min
Typ
Max
1.30
23
Unit
V
Test Conditions
Detecting voltage
Hysteresis voltage
1.20
9
1.25
15
∆VS
mV
VCC = 5V
Detecting voltage
VS/∆T
VCC
Vin
Iin
—
0.01
—
%/°C
V
temperature coefficient
Supply voltage range
Input voltage range
Input current
2
–0.3
–0.3
—
—
—
17
VCC
7.0
VCC ≤ 7V
V
—
VCC > 7V
100
390
360
3.4
500
590
540
7.0
nA
µA
ms
V
Vin = 1.25V
—
Type A, VCC = 5V
Type B, VCC = 5V
Cd = 0.01µF *
Circuit current
ICC
—
Delay time
tpd
1.6
Output saturation
voltage
Vsat
—
0.2
0.4
30
VCC = 5V, Vin < 1.35V, Isink = 4mA
Output leakage
current
IOH
—
—
nA
Type B
Output load current
Output high voltage
IOC
–40
–25
–17
—
µA
Type A, VCC = 5V, VO = 1/2 × VCC
VOH
VCC–0.2 VCC–0.06
V
Type A
Note: Please set the desired delay time by attaching capacitor of the range between 4700 pF and 10 µF.
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 3 of 11
RNA51958A,B
Typical Characteristics
Thermal Derating
Detection Voltage vs. Ambient Temperature
1.28
500
400
300
200
100
0
1.27
8-pin SOP
(PRSP0008DE-C)
VSH
1.26
VSL
1.25
1.24
1.23
1.22
85
0
25
50
75
100 125
–40 –20
0
20 40 60 80 100
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
Detection Voltage vs. Supply Voltage
1.28
Input Current vs. Supply Voltage
VIN = 1.25V
250
200
150
100
50
1.27
1.26
1.25
1.24
1.23
1.22
VSH
Ta = –40°C
VSL
Ta = 25°C
Ta = 85°C
0
0
0
4
8
12
16
20
4
8
12
16
20
Supply Voltage VCC (V)
Supply Voltage VCC (V)
Delay Capacitance vs. Delay Time
VCC = 5V
Delay Time vs. Ambient Temperature
10
7
5
6
CD = 0.01µF
3
5
4
3
2
1
0
1
7
5
3
VCC = 5V
0.1
7
5
10V
VCC = 15V
3
0.01
7
5
3
0.001
0.1 3 5 7 1
3 5 7 10 3 5 7 100 3 5 7 1000
–40 –20
0
20 40 60 80 100
Delay Time tpd (ms)
Ambient Temperature Ta (°C)
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 4 of 11
RNA51958A,B
Canstant Current at Cd pin vs. Ambient Temperature
Output Saturation Voltage vs. Output Sink Current
0.3
–12
–10
–8
–6
–4
–2
0
Supply voltage detecting
VCC = 5V
VCC = 15V
: VCC = 5V
0.2
0.1
0
0
1
2
3
4
5
6
–40 –20
0
20 40 60 80 100
Output Sink Current Isink (mA)
Ambient Temperature Ta (°C)
Circuit Current vs. Supply Voltage
(RNA51958B)
Output Load Current vs. Output Voltage
(RNA51958A)
800
–40
Ta = –40°C
600
400
200
0
–30
–20
–10
0
VCC = 5V VCC = 10V VCC = 15V
Ta = 25°C
Ta = 85°C
0
4
8
12
16
0
4
8
12
16
Supply Voltage VCC (V)
Output Voltage VO (V)
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 5 of 11
RNA51958A,B
Example of Application Circuit
Reset Circuit of RNA51958
VCC
Power-
supply
Power-
supply
R1
RL
Input
Output
RESET
Logic circuit
RNA51958x
R2
GND
Delay capacitor
Cd
GND
Figure 1 Reset Circuit of RNA51958
Notes: 1. When the detecting supply voltage is 4.25 V, RNA51953 are used. In this case, R1 and R2 are not necessary.
When the voltage is anything except 4.25 V, RNA51957 and RNA51958 are used. In this case, the detecting
supply voltage is 1.25 × (R1 +R2)/R2 (V) approximately.
The detecting supply voltage can be set between 2 V and 15 V.
2. If a longer delay time is necessary, RNA51953, RNA51957, RNA51958 are used. In this case, the delay
time is about 0.34 × Cd (pF) µs.
3. If the RNA51958 and the logic circuit share a common power source, type A (built-in load type) can be used
whether a pull-up resistor is included in the logic circuit or not.
4. The logic circuit preferably should not have a pull-down resistor, but if one is present, add load resistor RL to
overcome the pull-down resistor.
5. When the reset terminal in the logic circuit is of the low reset type, RNA51953 and RNA51957 are used and
when the terminal is of the high reset type, RNA51958 are used.
6. When a negative supply voltage is used, the supply voltage side of RNA51958 and the GND side are
connected to negative supply voltage respectively.
Case of Using Reset Signal except Supply Voltage in the RNA51958
(a) Reset at ON
(b) Reset at transistor ON
Power-
VCC
VCC
Power-
supply
Power-
supply
Power-
supply
supply
R1
R1
RL
RL
Out
put
Out
put
Input
Input
RESET
Logic circuit
RESET
Logic circuit
RNA51958x
RNA51958x
R2
R2
GND
Delay capacitor
Cd
GND
GND
Delay capacitor
Cd
GND
Control
signal
Figure 2 Case of Using Reset Signal except Supply Voltage in the RNA51958
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 6 of 11
RNA51958A,B
Delay Waveform Generating Circuit
When RNA51958 are used, a waveform with a large delay time can generate only by adding a small capacitor.
Power-supply
R1
Input
Output
RNA51958
R2
GND
Delay capacitor
Cd
Figure 3 Delay Waveform Generating Circuit
Operating Waveform
Input
(VCC partial
pressure)
td
Output
td ≈ 0.34 × Cd(pF) µs
Figure 4 Operating Waveform
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 7 of 11
RNA51958A,B
Notice for use
About the Power Supply Line
1. About bypass capacitor
Because the ripple and the spike of the high frequency noise and the low frequency are superimposed to the power
supply line, it is necessary to remove these.
Therefore, please install C1 and C2 for the low frequency and for the high frequency between the power supply line
and the GND line as shown in following figure 5.
VCC
+
C1
C2
Power-supply
Output
R1
Input
Example of ripple
noise measures
Vin
R2
RNA51958
GND
Delay capacitor
Cd
Figure 5 Example of Ripple Noise Measures
2. The sequence of voltage impression
Please do not impress the voltages to the input terminals earlier than the power supply terminal. Moreover, please
do not open the power supply terminal with the voltage impressed to the input terminal.
(The setting of the bias of an internal circuit collapses, and a parasitic element might operate.)
About the Input Terminal
1. Setting range of input voltage
The following voltage is recommended to be input to the input terminal (pin 2).
about 0.8 (V) < Vin < VCC – 0.3 (V) ... at VCC ≤ 7 V
about 0.8 (V) < Vin < 6.7 (V) ............. at VCC > 7 V
2. About using input terminal
Please do an enough verification to the transition characteristic etc. of the power supply when using independent
power supply to input terminal (pin 2).
VCC
Vin is decided to the VCC subordinating,
and operates in the range
about 0.8 (V) < Vin < VCC – 0.3 (V).
Power-supply
Input
Output
RNA51958
Vin
GND
Delay capacitor
Cd
Figure 6 Recommended Example
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 8 of 11
RNA51958A,B
Independent
VCC
1
VCC
2
VCC
Independent
Input
Power-supply
Output
Power-supply
Input
Output
RNA51958
RNA51958
Vin
Vin
VCC
GND
GND
Delay capacitor
Cd
GND
Delay capacitor
Cd
Example 1. Independent power supply system
Please do enough verifying about
Example 2. Logic pulse input
(not recommended)
transition characteristic of VCC
and VCC2.
1
Figure 7
3. Calculation of detecting voltage
Detecting voltage Vs can be calculated by the following expression.
However, the error margin is caused in the detecting voltage because input current Iin (standard 100 nA) exists if it
sets too big resistance.
Please set the constant to disregard this error margin.
R + R
1
2
V = 1.25 ×
S
+ Iin × R
1
R
2
error margin
VCC
Power-supply
Output
R1
Iin
→
RNA51958
Vin
R2
Input
GND
Delay capacitor
Cd
Figure 8 Influence of Input Current
4. About the voltage input outside ratings
Please do not input the voltage outside ratings to the input terminal.
An internal protection diode becomes order bias, and a large current flows.
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 9 of 11
RNA51958A,B
Setting of Delay Capacity
Please use capacitor Cd for the delay within the range of 10 µF or less.
When a value that is bigger than this is set, the problem such as following (1), (2), and (3) becomes remarkable.
t
VCC
tpd
Output
tPHL
Figure 9 Time Chart at Momentary Voltage-Decrease
(1) The difference at delay time becomes remarkable.
A long delay setting of tens of seconds is fundamentally possible. However, when set delay time is lengthened, the
range of the difference relatively grows, too. When a set value is assumed to be ‘tpd’, the difference occurs in the
range from 0.47 × tpd to 2.05 × tpd. For instance, 34 seconds can be calculated at 100 µF. However, it is likely to
vary within the ranges of 16-70 seconds.
(2) Difficulty to react to a momentary voltage decrease.
For example, the reaction time tPHL is 10 µs when delay capacitor Cd = 0.1 µF.
The momentary voltage-decrease that is longer than such tPHL are occurs, the detection becomes possible. When the
delay capacitance is enlarged, tPHL also becomes long. For instance, it becomes about 100 to 200 µs in case of
circuit constant C1 = 100 µF.
(Characteristic graph 1 is used and extrapolation in case of Cd = 100 µF.)
Therefore, it doesn't react to momentary voltage-decrease that is shorter than this.
(3) Original delay time is not obtained.
When the momentary voltage-decrease time ‘t’ is equivalent to tPHL, the discharge becomes insufficient and the
charge starts at that state. This phenomenon occurs at large capacitance. And, original delay time tpd is not
obtained.
Please refer to characteristic graph 2. (Delay time versus input pulse width)
Characteristic Graph 1
Reaction Time vs. Delay Capacitance
(Example data)
Characteristic Graph 2
Delay Time vs. Momentary Voltage Decrease Pulse Width
(Example data)
1000
10000
Delay Capacitance
0.01µF
0.033µF
0.1µF
0.33µF
1µF
2.2µF
3.3µF
200
100
1000
100
10
10
1
1
0.01
0.1
1
10
100
1
10
100
Pulse Width (µs)
1000
10000
Delay Capacitance Cd (µF)
Figure 10 Characteristic Graph
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 10 of 11
RNA51958A,B
Setting of Output Load Resistance (RNA51958B)
High level output voltage can be set without depending on the power-supply voltage because the output terminal is an
open collector type. However, please guard the following notes.
1. Please set it in value (2 V to 17 V) within the range of the power-supply voltage recommendation.
Moreover, please never impress the voltage of maximum ratings 18 V or more even momentarily either.
2. Please set output load resistance (pull-up resistance) RL so that the output current (output inflow current IL) at L
level may become 4 mA or less. Moreover, please never exceed absolute maximum rating (6 mA).
VCC (2V to 17V)
RL
6
IL ≤ 4mA
Figure 11 Output Load Resistance RL
Others
1. Notes when IC is handled are published in our reliability handbook, and please refer it.
The reliability handbook can be downloaded from our homepage (following URL).
http://www.renesas.com/fmwk.jsp?cnt=reliability_root.jsp&fp=/products/common_info/reliability
2. Additionally, please inquire of our company when there is an uncertain point on use.
Package Dimensions
JEITA Package Code
P-SOP8-4.4x4.85-1.27
RENESAS Code
PRSP0008DE-C
Previous Code
—
MASS[Typ.]
0.1g
F
*1
D
NOTE)
8
5
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
1
4
Min Nom Max
*3
e
bp
Z
D
E
A2
4.65 4.85 5.05
4.4 4.6
1.85
x
M
4.2
L1
A1 0.00 0.1 0.20
2.03
A
bp 0.34 0.4 0.46
b1
c
c1
0.15 0.20 0.25
L
θ
0° 8°
HE 5.7 6.2 6.5
y
Detail F
e
1.12 1.27 1.42
0.12
x
y
Z
L
0.10
0.75
0.25 0.45 0.65
0.90
L1
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Page 11 of 11
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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