UPA1814GR-9JG-E2-AT [RENESAS]
TRANSISTOR,MOSFET,P-CHANNEL,30V V(BR)DSS,7A I(D),TSSOP;
| 型号： | UPA1814GR-9JG-E2-AT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TRANSISTOR,MOSFET,P-CHANNEL,30V V(BR)DSS,7A I(D),TSSOP |
| 文件： | 总10页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA1814
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
PACKAGE DRAWING (Unit : mm)
The µPA1814 is a switching device which can be
driven directly by a 4 V power source.
8
5
The µPA1814 features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.
1, 5, 8 :Drain
2, 3, 6, 7:Source
1.2 MAX.
1.0±0.05
4
:Gate
0.25
FEATURES
+5°
–3°
3°
• Can be driven by a 4 V power source
• Low on-state resistance
0.5
0.1±0.05
+0.15
–0.1
0.6
1
4
RDS(on)1 = 16 mΩ MAX. (VGS = –10 V, ID = –3.5 A)
RDS(on)2 = 24 mΩ MAX. (VGS = –4.5 V, ID = –3.5 A)
RDS(on)3 = 27 mΩ MAX. (VGS = –4.0 V, ID = –3.5 A)
• Built-in G-S protection diode against ESD
6.4 ±0.2
4.4 ±0.1
3.15 ±0.15
3.0 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1814GR-9JG
Power TSSOP8
0.65
0.8 MAX.
0.1
+0.03
–0.08
0.27
0.10 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
EQUIVALENT CIRCUIT
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation Note2
Channel Temperature
Storage Temperature
VDSS
VGSS
ID(DC)
ID(pulse)
PT
–30
±20
V
V
Drain
±7.0
±28
2.0
A
Body
Diode
A
Gate
W
°C
Gate
Protection
Diode
Tch
150
Source
Tstg
–55 to +150 °C
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2. Mounted on ceramic substrate of 5000mm2 x 1.1 mm
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published May 2001 NS CP(K)
Printed in Japan
D13804EJ2V0DS00 (2nd edition)
1998, 1999
©
The mark ★ shows major revised points.
µPA1814
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = –30 V, VGS = 0 V
MIN. TYP. MAX. UNIT
–10
±10
–2.5
µA
µA
V
IGSS
VGS = ±20 V, VDS = 0 V
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –3.5 A
VGS = –10 V, ID = –3.5 A
VGS = –4.5 V, ID = –3.5 A
VGS = –4.0 V, ID = –3.5 A
VDS = –10 V
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
–1.0
–1.7
14
Forward Transfer Admittance
Drain to Source On-state Resistance
3
S
12
16
24
27
mΩ
mΩ
mΩ
pF
pF
pF
ns
18
20
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
2180
658
303
30
Coss
VGS = 0 V
Crss
f = 1MHz
td(on)
VDD = –15 V
tr
ID = –3.5 A
140
97
ns
Turn-off Delay Time
Fall Time
td(off)
VGS(on) = –10 V
ns
tf
RG = 10 Ω
86
ns
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Diode Forward Voltage
QG
VDS = –24 V
38
nC
nC
nC
V
QGS
ID = –7.0 A
5.9
8.5
0.79
QGD
VGS = –10 V
VF(S-D)
IF = 7.0 A, VGS = 0 V
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
I
G
= 2 mA
V
GS
RL
RL
90 %
V
GS
Wave Form
VGS(on)
10 %
0
R
G
PG.
PG.
V
DD
V
DD
50 Ω
R = 10 Ω
G
90 %
I
D
90 %
10 %
I
D
V
0
GS
10 %
I
D
0
Wave Form
t
r
t
d(on)
td(off)
t
f
τ
t
on
toff
τ = 1µ s
Duty Cycle ≤ 1 %
2
Data Sheet D13804EJ2V0DS
µPA1814
TYPICAL CHARACTERISTICS (TA = 25 °C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
★
FORWARD BIAS SAFE OPERATING AREA
100
−100
−10
−1
ID(pulse)
V)
) Limited
10
n
(o
RDS
(@
=
80
VGS
ID(DC)
60
40
20
−0.1
TA
= 25˚C
Single Pulse
Mounted on Ceramic
2
Substrate of 50cm x 1.1mm
0
−0.01
30
60
90
120
150
−0.1
−10
−100
−1
T
A - Ambient Temperature - ˚C
V
DS - Drain to Source Voltage - V
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
−100
−10
−25
−20
VDS = −10 V
TA = 125˚C
75˚C
V
GS = −10 V
−1
−4.5 V
−4.0 V
−15
−10
−5
−0.1
−0.01
TA = 25˚C
−25˚C
−
0.001
−
0.0001
−
0.00001
0
−0.5
−1.5
−2.5
−3.5
−0.2
−0.6
−0.4
−0.8
−1.0
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
FORWARD TRANSFER ADMITANCE Vs.
GATE TO SOURCE CUTOFF VOLTAGE vs.
CHANNEL TEMPERATURE
DRAIN CURRENT
100
10
−2.0
V
DS = −10 V
V
DS = −10 V
I
D = −1 mA
T
A
= −25˚C
25˚C
−1.5
−1.0
1
75˚C
125˚C
0.1
150
−50
0
50
100
0.01
−0.01
−10
D - Drain Current - A
−100
−0.1
−1
T
ch - Channel Temperature - ˚C
I
3
Data Sheet D13804EJ2V0DS
µPA1814
DRAIN TO SOURCE ON-STATE
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
RESISTANCE vs. DRAIN CURRENT
35
30
25
30
V
GS = −4.0 V
VGS = −4.5 V
T
A
= 125˚C
T
A
= 125˚C
75˚C
75˚C
25˚C
20
10
25˚C
−25˚C
20
15
−25˚C
−0.1
−1
−0.1
−1
−0.01
−10
−100
−0.01
−10
−100
ID
- Drain Current - A
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
30
25
ID = −3.5 A
V
GS = −10 V
VGS = −4.0 V
−4.5 V
25
20
15
T
A
= 125˚C
75˚C
20
15
10
5
−10 V
25˚C
−25˚C
10
5
100
−50
0
50
150
−0.1
−1
−0.01
−10
−100
ID - Drain Current - A
Tch - Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
10000
1000
100
50
40
30
f = 1 MHz
GS = 0 V
ID = −3.5 A
V
C
iss
Coss
C
rss
20
10
10
−1
−10
−100
0
−12
−16
−4
−8
−20
V
DS - Drain Source Voltage - V
V
GS - Gate to Source Voltage - V
4
Data Sheet D13804EJ2V0DS
µPA1814
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
SWITCHING CHARACTERISTICS
1000
100
100
tr
tf
10
td(off)
td(on)
1
10
1
0.1
0.01
V
V
R
DD = −15 V
GS(on) = −10 V
G
= 10 Ω
0.8
1.2
1.0
0.4
0.6
−0.1
−1
−10
I
D
- Drain Current - A
VF(S-D) - Source to Drain Voltage - V
DYNAMIC INPUT CHARACTERISTICS
12
10
I
D
= −7.0 A
8
6
4
V
DD = −24 V
−15 V
−6 V
2
0
5
10
15
20
25
30 35
40
Q
g - Gate Charge - nC
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
★
1000
100
Mounted on ceramic
substrate of50 cm2 x 1.1 mm
Single Pulse
62.5˚C/W
10
1
0.1
0.001
0.01
0.1
100
1000
1
10
PW - Pulse Width - s
5
Data Sheet D13804EJ2V0DS
µPA1814
[MEMO]
6
Data Sheet D13804EJ2V0DS
µPA1814
[MEMO]
7
Data Sheet D13804EJ2V0DS
µPA1814
•
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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