UPA1816GR-9JG [NEC]
P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING; P沟道MOS场效应晶体管切换
| 型号： | UPA1816GR-9JG |
| 厂家： | 
NEC |
| 描述： | P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING |
| 文件： | 总8页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA1816
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µPA1816 is a switching device which can be
driven directly by a 1.8 V power source.
8
5
This device features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power management of notebook
computers and so on.
1, 2, 3 : Source
: Gate
5, 6, 7, 8: Drain
1.2 MAX.
1.0 ±0.05
4
0.25
FEATURES
• 1.8 V drive available
• Low on-state resistance
RDS(on)1 = 15 mΩ MAX. (VGS = −4.5 V, ID = −4.5 A)
RDS(on)2 = 16 mΩ MAX. (VGS = −4.0 V, ID = −4.5 A)
RDS(on)3 = 22.5 mΩ MAX. (VGS = −2.5 V, ID = −4.5 A)
RDS(on)4 = 41.5 mΩ MAX. (VGS = −1.8 V, ID = −2.5 A)
• Built-in G-S protection diode against ESD
+5°
–3°
3°
0.5
0.1 ±0.05
+0.15
–0.1
0.6
1
4
6.4 ±0.2
4.4 ±0.1
3.15 ±0.15
3.0 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
0.65
0.8 MAX.
0.1
µPA1816GR-9JG
Power TSSOP8
+0.03
–0.08
0.27
0.10 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
EQUIVALENT CIRCUIT
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TA = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT
−12
V
V
m 8.0
Drain
9.0
A
m
36
A
m
Body
Total Power Dissipation Note2
Diode
Gate
2.0
W
°C
°C
Channel Temperature
Tch
150
Gate
Storage Temperature
Tstg
−55 to +150
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Mounted on ceramic substrate of 5000 mm2 x 1.1 mm
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published July 2002 NS CP(K)
Printed in Japan
G16252EJ1V0DS00 (1st edition)
2002
©
µPA1816
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDS = −12 V, VGS = 0 V
VGS = 8.0 V, VDS = 0 V
−1.0
µA
µA
V
10
IGSS
m
m
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
RDS(on)4
Ciss
VDS = −10 V, ID = −1.0 mA
VDS = −10 V, ID = −4.5 A
VGS = −4.5 V, ID = −4.5 A
VGS = −4.0 V, ID = −4.5 A
VGS = −2.5 V, ID = −4.5 A
VGS = −1.8 V, ID = −2.5 A
VDS = −10 V
−0.45 −0.75 −1.5
Forward Transfer Admittance
Drain to Source On-state Resistance
11
22
12.0
12.5
16.2
23.7
1570
400
240
16
S
15
16
mΩ
mΩ
mΩ
mΩ
pF
pF
pF
ns
22.5
41.5
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
VGS = 0 V
Crss
f = 1.0 MHz
td(on)
VDD = −10 V, ID = −4.5 A
VGS = −4.0 V
tr
132
223
295
15
ns
Turn-off Delay Time
Fall Time
td(off)
tf
RG = 10 Ω
ns
ns
Total Gate Charge
QG
VDD = −10 V
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
VGS = −4.0 V
3.0
QGD
ID = −9.0 A
4.5
VF(S-D)
trr
IF = 9.0 A, VGS = 0 V
IF = 9.0 A, VGS = 0 V
di/dt = 100 A/ µs
0.82
490
580
ns
Qrr
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
V
V
GS (−)
D.U.T.
D.U.T.
90%
VGS
V
GS
Wave Form
10%
I
G
= −2 mA
R
L
0
R
L
DS (−)
RG
PG.
V
DD
50 Ω
PG.
V
DD
90%
90%
VDS
0
10% 10%
V
DS
Wave Form
VGS (−)
0
td(on)
t
r
td(off)
tf
τ
ton
toff
τ = 1
µs
Duty Cycle ≤ 1%
2
Data Sheet G16252EJ1V0DS
µPA1816
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
120
100
80
60
40
20
0
2.5
2
1.5
1
Mounted on ceramic
substrate of
5000 mm2 x 1.1 mm
0.5
0
0
25
50
75
100 125 150 175
0
25
50
75 100 125 150 175
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
ID(pulse)
-100
-10
PW = 1 ms
ID(DC)
10 ms
-1
RDS(on) Limited
100 ms
(VGS = −4.5 V)
DC
Single Pulse
-0.1
Mounted on ceramic
substrate of
5000 mm2 x 1.1 mm
-0.01
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
10
1
62.5°C/W
Single Pulse
Mounted on ceramic
substrate of 5000 mm2 x 1.1 mm
1 m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
3
Data Sheet G16252EJ1V0DS
µPA1816
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
-40
-30
-20
-10
0
-100
-10
VDS = −10 V
Pulsed
Pulsed
−4.0 V
−2.5 V
VGS = −4.5 V
-1
TA = 125°C
75°C
25°C
−25°C
-0.1
−1.8 V
-0.01
-0.001
-0.0001
0
-0.2
-0.4
-0.6
-0.8
-1
0
-0.5
-1
-1.5
-2
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
-1
-0.8
-0.6
-0.4
100
10
1
VDS = −10 V
ID = −1.0 mA
VDS = −10 V
Pulsed
TA = −25°C
25°C
75°C
125°C
0.1
-50
0
50
100
150
-0.01
-0.1
-1
-10
-100
ID - Drain Current - A
Tch - Channel Temperature - °C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
40
40
Pulsed
VGS = −1.8 V, ID = −1.5 A
VGS = −2.5 V, ID = −4.5 A
Pulsed
30
20
10
0
30
20
10
0
ID = −4.5 A
VGS = −4.0 V, ID = −4.5 A
VGS = −4.5 V, ID = −4.5 A
-50
0
50
100
150
0
-2
-4
-6
-8
VGS - Gate to Source Voltage - V
Tch - Channel Temperature - °C
4
Data Sheet G16252EJ1V0DS
µPA1816
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
20
20
VGS = −4.0 V
VGS = −4.5 V
Pulsed
Pulsed
TA = 125°C
75°C
TA = 125°C
15
10
5
15
10
5
75°C
25°C
25°C
−25°C
−25°C
-0.01
-0.1
-1
-10
-100
-0.01
-0.1
-1
-10
-100
ID - Drain Current - A
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
40
40
VGS = −2.5 V
VGS = −1.8 V
Pulsed
Pulsed
TA = 125°C
30
20
10
0
30
20
10
0
75°C
25°C
−25°C
TA = 125°C
75°C
25°C
−25°C
-0.01
-0.1
-1
-10
-100
-0.01
-0.1
-1
-10
-100
ID - Drain Current - A
ID - Drain Current - A
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
SWITCHING CHARACTERISTICS
10000
1000
100
10
VDD = −10 V
VGS = −4.0 V
RG = 10 Ω
VGS = 0 V
f = 1.0 MHz
tf
Ciss
td(off)
1000
td(on)
tr
Coss
Crss
100
-0.1
1
-1
-10
-100
-0.01
-0.1
-1
-10
VDS - Drain to Source Voltage - V
ID - Drain Current - A
5
Data Sheet G16252EJ1V0DS
µPA1816
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
-5
-4
-3
-2
-1
0
ID = −9.0 A
Pulsed
10
1
VDD = −10 V
−6.0 V
−2.0 V
VGS = 0 V
0.1
0.01
0
5
10
15
20
0.4
0.6
0.8
1
1.2
QG - Gate Charge - nC
VF(S-D) - Source to Drain Voltage - V
6
Data Sheet G16252EJ1V0DS
µPA1816
[MEMO]
7
Data Sheet G16252EJ1V0DS
µPA1816
•
The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
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Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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