UPD16907K9-5B4 [RENESAS]
IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,LLCC,48PIN,PLASTIC;
| 型号： | UPD16907K9-5B4 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,LLCC,48PIN,PLASTIC |
| 文件： | 总24页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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LIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ PD16907
6-CHANNEL DC-DC CONVERTER CONTROLER IC
DESCRIPTION
The µ PD16907 is a DC-DC converter controller IC with Power MOS FET in its synchronous rectifier step-down
circuit and six output channels.
Employing a full CMOS process, this IC realizes a low current consumption and has an operating voltage of as low
as 1.5 V. Equipped with an ON/OFF sequencer, the µ PD16907 is ideal for the power supply of portable systems
such as digital still cameras.
FEATURES
• Employment of step-down type synchronous rectifier with Power MOS FET (ch2 and ch3)
• ON/OFF sequencer suitable for supplying power to low-voltage microcontroller operating on two power supplies
• Full CMOS process used to realize low-current consumption
• Low minimum operation voltage: VBATMIN = from 1.5 V
• ON/OFF control for each channel independent is possible.
• High-accuracy reference voltage of ± 1%: VREF = 0.8 V
• Adjustable oscillation frequency: 200 kHz to 1 MHz
• Timer latch short-circuit protection circuit, overheat protection circuit and current limiting circuit (only ch2 and ch3)
are incorporated.
ORDERING INFORMATION
Part Number
Package
µ PD16907K9-5B4
48-pin plastic WQFN (7 x 7)
EACH CHANNEL METHOD EXAMPLES
ch
Method
Example of
Example of
Applications
Output Voltage
Output Current
1
2
Step-up (synchronous rectification)
Step-down (synchronous rectification
incorporates Power MOS FET)
Step-down (synchronous rectification
incorporates Power MOS FET)
Step-up
4.5 to 5 V
900 mA
400 mA
Flash, IC bias, motor
DSP core
1.5 to 2.5 V
3
4
5
6
3.3 V
400 mA
30 mA/10 mA
30 mA/10mA
15 mA
DSP interface, memory, motor
CCD/CCD plus power supply
LCD/CCD minus power supply
LED
Transformer driving
/+10 V
Step-up/polarity inversion
Step-up
Transformer driving
/−8 V
13 V
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16949EJ1V0PM00 (1st edition)
Date Published December 2003 NS CP(K)
Printed in Japan
2003
µ PD16907
1. BLOCK DIAGRAM
AGND
16
C
30
SS1
C
29
SS2
R
9
T
C
8
T
C
31
DLY
V
19
REF
37
CTL
CTL
2
1
20
AVDD
Controller
36
Reference
Voltage
Circuit
SCP
Circuit
CTL Circuit
Oscillator
42
PVDD
SS Circuit
47
48
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
1
2
1
2
3
4
3
4
SHDN Circuit
Overheat
Protecion
Circuit
5
6
ON/OFF Sequencer
23
24
F
B
1
39
OUT1N
OUT1P
ch1
Synchronous
Rectification
Control
−
+
+
Control
+
−
V
REF
I
I1
40
38
E/A1
E/A2
E/A3
PWM1
PGND
OUT1S
1
41
10
11
P
P
IN2-1
IN2-2
12
13
F
B2
ch2
Control
−
+
+
+
Synchronous
Rectification
Control
6
7
LX2-1
LX2-2
I
I2
−
V
REF
PWM2
5
PGND
2
Discharge
Circuit
35
27
DCIN
3
3
25
26
P
P
IN3-1
IN3-2
FB
ch3
Control
−
+
+
+
Synchronous
Rectification
Control
32
33
28
LX3-1
LX3-2
−
I
I3
V
REF
PWM3
34
PGND
3
21
22
FB
4
ch4
−
+
+
+
Control
43
OUT
OUT
4
V
REF
−
I
I4
E/A4
E/A5
PWM4
17
18
FB5
ch5
Control
−
+
+
+
44
5
−
V
REF
I
I5
PWM5
14
15
FB
6
ch6
Control
−
+
+
+
45
46
OUT
6
−
V
REF
I
I6
E/A6
PWM6
PGND
4
2
Preliminary Product Information S16949EJ1V0PM
µ PD16907
2. PIN CONFIGURATION (Top View)
SHDNB
1
OUT
6
OUT
4
OUT1S
OUT1N
CTL
2
SHDNB
2
PGND
46
4
OUT
44
5
PVDD
42
OUT1P
PGND
1
48
1
47
45
43
41
40
39
38
37
SHDNB
SHDNB
SHDNB
SHDNB
PGND
3
4
5
6
2
CTL
1
36
35
34
33
32
31
30
29
28
27
26
25
2
3
4
5
6
7
8
9
DCIN
3
PGND
LX3-2
3
LX3-1
LX2-1
LX2-2
C
C
C
DLY
SS1
SS2
C
T
T
R
I
I3
P
P
IN2-1
IN2-2
10
FB
3
P
P
IN3-2
IN3-1
11
12
FB
2
13
14
15
16
17
18
19
20
21
22
23
24
I
I2
I
I6
FB
5
V
REF
FB
4
FB
1
FB
6
AGND
I
I5
AVDD
I
I4
I
I1
3
Preliminary Product Information S16949EJ1V0PM
µ PD16907
3. PIN FUNCTIONS
(1/2)
Pin No.
Symbol
SHDNB3
SHDNB4
SHDNB5
SHDNB6
PGND2
Pin Name
Shut-down input
I/O
Input
Input
Input
Input
−
Function
1
2
3
4
5
ch3 output ON/OFF
ch4 output ON/OFF
ch5 output ON/OFF
ch6 output ON/OFF
Shut-down input
Shut-down input
Shut-down input
Power ground
Power ground (Pin No.5 and No.46 are connected inside
mutually.)
6
7
LX2-1
LX2-2
Output 2-1
Output 2-2
Output
Output
ch2 inductor connection (Pin No.6 and No.7 are
connected inside mutually.)
ch2 inductor connection (Pin No.6 and No.7 are
connected inside mutually.)
8
9
CT
Timing capacitor
−
−
Capacitor connection for triangular wave generation
Resistor connection for triangular wave generation
ch2 driving power supply (Pin No.10 and No.11 are
connected inside mutually.)
RT
Timing resistor
10
PIN2-1
ch2 driving power supply
Input
11
PIN2-2
ch2 driving power supply
Input
ch2 driving power supply (Pin No.10 and No.11 are
connected inside mutually.)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FB2
II2
Feed back
−
Feed back of ch2 error amplifier
Inversion input
Feed back
Input
Inversion input of ch2 error amplifier
Feed back of ch6 error amplifier
FB6
II6
−
Inversion input
Analog ground
Feed back
Input
Inversion input of ch6 error amplifier
Analog ground
AGND
FB5
II5
−
−
Input
Feed back of ch5 error amplifier
Inversion input
Reference voltage
Power supply
Feed back
Inversion input of ch5 error amplifier
Reference voltage
VREF
AVDD
FB4
II4
Output
Power supply
−
Analog block power supply
Feed back of ch4 error amplifier
Inversion input
Feed back
Input
Inversion input of ch4 error amplifier
Feed back of ch1 error amplifier
FB1
II1
−
Inversion input
ch3 driving power supply
Input
Inversion input of ch1 error amplifier
ch3 driving power supply (Pin No.25 and No.26 are
connected inside mutually.)
PIN3-1
Input
26
PIN3-2
ch3 driving power supply
Input
ch3 driving power supply (Pin No.25 and No.26 are
connected inside mutually.)
27
28
29
30
FB3
II3
Feed back
−
Input
−
Feed back of ch3 error amplifier
Inversion input
Inversion input of ch3 error amplifier
Capacitance connection for soft start of ch4 to ch6
Capacitance connection for soft start of ch1 to ch3
CSS2
CSS1
Soft-start capacitance 2
Soft-start capacitance 1
−
4
Preliminary Product Information S16949EJ1V0PM
µ PD16907
(2/2)
Pin No.
31
Symbol
Pin Name
I/O
Function
CDLY
Delay capacitance of short-
circuit protection circuit
Output 3-1
−
Timer latch capacitor connection
32
33
34
LX3-1
Output
Output
−
ch3 inductor connection (Pin No.32 and No.33 are
connected inside mutually.)
LX3-2
Output 3-2
ch3 inductor connection (Pin No.32 and No.33 are
connected inside mutually.)
PGND3
Power ground
Power ground (Pin No.34 and No.38 are connected
inside mutually.)
35
36
37
38
DCIN3
CTL1
Discharge when ch3 = OFF
Control 1
Input
Input
Input
−
Output capacitance is discharged when ch3 = OFF.
ON/OFF sequence setting
CTL2
Control 2
ch5 circuit system setting mode
PGND1
Power ground
Power ground (Pin No.34 and No.38 are connected
inside mutually.)
39
40
41
42
OUT1N
OUT1P
OUT1S
PVDD
Output 1N
Output
Output
ch1 Power MOS FET on the high side connection
ch1 Power MOS FET on the low side connection
Power MOS FET connection
Output 1P
Output 1S
Output
Output buffer stage power
supply
Power supply
Output buffer stage power supply
43
44
45
46
OUT4
OUT5
OUT6
PGND4
Output 4
Output
Output
Output
−
ch4 Power MOS FET connection
ch5 Power MOS FET connection
ch6 Power MOS FET connection
Power ground (Pin No.5 and No.46 are connected inside
mutually.)
Output 5
Output 6
Power ground
47
48
SHDNB1
SHDNB2
Shut down 1
Shut down 2
Input
Input
ch1 output ON/OFF
ch2 output ON/OFF
5
Preliminary Product Information S16949EJ1V0PM
µ PD16907
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Condition
Rating
+8.0
Unit
V
Analog power supply voltage
Buffer stage power supply voltage
Power MOS FET input voltage
LX pin voltage
AVDD
PVDD
VPIN
+8.0
V
+8.0
V
VLX
+8.0
V
II pin voltage
VII
−0.3 to AVDD
−0.3 to AVDD
−0.3 to AVDD
−0.3 to AVDD
30
V
DCIN pin voltage
VDCIN
V
ON/OFF pin voltage
VON/OFF
VCONT
IO(DC)+
IO(DC)−
IO(pulse)+
IO(pulse)−
IOPMOS(DC)+
IOPMOS(DC)−
IONMOS(DC)+
IONMOS(DC)−
PT
V
CONT pin voltage
V
Buffer output source current (DC)
Buffer output sink current (DC)
Buffer output source current (pulse)
Buffer output sink current (pulse)
P-ch MOS output sink current (DC)
P-ch MOS output sink current (DC)
N-ch MOS output sink current (DC)
N-ch MOS output sink current (DC)
Power consumption
mA
mA
mA
mA
mA
mA
mA
mA
W
30
200
200
1000
1000
1000
1000
T.B.D. (1.0)
−20 to +85
−20 to +150
−55 to +150
Operation ambient temperature
Operation junction temperature
Storage temperature
TA
°C
°C
°C
Tj
Tstg
Remark T.B.D.: To be determined.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = 25°C, unless otherwise specified.)
Parameter
Battery voltage
Symbol
Condition
MIN.
1.5
TYP.
3.3
5
MAX.
4.5
Unit
V
VBAT
Analog power supply voltage
Buffer stage power supply voltage
ch2 Power MOS FET input voltage
ch3 Power MOS FET input voltage
Operation ambient temperature
Operation junction temperature
Operation frequency
AVDD
PVDD
VPIN2
VPIN3
TA
3.5
5.5
V
3.5
5
5.5
V
PIN2 ≤ AVDD = PVDD
PIN3 ≤ AVDD = PVDD
1.8
3.3
3.3
5.5
V
1.8
5.5
V
−20
−20
200
+85
+125
1000
°C
°C
kHz
Tj
fOSC
500
6
Preliminary Product Information S16949EJ1V0PM
µ PD16907
Electrical Characteristics
(Unless otherwise specified, TA = 25°C, AVDD = 5 V, PVDD = 5 V, PIN2 = 3.3 V, PIN3 = 5 V, fOSC = 500 kHz)
(1/2)
Overall
Parameter
Symbol
Condition
MIN.
TYP.
3.0
MAX.
5.0
Unit
mA
Circuit operation current
IDD
All channels operate,
ON-duty = 0%, no load
SHDNB1 = L
Standby current
IDD(SB)
1
µA
Reference Voltage Circuit Block
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Reference voltage
VREF
IREF = 1 mA
0.792
0.8
5
0.808
10
V
Input stability
VREF(LINE)
VREF(LOAD)
VREF(TC)
3.5 V ≤ AVDD ≤ 5.5 V
0.1 mA ≤ IREF ≤ 2 mA
TA = −20 to 85°C
0
0
mV
mV
%
Load stability
5
10
Reference voltage temperature
fluctuation rate
IO peak
1.0
IOpeak
1% down
3
7
mA
Oscillator Block
Condition
Parameter
Oscillation frequency
fOSC input stability
Symbol
fOSC
MIN.
450
TYP.
500
2
MAX.
550
Unit
kHz
%
RT = 0.82 kΩ, CT = 330 pF
3.5 V ≤ AVDD ≤ 5.5 V,
fOSC(LINE)
RT = 0.82 kΩ, CT = 330 pF
TA = −20 to 85°C, RT = 0.82 kΩ,
CT = 330 pF
Frequency temperature fluctuation rate
fOSC(TC)
15
%
Low-level threshold voltage
High-level threshold voltage
VTH-L
VTH-H
RT = 0.82 kΩ, CT = 330 pF
RT = 0.82 kΩ, CT = 330 pF
0.16
0.65
V
V
SCP Circuit Block
Condition
Parameter
Symbol
VTH(II)1
MIN.
TYP.
0.56
0.72
0.72
0.6
MAX.
Unit
V
II1 input detection voltage (ch1)
II2 input detection voltage (ch2)
II3 input detection voltage (ch3)
II4 input detection voltage (ch4)
II5 input detection voltage (ch5 step-up)
VTH(II)2
V
VTH(II)3
V
VTH(II)4
V
VTH(II)5R
Step-up circuit configuration: CTL2
= L
0.6
V
II5 input detection voltage (ch5 polarity
inversion)
VTH(II)5I
Polarity inversion circuit
configuration: CTL2 = H
0.65
V
II6 input detection voltage (ch6)
Short-circuit source current
CDLY detection voltage
VTH(II)6
ICDLY
0.3
1.1
0.9
V
µA
V
0.7
1.6
VCDLY
SS Circuit Block
Condition
Parameter
CSS1 detection voltage
CSS2 detection voltage
Charge current
Symbol
VTH(CSS)1
VTH(CSS)2
ICSS
MIN.
TYP.
1.25
1.25
10
MAX.
Unit
V
V
6
14
µA
PWM Block
Condition
Parameter
Maximum duty (ch1, ch4 to ch6)
Maximum duty (ch2, ch3)
Symbol
DMAX.1
MIN.
TYP.
90
MAX.
Unit
%
DMAX.2
100
%
7
Preliminary Product Information S16949EJ1V0PM
µ PD16907
(2/2)
E/A Block
Condition
Parameter
Symbol
MIN.
0.783
0.783
0.783
0.783
0.783
TYP.
0.8
0.8
0.8
0.8
0.8
MAX.
0.817
0.817
0.817
0.817
0.817
Unit
V
Input threshold voltage (ch1)
Input threshold voltage (ch2)
Input threshold voltage (ch3)
Input threshold voltage (ch4)
Input threshold voltage (ch5 step-up)
VITH1
VITH2
VITH3
V
V
VITH4
V
VITH5R
Step-up circuit configuration: CTL2
= L
V
Input threshold voltage (ch5 polarity
inversion)
VITH5I
Polarity inversion circuit
configuration: CTL2 = H
0.583
0.6
0.4
0.617
V
Input threshold voltage (ch6)
Input bias current
VITH6
IB
0.383
0.417
100
V
nA
dB
MHz
V
−100
Open loop gain
AV
84
3.0
Unity gain frequency
funity
+
Maximum output voltage amplitude (+)
Maximum output voltage amplitude (−)
Output sink current
VOM
IO = −45 µA
4.9
−
VOM
IO = 45 µA
0.02
3.0
V
IOsink
VII = AVDD, VFB = 0.5 V
VII = 0 V, VFB = 2 V
Output Block (ch1)
Condition
mA
µA
Output source current
IOsource
150
Parameter
Rise time
Symbol
tr1
MIN.
TYP.
15
MAX.
Unit
ns
ns
Ω
CL = 150 pF
Fall time
tf1
CL = 150 pF
15
Output on-state resistance 1
OUT1S output on-state resistance
Ron1-1
Ron1S
PVDD = 5 V, IO = 20 mA
PVDD = 5 V, IO = 20 mA
Output Block (ch2 and ch3)
Condition
6
15
30
20
Ω
Parameter
Symbol
MIN.
TYP.
0.35
MAX.
Unit
N-ch output on-state resistance
(LX2-3N) 1
RonLX2-3n1 PIN = 5 V, IO = 100 mA
Ω
P-ch output on-state resistance
(LX2-3P) 1
RonLX2-3p1 PIN = 5 V, IO = 100 mA
0.35
Ω
P-ch output limiting current (LX2-3P) 1
P-ch output limiting current (LX2-3P) 2
P-ch output limiting current (LX2-3P) 3
IlmtLX2-3p1
IlmtLX2-3p2
IlmtLX2-3p3
PIN1 = PIN2 = 5 V
PIN1 = PIN2 = 3.3 V
PIN1 = PIN2 = 2 V
Output Block (ch4 to ch6)
Condition
1000
800
mA
mA
mA
500
Parameter
Symbol
tr4-6
MIN.
TYP.
20
MAX.
17
Unit
ns
Rise time (OUT4 to OUT6)
Fall time (OUT4 to OUT6)
Output on-state resistance 1
(OUT4 to OUT6)
CL = 150 pF
tf4-6
CL = 150 pF
20
ns
Ron4-6-1
PVDD = 5 V, IO = 15 mA
10
Ω
Discharge Circuit Block
Condition
Parameter
Symbol
MIN.
TYP.
60
MAX.
100
Unit
Input on-state resistance
Ron(DCIN)3
Ω
8
Preliminary Product Information S16949EJ1V0PM
µ PD16907
Electrical Characteristics of Logic Block
(Unless otherwise specified, TA = 25°C, AVDD = 5 V, PVDD = 5 V, PIN2 = 3.3 V, PIN3 = 5 V, fOSC = 500 kHz)
Controller Block
Parameter
Control threshold voltage
Shut-down threshold voltage
Input leakage current 1
Input leakage current 2
Symbol
Condition
MIN.
0.8
TYP.
MAX.
1.2
Unit
V
VTH(CTL)
CTL1, CTL2
VTH(SHDN) SHDNB1 to SHDNB6
0.8
1.2
V
IL1
IL2
Logic input voltage = AVDD
Logic input voltage = 3.3 V
1.0
µA
µA
20
Power-supply Rise Sequence Block
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
V
ch1 rise detection voltage
VTH(L-H)1
(DCOUT1 x DCOUT1 x
0.6) 0.7
(DCOUT2 x DCOUT2 x
ch2 rise detection voltage
VTH(L-H)2
V
0.8)
0.9
0.55
2
ch3 fall detection voltage
ch2 - ch3 rise delay time
ch2 - ch3 rise delay time
VTH(H-L)3
TDLY2-3
TDLY2-3
0.65
V
PIN3 = 5 V, CSS1 = 0.1 µF
PIN3 = 4 V, CSS1 = 0.1 µF
ms
ms
1.8
Remarks The value enclosed in parentheses is a value when a circuit is designed, and is a reference value.
9
Preliminary Product Information S16949EJ1V0PM
µ PD16907
5. TIMING CHART
AVDD
SHDNB
2
, SHDNB
3
SHDNB
4
to SHDNB
SHDNB
6
1
CTL
1
0 V
0.8 V
VREF
5 V
VTH(L-H)1
DCOUT
1
1.8 V
VTH(L-H)2
DCOUT
2
TDLY2-3
TDLY2-3
TDLY2-3
3.3 V
VTH(H-L)3
DCOUT
3
DCOUT
4
DCOUT
5
6
DCOUT
10
Preliminary Product Information S16949EJ1V0PM
µ PD16907
6. FUNCTION OPERATION TABLE
6.1 CTL1 ON/OFF Sequence Setting Mode
Signal
ON/OFF Sequence Mode
ON/OFF sequencer = ON (Refer to 6.3 SHDNB ON/OFF Setting Mode.)
L
H
ON/OFF control for each channel independent is possible via SHDNB pin. (All of ch1 to ch6 is
independently controlled.)
Remark L: Low level, H: High level
6.2 CTL2 ch5 Circuit System Setting Mode
Signal
Circuit System
L
ch5 → Step-up circuit
H
ch5 → Polarity inversion circuit
6.3 SHDNB ON/OFF Setting Mode (when CTL1 = low level, and ON/FF sequencer = ON)
SHDNB1 SHDNB2 SHDNB3 SHDNB4 SHDNB5 SHDNB6
ch1
ch2
OFF
ON
ch3
ch4
ch5
ch6
L
L
L
L
L
L
L
L
L
L
L
OFF
H
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
H
L
H
L
H
L
H
L
H
OFF
ON
OFF
ON
OFF
ON
H
H
H
H
11
Preliminary Product Information S16949EJ1V0PM
µ PD16907
7. OPERATION EXPLANATION OF EACH BLOCK
7.1 Reference Voltage Circuit Block
The reference voltage circuit block outputs reference voltage (0.8 V TYP.) by which temperature compensation is
carried out by supplying voltage by the AVDD (No.20) pin. The reference voltage is used as the reference voltage of
each internal circuit, and can be extracted to outside by the VREF (No.19) pin to 7 mA TYP..
7.2 Oscillator Block
The oscillator block performs self-excited oscillation using the timing capacitance and timing resistor externally
attached to the CT (No.8) pin and RT (No.9) pin, respectively, and outputs a symmetric triangular wave with an
amplitude of 0.16 V TYP. to 0.65 V TYP. to the CT (No.8) pin. This triangular wave is supplied to the inversion input
pin of the PWM comparator.
7.3 E/A Block (Error Amplifier)
E/A1 to E/A6 of the E/A block have an identical circuit configuration.
The input threshold voltage of E/A1 to E/A4 in the E/A block is 0.8 V, and that of E/A5 is 0.8 V TYP. when a polarity
inversion circuit is configured (CTL2 = L) and 0.6 V TYP. when a polarity inversion circuit is configured (CTL2 = H).
The input threshold voltage of E/A6 is 0.4 V TYP..
7.4 PWM Block (PWM Comparator)
The PWM comparator compares the triangular wave signal and E/A output signal (or maximum duty) and controls
the output ON duty.
7.5 Output Circuit Block
The output circuits of ch1 and ch4 to ch6 are of push-pull configuration and can directly drive a Power MOS FET
transistor. The output current capacity is 200 mA MAX. for pulse output and 30 mA MAX. for DC output.
The output circuits of ch2 and ch3 have a Power MOS FET transistor that can output a current of 1 A MAX.. These
output circuits are configured as synchronous rectification type circuits, so that a highly efficient converter can be
created.
7.6 SS Circuit Block (Soft-start Circuit)
ch1 to ch3 are soft-started by a capacitor connected to the CSS1 (No.30) pin. ch4 to ch6 are soft-started by a
capacitor connected to the CSS2 (No.29) pin.
Soft start is executed by charging the capacitor connected to the CSS1 (No.30) pin or CSS2 (No.29) pin and gradually
increasing the voltage at the CSS1 (No.30) pin or CSS2 (No.29) pin. On starting the IC, the voltage at the CSS1 (No.30)
pin or CSS2 (No.29) pin is connected to the non-inverted input of E/A. Soft start is executed by increasing the non-
inverted input voltage of E/A from 0 V and gradually widening the output ON duty.
12
Preliminary Product Information S16949EJ1V0PM
µ PD16907
7.7 CTL Circuit Block
The CTL1 (No.36) pin is used to set operation of the ON/OFF sequencer. When CTL1 (No.36) pin = low level, the
ON/OFF sequencer turns on, and then rises in order of ch1, ch2 and ch3 at the rising and falls in order of ch3 and
ch2, and ch1 at the falling. When CTL1 (No.36) pin = high level, each channel can be independently turned on or
turned off by the SHDNB1 to SHDNB6 pins because of turning off the ON/OFF sequencer.
The CTL2 (No.37) pin is used to set the ch5 circuit system to either a step-up circuit or a polarity inversion circuit.
When CTL2 (No.37) pin = low level, ch5 operates as a step-up circuit. When CTL2 (No.37) pin = high level, ch5
operates as a polarity inversion circuit.
7.8 ON/OFF Sequencer Block
The ON/OFF sequencer specifies the rising and the falling of ch1 to ch3. The ON/OFF sequencer turns on
depending on setting the CTL1 pin to low level. At that time, The SHDNB2 (No.48) pin and SHDNB3 (No.1) pin are
fixed to high level and the output switching is performed by the SHDNB1 (No.47) pin.
The rising sequence starts the rising of ch1 at the beginning. When the output voltage of ch1 becomes about 70% of
setting output voltage, ch2 will start the rising, and when the output voltage of ch2 becomes about 90% of setting
output voltage, It begins then after about 3 ms that ch3 will start the rising.
The falling sequence starts the falling of ch3 at the beginning, and will start simultaneously the falling of ch1 and ch2
when the output voltage of ch3 becomes about 0.55 V.
7.9 Discharge Circuit Block
If the capacitance of the output capacitor of ch3 is too high when the IC is started with the ON/OFF sequencer set to
ON (CTL1 = L), the energy built up in the capacitor is hard to discharge and the fall time of ch1 to ch3 is extended. To
prevent this, this IC has an internal discharging circuit. The DCIN3 (No.35) pin serves as the open-drain input of an N-
channel MOS transistor. When ch3 falls, this N-channel MOS transistor turns ON, and the discharging circuit
discharges the output capacitor of ch3.
7.10 SCP Circuit Block (Timer Latch Short-circuit Protection Circuit)
If voltage of the DC/DC converter outputs ch1 to ch6 drops (or rises if the polarity of ch5 is inverted), the voltage of
the inversion input pin of the E/A, which is feeding back the output, also drops. If the voltage on the inversion input
pin falls below the input detection voltage of the SCP circuit (ch1 = VTH(II)1 = 0.56 V, ch2 = VTH(II)2 = 0.72 V, ch3 =
VTH(II)3 = 0.72 V, ch4 = VTH(II)4 = 0.6 V, ch5 step-up voltage = VTH(II)5R = 0.6 V, ch5 polarity inversion voltage = VTH(II)5I =
0.8 V, ch6 = VTH(II)6 = 0.3 V), the timer circuit operates and the capacitor connected to the CDLY (No.31) pin is charged.
When the voltage of the capacitor connected to the CDLY (No.31) pin reaches 0.9 V TYP., all the outputs of the IC is
latched to OFF.
If the E/A inversion input pin voltage of any of ch1 to ch6 is less than the input detection voltage of the SCP circuit,
the capacitor connected to the CDLY (No.31) pin stays charged.
To reset the latch circuit when the short-circuit protection circuit is activated, decrease the supply voltage (AVDD) to
the GND level once, or reset the SHDNB1 (No.47) pin to OFF.
13
Preliminary Product Information S16949EJ1V0PM
µ PD16907
7.11 SHDN Circuit Block (Shut-down Circuit)
The SHDNB1 to SHDNB6 are used to turn on or to turn off the output of each channel by external signal.
When SHDNB1 to SHDNB6 = low level, the shut-down circuit operates and shuts down the output of each channel.
When SHDNB1 to SHDNB6 = high level, the shut-down circuit stops and the output rises while a soft start is being
executed by the voltage on the CSS1 (No.30) pin and CSS2 (No.29) pin.
If ch1 does not turn on even if SHNB2 to SHDNB6 are set to high level, ch2 to ch6 will not turn on.
7.12 Current Limiting Circuit Block
The output block of ch2 and ch3 incorporates the current limiting circuit of the pulse by pulse. At the state of PIN1 =
PIN2 = 5 V, when current 1000 mA TYP. or more flows between drain and source of the Power MOS FET transistor on
the high side, the Power MOS FET transistor on the high side is made to latch to OFF. Similarly, When current 800
mA TYP. or more flows at the state of PIN1 = PIN2 = 3.3 V and current 500 mA TYP. or more flows at the of PIN1 =
PIN2 = 2 V, the Power MOS FET transistor on the high side is made to latch to OFF. Because latch is reset with one
cycle of the oscillation pulse, the restriction of pulse width is possible at every cycle.
7.13 Overheat Protection Circuit Block
This IC has an internal temperature detector. This circuit operates SCP and shuts down all the outputs of the IC if
the internal temperature of the IC exceeds 150°C.
14
Preliminary Product Information S16949EJ1V0PM
µ PD16907
8. NOTES ON USE
8.1 Method of Setting Output Voltage
The method of setting the output voltage is illustrated below. The output voltage can be calculated by the expression
shown in the figure.
The input threshold voltage of E/A1 to E/A4 in the error amplifier block is 0.8 V, and that of E/A5 is 0.8 V TYP. when
a step-up circuit is configured (CTL2 = L) and 0.6 V TYP. when a polarity inversion circuit is configured (CTL2 = H).
The input threshold voltage of E/A6 is 0.4 V TYP..
Method of setting output voltage
when the step-up circuits of ch1 to ch5 are configured
VOUT = (1 + R1/R2) x 0.8
V
OUT (output voltage)
When the step-up circuits
of E/A1 to E/A5 are confiugred.
R1
−
+
R2
0.8 V
Method of setting output voltage
when the polarity inversion circuit of ch5 is configured
VOUT = (1 + R2/R1) x 0.6 − R2/R1 x VREF
V
REF (reference voltage, pin No.19)
When the polarity inversion circuit
is configured.
R1
R2
−
+
0.6 V
−VOUT (output voltage)
Method of setting output voltage of ch6
OUT = (1 + R1/R2) x 0.4
V
V
OUT (output voltage)
R1
E/A6
−
+
R2
0.4 V
15
Preliminary Product Information S16949EJ1V0PM
µ PD16907
8.2 Method of Setting Oscillation Frequency
The oscillation frequency can be arbitrarily set by the timing resistor connected to the RT (No.9) pin, and the timing
capacitance value connected to the CT (No.8) pin.
The fOSC vs. RT characteristics are as follows, with CT as the parameter.
OSCILLATION FREQUENCY vs. RT characteristics
1000
CT
= 100 pF
220 pF
330 pF
500
0
0.1
1
10
RT - kΩ
8.3 Method of Setting Soft-start Time
The soft-start time of ch1 to ch3 can be arbitrarily set by capacitor connected to the CSS1 (No.30) pin. The soft-start
time of ch4 to ch6 can be arbitrarily set by capacitor connected to the CSS2 (No.29) pin.
8.4 Note on Actual Pattern Writing
When actually wiring the pattern, separate the ground of the control lines from the ground of the power lines, so that
there is as little common impedance as possible. In addition, decrease the high-frequency impedance by using a
capacitor, so that noise is not superimposed on the VREF (No.19) pin.
16
Preliminary Product Information S16949EJ1V0PM
µ PD16907
9. APPLICATION CIRCUIT EXAMPLES
9.1 Application Circuit Example 1
SS of ch1 to ch3
SS of ch4 to ch6
AGND
CSS1
CSS2
R
T
CT
C
DLY
VREF
AVDD
CTL
2
1
AVDD
PVDD
Controller
CTL
Reference
Voltage
Circuit
SCP
CTL Circuit
Circuit
Oscillator
SS Circuit
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
1
2
All channels latch.
3
4
SHDN Circuit
VBAT
Overheat
Protecion
Circuit
5
6
ON/OFF Sequencer
DCOUT
(5 V)
1
FB1
OUT1N
OUT1P
DCIN
1
ch1
Control
Synchronous
Rectification
Control
−
+
+
+
−
VREF
E/A1
II1
PWM1
PGND
1
OUT1S
V
BAT
P
IN2-1
FB2
DCIN
2
ch2
Control
P
IN2-2
+
−
+
+
Synchronous
Rectification
Control
LX2-1
DCOUT
2
−
VREF
(1.8 V)
E/A2
II2
PWM2
LX2-2
PGND
2
DCIN
3
DCIN3
Discharge
Circuit
PIN3-1
FB
3
P
LX3-1
IN3-2
ch3
Control
DCOUT
(3.3 V)
3
+
−
+
+
Synchronous
Rectification
Control
−
VREF
E/A3
II3
PWM3
LX3-2
PGND
3
VBAT
FB
4
DCIN
4
DCOUT
(+10 V)
4
ch4
Control
OUT
4
−
+
+
+
−
VREF
E/A4
E/A5
I
I4
PWM4
FB
5
DCIN
5
ch5
Control
OUT
5
−
+
+
+
−
DCOUT5
(−8 V)
VREF
I
I5
PWM5
V
REF
FB6
DCOUT
(+12 V)
6
ch6
Control
OUT
6
−
+
+
−
DCIN
6
VREF
+
E/A6
II6
PWM6
PGND
4
Caution The constants shown in this figure are for reference only and do not guarantee the characteristics.
Set the constants and use appropriate components in accordance with the actual operating
conditions.
17
Preliminary Product Information S16949EJ1V0PM
µ PD16907
9.2 Application Circuit Example 2
SS of ch1 to ch3
SS of ch4 to ch6
AGND
C
SS1
C
SS2
R
T
C
T
CDLY
VREF
CTL
2
1
AVDD
PVDD
Controller
CTL
Reference
Voltage
Circuit
SCP
CTL Circuit
Circuit
Oscillator
SS Circuit
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
SHDNB
1
2
All channels latch.
3
4
SHDN Circuit
V
BAT
Overheat
Protecion
Circuit
5
6
ON/OFF Sequencer
DCOUT
(5 V)
1
FB1
OUT1N
OUT1P
DCIN
1
ch1
Control
Synchronous
Rectification
Control
−
+
+
+
−
V
REF
E/A1
E/A2
E/A3
I
I1
PWM1
PGND
1
OUT1S
V
IN2-1
BAT
P
FB
2
DCIN
2
ch2
PIN2-2
+
−
+
+
Control
Synchronous
Rectification
Control
LX2-1
DCOUT
(1.8 V)
2
−
V
REF
I
I2
PWM2
LX2-2
PGND
2
DCIN
3
DCIN3
Discharge
Circuit
P
IN3-1
FB
3
P
IN3-2
ch3
Control
DCOUT
(3.3 V)
3
+
−
+
+
Synchronous
Rectification
Control
LX3-1
−
V
REF
I
I3
PWM3
LX3-2
PGND
3
DCOUT
(+10 V)
4
V
BAT
FB4
DCIN
4
ch4
Control
OUT
4
−
+
+
+
−
DCOUT
(−3 V)
4
V
REF
E/A4
E/A5
I
I4
PWM4
DCOUT
(+12 V)
5
V
BAT
FB5
DCIN
5
ch5
Control
OUT
5
−
+
+
+
DCOUT
(−5 V)
5
−
V
REF
I
I5
PWM5
V
BAT
FB
6
DCOUT
(+12 V)
6
ch6
Control
OUT
6
−
+
+
−
DCIN
6
V
REF
+
E/A6
I
I6
PWM6
PGND
4
Caution The constants shown in this figure are for reference only and do not guarantee the characteristics.
Set the constants and use appropriate components in accordance with the actual operating
conditions.
18
Preliminary Product Information S16949EJ1V0PM
µ PD16907
10. PACKAGE DRAWING
48-PIN PLASTIC WQFN (7x7)
HD
D
HD
/2
D
/2
4−C0.5
detail of P part
36
37
25
24
A
A2
c
S
48
13
12
y
S
A1
1
x4
terminal section
c2
ZE
f
S A B
ZD
P
c1
y1
S
S
t
x4
b1
b
B
S A B
(UNIT:mm)
ITEM DIMENSIONS
6.75
6.75
0.20
7.00
7.00
0.20
0.67
D
E
A
f
HD
HE
t
+0.08
−0.04
A
+0.02
A1
A2
b
0.03
0.64
−0.025
e
Lp
A
0.08MIN.
0.23 0.05
0.20 0.03
0.17
b1
c
M
b
x
S
B
0.08MIN.
c1
c2
e
0.14∼0.16
0.14∼0.20
0.50
NOTES
1 "t" AND "f" EXCLUDES MOLD FLASH
Lp
x
0.40 0.10
0.05
2 ALTHOUGH THERE ARE 4 TERMINALS IN THE CORNER PART
OF A PACKAGE, THESE TERMINALS ARE NOT DESIGNED FOR
INTERCONNECTION, BUT FOR MANUFACTURING PROCESS OF
THE PACKAGE, THEREFOR DO NOT INTEND TO SOLDER THESE
4 TERMINALS, SOLDERABLITY OF THE 4 TERMINALS ARE NOT
GUARANTEED.
0.08
y
0.10
y1
ZD
ZE
0.625
0.625
P48K9-50-5B4-1
19
Preliminary Product Information S16949EJ1V0PM
µ PD16907
11. RECOMMENDED SOLDERING CONDITIONS
The µ PD16907 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
µ PD16907K9-5B4: 48-pin plastic WQFN (7 x 7)
Process
Conditions
Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher) ,
Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended.
<Precaution>
IR60-103-3
Products other than in heat-resistant trays (such as those packaged in a magazine,
taping, or non-thermal-resistant tray) cannot be baked in their package.
Note After opening the dry pack, store it a 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating) .
20
Preliminary Product Information S16949EJ1V0PM
µ PD16907
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
21
Preliminary Product Information S16949EJ1V0PM
µ PD16907
•
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics products before using it in a particular application.
•
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
"Standard":
"Special":
"Specific":
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5 02. 11-1
相关型号：
UPD17002CU
Microcontroller, 4-Bit, MROM, 8MHz, CMOS, PDIP48, 0.600 INCH, SHRINK, PLASTIC, DIP-48
NEC
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