UPD789062MC-XXX-5A4 [RENESAS]
8-BIT, MROM, 5MHz, MICROCONTROLLER, PDSO20, 0.300 INCH, PLASTIC, SSOP-20;
| 型号： | UPD789062MC-XXX-5A4 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT, MROM, 5MHz, MICROCONTROLLER, PDSO20, 0.300 INCH, PLASTIC, SSOP-20 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总213页 (文件大小：1229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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April 1st, 2010
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User’s Manual
µPD789052, 789062 Subseries
8-Bit Single-Chip Microcontrollers
µPD789052
µPD78E9860A
µPD789062
µPD78E9861A
Document No. U15861EJ3V1UD00 (3rd edition)
Date Published August 2005 N CP(K)
©
2002, 2003
Printed in Japan
[MEMO]
2
User’s Manual U15861EJ3V1UD
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
User’s Manual U15861EJ3V1UD
FIP and EEPROM are trademarks of NEC Electronics Corporation.
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PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
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(Note)
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(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U15861EJ3V1UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
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•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
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J05.6
5
User’s Manual U15861EJ3V1UD
Major Revisions in This Edition
Pages
Description
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
pp. 22, 23, 30, 31
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
• Update of 1.5 78K/0S Series Lineup and 2.5 78K/0S Series Lineup to latest version
CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
• Deletion of non-selectable clock settings
pp. 60, 61, 62, 64
• Addition of Notes to Figure 5-2 Format of EEPROM Write Control Register 10
• Modification of description of (8) in 5.4 Notes for EEPROM Writing
p. 88
CHAPTER 9 8-BIT TIMERS 30 AND 40
• Addition of description “output to EEPROM” to Figure 9-2 Block Diagram of Timer 40
p. 144
CHAPTER 14 INTERRUPT FUNCTIONS
• Modification of a signal name in Figure 14-6 Timing of Non-Maskable Interrupt Request
Acknowledgment
pp. 153, 154, 156, 157
CHAPTER 15 STANDBY FUNCTIONS
• Specification of non-maskable interruption for HALT release in 15.2.1 HALT Mode
• Addition of non-maskable interruption for STOP release to 15.2.2 STOP Mode
CHAPTER 17 µPD78E9860A, 78E9861A
p. 161
• Addition of descriptions of oscillation stabilization time in Table 17-1 Differences Between
µPD78E9860A, 78E9861A and Mask ROM Versions
• Modification of description of CLK connection in Table 17-3 Pin Connection List
p. 189
p. 198
CHAPTER 20 ELECTRICAL SPECIFICATIONS
• Modification of condition of supply currents of µPD78E9860A in DC Characteristics
CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
• Modification of soldering conditions of µPD789052 and 789062 in Table 23-1 Surface Mounting
Type Soldering Conditions
Major revisions in modification version (U15861JE3V1UD00)
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
• Addition of lead-free products
pp. 20, 21, 28, 29
p. 199
CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
• Addition of soldering conditions of lead-free products in Table 23-1 Surface Mounting Type
Soldering Conditions
The mark shows major revised points.
6
User’s Manual U15861EJ3V1UD
INTRODUCTION
Target Readers
This manual is intended for user engineers who wish to understand the functions of
the µPD789052, 789062 Subseries in order to design and develop its application
systems and programs.
The target devices are the following subseries products.
• µPD789052 Subseries: µPD789052, 78E9860A
• µPD789062 Subseries: µPD789062, 78E9861A
The system clock oscillation frequency of the ceramic/crystal oscillation (µPD789052
Subseries) is described as fX and the system clock oscillation frequency of the RC
oscillation (µPD789062 Subseries) is described as fCC.
Purpose
This manual is intended to give users on understanding of the functions described in
the Organization below.
Organization
Two manuals are available for the µPD789052, 789062 Subseries: this manual and
the Instruction Manual (common to the 78K/0S Series).
µPD789052, 789062
Subseries
78K/0S Series
User’s Manual
Instructions
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupts
• Instruction set
• Instruction description
• Other internal peripheral functions
• Electrical specifications
How to Use This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
To understand the overall functions of the µPD789052, 789062 Subseries
→ Read this manual in the order of the CONTENTS.
How to read register formats
→
The name of a bit whose number is enclosed with <> is reserved in the
assembler and is defined as an sfr variable by the #pragma sfr directive for
the C compiler.
To learn the detailed functions of a register whose register name is known
→ See APPENDIX C REGISTER INDEX.
To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
To learn the electrical specifications of the µPD789052, 789062 Subseries
→ See CHAPTER 20 ELECTRICAL SPECIFICATIONS.
7
User’s Manual U15861EJ3V1UD
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
µPD789052, 789062 Subseries User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
Document No.
U16656E
U14877E
U11623E
U16654E
U14872E
U16768E
U15802E
U16584E
U16569E
RA78K0S Assembler Package
Operation
Language
Structured Assembly Language
CC78K0S C Compiler
Operation
Language
SM78K Series Ver. 2.52 System Simulator
Operation
External Part User Open Interface Specification
Operation
ID78K0S-NS Ver. 2.52 Integrated Debugger
PM plus Ver.5.10
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
IE-789860-NS-EM1 Emulation Board
U16499E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
8
User’s Manual U15861EJ3V1UD
Documents Related to Flash Memory Writing
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
9
User’s Manual U15861EJ3V1UD
CONTENTS
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)............................................................................20
1.1 Features ......................................................................................................................................20
1.2 Applications................................................................................................................................20
1.3 Ordering Information .................................................................................................................20
1.4 Pin Configuration (Top View)....................................................................................................21
1.5 78K/0S Series Lineup.................................................................................................................22
1.6 Block Diagram............................................................................................................................25
1.7 Overview of Functions...............................................................................................................26
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)............................................................................28
2.1 Features ......................................................................................................................................28
2.2 Applications................................................................................................................................28
2.3 Ordering Information .................................................................................................................28
2.4 Pin Configuration (Top View)....................................................................................................29
2.5 78K/0S Series Lineup.................................................................................................................30
2.6 Block Diagram............................................................................................................................33
2.7 Overview of Functions...............................................................................................................34
CHAPTER 3 PIN FUNCTIONS...............................................................................................................36
3.1 Pin Function List........................................................................................................................36
3.2 Description of Pin Functions....................................................................................................37
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
P00 to P07 (Port 0)......................................................................................................................37
P20, P21 (Port 2).........................................................................................................................37
P40 to P43 (Port 4)......................................................................................................................37
RESET ........................................................................................................................................37
X1, X2 (µPD789052 Subseries) ..................................................................................................37
CL1, CL2 (µPD789062 Subseries) ..............................................................................................37
V
DD ..............................................................................................................................................38
VSS ..............................................................................................................................................38
VPP (µPD78E9860A, 78E9861A only)..........................................................................................38
IC (mask ROM version only) .......................................................................................................38
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................39
CHAPTER 4 CPU ARCHITECTURE......................................................................................................40
4.1 Memory Space............................................................................................................................40
4.1.1
4.1.2
4.1.3
4.1.4
Internal program memory space..................................................................................................42
Internal data memory space........................................................................................................42
Special function register (SFR) area............................................................................................43
Data memory addressing ............................................................................................................43
4.2 Processor Registers ..................................................................................................................45
10
User’s Manual U15861EJ3V1UD
4.2.1
4.2.2
4.2.3
Control registers ..........................................................................................................................45
General-purpose registers...........................................................................................................48
Special function registers (SFRs) ................................................................................................49
4.3 Instruction Address Addressing ..............................................................................................51
4.3.1
4.3.2
4.3.3
4.3.4
Relative addressing.....................................................................................................................51
Immediate addressing .................................................................................................................52
Table indirect addressing.............................................................................................................53
Register addressing.....................................................................................................................53
4.4 Operand Address Addressing..................................................................................................54
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
Direct addressing.........................................................................................................................54
Short direct addressing................................................................................................................55
Special function register (SFR) addressing .................................................................................56
Register addressing.....................................................................................................................57
Register indirect addressing ........................................................................................................58
Based addressing........................................................................................................................59
Stack addressing.........................................................................................................................59
CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)...............................60
5.1 Memory Space............................................................................................................................60
5.2 EEPROM Configuration.............................................................................................................60
5.3 EEPROM Control Register ........................................................................................................60
5.4 Notes for EEPROM Writing .......................................................................................................63
CHAPTER 6 PORT FUNCTIONS...........................................................................................................65
6.1 Port Functions............................................................................................................................65
6.2 Port Configuration .....................................................................................................................65
6.2.1
6.2.2
6.2.3
Port 0...........................................................................................................................................66
Port 2...........................................................................................................................................67
Port 4...........................................................................................................................................68
6.3 Port Function Control Registers ..............................................................................................69
6.4 Operation of Port Functions .....................................................................................................70
6.4.1
6.4.2
6.4.3
Writing to I/O port ........................................................................................................................70
Reading from I/O port..................................................................................................................70
Arithmetic operation of I/O port....................................................................................................70
CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES) .......................................................71
7.1 Clock Generator Functions.......................................................................................................71
7.2 Clock Generator Configuration ................................................................................................71
7.3 Clock Generator Control Register............................................................................................72
7.4 System Clock Oscillators..........................................................................................................73
7.4.1
7.4.2
7.4.3
System clock oscillator ................................................................................................................73
Examples of incorrect resonator connection................................................................................74
Frequency divider........................................................................................................................75
7.5 Clock Generator Operation .......................................................................................................76
11
User’s Manual U15861EJ3V1UD
7.6 Changing Setting of CPU Clock ...............................................................................................77
7.6.1
7.6.2
Time required for switching CPU clock........................................................................................77
Switching CPU clock ...................................................................................................................77
CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES) .......................................................78
8.1 Clock Generator Functions.......................................................................................................78
8.2 Clock Generator Configuration ................................................................................................78
8.3 Clock Generator Control Register............................................................................................79
8.4 System Clock Oscillators..........................................................................................................80
8.4.1
8.4.2
8.4.3
System clock oscillator ................................................................................................................80
Examples of incorrect resonator connection................................................................................81
Frequency divider........................................................................................................................82
8.5 Clock Generator Operation.......................................................................................................83
8.6 Changing Setting of CPU Clock ...............................................................................................84
8.6.1
8.6.2
Time required for switching CPU clock........................................................................................84
Switching CPU clock ...................................................................................................................84
CHAPTER 9 8-BIT TIMERS 30 AND 40..............................................................................................85
9.1 8-Bit Timers 30 and 40 Functions.............................................................................................85
9.2 8-Bit Timers 30 and 40 Configuration ......................................................................................86
9.3 8-Bit Timers 30 and 40 Control Registers ...............................................................................90
9.4 8-Bit Timers 30 and 40 Operation.............................................................................................95
9.4.1
9.4.2
9.4.3
9.4.4
Operation as 8-bit timer counter ..................................................................................................95
Operation as 16-bit timer counter ..............................................................................................104
Operation as carrier generator...................................................................................................111
Operation as PWM output (timer 40 only) .................................................................................116
9.5 Notes on Using 8-Bit Timers 30 and 40 .................................................................................118
CHAPTER 10 WATCHDOG TIMER .....................................................................................................120
10.1 Watchdog Timer Functions.....................................................................................................120
10.2 Watchdog Timer Configuration ..............................................................................................121
10.3 Watchdog Timer Control Registers........................................................................................122
10.4 Watchdog Timer Operation.....................................................................................................124
10.4.1
10.4.2
Operation as watchdog timer.....................................................................................................124
Operation as interval timer ........................................................................................................125
CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)......................126
11.1 Power-on-Clear Circuit Functions..........................................................................................126
11.2 Power-on-Clear Circuit Configuration ...................................................................................126
11.3 Power-on-Clear Circuit Control Registers.............................................................................128
11.4 Power-on-Clear Circuit Operation..........................................................................................130
11.4.1
11.4.2
Power-on-clear (POC) circuit operation.....................................................................................130
Operation of low-voltage detection (LVI) circuit .........................................................................131
12
User’s Manual U15861EJ3V1UD
CHAPTER 12 BIT SEQUENTIAL BUFFER ........................................................................................133
12.1 Bit Sequential Buffer Functions .............................................................................................133
12.2 Bit Sequential Buffer Configuration.......................................................................................133
12.3 Bit Sequential Buffer Control Register ..................................................................................134
12.4 Bit Sequential Buffer Operation .............................................................................................135
CHAPTER 13 KEY RETURN CIRCUIT...............................................................................................136
13.1 Key Return Circuit Function ...................................................................................................136
13.2 Key Return Circuit Configuration and Operation .................................................................136
CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................137
14.1 Interrupt Function Types.........................................................................................................137
14.2 Interrupt Sources and Configuration.....................................................................................137
14.3 Interrupt Function Control Registers.....................................................................................140
14.4 Interrupt Servicing Operation .................................................................................................143
14.4.1
14.4.2
14.4.3
14.4.4
Non-maskable interrupt request acknowledgement operation...................................................143
Maskable interrupt request acknowledgement operation...........................................................145
Multiple interrupt servicing.........................................................................................................147
Interrupt request pending...........................................................................................................149
CHAPTER 15 STANDBY FUNCTION..................................................................................................150
15.1 Standby Function and Configuration.....................................................................................150
15.1.1
15.1.2
Standby function........................................................................................................................150
Standby function control register ...............................................................................................151
15.2 Standby Function Operation...................................................................................................152
15.2.1
15.2.2
HALT mode ...............................................................................................................................152
STOP mode...............................................................................................................................155
CHAPTER 16 RESET FUNCTION .......................................................................................................158
CHAPTER 17 µPD78E9860A, 78E9861A............................................................................................161
17.1 EEPROM (Program Memory)...................................................................................................162
17.1.1
17.1.2
17.1.3
17.1.4
Programming environment ........................................................................................................162
Communication mode................................................................................................................163
On-board pin processing ...........................................................................................................166
Connection of adapter for flash memory (EEPROM) writing......................................................169
CHAPTER 18 MASK OPTIONS ...........................................................................................................171
CHAPTER 19 INSTRUCTION SET OVERVIEW.................................................................................172
19.1 Operation ..................................................................................................................................172
19.1.1
Operand identifiers and description methods ............................................................................172
13
User’s Manual U15861EJ3V1UD
19.1.2 Description of “Operation” column.................................................................................................173
19.1.3 Description of “Flag” column..........................................................................................................173
19.2 Operation List...........................................................................................................................174
19.3 Instructions Listed by Addressing Type ...............................................................................179
CHAPTER 20 ELECTRICAL SPECIFICATIONS.................................................................................182
CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) ..............................................................................................196
CHAPTER 22 PACKAGE DRAWING ..................................................................................................197
CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS...........................................................198
APPENDIX A DEVELOPMENT TOOLS...............................................................................................200
A.1 Software Package ....................................................................................................................202
A.2 Language Processing Software .............................................................................................202
A.3 Control Software ......................................................................................................................203
A.4 EEPROM (Program Memory) Writing Tools ..........................................................................203
A.5 Debugging Tools (Hardware)..................................................................................................204
A.6 Debugging Tools (Software)...................................................................................................205
APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................206
APPENDIX C REGISTER INDEX.........................................................................................................208
C.1 Register Name Index (in Alphabetical Order) .......................................................................208
C.2 Register Symbol Index (in Alphabetical Order) ....................................................................209
APPENDIX D REVISION HISTORY .....................................................................................................210
14
User’s Manual U15861EJ3V1UD
LIST OF FIGURES (1/3)
Figure No.
Title
Page
3-1
Pin I/O Circuits...............................................................................................................................................39
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
Memory Map (µPD789052, 789062)..............................................................................................................40
Memory Map (µPD78E9860A, 78E9861A) ....................................................................................................41
Data Memory Addressing (µPD789052, 789062) ..........................................................................................43
Data Memory Addressing (µPD78E9860A, 78E9861A).................................................................................44
Program Counter Configuration .....................................................................................................................45
Program Status Word Configuration ..............................................................................................................45
Stack Pointer Configuration ...........................................................................................................................47
Data to Be Saved to Stack Memory...............................................................................................................47
Data to Be Restored from Stack Memory ......................................................................................................47
General-Purpose Register Configuration .......................................................................................................48
5-1
5-2
EEPROM Block Diagram...............................................................................................................................60
Format of EEPROM Write Control Register 10..............................................................................................61
6-1
6-2
6-3
6-4
6-5
Block Diagram of P00 to P07.........................................................................................................................66
Block Diagram of P20 ....................................................................................................................................67
Block Diagram of P21 ....................................................................................................................................68
Block Diagram of P40 to P43.........................................................................................................................68
Format of Port Mode Register........................................................................................................................69
7-1
7-2
7-3
7-4
7-5
Block Diagram of Clock Generator.................................................................................................................71
Format of Processor Clock Control Register..................................................................................................72
External Circuit of System Clock Oscillator....................................................................................................73
Example of Incorrect Resonator Connection .................................................................................................74
Switching Between System Clock and CPU Clock ........................................................................................77
8-1
8-2
8-3
8-4
8-5
Block Diagram of Clock Generator.................................................................................................................78
Format of Processor Clock Control Register..................................................................................................79
External Circuit of System Clock Oscillator....................................................................................................80
Example of Incorrect Resonator Connection .................................................................................................81
Switching Between System Clock and CPU Clock ........................................................................................84
9-1
9-2
9-3
9-4
9-5
9-6
Timer 30 Block Diagram ................................................................................................................................87
Timer 40 Block Diagram ................................................................................................................................88
Block Diagram of Output Controller (Timer 40)..............................................................................................89
Format of 8-Bit Timer Mode Control Register 30 ...........................................................................................91
Format of 8-Bit Timer Mode Control Register 40 ...........................................................................................92
Format of Carrier Generator Output Control Register 40...............................................................................93
15
User’s Manual U15861EJ3V1UD
LIST OF FIGURES (2/3)
Figure No.
Title
Page
9-7
Format of Port Mode Register 2.....................................................................................................................94
Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) ..................................................97
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H)...................................97
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) ..................................98
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) ........98
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) ........99
Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal
9-8
9-9
9-10
9-11
9-12
9-13
Is Selected for Timer 30 Count Clock) .........................................................................................................100
Timing of Operation of External Event Counter with 8-Bit Resolution..........................................................101
Timing of Square-Wave Output with 8-Bit Resolution..................................................................................103
Timing of Interval Timer Operation with 16-Bit Resolution...........................................................................106
Timing of External Event Counter Operation with 16-Bit Resolution............................................................108
Timing of Square-Wave Output with 16-Bit Resolution................................................................................110
Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) .........................................113
Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) .........................................114
Timing of Carrier Generator Operation (When CR40 = CRH40 = N) ...........................................................115
PWM Output Mode Timing (Basic Operation)..............................................................................................117
PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten) ......................................................117
Case of Error Occurrence of up to 1.5 Clocks .............................................................................................118
Counting Operation if Timer Is Started When TMI Is High...........................................................................119
Timing of Operation as External Event Counter (8-Bit Resolution) ..............................................................119
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
10-1
10-2
10-3
Block Diagram of Watchdog Timer ..............................................................................................................121
Format of Timer Clock Selection Register 2 ................................................................................................122
Format of Watchdog Timer Mode Register..................................................................................................123
11-1
11-2
11-3
11-4
11-5
11-6
11-7
Block Diagram of Power-on-Clear Circuit ....................................................................................................127
Block Diagram of Low-Voltage Detection Circuit..........................................................................................127
Format of Power-on-Clear Register 1 ..........................................................................................................128
Format of Low-Voltage Detection Register 1 ...............................................................................................129
Format of Low-Voltage Detection Level Selection Register 1......................................................................129
Timing of Internal Reset Signal Generation in POC Switching Circuit .........................................................130
LVI Circuit Operation Timing........................................................................................................................132
12-1
12-2
12-3
12-4
Block Diagram of Bit Sequential Buffer........................................................................................................133
Format of Bit Sequential Buffer Output Control Register 10 ........................................................................134
Format of Port Mode Register 2...................................................................................................................134
Operation Timing of Bit Sequential Buffer....................................................................................................135
13-1
Block Diagram of Key Return Circuit............................................................................................................136
16
User’s Manual U15861EJ3V1UD
LIST OF FIGURES (3/3)
Figure No.
Title
Page
13-2
Generation Timing of Key Return Interrupt ..................................................................................................136
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
Basic Configuration of Interrupt Function.....................................................................................................139
Format of Interrupt Request Flag Register 0................................................................................................141
Format of Interrupt Mask Flag Register 0 ....................................................................................................141
Program Status Word Configuration ............................................................................................................142
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement (INTWDT)...................144
Timing of Non-Maskable Interrupt Request Acknowledgement ...................................................................144
Acknowledgement of Non-Maskable Interrupt Request ...............................................................................144
Interrupt Request Acknowledgement Processing Algorithm ........................................................................146
Interrupt Request Acknowledgement Timing (Example of MOV A, r) ..........................................................147
14-10 Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Set at Last Clock During
Instruction Execution) ..................................................................................................................................147
14-11 Example of Multiple Interrupts......................................................................................................................148
15-1
15-2
15-3
15-4
15-5
Format of Oscillation Stabilization Time Selection Register.........................................................................151
Releasing HALT Mode by Interrupt..............................................................................................................153
Releasing HALT Mode by RESET Input ......................................................................................................154
Releasing STOP Mode by Interrupt .............................................................................................................156
Releasing STOP Mode by RESET Input......................................................................................................157
16-1
16-2
16-3
16-4
Block Diagram of Reset Function.................................................................................................................158
Reset Timing by RESET Input.....................................................................................................................159
Reset Timing by Watchdog Timer Overflow.................................................................................................159
Reset Timing by RESET Input in STOP Mode.............................................................................................159
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
Environment for Writing Program to EEPROM (Program Memory) .............................................................162
Communication Mode Selection Format......................................................................................................163
Example of Connection with Dedicated Flash Programmer.........................................................................164
VPP Pin Connection Example.......................................................................................................................166
Signal Conflict (Input Pin of Serial Interface)................................................................................................167
Abnormal Operation of Other Device...........................................................................................................167
Signal Conflict (RESET Pin) ........................................................................................................................168
Wiring Example for Flash Memory (EEPROM) Writing Adapter with Pseudo 3-Wire ..................................169
A-1
Development Tools......................................................................................................................................201
B-1
B-2
Distance Between In-Circuit Emulator and Conversion Socket....................................................................206
Connection Conditions of Target System.....................................................................................................207
17
User’s Manual U15861EJ3V1UD
LIST OF TABLES (1/2)
Table No.
Title
Page
3-1
Types of Pin I/O Circuits and Recommended Connection of Unused Pins....................................................39
4-1
4-2
4-3
Internal ROM Capacity...................................................................................................................................42
Vector Table ..................................................................................................................................................42
Special Function Registers ............................................................................................................................50
5-1
5-2
EEPROM Write Time (When Operating at fX = 5.0 MHz)...............................................................................62
EEPROM Write Time (When Operating at fCC = 1.0 MHz).............................................................................62
6-1
6-2
6-3
Port Functions................................................................................................................................................65
Configuration of Port......................................................................................................................................65
Port Mode Register and Output Latch Settings for Using Alternate Functions...............................................69
7-1
7-2
Configuration of Clock Generator...................................................................................................................71
Maximum Time Required for Switching CPU Clock.......................................................................................77
8-1
8-2
Configuration of Clock Generator...................................................................................................................78
Maximum Time Required for Switching CPU Clock.......................................................................................84
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
Mode List .......................................................................................................................................................85
Configuration of 8-Bit Timers 30 and 40 ........................................................................................................86
Interval Time of Timer 30 (During fX = 5.0 MHz Operation) ...........................................................................96
Interval Time of Timer 30 (During fCC = 1.0 MHz Operation)..........................................................................96
Interval Time of Timer 40 (During fX = 5.0 MHz Operation) ...........................................................................96
Interval Time of Timer 40 (During fCC = 1.0 MHz Operation)..........................................................................96
Square-Wave Output Range of Timer 40 (During fX = 5.0 MHz Operation).................................................102
Square-Wave Output Range of Timer 40 (During fCC = 1.0 MHz Operation) ...............................................102
Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation).........................................................105
Interval Time with 16-Bit Resolution (During fCC = 1.0 MHz Operation) .......................................................105
Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation).................................109
Square-Wave Output Range with 16-Bit Resolution (During fCC = 1.0 MHz Operation)...............................109
10-1
10-2
10-3
10-4
10-5
Inadvertent Program Loop Detection Time of Watchdog Timer...................................................................120
Interval Time of Watchdog Timer.................................................................................................................120
Configuration of Watchdog Timer ................................................................................................................121
Inadvertent Program Loop Detection Time of Watchdog Timer...................................................................124
Interval Time of Watchdog Timer.................................................................................................................125
12-1
Configuration of Bit Sequential Buffer..........................................................................................................133
18
User’s Manual U15861EJ3V1UD
LIST OF TABLES (2/2)
Table No.
Title
Page
14-1
14-2
14-3
Interrupt Sources .........................................................................................................................................138
Interrupt Request Signals and Corresponding Flags ...................................................................................140
Time from Generation of Maskable Interrupt Request to Servicing..............................................................145
15-1
15-2
15-3
15-4
Operation Statuses in HALT Mode ..............................................................................................................152
Operation After Releasing HALT Mode........................................................................................................154
Operation Statuses in STOP Mode..............................................................................................................155
Operation After Releasing STOP Mode.......................................................................................................157
16-1
Status of Hardware After Reset ...................................................................................................................160
17-1
17-2
17-3
Differences Between µPD78E9860A, 78E9861A and Mask ROM Versions................................................161
Communication Mode List ...........................................................................................................................163
Pin Connection List......................................................................................................................................165
19-1
23-1
B-1
Operand Identifiers and Description Methods..............................................................................................172
Surface Mounting Type Soldering Conditions .............................................................................................198
Distance Between IE System and Conversion Socket.................................................................................206
19
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
1.1 Features
• ROM and RAM capacity
Item
Program Memory
(ROM)
Data Memory
Product Name
Internal High-Speed RAM
128 bytes
EEPROMTM
µPD789052
−
Mask ROM
EEPROM
4 KB
4 KB
µPD78E9860A
32 bytes
•
•
System clock: Ceramic/crystal oscillation
Minimum instruction execution time can be changed from high-speed (0.4 µs) to low-speed (1.6 µs) at 5.0 MHz
operation with system clock.
I/O ports: 14
•
•
Timer: 3 channels
•
8-bit timer:
2 channels
1 channel
•
Watchdog timer:
•
•
•
On-chip power-on-clear circuit (µPD78E9860A only)
On-chip bit sequential buffer
Power supply voltage
•
µPD789052:
VDD = 1.8 to 5.5 V
VDD = 1.8 to 5.5 V
•
µPD78E9860A:
•
Operating ambient temperature: TA = −40 to +85°C
1.2 Applications
TPMS (Tire Pressure Monitoring Systems) and other automotive electrical equipment.
1.3 Ordering Information
Part Number
Package
Internal ROM
Mask ROM
EEPROM
µPD789052MC-×××-5A4
µPD78E9860AMC-5A4
µPD789052MC-×××-5A4-A
µPD78E9860AMC-5A4-A
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
Mask ROM
EEPROM
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
20
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
1.4 Pin Configuration (Top View)
20-pin plastic SSOP (7.62 mm (300))
µPD789052MC-×××-5A4
µPD78E9860AMC-5A4
µPD789052MC-×××-5A4-A
µPD78E9860AMC-5A4-A
20
19
18
17
16
15
14
13
12
11
RESET
X1
P21/TMI
P20/TMO/BSFO
P07
1
2
3
4
5
6
7
8
9
10
X2
VSS
P06
IC (VPP
)
P05
VDD
P04
P00
P01
P02
P03
P43/KR13
P42/KR12
P41/KR11
P40/KR10
Caution Connect the IC (Internally Connected) pin directly to VSS.
Remark Pin connections in parentheses are intended for the µPD78E9860A.
BSFO:
Bit sequential buffer output
TMI:
Timer input
IC:
Internally connected
Key return
Port 0
TMO:
VDD:
Timer output
KR10 to KR13:
P00 to P07:
P20, P21:
P40 to P43:
RESET:
Power supply
VPP:
Programming power supply
Ground
Port 2
VSS:
Port 4
X1, X2:
Crystal/ceramic oscillator
Reset
21
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass
production
Products under
development
Y subseries supports SMB.
Small-scale package, general-purpose applications
µ
µ
µ
µ
µ
µ
µ
PD789074 with subsystem clock added
On-chip UART and capable of low-voltage (1.8 V) operation
44-pin
PD789046
PD789026
42-/44-pin
30-pin
PD789074 with enhanced timer function and expanded ROM and RAM
PD789026 with enhanced timer function
µ
PD789088
PD789074
PD789062
30-pin
µ
20-pin
RC oscillation version of PD789052
µ
PD789860 without EEPROM, POC, and LVI
µ
PD789052
20-pin
Small-scale package, general-purpose applications and A/D function
µ
PD789177
PD789177Y
PD789167Y
µ
µ
PD789167 with 10-bit A/D
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
µ
µ
µ
µ
PD789167
PD789134A
PD789124A
PD789114A
PD789104A
PD789104A with enhanced timer
PD789124A with 10-bit A/D
µ
µ
µ
µ
RC oscillation version of PD789104A
µ
µ
PD789104A with 10-bit A/D
PD789026 with 8-bit A/D and multiplier added
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789835
PD789830
PD789489
UART + 8-bit A/D + dot LCD (total display outputs: 96)
UART + dot LCD (40 × 16)
SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789479
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
PD789327
80-pin
80-pin
µ
PD789407A with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789446 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
78K/0S
Series
µ
µ
PD789426 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)
RC oscillation version of PD789306
µ
SIO + internal voltage boosting method LCD (24 × 4)
8-bit A/D + internal voltage boosting method LCD (23 × 4)
SIO + resistance division method LCD (24 × 4)
64-pin
52-pin
52-pin
µ
USB
44-pin
44-pin
µ
PD789800
For PC keyboard. On-chip USB function
On-chip inverter controller and UART
Inverter control
µ
PD789842
On-chip bus controller
44-pin
30-pin
PD789852
µ
µ
µ
PD789850A with enhanced timer and A/D converter, etc.
PD789850A
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
µ
PD789860 with enhanced timer function, SIO, and expanded ROM and RAM
PD789862
PD789861
PD789860
µ
RC oscillation version of PD789860
On-chip POC and key return circuit
VFD drive
µ
PD789871
52-pin
64-pin
On-chip VFD controller (total display outputs: 25)
Meter control
µ
PD789881
UART + resistance division method LCD (26 × 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
22
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
The major differences between subseries are shown below.
Series for General-Purpose and LCD Drive
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 10-Bit
Serial Interface
I/O
VDD
Remarks
A/D
A/D
Subseries
8-Bit 16-Bit Watch WDT
MIN.Value
Small-
scale
µPD789046
16 K
1 ch 1 ch 1 ch 1 ch
−
−
1 ch (UART: 1 ch) 34
24
1.8 V
−
µPD789026
µPD789088
µPD789074
µPD789062
4Kto16K
−
package,
general-
purpose
applica-
tions
16 K to 32 K 3 ch
2 K to 8 K 1 ch
4 K
2 ch
−
−
14
RC-oscillation
version
µPD789052
µPD789177
µPD789167
−
−
Small-
scale
16 K to 24 K 3 ch 1 ch 1 ch
1ch
−
8 ch
−
8 ch 1 ch (UART: 1 ch) 31
1.8 V
−
package,
general-
purpose
applica-
tions +
A/D
µPD789134A 2 K to 8 K 1 ch
µPD789124A
−
4 ch
−
20
RC-oscillation
version
4 ch
−
µPD789114A
4 ch
−
−
µPD789104A
4 ch
converter
LCD
drive
µPD789835
µPD789830
µPD789489
µPD789479
24 K to 60 K 6 ch
−
1 ch 1 ch 3 ch
−
1 ch (UART: 1 ch) 37 1.8 VNote Dot LCD
supported
24 K 1 ch 1 ch
−
30 2.7 V
32 K to 48 K 3 ch
24 K to 48 K
8 ch 2 ch (UART: 1 ch) 45 1.8 V
−
8 ch
−
−
µPD789417A 12 K to 24 K
µPD789407A
7 ch 1 ch (UART: 1 ch) 43
7 ch
−
−
µPD789456
µPD789446
µPD789436
µPD789426
µPD789316
12 K to 16 K 2 ch
6 ch
−
30
40
6 ch
−
6 ch
−
6 ch
−
8 K to 16 K
4 K to 24 K
2 ch (UART: 1 ch) 23
RC-oscillation
version
µPD789306
µPD789467
µPD789327
−
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
23
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
Series for ASSP
Subseries Name
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
µPD789800
µPD789842
µPD789852
µPD789850A
µPD789861
−
−
−
−
−
−
−
−
USB
8 KB
2 ch
1 ch
2 ch
31
30
31
18
14
4.0 V
4.0 V
4.0 V
(USB: 1 ch)
Inverter
control
8 KB to 16 KB 3 ch
1 ch 1 ch 8 ch
1 ch
Note 1
(UART: 1 ch)
−
−
4 ch
−
On-chip bus
controller
24 KB to
32 KB
3 ch 1 ch
1 ch
1 ch
8 ch 3 ch
(UART: 2 ch)
−
16 KB
2 ch
(UART: 1 ch)
−
−
−
−
Keyless
entry
4 KB
2 ch
1 ch
1.8 V RC oscillation
version, on-
chip EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
1 ch 2 ch
1 ch
22
33
(UART: 1 ch)
µPD789871
µPD789881
−
−
−
−
−
−
−
VFD drive
4 KB to 8 KB 3 ch
1 ch 1 ch
1 ch
2.7 V
28 2.7 VNote 2
−
Meter
16 KB
2 ch 1 ch
1 ch
1 ch
control
(UART: 1 ch)
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
24
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
1.6 Block Diagram
(1) µPD789052
Port 0
Port 2
Port 4
P00 to P07
P20, P21
8-bit
timer 30
Cascaded
16-bit
timer
78K/0S
CPU core
8-bit timer/
event
counter 40
TMI/P21
ROM
(4 KB)
counter
TMO/P20
P40 to P43
BSFO/P20
Bit seq. buffer
RESET
X1
System control
X2
Watchdog timer
RAM
(128 bytes)
KR10/P40 to
KR13/P43
Key return 10
VDD
VSS
IC
(2) µPD78E9860A
Port 0
Port 2
Port 4
P00 to P07
8-bit
timer 30
Cascaded
16-bit
timer
P20, P21
78K/0S
CPU core
8-bit timer/
event
counter 40
EEPROM
(4 KB)
TMI/P21
counter
TMO/P20
P40 to P43
BSFO/P20
Bit seq. buffer
RESET
X1
System control
X2
Watchdog timer
RAM
(128 bytes)
EEPROM
(32 bytes)
Power
on
Power
on
KR10/P40 to
KR13/P43
clear
clear
Key return 10
Low
voltage
indicator
VDD
VSS
VPP
25
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
1.7 Overview of Functions
µPD789052
µPD78E9860A
Part Number
Item
Internal memory
ROM
Mask ROM
4 KB
EEPROM
32 bytes
High-speed RAM
EEPROM
128 bytes
–
Oscillator
Ceramic/crystal oscillator
0.4/1.6 µs (@5.0 MHz operation with system clock)
8 bits × 8 registers
Minimum instruction execution time
General-purpose registers
Instruction set
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
I/O ports
Timers
Total:
14
10
4
CMOS I/O:
CMOS input:
• 8-bit timer:
2 channels
1 channel
• Watchdog timer:
Power-on-clear
circuit
POC circuit
LVI circuit
–
–
Generates internal reset signal
according to comparison of detection
voltage to power supply voltage
Generates interrupt request signal
according to comparison of detection
voltage to power supply voltage
Bit sequential buffer
Key return function
8 bits + 8 bits = 16 bits
Generates key return signal according to falling edge detection
Vectored interrupt
sources
Maskable
Internal: 3
Internal: 5
Non-maskable
Internal: 1, external: 1
VDD = 1.8 to 5.5 V
Power supply voltage
TA = −40 to +85°C
Operating ambient temperature
Package
20-pin plastic SSOP (7.62 mm (300))
26
User’s Manual U15861EJ3V1UD
CHAPTER 1 GENERAL (µPD789052 SUBSERIES)
An outline of the timer is shown below.
8-Bit Timer 30
8-Bit Timer 40
1 channel
1 channel
1 output
1 output
1 output
−
Watchdog Timer
Operation
mode
Interval timer
1 channel
1 channelNote
−
−
−
−
−
−
−
2
External event counter
Timer outputs
Function
1 output
−
−
−
−
1
PWM outputs
Square-wave outputs
Buzzer outputs
Capture
−
Interrupt sources
1
Note The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or interval timer function.
27
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
2.1 Features
• ROM and RAM capacity
Item
Program Memory
(ROM)
Data Memory
Product Name
µPD789062
Internal High-Speed RAM
128 bytes
EEPROM
−
Mask ROM
EEPROM
4 KB
4 KB
µPD78E9861A
32 bytes
•
•
System clock: Ceramic/crystal oscillation
Minimum instruction execution time can be changed from high-speed (2.0 µs) to low-speed (8.0 µs) at 1.0 MHz
operation with system clock.
I/O ports: 14
•
•
Timer: 3 channels
•
8-bit timer:
2 channels
1 channel
•
Watchdog timer:
•
•
•
•
On-chip power-on-clear circuit (µPD78E9861A only)
On-chip bit sequential buffer
Power supply voltage: VDD = 1.8 to 3.6 V
Operating ambient temperature: TA = −40 to +85°C
2.2 Applications
TPMS (Tire Pressure Monitoring Systems) and other automotive electrical equipment.
2.3 Ordering Information
Part Number
Package
Internal ROM
Mask ROM
EEPROM
µPD789062MC-×××-5A4
µPD78E9861AMC-5A4
µPD789062MC-×××-5A4-A
µPD78E9861AMC-5A4-A
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
Mask ROM
EEPROM
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
28
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
2.4 Pin Configuration (Top View)
20-pin plastic SSOP (7.62 mm (300))
µPD789062MC-×××-5A4
µPD78E9861AMC-5A4
µPD789062MC-×××-5A4-A
µPD78E9861AMC-5A4-A
20
19
18
17
16
15
14
13
12
11
RESET
CL1
P21/TMI
P20/TMO/BSFO
P07
1
2
3
4
5
6
7
8
9
10
CL2
V
SS
P06
IC (VPP
)
P05
VDD
P04
P00
P01
P02
P03
P43/KR13
P42/KR12
P41/KR11
P40/KR10
Caution Connect the IC (Internally Connected) pin directly to VSS.
Remark Pin connections in parentheses are intended for the µPD78E9861A.
BSFO:
Bit sequential buffer output
RC oscillator
Internally connected
Key return
RESET:
TMI:
Reset
CL1, CL2:
IC:
Timer input
TMO:
VDD:
Timer output
Power supply
Programming power supply
Ground
KR10 to KR13:
P00 to P07:
P20, P21:
P40 to P43:
Port 0
VPP:
Port 2
VSS:
Port 4
29
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
2.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass
production
Products under
development
Y subseries supports SMB.
Small-scale package, general-purpose applications
µ
µ
µ
µ
µ
µ
µ
PD789074 with subsystem clock added
On-chip UART and capable of low-voltage (1.8 V) operation
44-pin
PD789046
PD789026
42-/44-pin
30-pin
PD789074 with enhanced timer function and expanded ROM and RAM
PD789026 with enhanced timer function
µ
PD789088
PD789074
PD789062
30-pin
µ
20-pin
RC oscillation version of PD789052
µ
PD789860 without EEPROM, POC, and LVI
µ
PD789052
20-pin
Small-scale package, general-purpose applications and A/D function
µ
PD789177
PD789177Y
PD789167Y
µ
µ
PD789167 with 10-bit A/D
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
µ
µ
µ
µ
PD789167
PD789134A
PD789124A
PD789114A
PD789104A
PD789104A with enhanced timer
PD789124A with 10-bit A/D
µ
µ
µ
µ
RC oscillation version of PD789104A
µ
µ
PD789104A with 10-bit A/D
PD789026 with 8-bit A/D and multiplier added
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789835
PD789830
PD789489
UART + 8-bit A/D + dot LCD (total display outputs: 96)
UART + dot LCD (40 × 16)
SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789479
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
PD789327
80-pin
80-pin
µ
PD789407A with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789446 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
78K/0S
Series
µ
µ
PD789426 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)
RC oscillation version of PD789306
µ
SIO + internal voltage boosting method LCD (24 × 4)
8-bit A/D + internal voltage boosting method LCD (23 × 4)
SIO + resistance division method LCD (24 × 4)
64-pin
52-pin
52-pin
µ
USB
44-pin
44-pin
µ
PD789800
For PC keyboard. On-chip USB function
On-chip inverter controller and UART
Inverter control
µ
PD789842
On-chip bus controller
44-pin
30-pin
PD789852
µ
µ
µ
PD789850A with enhanced timer and A/D converter, etc.
PD789850A
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
µ
PD789860 with enhanced timer function, SIO, and expanded ROM and RAM
PD789862
PD789861
PD789860
µ
RC oscillation version of PD789860
On-chip POC and key return circuit
VFD drive
µ
PD789871
52-pin
64-pin
On-chip VFD controller (total display outputs: 25)
Meter control
µ
PD789881
UART + resistance division method LCD (26 × 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
30
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
The major differences between subseries are shown below.
Series for General-Purpose and LCD Drive
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 10-Bit
Serial Interface
I/O
VDD
Remarks
A/D
A/D
Subseries
8-Bit 16-Bit Watch WDT
MIN.Value
Small-
scale
µPD789046
16 K
1 ch 1 ch 1 ch 1 ch
−
−
1 ch (UART: 1 ch) 34
24
1.8 V
−
µPD789026
µPD789088
µPD789074
µPD789062
4Kto16K
−
package,
general-
purpose
applica-
tions
16 K to 32 K 3 ch
2 K to 8 K 1 ch
4 K
2 ch
−
−
14
RC-oscillation
version
µPD789052
µPD789177
µPD789167
−
−
Small-
scale
16 K to 24 K 3 ch 1 ch 1 ch
1ch
−
8 ch
−
8 ch 1 ch (UART: 1 ch) 31
1.8 V
−
package,
general-
purpose
applica-
tions +
A/D
µPD789134A 2 K to 8 K 1 ch
µPD789124A
−
4 ch
−
20
RC-oscillation
version
4 ch
−
µPD789114A
4 ch
−
−
µPD789104A
4 ch
converter
LCD
drive
µPD789835
µPD789830
µPD789489
µPD789479
24 K to 60 K 6 ch
−
1 ch 1 ch 3 ch
−
1 ch (UART: 1 ch) 37 1.8 VNote Dot LCD
supported
24 K 1 ch 1 ch
−
30 2.7 V
32 K to 48 K 3 ch
24 K to 48 K
8 ch 2 ch (UART: 1 ch) 45 1.8 V
−
8 ch
−
−
µPD789417A 12 K to 24 K
µPD789407A
7 ch 1 ch (UART: 1 ch) 43
7 ch
−
−
µPD789456
µPD789446
µPD789436
µPD789426
µPD789316
12 K to 16 K 2 ch
6 ch
−
30
40
6 ch
−
6 ch
−
6 ch
−
8 K to 16 K
4 K to 24 K
2 ch (UART: 1 ch) 23
RC-oscillation
version
µPD789306
µPD789467
µPD789327
−
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
31
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
Series for ASSP
Subseries Name
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
µPD789800
µPD789842
µPD789852
µPD789850A
µPD789861
−
−
−
−
−
−
−
−
USB
8 KB
2 ch
1 ch
2 ch
31
30
31
18
14
4.0 V
4.0 V
4.0 V
(USB: 1 ch)
Inverter
control
8 KB to 16 KB 3 ch
1 ch 1 ch 8 ch
1 ch
Note 1
(UART: 1 ch)
−
−
4 ch
−
On-chip bus
controller
24 KB to
32 KB
3 ch 1 ch
1 ch
1 ch
8 ch 3 ch
(UART: 2 ch)
−
16 KB
2 ch
(UART: 1 ch)
−
−
−
−
Keyless
entry
4 KB
2 ch
1 ch
1.8 V RC oscillation
version, on-
chip EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
1 ch 2 ch
1 ch
22
33
(UART: 1 ch)
µPD789871
µPD789881
−
−
−
−
−
−
−
VFD drive
4 KB to 8 KB 3 ch
1 ch 1 ch
1 ch
2.7 V
28 2.7 VNote 2
−
Meter
16 KB
2 ch 1 ch
1 ch
1 ch
control
(UART: 1 ch)
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
32
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
2.6 Block Diagram
(1) µPD789062
Port 0
Port 2
Port 4
P00 to P07
P20, P21
8-bit
timer 30
Cascaded
16-bit
timer
78K/0S
ROM
8-bit timer/
event
counter 40
TMI/P21
counter
CPU core
(4 KB)
TMO/P20
P40 to P43
BSFO/P20
Bit seq. buffer
RESET
CL1
System control
CL2
Watchdog timer
RAM
(128 bytes)
KR10/P40 to
KR13/P43
Key return 10
VDD
VSS
IC
(2) µPD78E9861A
Port 0
Port 2
Port 4
P00 to P07
P20, P21
8-bit
timer 30
Cascaded
16-bit
timer
78K/0S
CPU core
8-bit timer/
event
counter 40
EEPROM
(4 KB)
TMI/P21
counter
TMO/P20
P40 to P43
BSFO/P20
Bit seq. buffer
RESET
CL1
System control
CL2
Watchdog timer
RAM
EEPROM
Power
on
(128 bytes) (32 bytes)
Power
on
KR10/P40 to
KR13/P43
clear
clear
Key return 10
Low
voltage
indicator
V
DD
V
SS
V
PP
33
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
2.7 Overview of Functions
µPD789062
µPD78E9861A
Part Number
Item
Internal memory
ROM
Mask ROM
4 KB
EEPROM
32 bytes
High-speed RAM
EEPROM
128 bytes
–
Oscillator
RC oscillator
2.0/8.0 µs (@1.0 MHz operation with system clock)
8 bits × 8 registers
Minimum instruction execution time
General-purpose registers
Instruction set
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
I/O ports
Timers
Total:
14
10
4
CMOS I/O:
CMOS input:
• 8-bit timer:
2 channels
1 channel
• Watchdog timer:
Power-on-clear
circuit
POC circuit
LVI circuit
–
–
Generates internal reset signal
according to comparison of detection
voltage to power supply voltage
Generates interrupt request signal
according to comparison of detection
voltage to power supply voltage
Bit sequential buffer
Key return function
8 bits + 8 bits = 16 bits
Generates key return signal according falling edge detection
Vectored interrupt
sources
Maskable
Internal: 3
Internal: 5
Non-maskable
Internal: 1, external: 1
VDD = 1.8 to 3.6 V
Power supply voltage
TA = −40 to +85°C
Operating ambient temperature
Package
20-pin plastic SSOP (7.62 mm (300))
34
User’s Manual U15861EJ3V1UD
CHAPTER 2 GENERAL (µPD789062 SUBSERIES)
An outline of the timer is shown below.
8-Bit Timer 30
8-Bit Timer 40
1 channel
1 channel
1 output
1 output
1 output
−
Watchdog Timer
Operation
mode
Interval timer
1 channel
1 channelNote
−
−
−
−
−
−
−
2
External event counter
Timer outputs
Function
1 output
−
−
−
−
1
PWM outputs
Square-wave outputs
Buzzer outputs
Capture
−
Interrupt sources
1
Note The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or interval timer function.
35
User’s Manual U15861EJ3V1UD
CHAPTER 3 PIN FUNCTIONS
3.1 Pin Function List
(1) Port pins
Pin Name
P00 to P07
I/O
I/O
Function
After Reset
Input
Alternate Function
−
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
P20
I/O
Port 2
Input
Input
TMO/BSFO
TMI
2-bit I/O port
P21
Input/output can be specified in 1-bit units.
P40 to P43
Input
Port 4
KR10 to KR13
4-bit input-only port
For mask ROM versions, an on-chip pull-up resistor can be
specified by means of the mask option.
(2) Non-port pins
Pin Name
TMI
I/O
Function
After Reset
Alternate Function
Input
8-bit timer (TM40) input
Input
P21
TMO
Output 8-bit timer (TM40) output
Input
P20/BSFO
BSFO
KR10 to KR13
X1Note 1
X2Note 1
CL1Note 2
CL2Note 2
RESET
VDD
Output Bit sequential buffer (BSF10) output
Input
P20/TMO
Input
Key return input
Input
P40 to P43
−
−
−
−
−
−
−
−
−
−
Input
Connecting ceramic/crystal resonator for system clock
oscillation
−
−
−
Input
Connecting resistor (R) and capacitor (C) for system clock
oscillation
−
−
Input
System reset input
Input
−
−
−
−
−
−
−
−
Positive supply voltage
VSS
Ground potential
IC
Internally connected. Connect directly to VSS.
VPP
This pin is used to set the EEPROM programming mode and
applies a high voltage when a program is written or verified.
Notes 1. µPD789052 Subseries only
2. µPD789062 Subseries only
36
User’s Manual U15861EJ3V1UD
CHAPTER 3 PIN FUNCTIONS
3.2 Description of Pin Functions
3.2.1 P00 to P07 (Port 0)
These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port
mode register 0 (PM0).
3.2.2 P20, P21 (Port 2)
These pins constitute a 2-bit I/O port. In addition, these pins function as the timer input/output and bit sequential
buffer output.
Port 2 can be set to the following operation modes in 1-bit units.
(1) Port mode
In port mode, P20 and P21 function as a 2-bit I/O port. Port 2 can be set to input or output port mode in 1-bit
units by using port mode register 2 (PM2).
(2) Control mode
In this mode, P20 and P21 function as the timer input/output and the bit sequential buffer output.
(a) BSFO
This is the output pin of the bit sequential buffer.
(b) TMI
This is the external clock input pin for the timer 40.
(c) TMO
This is the output pin of the timer 40.
3.2.3 P40 to P43 (Port 4)
These pins constitute a 4-bit input-only port. In addition, these pins function as the key return input.
(1) Port mode
In port mode, P40 to P43 function as a 4-bit input-only port. For mask ROM versions, an on-chip pull-up
resistor can be specified by means of the mask option.
(2) Control mode
In this mode, P40 to P43 function as the key return input (KR10 to KR13).
3.2.4 RESET
An active-low system reset signal is input to this pin.
3.2.5 X1, X2 (µPD789052 Subseries)
These pins are used to connect a crystal resonator for system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
3.2.6 CL1, CL2 (µPD789062 Subseries)
These pins are used to connect a resistor (R) and capacitor (C) for system clock oscillation.
To supply an external clock, input the clock to CL1 and input the inverted signal to CL2.
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User’s Manual U15861EJ3V1UD
CHAPTER 3 PIN FUNCTIONS
3.2.7 VDD
This pin supplies positive power.
3.2.8 VSS
This pin is the ground potential pin.
3.2.9 VPP (µPD78E9860A, 78E9861A only)
A high voltage should be applied to this pin when the EEPROM programming mode is set and when the program
is written or verified.
Perform either of the following.
• Independently connect a 10kΩ pull-down resistor to VPP.
• Use the jumper on the board to connect VPP to the dedicated flash programmer or Vss, in programming mode or
normal operation mode, respectively.
If the wiring length between the VPP and VSS pins is too long or if external noise is superimposed on the VPP pin,
your program may not be executed correctly.
3.2.10 IC (mask ROM version only)
The IC (Internally Connected) pin is used to set the µPD789052 and 789062 to test mode before shipment. In
normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible.
If a potential difference is generated between the IC pin and the VSS pin due to a long wiring length between these
pins or an external noise superimposed on the IC pin, the user program may not run correctly.
• Directly connect the IC pin to the VSS pin.
V
SS IC
Keep short
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User’s Manual U15861EJ3V1UD
CHAPTER 3 PIN FUNCTIONS
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the I/O circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
P00 to P07
I/O Circuit Type
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to VDD or VSS via a resistor.
5
8
Output: Leave open.
P20/TMO/BSFO
P21/TMI
Connect directly to VDD or VSS.
P40/KR10 to P43/KR13
(mask ROM version)
2-E
2
Input
P40/KR10 to P43/KR13
(µPD78E9860A, 78E9861A)
−
RESET
IC
−
−
Connect directly to VSS.
Independently connect VPP to a 10 kΩ pull-down resistor or directry
VPP
connect to VSS.
Figure 3-1. Pin I/O Circuits
Type 2
Type 5
V
DD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
V
SS
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 2-E
Type 8
V
DD
V
DD
Pull-up resistor
(mask option)
Data
P-ch
IN/OUT
Output
disable
N-ch
V
SS
IN
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User’s Manual U15861EJ3V1UD
CHAPTER 4 CPU ARCHITECTURE
4.1 Memory Space
The µPD789052, 789062 Subseries can each access up to 64 KB of memory space. Figures 4-1 and 4-2 show
the memory maps.
Figure 4-1. Memory Map (µPD789052, 789062)
F F F F H
Special function registers
(SFR)
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Reserved
Data memory
space
0 F F F H
1 0 0 0 H
0 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Internal ROM
4,096 × 8 bits
Program memory
space
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 0 E H
0 0 0 D H
Vector table area
0 0 0 0 H
0 0 0 0 H
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CHAPTER 4 CPU ARCHITECTURE
Figure 4-2. Memory Map (µPD78E9860A, 78E9861A)
F F F F H
Special function registers
(SFR)
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Reserved
F 8 2 0 H
F 8 1 F H
EEPROM
(data memory)
32 × 8 bits
F 8 0 0 H
F 7 F F H
Data memory
space
0 F F F H
Reserved
1 0 0 0 H
0 F F F H
Program area
EEPROM
(program memory)
4,096 × 8 bits
0 0 8 0 H
0 0 7 F H
Program memory
space
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 0 E H
0 0 0 D H
Vector table area
0 0 0 0 H
0 0 0 0 H
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CHAPTER 4 CPU ARCHITECTURE
4.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789052, 789062 Subseries provide the following internal ROMs (or EEPROM) containing the following
capacities.
Table 4-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
EEPROM
Capacity
4,096 × 8 bits
µPD789052, 789062
µPD78E9860A, 78E9861A
The following areas are allocated to the internal program memory space:
(1) Vector table area
The 14-byte area of addresses 0000H to 000DH is reserved as a vector table area. This area stores
program start addresses to be used when branching by RESET input or interrupt request generation. Of a
16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 4-2. Vector Table
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
0008H
Interrupt Request
INTTM40
0002H
0004H
0006H
INTKR1
INTWDT
INTTM30
000AH
000CH
INTLVI1Note
INTEE0Note
Note µPD78E9860A, 78E9861A only
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
4.1.2 Internal data memory space
The µPD789052, 789062 Subseries provide the following RAMs.
(1) Internal high-speed RAM
The internal high-speed RAM is provided in the area of FE80H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.
(2) EEPROM (µPD78E9860A, 78E9861A only)
In the µPD78E9860A, 78E9861A, the EEPROM is provided in the area of F800H to F81FH.
For details of EEPROM, refer to CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A
ONLY).
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CHAPTER 4 CPU ARCHITECTURE
4.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH
(see Table 4-3).
4.1.4 Data memory addressing
Each of the µPD789052, 789062 Subseries is provided with a wide range of addressing modes to make memory
manipulation as efficient as possible. The data memory area (FE80H to FFFFH) can be accessed using a unique
addressing mode according to its use, such as a special function register (SFR). Figures 4-3 and 4-4 illustrate the
data memory addressing.
Figure 4-3. Data Memory Addressing (µPD789052, 789062)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Direct addressing
Register indirect addressing
Based addressing
Reserved
1 0 0 0 H
0 F F F H
Internal ROM
4,096 × 8 bits
0 0 0 0 H
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CHAPTER 4 CPU ARCHITECTURE
Figure 4-4. Data Memory Addressing (µPD78E9860A, 78E9861A)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Direct addressing
Reserved
Register indirect addressing
Based addressing
F 8 2 0 H
F 8 1 F H
EEPROM
(data memory)
32 × 8 bits
F 8 0 0 H
F 7 F F H
Reserved
1 0 0 0 H
0 F F F H
EEPROM
(program memory)
4,096 × 8 bits
0 0 0 0 H
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CHAPTER 4 CPU ARCHITECTURE
4.2 Processor Registers
The µPD789052, 789062 Subseries provide the following on-chip processor registers:
4.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 4-5. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 4-6. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
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CHAPTER 4 CPU ARCHITECTURE
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt
are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
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CHAPTER 4 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 4-7. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 4-8 and 4-9.
Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before using
the stack.
Figure 4-8. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP
SP
SP
SP
SP
3
3
2
1
_
_
_
_
_
_
SP
SP
SP
SP
2
2
1
SP
SP
SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower half
register pairs
PC7 to PC0
Upper half
register pairs
PC15 to PC8
SP
SP
SP
Figure 4-9. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower half
register pairs
SP
SP
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Upper half
register pairs
PC15 to PC8
SP + 1
SP + 2
SP + 1
SP + 2
SP + 1
SP + 2
SP + 3
SP
SP
SP
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CHAPTER 4 CPU ARCHITECTURE
4.2.2 General-purpose registers
A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit
register (AX, BC, DE, and HL).
Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 4-10. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Function names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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CHAPTER 4 CPU ARCHITECTURE
4.2.3 Special function registers (SFRs)
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and
bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying
an address, describe an even address.
Table 4-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. The symbols shown in this column are
reserved words in the assembler, and have already been defined as an sfr variable by the #pragma sfr directive
for the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated
debugger is used.
• R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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CHAPTER 4 CPU ARCHITECTURE
Table 4-3. Special Function Registers
Address Special Function Register (SFR) Name
Symbol
R/W Number of Bits Manipulated Simultaneously After Reset
1 Bit
√
8 Bits
16 Bits
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
FF00H
FF02H
FF04H
FF10H
FF11H
FF20H
FF22H
FF42H
FF50H
FF51H
FF52H
FF53H
FF54H
FF55H
FF56H
FF57H
Port 0
Port 2
Port 4
P0
R/W
00H
√
P2
P4
√
R
Note 1
√
−
Bit sequential buffer 10 data register L BSFRL10
Bit sequential buffer 10 data register H BSFRH10
W
Undefined
FFH
−
√
−
−
−
−
−
−
−
−
−
−
−
Port mode register 0
PM0
R/W
√
Port mode register 2
PM2
−
Timer clock selection register 2
8-bit compare register 30
8-bit timer counter 30
TCL2
CR30
TM30
TMC30
CR40
CRH40
TM40
TMC40
00H
−
W
R
Undefined
00H
−
√
8-bit timer mode control register 30
8-bit compare register 40
8-bit compare register H40
8-bit timer counter 40
R/W
W
−
Undefined
00H
−
−
R
R/W
W
√
8-bit timer mode control register 40
−
Carrier generator output control register TCA40
40
√
√
−
FF60H
Bit sequential buffer output control
register 10
BSFC10
R/W
√
√
√
√
√
√
√
√
−
−
−
−
FFD8H
FFDDH
FFDEH
FFDFH
EEPROM write control register 10Note 2
Power-on-clear register 1Note 2
EEWC10
POCF1
LVIF1
08H
00HNote 3
Low-voltage detection register 1Note 2
00H
Low-voltage detection level selection
register 1Note 2
LVIS1
√
√
√
−
√
√
√
√
−
−
−
−
FFE0H
FFE4H
FFF9H
FFFAH
Interrupt request flag register 0
Interrupt mask flag register 0
Watchdog timer mode register
IF0
MK0
FFH
00H
04H
WDTM
OSTS
Oscillation stabilization time selection
registerNote 4
√
√
−
FFFBH
Processor clock control register
PCC
02H
Notes 1. Specify address FF10H directly for 16-bit access.
2. µPD78E9860A, 78E9861A only
3. This value is 04H only after a power-on-clear reset.
4. µPD789052 Subseries only
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CHAPTER 4 CPU ARCHITECTURE
4.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination address
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User’s Manual (U11047E)).
4.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) to branch. The displacement
value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,
the range of branch in relative addressing is between –128 and +127 of the start address of the following
instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates that all bits are "0".
When S = 1, α indicates that all bits are "1".
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CHAPTER 4 CPU ARCHITECTURE
4.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) to branch.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low addr.
High addr.
15
8 7
0
PC
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CHAPTER 4 CPU ARCHITECTURE
4.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the immediate data
of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be
used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.
[Illustration]
7
0
6
1
5
1
0
0
Instruction code
Effective address
ta4–0
15
0
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
7
Memory (Table)
Low addr.
0
High addr.
Effective address + 1
15
8
7
0
PC
4.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) to branch.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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CHAPTER 4 CPU ARCHITECTURE
4.4 Operand Address Addressing
The following methods (addressing) are available to specify the register and memory to undergo manipulation
during instruction execution.
4.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP Code
00H
FEH
[Illustration]
7
0
OP code
addr16 (low)
addr16 (high)
Memory
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CHAPTER 4 CPU ARCHITECTURE
4.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to
FF1FH.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,
and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
8
0
Effective
address
1
1
1
1
1
1
1
α
α
When 8-bit immediate data is 20H to FFH, = 0.
α
When 8-bit immediate data is 00H to 1FH, = 1.
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CHAPTER 4 CPU ARCHITECTURE
4.4.3 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction
word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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CHAPTER 4 CPU ARCHITECTURE
4.4.4 Register addressing
[Function]
A general-purpose register is accessed as an operand.
The general-purpose register to be accessed is specified with the register specify code and functional name in
the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specify code
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CHAPTER 4 CPU ARCHITECTURE
4.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address specified
by register pair DE
The contents of addressed
memory are transferred
7
0
A
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CHAPTER 4 CPU ARCHITECTURE
4.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
4.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon interrupt request generation.
Stack addressing can be used to access the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
5.1 Memory Space
Besides internal high-speed RAM, the µPD78E9860A and 78E9861A have 32 × 8 bits of electrically erasable
PROM (EEPROM) on-chip as data memory.
Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. In addition, unlike
EPROM, its electrical contents can be erased without using ultraviolet rays.
5.2 EEPROM Configuration
EEPROM consists of the EEPROM itself and a control section.
The control section consists of EEPROM write control register 10 (EEWC10) which controls EEPROM writing and
a part that detects the termination of writing and generates an interrupt request signal (INTEE0).
Figure 5-1. EEPROM Block Diagram
Internal bus
EEPROM write control register 10 (EEWC10)
EWCS102
EWST10
EWE10
EWCS101 EWCS100
ERE10
Data latch
f
X
/25 to f
CC/25 (µPD78E9861A)
X
/27 (µPD78E9860A)
EEPROM timer
Prescaler
f
EEPROM
8-bit timer 40 output
Address
latch
(32 × 8 bits)
Read/write
controller
INTEE0
5.3 EEPROM Control Register
EEPROM is controlled by EEPROM write control register 10 (EEWC10).
EEWC10 is the register that sets the EEPROM count clock selection, and EEPROM write control.
EEWC10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 08H.
Figure 5-2 shows the format of EEPROM write control register 10. Tables 5-1 and 5-2 show EEPROM write times.
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CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
Figure 5-2. Format of EEPROM Write Control Register 10
Symbol
7
0
6
5
4
3
1
<2>
<1>
<0>
Address After reset
FFD8H 08H
R/W
EEWC10
EWCS102 EWCS101 EWCS100
ERE10 EWST10 EWE10
R/WNote 1
EWCS102 EWCS101 EWCS100
EEPROM timer count clock selection
(Setting enabled only when fCC or fX < 1.41 MHz)
(Setting enabled only when 1.41 ≤ fX ≤ 2.81 MHz)
(Setting enabled only when fX > 2.81 MHz)
0
0
1
1
1
1
0
1
0
1
0
0
fX/25 or fCC/25
fX/26
fX/27
Output of 8-bit timer 40Note 2
(Setting enabled only when 8-bit timer 40 is
operating in discrete mode)
Other than above
Setting prohibited
ERE10
EWE10
Write
Read
Remarks
0
0
1
1
0
1
0
1
Disabled Disabled EEPROM is in standby state (low power consumption mode)
Setting prohibited
Disabled Enabled
Enabled Enabled
EWST10
EEPROM write status flag
0
1
Not writing to EEPROM (EEPROM can be read or written. However, writing is disabled if EWE10 = 0.)
Writing to EEPROM (EEPROM cannot be read or written.)
Notes 1. Bit 1 is read only.
2. Even if timer 40 output is disabled (TOE40 = 0), the timer output signal is internally supplied to
EEPROM.
Caution Be sure to set bit 3 to 1 and bit 7 to 0.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
Table 5-1. EEPROM Write Time (When Operating at fX = 5.0 MHz)
EWCS102
EWCS101
EWCS100
EEPROM Timer Count Clock
fX/27 (39.1 kHz)
EEPROM Data Write TimeNote 1
27/fX × 145 (3.71 ms)
Output of 8-bit timer 40 × 145
1
1
0
0
0
1
Output of 8-bit timer 40Note 2
Other than above
Setting prohibited
Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms.
2. Even if timer 40 output is disabled (TOE40 = 0), the timer output signal is internally supplied to
EEPROM.
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 5-2. EEPROM Write Time (When Operating at fCC = 1.0 MHz)
EWCS102
EWCS101
EWCS100
EEPROM Timer Count Clock
fCC/25 (31.3 kHz)
EEPROM Data Write TimeNote 1
25/fCC × 145 (4.64 ms)
Output of 8-bit timer 40 × 145
0
1
1
0
0
1
Output of 8-bit timer 40Note 2
Other than above
Setting prohibited
Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms.
2. Even if timer 40 output is disabled (TOE40 = 0), the timer output signal is internally supplied to
EEPROM.
Remark fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
5.4 Notes for EEPROM Writing
The following caution points pertain to writing to EEPROM.
(1) When fetching an instruction from EEPROM or stopping the system clock oscillator, be sure to do so after
setting EEPROM to write-disabled (EWE10 = 0).
(2) Set the count clock in a state in which the selected clock is operating (oscillating). If the selected count clock
is stopped, there is no transition to the state in which writing is possible even if the clock operation is
subsequently started and EEPROM is set to write-enabled (EWE10 = 1).
(3) Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms.
(4) When setting ERE10 and EWE10, be sure to use the following procedure. If you set these using other than
the following procedure, there is no transition to the state in which writing to EEPROM is possible.
<1> Set ERE10 to 1 (In a state in which EWE10 = 0)
<2> Set EWE10 to 1 (In a state in which ERE10 = 1)
<3> Wait 1 ms or more using software
<4> Shift to state in which writing to EEPROM is possible
ERE10
A
EWE10
1 ms or more
D
C
B
A (ERE10 = 1): Transition to state in which reading is possible
B (EWE10 = 1): Set count clock before this point.
C:
D:
Transition to state in which writing is possible
When ERE10 is cleared (ERE10 = 0), EWE10 is also cleared (EWE10 = 0).
Reading or writing is not possible in this state.
(5) When performing a write to EEPROM, execute it after confirming that EWST10 = 0.
If a write is executed to EEPROM when EWST10 = 1, the instruction is ignored.
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CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A ONLY)
(6) Do not execute the following operations while writing to EEPROM, as execution will cause the EEPROM cell
value at that address to become undefined.
•
•
•
•
•
Turn off the power
Execute a reset
Set ERE10 to 0
Set EWE10 to 0
Switch the EEPROM timer count clock
(7) Do not execute the following operation while writing to EEPROM after selecting system clock division for the
EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become
undefined.
•
Execute a STOP instruction
(8) Do not execute the following operations while writing to EEPROM after selecting 8-bit timer 40 (TM40) output
for the EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become
undefined.
•
•
•
Execute a STOP instruction
Set 8-bit timer 40 operation mode to other than “discrete mode”
Stop 8-bit timer 40 operation
(9) Do not execute the following operations while writing to or reading from EEPROM, as execution will cause the
EEPROM data read next to become undefined, and a CPU inadvertent program loop could result.
•
•
Set ERE10 to 0
Execute a write to EEPROM
(10) When not writing to or reading from EEPROM, it is possible to enter low-power consumption mode by setting
ERE10 to 0. In the ERE10 = 1 state, a current of about 0.27 mA (VDD = 3.6 V) is always flowing. If an
instruction to read from EEPROM is then executed, a further 0.9 mA current will flow, increasing the total
current flow at this time to approximately 1.17 mA (VDD = 3.6 V).
In the ERE10 = 1, EWE10 = 1 state, a current of about 0.3 mA (VDD = 3.6 V) is always flowing. If an instruction
to write to EEPROM is then executed, a further 0.7 mA current will flow, and if an instruction to read from
EEPROM is executed, a further 0.9 mA current will flow, increasing the total current flow at this time to
approximately 1.0 mA (VDD = 3.6 V) for the former case and 1.2 mA (VDD = 3.6 V) for the latter.
(11) Execution of a STOP instruction causes an automatic change to low-power consumption mode, regardless of
the ERE10 and EWE10 settings. The states of ERE10 and EWE10 at the time are maintained. During the
wait time following STOP mode release, a current of approximately 300 µA (VDD = 3.6 V) flows.
Executing a HALT instruction does not change the mode to low-power consumption mode.
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CHAPTER 6 PORT FUNCTIONS
6.1 Port Functions
The µPD789052, 789062 Subseries is provided with the ports shown in Table 6-1. These ports enable several
types of control.
These ports, while originally designed as digital input/output ports, have alternate functions. For the alternate
functions, refer to CHAPTER 3 PIN FUNCTIONS.
Table 6-1. Port Functions
Name
Pin Name
P00 to P07
Function
Port 0
Port 2
Port 4
I/O port. Input/output can be specified in 1-bit units.
I/O port. Input/output can be specified in 1-bit units.
P20, P21
P40 to P43
Input-only port. Mask ROM versions can specify an on-chip pull-up resistor
by means of the mask option.
6.2 Port Configuration
Ports include the following hardware.
Table 6-2. Configuration of Port
Item
Configuration
Control registers
Ports
Port mode registers (PMm: m = 0, 2)
Total: 14 (CMOS I/O: 10, CMOS input: 4)
Mask ROM version: 4 (mask option control only)
Pull-up resistors
EEPROM version:
None
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CHAPTER 6 PORT FUNCTIONS
6.2.1 Port 0
This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port
mode register 0 (PM0).
RESET input sets port 0 to input mode.
Figure 6-1 shows a block diagram of port 0.
Figure 6-1. Block Diagram of P00 to P07
RD
WRPORT
Output latch
(P00 to P07)
P00 to P07
WRPM
PM00 to PM07
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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CHAPTER 6 PORT FUNCTIONS
6.2.2 Port 2
This is a 2-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port
mode register 2 (PM2).
RESET input sets port 2 to input mode.
Figures 6-2 and 6-3 show block diagrams of port 2.
Figure 6-2. Block Diagram of P20
RD
WRPORT
Output latch
P20/TMO
/BSFO
(P20)
WRPM
PM20
Alternate
function
Alternate
function
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 6 PORT FUNCTIONS
Figure 6-3. Block Diagram of P21
Alternate
function
RD
WRPORT
Output latch
(P21)
P21/TMI
WRPM
PM21
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
6.2.3 Port 4
This is a 4-bit input-only port. Mask ROM versions can specify an on-chip pull-up resistor by means of the mask
option.
The port is also used as key return input.
RESET input sets port 4 to input mode.
Figure 6-4 shows a block diagram of port 4.
Figure 6-4. Block Diagram of P40 to P43
VDD
Alternate
function
Mask option resistor
(mask ROM versions only.
EEPROM versions
have no pull-up resistor.)
RD
P40/KR10 to P43/KR13
RD: Port 4 read signal
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CHAPTER 6 PORT FUNCTIONS
6.3 Port Function Control Registers
The following registers are used to control the ports.
• Port mode registers (PM0, PM2)
(1) Port mode registers (PM0, PM2)
The port mode registers separately set each port bit to either input or output.
Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the port mode registers to FFH.
When port pins are used for alternate functions, the corresponding port mode register and output latch must
be set or reset as described in Table 6-3.
Figure 6-5. Format of Port Mode Register
Symbol
PM0
7
6
5
4
3
2
1
0
Address
FF20H
After reset
FFH
R/W
R/W
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
PM2
1
1
1
1
1
1
PM21
PM20
FF22H
FFH
R/W
Pmn pin input/output mode selection
(m = 0, 2, n = 0 to 7)
PMmn
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Table 6-3. Port Mode Register and Output Latch Settings for Using Alternate Functions
PM××
P××
Pin Name
Alternate Function
Input/Output
Name
P20
TMO
BSFO
TMI
Output
Output
Input
0
0
1
0
0
×
P21
Remark ×:
PM××: Port mode register
P××: Port output latch
don’t care
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CHAPTER 6 PORT FUNCTIONS
6.4 Operation of Port Functions
The operation of a port differs depending on whether the port is set to input or output mode, as described below.
6.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
The data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the
contents of the output latch of the pin that is set to input mode and not subject to
manipulation become undefined.
6.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch
are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
6.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the
contents of the output latch of the pin that is set to input mode and not subject to
manipulation become undefined.
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following type of system clock oscillator is used.
• System clock (crystal/ceramic) oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction.
7.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 7-1. Configuration of Clock Generator
Item
Control register
Oscillator
Configuration
Processor clock control register (PCC)
Crystal/ceramic oscillator
Figure 7-1. Block Diagram of Clock Generator
Prescaler
Clock to peripheral
hardware
X1
X2
System clock
oscillator
Prescaler
f
X
f
X
22
Standby
controller
Wait
controller
STOP
CPU clock (fCPU
)
PCC0
Processor clock control
register (PCC)
Internal bus
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.3 Clock Generator Control Register
The clock generator is controlled by the following register:
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC selects the CPU clock and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 7-2. Format of Processor Clock Control Register
Symbol
PCC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFFBH
After reset
02H
R/W
R/W
PCC0
PCC0
CPU clock (fCPU) selection
Minimum instruction execution time: 2/fCPU
At f = 5.0 MHz operation
X
0
1
0.4
1.6
µ
µ
s
s
f
X
X
f
/22
Caution Bits 0 and 2 to 7 must all be set to 0.
Remark fX: System clock oscillation frequency
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.4 System Clock Oscillators
7.4.1 System clock oscillator
The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the
X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 7-3 shows the external circuit of the system clock oscillator.
Figure 7-3. External Circuit of System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
External
clock
V
X1
SS
X1
X2
X2
Crystal
or
ceramic resonator
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in Figure 7-3 to avoid an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.4.2 Examples of incorrect resonator connection
Figure 7-4 shows an example of incorrect resonator connections.
Figure 7-4. Example of Incorrect Resonator Connection (1/2)
(a) Wiring too long
(b) Crossed signal line
PORTn
(n = 0, 2, 4)
VSS
X1
X2
VSS
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
PORTn
(n = 0, 2, 4)
V
SS
X1
X2
VSS
X1
X2
High current
A
B
C
High current
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
Figure 7-4. Example of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
VSS
X1
X2
7.4.3 Frequency divider
The frequency divider divides the system clock oscillator output (fX) and generates clocks.
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as
standby mode:
• System clock
• CPU clock
fX
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC) as follows:
(a) The slow mode (1.6 µs: at 5.0 MHz operation) of the system clock is selected when the RESET signal is
generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.
(b) Two types of minimum instruction execution time (fCPU) (0.4 µs, 1.6 µs: at 5.0 MHz operation) can be
selected by the PCC setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock for the peripheral hardware is generated by dividing the frequency of the system clock. Therefore,
the peripheral hardware stops when the system clock stops (except for an external input clock).
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CHAPTER 7 CLOCK GENERATOR (µPD789052 SUBSERIES)
7.6 Changing Setting of CPU Clock
7.6.1 Time required for switching CPU clock
The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 7-2).
Table 7-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
PCC0
Set Value After Switching
PCC0 PCC0
0
1
0
1
4 clocks
2 clocks
Remark Two clocks are the minimum instruction execution time of the CPU clock before switching.
7.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 7-5. Switching Between System Clock and CPU Clock
VDD
RESET
CPU Clock
Slow
Fast operation
operation
Wait (6.55 ms: @5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the oscillation
stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the system clock (1.6 µs: @
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high
speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation
can be selected.
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following type of system clock oscillator is used.
• System clock (RC) oscillator
This circuit oscillates at 1.0 MHz 15%. Oscillation can be stopped by executing the STOP instruction.
8.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 8-1. Configuration of Clock Generator
Item
Control register
Oscillator
Configuration
Processor clock control register (PCC)
RC oscillator
Figure 8-1. Block Diagram of Clock Generator
Prescaler
Clock to peripheral
hardware
CL1
CL2
System clock
oscillator
Prescaler
f
CC
f
CC
22
Standby
controller
Wait
controller
STOP
CPU clock (fCPU
)
PCC0
Processor clock control
register (PCC)
Internal bus
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.3 Clock Generator Control Register
The clock generator is controlled by the following register:
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC selects the CPU clock and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 8-2. Format of Processor Clock Control Register
Symbol
PCC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFFBH
After reset
02H
R/W
R/W
PCC0
PCC0
CPU clock (fCPU) selection
Minimum instruction execution time: 2/fCPU
At fCC = 1.0 MHz operation
s
f
CC
2.0
8.0
µ
µ
0
1
f
CC/22
s
Caution Bits 0 and 2 to 7 must all be set to 0.
Remark fCC: System clock oscillation frequency
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.4 System Clock Oscillators
8.4.1 System clock oscillator
The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (1.0 MHz TYP.) connected across
the CL1 and CL2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the
inverted signal to the CL2 pin.
Figure 8-3 shows the external circuit of the system clock oscillator.
Figure 8-3. External Circuit of System Clock Oscillator
(a) RC oscillation
(b) External clock
External
clock
CL1
CL1
C
R
CL2
CL2
V
SS
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in Figure 8-3 to avoid an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.4.2 Examples of incorrect resonator connection
Figure 8-4 shows an example of incorrect resonator connections.
Figure 8-4. Example of Incorrect Resonator Connection (1/2)
(a) Wiring too long
(b) Crossed signal line
PORTn
(n = 0, 2, 4)
CL1
CL2
V
SS
CL1
CL2
V
SS
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
PORTn
(n = 0, 2, 4)
CL1
CL2
V
SS
CL1
CL2
VSS
High current
A
B
High current
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
Figure 8-4. Example of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
CL1
CL2
V
SS
8.4.3 Frequency divider
The frequency divider divides the system clock oscillator output (fCC) and generates clocks.
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as
standby mode:
• System clock
• CPU clock
fCC
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC) as follows:
(a) The slow mode (8.0 µs: at 1.0 MHz operation) of the system clock is selected when the RESET signal is
generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.
(b) Two types of minimum instruction execution time (fCPU) (2.0 µs, 8.0 µs: at 1.0 MHz operation) can be
selected by the PCC setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock for the peripheral hardware is generated by dividing the frequency of the system clock. Therefore,
the peripheral hardware stops when the system clock stops (except for an external input clock).
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CHAPTER 8 CLOCK GENERATOR (µPD789062 SUBSERIES)
8.6 Changing Setting of CPU Clock
8.6.1 Time required for switching CPU clock
The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 8-2).
Table 8-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
PCC0
Set Value After Switching
PCC0 PCC0
0
1
0
1
4 clocks
2 clocks
Remark Two clocks are the minimum instruction execution time of the CPU clock before switching.
8.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 8-5. Switching Between System Clock and CPU Clock
VDD
RESET
CPU Clock
Slow
Fast operation
operation
Wait (128
µ
s: @1.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the oscillation
stabilization time (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the system clock (8.0 µs: @
1.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high
speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation
can be selected.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.1 8-Bit Timers 30 and 40 Functions
The µPD789052, 789062 Subseries have on chip an 8-bit timer (timer 30) (1 channel) and an 8-bit timer/event
counter (timer 40) (1 channel). The operation modes shown in the table below are possible by means of mode
register settings.
Table 9-1. Mode List
Channel
Timer 30
Timer 40
Mode
√
√
8-bit timer counter mode
(discrete mode)
√
√
16-bit timer counter mode
(cascade connection mode)
Carrier generator mode
PWM output mode
×
√
(1) 8-bit timer counter mode (discrete mode)
The following functions can be used.
•
•
•
8-bit resolution interval timer
8-bit resolution external event counter (timer 40 only)
8-bit resolution square wave output (timer 40 only)
(2) 16-bit timer counter mode (cascade connection mode)
Operates as a 16-bit timer/event counter due to cascade connection.
The following functions can be used.
•
•
•
16-bit resolution interval timer
16-bit resolution external event counter
16-bit resolution square wave output
(3) Carrier generator mode
In this mode, the carrier clock generated by timer 40 is output in the cycle set by timer 30.
(4) PWM output mode (timer 40 only)
Outputs a pulse of an arbitrary duty factor set by timer 40.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.2 8-Bit Timers 30 and 40 Configuration
The 8-bit timer includes the following hardware.
Table 9-2. Configuration of 8-Bit Timers 30 and 40
Item
Timer counter
Registers
Configuration
8 bits × 2 (TM30, TM40)
Compare registers: 8 bits × 3 (CR30, CR40, CRH40)
Timer output
Control registers
1 (TMO)
8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 2 (PM2)
Port 2 (P2)
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Figure 9-1. Timer 30 Block Diagram
Internal bus
8-bit timer mode control
register 30 (TMC30)
TCL301 TCL300
TCE30 TCL302
TMD301 TMD300
8-bit compare
register 30 (CR30)
Decoder
Selector
Match
(A)
Bit 7 of TM40
(From Figure 9-2 (A))
OVF
8-bit timer
counter 30 (TM30)
f
f
CLK/26
CLK/28
Clear
Timer 40 interrupt request signal
(From Figure 9-2 (B))
(B)
(C)
Carrier clock
(From Figure 9-2 (C))
Internal reset signal
(D)
From Figure 9-2 (D)
Selector
Count operation start signal
(in cascade connection mode)
Cascade connection mode
INTTM30
(G)
(E)
To Figure 9-2 (G)
Timer 30 match signal
From Figure 9-2 (E)
Timer 40 match signal
(in cascade connection mode)
(in carrier generator mode)
(F)
To Figure 9-2 (F)
Timer 30 match signal
(in cascade connection mode)
Remark fCLK: fX or fCC
Figure 9-2. Timer 40 Block Diagram
Internal bus
Carrier generator output
control register 40
(TCA40)
8-bit timer mode control
register 40 (TMC40)
8-bit compare
8-bit compare
register H40
register 40 (CR40)
(CRH40)
RMC40 NRZB40 NRZ40
TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
Decoder
From Figure 9-1 (G)
Timer counter match
signal from timer 30
Selector
(G)
(in carrier generator mode)
Output controllerNote
F/F
TMO/P20/BSFO
Match
To Figure 9-1 (C)
Carrier clock
f
CLK
8-bit timer counter 40
(TM40)
(C)
f
CLK/22
OVF
Clear
TMI/P21
Output to
EEPROM (data memory)
Carrier generator mode
TMI/2
TMI/22
TMI/23
PWM mode
To Figure 9-1 (A)
Bit 7 of TM40
(in cascade connection mode)
Reset
(A)
Cascade connection mode
Internal reset signal
INTTM40
(D)
To Figure 9-1 (D)
Count operation start
signal to timer 30
To Figure 9-1 (B)
Timer 40 interrupt request signal
count clock input
signal to TM30
(E)
To Figure 9-1 (E)
TM40 timer counter match signal
(in cascade connection mode)
(B)
(in cascade connection mode)
(F)
From Figure 9-1 (F)
TM30 match signal
(in cascade connection mode)
Note
For details, refer to Figure 9-3.
Remark fCLK: fX or fCC
CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-3. Block Diagram of Output Controller (Timer 40)
RMC40
TOE40
NRZ40
P20
output latch
PM20
TMO/P20/
BSFO
F/F
Carrier clock
Carrier generator mode
(1) 8-bit compare register 30 (CR30)
This register is an 8-bit register that always compares the count value of 8-bit timer counter 30 (TM30) with
the value set in CR30 and generates an interrupt request (INTTM30) if they match.
CR30 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution CR30 cannot be used in PWM output mode.
(2) 8-bit compare register 40 (CR40)
This register is an 8-bit register that always compares the count value of 8-bit timer counter 40 (TM40) with
the value set in CR40 and generates an interrupt request (INTTM40) if they match. In addition, when
cascade-connected to TM30 and used as a 16-bit timer/event counter, an interrupt request (INTTM40) is
generated only if TM30 matches with CR30 and TM40 matches with CR40 simultaneously (INTTM30 is not
generated).
In carrier generator mode or PWM output mode, set the low-level width of the timer output.
CR40 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) 8-bit compare register H40 (CRH40)
In carrier generator mode or PWM output mode, writing a CRH40 value sets the width of high level timer
output.
The value set in CRH40 is constantly compared with the TM40 count value, and an interrupt request
(INTTM40) is generated if they match.
CRH40 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(4) 8-bit timer counters 30 and 40 (TM30, TM40)
These 8-bit registers count pulse counts.
Each of TM30 and TM40 is read with an 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
The conditions under which TM30 and TM40 are cleared to 00H are shown next.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(a) Discrete mode
(i) TM30
•
•
•
•
Reset
Clearing of TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) to 0
Match of TM30 and CR30
TM30 count value overflow
(ii) TM40
•
•
•
•
Reset
Clearing of TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) to 0
Match of TM40 and CR40
TM40 count value overflow
(b) Cascade connection mode (TM30, TM40 simultaneously cleared to 00H)
•
•
•
•
Reset
Clearing of the TCE40 flag to 0
Simultaneous match of TM30 with CR30 and TM40 with CR40
TM30 and TM40 count values overflow simultaneously
(c) Carrier generator/PWM output mode (TM40 only)
•
•
•
•
•
Reset
Clearing of the TCE40 flag to 0
Match of TM40 and CR40
Match of TM40 and CRH40
TM40 count value overflow
9.3 8-Bit Timers 30 and 40 Control Registers
The 8-bit timer is controlled by the following five registers.
•
•
•
•
•
8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 2 (PM2)
Port 2 (P2)
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(1) 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 30 (TMC30) is the register that controls the setting of the timer 30 count
clock and the setting of the operating mode.
TMC30 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 9-4. Format of 8-Bit Timer Mode Control Register 30
Symbol
TMC30
<7>
6
0
5
4
3
2
1
0
0
Address After reset
FF52H 00H
R/W
R/W
TCE30
TCL302 TCL301 TCL300 TMD301 TMD300
TCE30
TM30 count operation controlNote 1
0
1
Clears TM30 count value and halt operation
Starts count operation
Selection of timer 30 count clock
When operating at fX = 5.0 MHz When operating at fCC = 1.0 MHz
fX/26 (78.1 kHz) fCC/26 (15.6 kHz)
TCL302 TCL301 TCL300
0
0
0
0
0
0
1
1
0
1
0
1
fX/28 (19.5 kHz)
fCC/28 (3.91 kHz)
Timer 40 match signal
Carrier clock generated by timer 40
Setting prohibited
Other than above
TMD301 TMD300 TMD401 TMD400
Selection of timer 30, timer 40 operating modeNote 2
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
0
Discrete mode
Cascade connection mode
Carrier generator mode
PWM output mode
Other than above
Setting prohibited
Notes 1. In cascade connection mode, since count operations are controlled by TCE40 (bit 7 of TMC40),
TCE30 is ignored even if it is set.
2. The selection of operating mode is made by combining the two registers TMC30 and TMC40.
Cautions 1. Be sure to set bits 0 and 6 to 0.
2. In cascade connection mode, timer 40 output signal is forcibly selected for count clock.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
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(2) 8-bit timer mode control register 40 (TMC40)
8-bit timer mode control register 40 (TMC40) is the register that controls the setting of the timer 40 count
clock and the setting of the operating mode.
TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 9-5. Format of 8-Bit Timer Mode Control Register 40
Symbol
TMC40
<7>
6
0
5
4
3
2
1
<0>
Address After reset
FF56H 00H
R/W
R/W
TCE40
TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
TCE40
0
TM40 count operation controlNote 1
Clears TM40 count value and halt operation (in cascade connection mode, the TM30 count value is
simultaneously cleared as well.)
1
Starts count operation (in cascade connection mode, the TM30 count operation is simultaneously started as
well.)
Selection of timer 40 count clock
TCL402 TCL401 TCL400
When operating at fX = 5.0 MHz
When operating at fCC = 1.0 MHz
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fX (5.0 MHz)
fCC (1.0 MHz)
fX/22 (1.25 MHz)
fTMI
fCC/22 (250 kHz)
fTMI/2
fTMI/22
fTMI/23
TMD301 TMD300 TMD401 TMD400
Selection of timer 30, timer 40 operating modeNote 2
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
0
Discrete mode
Cascade connection mode
Carrier generator mode
PWM output mode
Other than above
Setting prohibited
TOE40
Timer output control
0
1
Output disabled
Output enabled (port mode)
Notes 1. In cascade connection mode, since count operations are controlled by TCE40, TCE30 (bit 7 of
TMC30) is ignored even if it is set.
2. The selection of operating mode is made by combining the two registers TMC30 and TMC40.
Caution Be sure to clear bit 6 to 0.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
3. fTMI: External clock input from TMI/P21 pin
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data in the carrier generator mode.
TCA40 is set with an 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 9-6. Format of Carrier Generator Output Control Register 40
Symbol
TCA40
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After reset
FF57H 00H
R/W
W
RMC40 NRZB40 NRZ40
RMC40
Remote controller output control
0
1
When NRZ40 = 1, a carrier pulse is output to the TMO/P20/BSFO pin
When NRZ40 = 1, a high level is output to the TMO/P20/BSFO pin
NRZB40 This bit stores the data that NRZ40 will output next. Data is transferred to NRZ40 at the rising edge of the
timer 30 match signal. Input the necessary value in NRZB40 in advance by program.
NRZ40
No return, zero data
A low level is output (the carrier clock is stopped)
A carrier pulse or high level is output
0
1
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-
bit memory manipulation instruction to set TCA40.
3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 =
0). The data cannot be overwritten when TOE40 = 1.
4. When the carrier generator is stopped once and then started again, NRZB40 does not
hold the previous data. Re-set data to NRZB40. At this time, a 1-bit memory
manipulation instruction must not be used. Be sure to use an 8-bit memory
manipulation instruction.
5. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40
flags in advance. Otherwise, the signal of the timer match circuit will become unstable
and the NRZ40 flag will be undefined.
6. Note that the µPD78E9860 and 78E9861 have the following restrictions (which do not
apply to the mask ROM version and the µPD78E9860A and 78E9861A).
(a) While INTTM30 (interrupt generated by the match signal of timer 30) is being output,
accessing TCA40 is prohibited.
(b) Accessing TCA40 is prohibited while 8-bit timer/counter 30 (TM30) is 00H.
To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30
count clock and then rewrite TCA40.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(4) Port mode register 2 (PM2)
This register sets port 2 to input/output in 1-bit units.
When using the P20/TMO/BSFO pin as a timer output, set the PM20 and P20 output latch to 0.
When using the P21/TMI pin as a timer input, set the PM21 to 1.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 9-7. Format of Port Mode Register 2
Symbol
PM2
7
1
6
1
5
1
4
1
3
1
2
1
1
0
Address After reset
FF22H FFH
R/W
R/W
PM21
PM20
PM2m
P2m pin input/output mode (m = 0, 1)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.4 8-Bit Timers 30 and 40 Operation
9.4.1 Operation as 8-bit timer counter
Timer 30 and timer 40 can independently be used as an 8-bit timer counter.
The following modes can be used for the 8-bit timer counter.
•
•
•
Interval timer with 8-bit resolution
External event counter with 8-bit resolution (timer 40 only)
Square wave output with 8-bit resolution (timer 40 only)
(1) Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register n0 (CRn0).
To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0).
<2> Disable timer output of TMO (TOE40 = 0)Note
.
<3> Set a count value in CRn0.
<4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 9-4 and 9-5).
<5> Set the count clock for timer n0 (see Tables 9-3 to 9-6).
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to 0
and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated.
Tables 9-3 to 9-6 show interval time, and Figures 9-8 to 9-13 show the timing of the interval timer operation.
Note Timer 40 only
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Table 9-3. Interval Time of Timer 30 (During fX = 5.0 MHz Operation)
TCL302 TCL301 TCL300
Minimum Interval Time
26/fX (12.8 µs)
Maximum Interval Time
214/fX (3.28 ms)
Resolution
26/fX (12.8 µs)
0
0
0
0
0
1
0
1
0
28/fX (51.2 µs)
28/fX (51.2 µs)
216/fX (13.1 ms)
Input cycle of timer 40
match signal
Input cycle of timer 40
match signal × 28
Input cycle of timer 40
match signal
0
1
1
Carrier clock cycle
Carrier clock cycle
generated by timer 40× 28
Carrier clock cycle
generated by timer 40
generated by timer 40
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 9-4. Interval Time of Timer 30 (During fCC = 1.0 MHz Operation)
TCL302 TCL301 TCL300
Minimum Interval Time
26/fCC (64 µs)
Maximum Interval Time
214/fCC (16.4 ms)
Resolution
26/fCC (64 µs)
0
0
0
0
0
1
0
1
0
28/fCC (256 µs)
28/fCC (256 µs)
216/fCC (65.5 ms)
Input cycle of timer 40
match signal
Input cycle of timer 40
match signal × 28
Input cycle of timer 40
match signal
0
1
1
Carrier clock cycle
Carrier clock cycle
generated by timer 40× 28
Carrier clock cycle
generated by timer 40
generated by timer 40
Remark fCC: System clock oscillation frequency (RC oscillation)
Table 9-5. Interval Time of Timer 40 (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fX (0.2 µs)
Maximum Interval Time
28/fX (51.2 µs)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
210/fX (204.8 µs)
22/fX (0.8 µs)
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 9-6. Interval Time of Timer 40 (During fCC = 1.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fCC (1.0 µs)
Maximum Interval Time
28/fCC (256 µs)
Resolution
1/fCC (1.0 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (4.0 µs)
210/fCC (1024 µs)
22/fCC (4.0 µs)
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remark fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
t
TMn0
count clock
N
00H 01H
Clear
00H
01H
00H 01H
Clear
00H 01H
Clear
00H
N
N
TMn0
N
CRn0
TCEn0
Count start
Count stop
INTTMn0
TMONote
Interrupt acknowledgement
Interval time
Interrupt acknowledgement
Interval time
Interrupt acknowledgement
Note Timer 40 only
Remarks 1. Interval time: (N + 1) × t: N = 00H to FFH
2. n = 3, 4
Figure 9-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H)
TMn0
count clock
00H
00H
TMn0
CRn0
TCEn0
Count start
INTTMn0
TMONote
Note Timer 40 only
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
TMn0
count clock
00H
00H
01H
00H 01H
Clear
00H 01H
Clear
FFH
00H
FFH
FFH
TMn0
FFH
Clear
FFH
CRn0
TCEn0
Count start
INTTMn0
TMONote
Note Timer 40 only
Remark n = 3, 4
Figure 9-11. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N < M))
TMn0
count clock
00H
N
N
M
00H
M
00H
Clear
01H
01H
00H
TMn0
N
Clear
Clear
N
CRn0
M
TCEn0
Count start
INTTMn0
TMONote
Interrupt acknowledgement
CRn0 overwritten
Interrupt acknowledgement
Note Timer 40 only
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-12. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N > M))
TMn0
count clock
N − 1
M
N
FFH
00H
M
M
00H
N
00H
00H
TMn0
Clear
Clear
Clear
N
CRn0
M
H
TCEn0
TMn0 overflows
because M < N
INTTMn0
TMONote
CRn0 overwritten
Note Timer 40 only
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-13. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
Timer 40
count clock
M
M
M
00H
00H
01H
N
00H
00H
00H
M
TM40
Clear
Clear
Clear
Clear
N
CR40
TCE40
Count start
INTTM40
Input clock to timer 30
(timer 40 match signal)
Y
00H
00H
00H
01H
Y - 1
Y
TM30
CR30
Y
TCE30
INTTM30
TMO
Count start
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(2) Operation as external event counter with 8-bit resolution (timer 40 only)
The external event counter counts the number of external clock pulses input to the TMI/P21 pin by using 8-
bit timer counter 40 (TM40).
To operate timer 40 as an external event counter, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0).
<2> Disable timer output of TMO (TOE40 = 0).
<3> Set P21 to input mode (PM21 = 1).
<4> Select the external input clock for timer 40 (see Tables 9-5 and 9-6).
<5> Set the operation mode of timer 40 to 8-bit timer counter mode (see Figures 9-4 and 9-5).
<6> Set a count value in CR40.
<7> Enable the operation of TM40 (TCE40 = 1).
Each time the valid edge is input, the value of TM40 is incremented.
When the count value of TM40 matches the value set in CR40, TM40 is cleared to 00H and continues
counting. At the same time, an interrupt request signal (INTTM40) is generated.
Figure 9-14 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Figure 9-14. Timing of Operation of External Event Counter with 8-Bit Resolution
TMI pin input
TM40 count value
CR40
00H 01H 02H 03H 04H 05H
N - 1
N
00H 01H 02H 03H
N
TCE40
INTTM40
Remark N = 00H to FFH
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(3) Operation as square-wave output wit 8-bit resolution (timer 40 only)
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register 40 (CR40).
To operate timer 40 for square-wave output, settings must be made in the following sequence.
<1> Set P20 to output mode (PM20 = 0).
<2> Set the output latches of P20 to 0.
<3> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0).
<4> Set a count clock for timer 40 and enable output of TMO (TOE40 = 1).
<5> Set a count value in CR40.
<6> Enable the operation of TM40 (TCE40 = 1).
When the count value of TM40 matches the value set in CR40, the TMO pin output will be inverted. Through
application of this mechanism, square waves of any frequency can be output. As soon as a match occurs,
TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is
generated.
The square-wave output is cleared to 0 by setting TCE40 to 0.
Tables 9-7 and 9-8 show the square-wave output range, and Figure 9-15 shows the timing of square-wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 9-7. Square-Wave Output Range of Timer 40 (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Pulse Width
28/fX (51.2 µs)
210/fX (204.8 µs)
Resolution
1/fX (0.2 µs)
22/fX (0.8 µs)
0
0
0
0
0
1
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 9-8. Square-Wave Output Range of Timer 40 (During fCC = 1.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fCC (1.0 µs)
22/fCC (4.0 µs)
Maximum Pulse Width
Resolution
1/fCC (1.0 µs)
22/fCC (4.0 µs)
28/fCC (256 µs)
210/fCC (1024 µs)
0
0
0
0
0
1
Remark fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-15. Timing of Square-Wave Output with 8-Bit Resolution
t
TM40
count clock
N
00H 01H
Clear
01H
00H 01H
Clear
00H 01H
Clear
00H
N
N
TM40
N
CR40
TCE40
Count start
INTTM40
TMONote
Interrupt acknowledgement
Interrupt acknowledgement
Interrupt acknowledgement
Square-wave output cycle
Note The initial value of TMO is low level when output is enabled (TOE40 = 1).
Remark Square-wave output cycle = 2 (N+1) × t
N = 00H to FFH
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.4.2 Operation as 16-bit timer counter
Timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer
counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls
reset and clear.
The following modes can be used for the 16-bit timer counter.
•
•
•
Interval timer with 16-bit resolution
External event counter with 16-bit resolution
Square wave output with 16-bit resolution
(1) Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0,
TCE40 = 0).
<2> Disable timer output of TMO (TOE40 = 0)Note 1
.
<3> Set the count clock for timer 40 (see Tables 9-9 and 9-10).
<4> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 9-4 and 9-
5).
<5> Set a count value in CR30 and CR40.
<6> Enable the operation of TM30 and TM40 (TCE40 = 1Note 2).
Notes 1. Timer 40 only
2. Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value
of TCE30 is invalid).
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30
and TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request
signal (INTTM40) is generated (INTTM30 is not generated).
Tables 9-9 and 9-10 show interval time, and Figure 9-16 shows the timing of the interval timer operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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Table 9-9. Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fX (0.2 µs)
Maximum Interval Time
216/fX (13.1 ms)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
22/fX (0.8 µs)
218/fX (52.4 ms)
fTMI input cycle × 216
fTMI/2 input cycle × 216
fTMI/22 input cycle × 216
fTMI/23 input cycle × 216
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 9-10. Interval Time with 16-Bit Resolution (During fCC = 1.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fCC (1.0 µs)
Maximum Interval Time
216/fCC (65.5 ms)
Resolution
1/fCC (1.0 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (4.0 µs)
22/fCC (4.0 µs)
218/fCC (262.1 ms)
fTMI input cycle × 216
fTMI/2 input cycle × 216
fTMI/22 input cycle × 216
fTMI/23 input cycle × 216
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remark fCC: System clock oscillation frequency (RC oscillation)
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Figure 9-16. Timing of Interval Timer Operation with 16-Bit Resolution
t
TM40
count clock
TM40 count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM30 does not match
Cleared because TM30 and TM40 match simultaneously
CR40
N
N
N
N
N
N
N
N
TCE40
Count start
TM30 count clock
TM30
count value
X
X-1
00H
X
00H
X
01H
00H
X-1
X
CR30
X
INTTM40
TMO
Interrupt acknowledgement
Interrupt acknowledgement
Interrupt not generated because
TM30 does not match
Interval time
Remark Interval time: (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
CHAPTER 9 8-BIT TIMERS 30 AND 40
(2) Operation as external event counter with 16-bit resolution
The external event counter counts the number of external clock pulses input to the TMI/P21 pin by TM30 and
TM40.
To operate as an external event counter with 16-bit resolution, settings must be made in the following
sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TMO (TOE40 = 0)Note 1
.
<3> Set P21 to input mode (PM21 = 1).
<4> Select the external input clock for timer 40 (see Tables 9-9 and 9-10).
<5> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 9-4 and 9-
5).
<6> Set a count value in CR30 and CR40.
<7> Enable the operation of TM30 and TM40 (TCE40 = 1Note 2).
Notes 1. Timer 40 only
2. Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value
of TCE30 is invalid).
Each time the valid edge is input, the values of TM30 and TM40 are incremented.
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30
and TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request
signal (INTTM40) is generated (INTTM30 is not generated).
Figure 9-17 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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Figure 9-17. Timing of External Event Counter Operation with 16-Bit Resolution
TMI pin input
TM40
count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM30 does not match
Cleared because TM30 and TM40 match simultaneously
CR40
N
N
N
N
N
N
N
N
TCE40
Count start
TM30
count clock
TM30
count value
X
X-1
00H
X
00H
01H
00H
X-1
X
X
X
CR30
INTTM40
Interrupt not generated because
TM30 does not match
Interrupt acknowledgement
Interrupt
acknowledgement
Remark X = 00H to FFH, N = 00H to FFH
CHAPTER 9 8-BIT TIMERS 30 AND 40
(3) Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and
CR40.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable output of TMO (TOE40 = 0).
<3> Set a count clock for timer 40.
<4> Set P20 to output mode (PM20 = 0) and P20 output latch to 0 and enable TMO output (TOE40 = 1).
<5> Set count values in CR30 and CR40.
<6> Enable the operation of TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, the TMO pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting
continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated).
The square-wave output is cleared to 0 by setting TCE40 to 0.
Tables 9-11 and 9-12 show the square wave output range, and Figure 9-18 shows timing of square wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 9-11. Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Time
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Pulse Time
216/fX (13.1 ms)
218/fX (52.4 ms)
Resolution
1/fX (0.2 µs)
22/fX (0.8 µs)
0
0
0
0
0
1
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
Table 9-12. Square-Wave Output Range with 16-Bit Resolution (During fCC = 1.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Time
1/fCC (1.0 µs)
22/fCC (4.0 µs)
Maximum Pulse Time
216/fCC (65.5 ms)
Resolution
1/fCC (1.0 µs)
22/fCC (4.0 µs)
0
0
0
0
0
1
218/fCC (262.1 ms)
Remark fCC: System clock oscillation frequency (RC oscillation)
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Figure 9-18. Timing of Square-Wave Output with 16-Bit Resolution
TM40
count clock
TM40
count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM30 does not match
Cleared because TM30 and TM40 match simultaneously
CR40
N
N
N
N
N
N
N
N
TCE40
Count start
TM30
count clock
X
X-1
00H
X
TM30
CR30
00H
X
01H
00H
X-1
X
X
INTTM40
TMONote
Interrupt acknowledgement
Interrupt not generated because
TM30 does not match
Interrupt acknowledgement
Note The initial value of TMO is low level when output is enabled (TOE40 = 1).
Remark X = 00H to FFH, N = 00H to FFH
CHAPTER 9 8-BIT TIMERS 30 AND 40
9.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30.
To operate timer 30 and timer 40 as carrier generators, setting must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TMO (TOE40 = 0).
<3> Set count values in CR30, CR40, and CRH40.
<4> Set the operation mode of timer 40 to carrier generator mode (see Figures 9-4 and 9-5).
<5> Set the count clock for timer 30 and timer 40.
<6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40
(TCA40)) = 0).
Input the required value to NRZB40 (bit 1 of TCA40) by program.
Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40.
<7> Set P20 to output mode (PM20 = 0) and the P20 output latch to 0 and enable TMO output by setting TOE40
to 1.
<8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1).
<9> Save the value of NRZB40 to a general-purpose register.
<10> When INTTM30 rises, the value of NRZB40 is transferred to NRZ40. After that, rewrite TCA40 with an 8-bit
memory manipulation instruction. Input the value to be transferred to NRZ40 next time to NRZB40, and
input the value saved in <9> to NRZ40.
<11> Generate the desired carrier signal by repeating <9> and <10>.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
The operation of the carrier generator is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40.
<2> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is
generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40.
<5> When NRZ40 is 1, a carrier clock is output from TMO pin.
Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction to set TCA40.
2. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 = 0).
The data cannot be overwritten when TOE40 = 1.
3. When the carrier generator is stopped once and then started again, NRZB40 does not hold
the previous data. Re-set data to NRZB40. At this time, a 1-bit memory manipulation
instruction must not be used. Be sure to use an 8-bit memory manipulation instruction.
4. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in
advance. Otherwise, the signal of the timer match circuit will become unstable and the
NRZ40 flag will be undefined.
5. Note that the µPD78E9860 and 78E9861 have the following restrictions (which do not apply
to the mask ROM version and the µPD78E9860A and 78E9861A).
(a) While INTTM30 (interrupt generated by the match signal of timer 30) is being output,
accessing TCA40 is prohibited.
(b) Accessing TCA40 is prohibited while 8-bit timer/counter 30 (TM30) is 00H.
To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30 count
clock and then rewrite TCA40.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figures 9-19 to 9-21 show the operation timing of the carrier generator.
Figure 9-19. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
TM40
count clock
TM40
count value
00H
01H
N
00H
N
M
N
00H
00H
00H
N
M
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
Carrier clock
TM30
count clock
TM30
count value
X
00H
X
00H
00H
00H
X
01H
01H
01H
00H
01H
X
CR30
X
TCE30
INTTM30
0
0
1
0
NRZB40
NRZ40
1
1
0
0
1
0
Carrier clock
TMO
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-20. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
TM40
count clock
TM40
count value
00H
M
N
00H
M
00H
M
N
00H
M
00H
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
Carrier clock
TM30
count clock
TM30
count value
00H
X
X
00H
01H
01H
X
01H
00H
00H
X
00H 01H
CR30
X
TCE30
INTTM30
0
0
1
0
NRZB40
NRZ40
1
1
0
0
1
0
Carrier clock
TMO
Remark This timing chart shows an example in which the value of NRZ40 is changed while the carrier clock is
high.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-21. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
TM40
count clock
TM40
count value
00H
N
00H
N
N
N
00H
00H
00H
00H
N
N
Clear
Clear
Clear
Clear
Clear
CR40
N
N
CRH40
TCE40
Count start
INTTM40
Carrier clock
TM30
count clock
TM30
count value
00H
01H
00H
X
00H
00H
01H
X
01H
X
00H
01H
X
CR30
X
TCE30
INTTM30
0
0
1
0
NRZB40
NRZ40
1
1
0
0
1
0
Carrier clock
TMO
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.4.4 Operation as PWM output (timer 40 only)
In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a
high-level width using CRH40.
To operate timer 40 in PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM40 (TCE40 = 0).
<2> Disable timer output of TMO (TOE40 = 0).
<3> Set count values in CR40 and CRH40.
<4> Set the operation mode of timer 40 to PWM output mode (see Figure 9-5).
<5> Set the count clock for timer 40.
<6> Set P20 to output mode (PM20 = 0) and the P20 output latch to 0 and enable timer output of TMO (TOE40 =
1).
<7> Enable the operation of TM40 (TCE40 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40.
<2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again.
<3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 9-22 and 9-23 show the operation
timing in the PWM output mode.
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CHAPTER 9 8-BIT TIMERS 30 AND 40
Figure 9-22. PWM Output Mode Timing (Basic Operation)
TM40
count clock
TM40
count value
01H
M
00H
M
00H
N
01H
00H
N
01H
00H
00H
01H
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
TMONote
Note The initial value of TMO is low level when output is enabled (TOE40 = 1).
Figure 9-23. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)
TM40
count clock
TM40
count value
N
00H
N
00H
01H
Y
00H
X
M
00H
Clear
00H
X
Clear
Clear
Clear
CR40
N
X
CRH40
TCE40
M
Y
M
Count start
INTTM40
TMONote
Note The initial value of TMO is low level when output is enabled (TOE40 = 1).
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CHAPTER 9 8-BIT TIMERS 30 AND 40
9.5 Notes on Using 8-Bit Timers 30 and 40
(1) Error on starting timer
An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being
generated. This is because the rising edge is detected and the counter is incremented if the timer is started
while the count clock is high (see Figure 9-24).
Figure 9-24. Case of Error Occurrence of up to 1.5 Clocks
Delay A
Count
pulse
8-bit timer counter n0
(TMn0)
Selected clock
TCEn0
Clear signal
Delay B
Selected clock
TCEn0
Clear signal
Count pulse
TMn0 counter value
00H
01H
02H
03H
Delay A
Delay B
An error of up to 1.5 clocks occurs if the timer is started
when the selected clock is high and delay A > delay B.
Remark n = 3, 4
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CHAPTER 9 8-BIT TIMERS 30 AND 40
(2) Count value if external clock input from TMI pin is selected
When the external clock signal input from the TMI pin is selected as the count clock, the count value may
start from 01H if the timer is enabled (TCE40 = 0 → 1) while the TMI pin is high. This is because the input
signal of the TMI pin is internally ANDed with the TCE40 signal. Consequently, the counter is incremented
because the rising edge of the count clock is input to the timer immediately when the TCE40 pin is set.
Depending on the delay timing, the count value is incremented by one if the rising edge is input after the
counter is cleared. Counting is not affected if the rising edge is input before the counter is cleared (the
counter operates normally).
Use the timer being aware that it has an error of one count, or take either of the following actions A or B.
<Action A> Always start the timer when the TMI pin is low.
<Action B> Save the count value to a control register when the timer is started, SUB the count value with
the count value saved to the control register when reading the count value, and take the result
of SUB as the true count value.
Figure 9-25. Counting Operation if Timer Is Started When TMI Is High
Clear
TCE40 flag
TMI
Increment
Rising edge
detector
Counter
H
(3) Setting of 8-bit compare register n0
8-bit compare register n0 (CRn0) can be set to 00H.
Therefore, one pulse can be counted when the 8-bit timer operates as an event counter.
Figure 9-26. Timing of Operation as External Event Counter (8-Bit Resolution)
TMI input
CR40
00H
00H
00H
00H
00H
TM40
count value
Interrupt request flag
Remark n = 3, 4
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CHAPTER 10 WATCHDOG TIMER
10.1 Watchdog Timer Functions
The watchdog timer has the following functions:
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect inadvertent program loops. When the inadvertent program loop is
detected, a non-maskable interrupt or a RESET signal can be generated.
Table 10-1. Inadvertent Program Loop Detection Time of Watchdog Timer
Inadvertent Program Loop
Detection Time
At fX = 5.0 MHz
At fCC = 1.0 MHz
211 × 1/fCLK
211/fX (410 µs)
211/fCC (2.05 ms)
213 × 1/fCLK
215 × 1/fCLK
217 × 1/fCLK
213/fX (1.64 ms)
215/fX (6.55 ms)
217/fX (26.2 ms)
213/fCC (8.19 ms)
215/fCC (32.8 ms)
217/fCC (131.1 ms)
Remarks 1. fCLK: fX or fCC
2. fX: System clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: System clock oscillation frequency (RC oscillation)
(2) Interval timer
The interval timer generates an interrupt at an arbitrary preset interval.
Table 10-2. Interval Time of Watchdog Timer
Interval
At fX = 5.0 MHz
211/fX (410 µs)
At fCC = 1.0 MHz
211/fCC (2.05 ms)
211 × 1/fCLK
213 × 1/fCLK
215 × 1/fCLK
217 × 1/fCLK
213/fX (1.64 ms)
215/fX (6.55 ms)
217/fX (26.2 ms)
213/fCC (8.19 ms)
215/fCC (32.8 ms)
217/fCC (131.1 ms)
Remarks 1. fCLK: fX or fCC
2. fX: System clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 10 WATCHDOG TIMER
10.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 10-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 10-1. Block Diagram of Watchdog Timer
Internal bus
f
CLK
24
TMMK4
Prescaler
f
CLK
26
f
CLK
28
f
CLK
210
INTWDT
Maskable
TMIF4
interrupt request
7-bit counter
Clear
Controller
RESET
INTWDT
Non-maskable
interrupt request
3
TCL22 TCL21 TCL20
RUN WDTM4 WDTM3
Timer clock selection
register 2 (TCL2)
Watchdog timer mode register (WDTM)
Internal bus
Remark fCLK: fX or fCC
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CHAPTER 10 WATCHDOG TIMER
10.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer.
•
•
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
(1) Timer clock selection register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Figure 10-2. Format of Timer Clock Selection Register 2
Symbol
TCL2
7
0
6
0
5
0
4
0
3
0
<2>
<1>
<0>
Address
FF42H
After reset
00H
R/W
R/W
TCL22
TCL21
TCL20
TCL22
TCL21
TCL20
Count clock selection
At f
X
= 5.0 MHz
At fCC = 1.0 MHz
CC/24 (62.5 kHz)
CC/26 (15.6 kHz)
fX
fX
fX
fX
/24 (313 kHz)
f
f
f
f
0
0
1
1
0
1
0
1
0
0
0
0
/26 (78.1 kHz)
/28 (19.5 kHz)
/210 (4.88 kHz)
CC/28 (3.91 kHz)
CC/210 (977 Hz)
Other than above
Setting prohibited
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 10 WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 10-3. Format of Watchdog Timer Mode Register
Symbol
WDTM
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
RUN
WDTM4 WDTM3
Watchdog timer operation selectionNote 1
RUN
0
1
Stops counting.
Clears counter and starts counting.
Watchdog timer operation mode selectionNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stop
Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)Note 3
Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.)
Watchdog timer mode 2 (Starts a reset operation upon overflow occurrence.)
Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the timer clock selection register 2 (TCL2).
2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of
interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2
is selected with TMIF4 set to 1, a non-maskable interrupt is generated upon the
completion of rewriting WDTM.
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CHAPTER 10 WATCHDOG TIMER
10.4 Watchdog Timer Operation
10.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode
register (WDTM) is set to 1.
The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 0
to 2 (TCL20 to TCL22) of the timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the
watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after the
watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN
is not set to 1, and the inadvertent program loop detection time is exceeded, a system reset signal or a non-maskable
interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the watchdog timer before executing the STOP instruction.
Caution The actual inadvertent program loop detection time may be up to 0.8% shorter than the set time.
Table 10-4. Inadvertent Program Loop Detection Time of Watchdog Timer
TCL22
TCL21
TCL20
At fX = 5.0 MHz
211/fX (410 µs)
At fCC = 1.0 MHz
211/fCC (2.05 ms)
0
0
1
1
0
1
0
1
0
0
0
0
213/fX (1.64 ms)
215/fX (6.55 ms)
217/fX (26.2 ms)
Setting prohibited
213/fCC (8.19 ms)
215/fCC (32.8 ms)
217/fCC (131.1 ms)
Other than above
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 10 WATCHDOG TIMER
10.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval
specified by a preset count value.
Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of the timer clock selection register 2
(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
In interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the interval timer before executing the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval
timer mode is not set unless a RESET signal is input.
2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set.
Table 10-5. Interval Time of Watchdog Timer
TCL22
TCL21
TCL20
At fX = 5.0 MHz
211/fX (410 µs)
At fCC = 1.0 MHz
211/fCC (2.05 ms)
0
0
1
1
0
1
0
1
0
0
0
0
213/fX (1.64 ms)
215/fX (6.55 ms)
217/fX (26.2 ms)
Setting prohibited
213/fCC (8.19 ms)
215/fCC (32.8 ms)
217/fCC (131.1 ms)
Other than above
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
11.1 Power-on-Clear Circuit Functions
The power-on-clear circuits include the following two circuits, which have the following function.
(1) Power-on-clear (POC) circuit
•
•
Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal
reset signal if VDD < VPOC.
This circuit can operate even in STOP mode.
(2) Low-voltage detection (LVI) circuit
•
Compares the detection voltage (VLVI) with the power supply voltage (VDD) and generates an interrupt
request signal (INTLVI1) if VDD < VLVI.
•
•
Eight levels of detection voltage can be selected using software.
This circuit stops operation in STOP mode.
11.2 Power-on-Clear Circuit Configuration
Figures 11-1 and 11-2 show the block diagrams of the power-on-clear circuits.
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
Figure 11-1. Block Diagram of Power-on-Clear Circuit
V
DD
V
DD
P-ch
P-ch
+
Internal reset signal
−
Detection
voltage
source (VPOC
POCOF1 POCMK1 POCMK0
)
Power on clear
register 1 (POCF1)
Internal bus
Figure 11-2. Block Diagram of Low-Voltage Detection Circuit
VDD
P-ch
VDD
LVI stop signal
(set during STOP
instruction execution
or reset signal
P-ch
generation)
+
−
INTLVI1
N-ch
Detection
voltage
source (VLVI)
LVS12 LVS11 LVS10
LVION1 LVF10
Low-voltage detection level
selection register 1 (LVIS1)
Low-voltage detection
register 1 (LVIF1)
Internal bus
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
11.3 Power-on-Clear Circuit Control Registers
The following three registers control the power-on-clear circuits.
•
•
•
Power-on-clear register 1 (POCF1)
Low-voltage detection register 1 (LVIF1)
Low-voltage detection level selection register 1 (LVIS1)
(1) Power-on-clear register 1 (POCF1)
This register controls POC circuit operation.
POCF1 is set with a 1-bit or 8-bit memory manipulation instruction.
Figure 11-3. Format of Power-on-Clear Register 1
Symbol
POCF1
7
0
6
0
5
0
4
0
3
0
<2>
<1>
<0>
Address After reset
00HNote
R/W
R/W
POCOF1 POCMK1 POCMK0 FFDDH
POCOF1
POC output detection flag
0
1
Non-generation of reset signal by POC or in cleared state due to a write operation to POCF1
Generation of reset signal by POC
POCMK1
POC reset control
Generation of reset signal by POC enabled
0
1
Generation of reset signal by POC disabled
POCMK0
POC operation control
0
1
POC operating
POC halted
Note This value is 04H only after a power-on-clear reset.
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
(2) Low-voltage detection register 1 (LVIF1)
This register controls the operation of the LVI circuit.
LVIF1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 11-4. Format of Low-Voltage Detection Register 1
Symbol
LVIF1
<7>
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address After reset
FFDEH 00H
R/W
LVION1
LVF10
R/WNote
LVION1
LVI operation enable flag
0
1
LVI disabled
LVI enabled
LVF10
LVI output detection flag
0
1
Power supply voltage (VDD) > LVI detection voltage (VLVI) or operation disabled
VDD < VLVI
Note Bit 0 is read only.
(3) Low-voltage detection level selection register 1 (LVIS1)
This register selects the level of the detection voltage (VLVI).
LVIS1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 11-5. Format of Low-Voltage Detection Level Selection Register 1
Symbol
LVIS1
7
0
6
0
5
0
4
0
3
0
<2>
<1>
<0>
Address After reset
FFDFH 00H
R/W
R/W
LVS12
LVS11
LVS10
LVS12
LVS11
LVS10
Selection of detection voltage (VLVI) levelNote
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLVI0
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
Note Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS for detection voltage specifications.
Caution When changing the detection voltage level (VLVI), an operation stabilization time of about 2
ms is required in order for the LVI output to stabilize. Do not, therefore, set the LVI circuit
to operation-enable until the operation has stabilized.
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
11.4 Power-on-Clear Circuit Operation
11.4.1 Power-on-clear (POC) circuit operation
The POC circuit compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an
internal reset signal if VDD < VPOC.
For the µPD78E9860A and 78E9861A, POC operation can be controlled by the POC switching circuit.
Observe the following procedure when switching POC operation.
(1) Switching from POC stopped to POC operating
<1> Check that POCMK1 = 1
<2> Set POCMK0 to 0 to put the POC circuit into the operating state
<3> Wait until the operation stabilization time has elapsed (because the output signal is unstable,
generation of the reset signal via the POC circuit is set to disabled)
<4> Set POCMK1 to 0 to enable generation of the reset signal via the POC circuit
(2) Switching from POC operating to POC stopped
<1> Set POCMK1 to 1 to disable generation of the reset signal via the POC circuit
<2> Set POCMK0 to 1 to put the POC circuit into the operation stopped state
Generation of the reset signal via the POC circuit can be determined by reading the POCOF1 flag. When the
reset signal is generated via the POC circuit, POCOF1 is set to 1. POCOF1 is cleared by writing 0 to POCF1Note
.
When using the POC circuit, clear the POCOF1 beforehand.
Note POCOF1 is cleared when data is written to any of bits 0 to 2 in the POCF1 register.
Figure 11-6 shows the timing of reset signal generation via the POC circuit.
Figure 11-6. Timing of Internal Reset Signal Generation in POC Switching Circuit
Power supply voltage (VDD
)
)
Detection voltage (VPOC
1.8 V
Time
POCMK0
POCMK1
Wait
Internal reset
signal
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
11.4.2 Operation of low-voltage detection (LVI) circuit
The LVI circuit compares the detection voltage (VLVI) with the power supply voltage (VDD) and generates an
interrupt request signal (INTLVI1) if VDD < VLVI (LVI circuit operating).
As shown in Figure 11-2 Block Diagram of Low-Voltage Detection Circuit, the divided resistors and
comparators of the LVI circuit turn OFF when the reset signal is generated or in STOP mode. After reset is released,
LVI operation starts when LVION1 (bit 7 of low-voltage detection register 1 (LVIF1)) is set. At this time, approximately
2 ms are required until the LVI circuit operation is stabilized.
Once the LVI operation is started, divided resistors and comparators cannot be OFF unless the STOP instruction
or reset signal is generated, even LVION1 is cleared. Low-voltage detection is enabled immediately after LVION1 is
set again.
Caution The divider resistor and comparator of the LVI circuit are turned ON after reset is released.
Use one of the following methods to constantly monitor low voltage.
<1> Low-voltage monitoring by LVFI0 (bit 0 of low-voltage detection register 1 (LVIF1)) without using LVI
detection interrupt.
<2> Low-voltage monitoring using LVI detection interrupt. In this case, disable the LVI operation once, and then
enable it (LVION1 = 0 → 1) before enabling interrupts (LVIMK1 = 0).
An example of a program in which low voltage is constantly monitored using the LVI detection interrupt is shown
below.
(a) Processing when reset mode is released
DI
MOV
SET1
SET1
CALL
CLR1
CLR1
SET1
CLR1
EI
LVIS1, #xxH; Setting LVI detection voltage
LVIMK1;
LVION1;
!WAIT_2ms;
LVIIF1;
LVI interrupt disabled
LVI operation enabled
2 ms wait
LVION1;
LVION1;
LVIMK1;
LVI operation disabled
LVI operation enabled
LVI interrupt enabled
(b) Processing when STOP mode is released
SET1
STOP
CALL
CLR1
CLR1
SET1
CLR1
EI
LVIMK1;
LVI interrupt disabled
!WAIT;
Total 2 ms wait, combined with oscillation stabilization time
LVIIF1
LVION1;
LVION1;
LVIMK1;
LVI operation disabled
LVI operation enabled
LVI interrupt enabled
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS (µPD78E9860A, 78E9861A ONLY)
(c) Processing to enable LVI interrupt again after LVI interrupt servicing
SET1
CLR1
SET1
CLR1
EI
LVIMK1;
LVION1;
LVION1;
LVIMK1;
LVI interrupt disabled
LVI operation disabled
LVI operation enabled
LVI interrupt enabled
Figure 11-7 shows the LVI circuit operation timing.
Figure 11-7. LVI Circuit Operation Timing
Power supply voltage (VDD
)
)
Detection voltage (VLVI
1.8 V
LVION1
2 ms
Vectored interrupt
IE
INTLVI1
LVIIF1
LVIMK1
Vectored interrupt does not occur
Caution The low-voltage detection interrupt request flag (LVIIF1) is set at the rising edge of the LVI
circuit comparator output signal (INTLVI1). Therefore, the power supply voltage (VDD) becomes
lower than the detection voltage (VLVI) during LVI operation, and if that state continues after
INTLVI1 generation, LVIIF1 is not set. After low-voltage detection, when set as VDD > VLVI and
then VDD < VLVI again, LVIIF1 is set.
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CHAPTER 12 BIT SEQUENTIAL BUFFER
12.1 Bit Sequential Buffer Functions
The µPD789052, 789062 Subseries have an on-chip bit sequential buffer of 8 bits + 8 bits = 16 bits.
The functions of the bit sequential buffer are shown below.
•
•
•
If the value of the bit sequential buffer 10 data register (BSFRL10, BSFRH10) is shifted 1 bit to the lower side,
the LSB can be output to the port at the same time.
It is possible to write to BSFRL10 and BSFRH10 using an 8-bit or 16-bit memory manipulation instruction
(reading is not possible).
Overwriting is enabled during a shift operation on the higher 8 bits (BSFRH10) only (the period in which shift
clock is low level).
12.2 Bit Sequential Buffer Configuration
The bit sequential buffer includes the following hardware.
Table 12-1. Configuration of Bit Sequential Buffer
Item
Data register
Control register
Configuration
Bit sequential buffer: 8 bits + 8 bits = 16 bits
Bit sequential buffer output control register 10 (BSFC10)
Port mode register 2 (PM2)
Port 2 (P2)
Figure 12-1. Block Diagram of Bit Sequential Buffer
Internal bus
TM40 match
interrupt request signal
BSFRH10
BSFRL10
BSFO/P20
/TMO
BSFE10
P20
output latch
PM20
Bit sequential buffer output
control register 10 (BSFC10)
Internal bus
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CHAPTER 12 BIT SEQUENTIAL BUFFER
12.3 Bit Sequential Buffer Control Register
The bit sequential buffer is controlled by the following three registers.
• Bit sequential buffer output control register 10 (BSFC10)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) Bit sequential buffer output control register 10 (BSFC10)
This register controls the operation of the bit sequential buffer.
BSFC10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 12-2. Format of Bit Sequential Buffer Output Control Register 10
Symbol
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address After reset
FF60H 00H
R/W
R/W
BSFC10
BSFE10
BSFE10
Bit sequential buffer operation control
0
1
Operation disabled
Operation enabled
(2) Port mode register 2 (PM2)
PM2 sets port 2 to input/output in 1-bit units.
When using the P20/TMO/BSFO pin as a data output of the bit sequential buffer, clear the PM20 and P20
output latch to 0.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 12-3. Format of Port Mode Register 2
Symbol
PM2
7
1
6
1
5
1
4
1
3
1
2
1
1
0
Address After reset
FF22H FFH
R/W
R/W
PM21
PM20
PM20
P20 pin input/output mode
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 12 BIT SEQUENTIAL BUFFER
12.4 Bit Sequential Buffer Operation
Set as follows to operate the bit sequential buffer.
<1> Set values to bit sequential buffer 10 data registers L and H (BSFRL10, BSFRH10)
<2> Set the bit sequential buffer to operation enabled (BSFE10 = 1)
If the LSB of BSFRL10 is being output at the P20/BSFO/TMO pin, set P20 to output mode (PM20 = 0) and
the output latch of P20 to 0
<3> Start the clock operation
If the clock is input before the bit sequential buffer starts operation, the output time of the start bit may be shorter
than one cycle of the clock when output commences, as shown in the figure below.
Timer 40
match signal
t0
BSFE10
BSFRL10,
BSFRH10
5555H
2AAAH
0AAAH
1555H
Bit sequential
buffer output
t2
t1
t1< t0
t2 = t0
Figure 12-4 shows the operation timing of the bit sequential buffer.
Figure 12-4. Operation Timing of Bit Sequential Buffer
Timer 40
match signal
BSFE10
BSFRL10,
BSFRH10
0AAAH
Undefined
2AAAH
×555H
1555H
5555H
×2AAH
Bit sequential
buffer output
Cautions 1. Even if data is written to the data register while the bit sequential buffer is operating, the
shift clock (timer 40 match signal) will not stop. Data should therefore be written to the
data register when the shift clock is low level.
2. The value of the data register is undefined after a shift.
Remark ×: Undefined
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CHAPTER 13 KEY RETURN CIRCUIT
13.1 Key Return Circuit Function
In STOP mode, this circuit generates a key return interrupt (INTKR1) by inputting a P40/KR10 to P43/KR13 falling
edge.
Cautions 1. The key return interrupt is a non-maskable interrupt that is effective only in STOP mode.
In addition, P40/KR10 to P43/KR13 key input cannot be performed by mask control.
2. A key return signal cannot be detected while any one of the key return pins (P40/KR10 to
P43/KR13) is low level even when a falling edge occurred at another pin.
13.2 Key Return Circuit Configuration and Operation
Figure 13-1 shows the block diagram of the key return circuit. Figure 13-2 shows the generation timing of the key
return interrupt (INTKR1).
Figure 13-1. Block Diagram of Key Return Circuit
P40/KR10
Falling edge detector
Key return interrupt
(INTKR1)
P41/KR11
P42/KR12
P43/KR13
STOP mode
Figure 13-2. Generation Timing of Key Return Interrupt
STOP signal
P4n/KR1n
INTKR1
Remark n = 0 to 3
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CHAPTER 14 INTERRUPT FUNCTIONS
14.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupts
This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt
priority control and is given top priority over all other interrupt requests.
A standby release signal is generated.
There are one external source and one internal source of non-maskable interrupts.
(2) Maskable interrupts
These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated,
each interrupt has a predetermined priority as shown in Table 14-1.
A standby release signal is generated.
The number of maskable interrupt sources differs depending on the product as follows.
•
•
µPD789052, 789062:
3 internal sources
µPD78E9860A, 78E9861A: 5 internal sources
14.2 Interrupt Sources and Configuration
There are a total of 5 non-maskable and maskable interrupt sources in the µPD789052 and 789062, and a total of
7 in the µPD78E9860A and 78E9861A (see Table 14-1).
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Table 14-1. Interrupt Sources
Interrupt Type
PriorityNote 1
Interrupt Source
Trigger
Internal/External Vector Table
Basic
Address
0002H
0004H
Configuration
TypeNote 2
Name
INTKR1
−
Non-maskable
interrupt
Key return input falling edge
detection
External
Internal
(A)
INTWDT
INTWDT
Watchdog timer overflow
(when watchdog timer mode 1
is selected)
Maskable
interrupt
0
Watchdog timer overflow
(when interval timer mode is
selected)
(B)
1
2
INTTM30
INTTM40
Generation of match signal for
8-bit timer 30
0006H
0008H
Generation of match signal for
8-bit timer 40
3
4
INTLVI1Note 3
INTEE0Note 3
LVI interrupt request signal
000AH
000CH
EEPROM write termination
signal
Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time.
0 is the highest and 4 is the lowest.
2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 14-1.
3. µPD78E9860A, 78E9861A only
Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable interrupts and
maskable interrupts (internal). Either one (but not both) should be selected for actual use.
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Figure 14-1. Basic Configuration of Interrupt Function
(A) External/internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
IF
Interrupt request
Standby release signal
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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14.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following three types of registers.
• Interrupt request flag register 0 (IF0)
• Interrupt mask flag register 0 (MK0)
• Program status word (PSW)
Table 14-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Table 14-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Signal
INTWDT
Interrupt Request Flag
Interrupt Mask Flag
TMIF4
TMMK4
INTTM30
INTTM40
INTLVI1Note
INTEE0Note
TMIF30
TMIF40
LVIF1Note
EEIF0Note
TMMK30
TMMK40
LVIMK1Note
EEMK0Note
Note µPD78E9860A, 78E9861A only
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(1) Interrupt request flag register 0 (IF0)
An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the
instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is
acknowledged or when a RESET signal is input.
IF0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 to 00H.
Figure 14-2. Format of Interrupt Request Flag Register 0
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FFE0H
After reset
00H
R/W
R/W
Symbol
IF0
7
0
LVIIF1Note TMIF40
TMIF30
TMIF4
EEIF0Note
××IF×
Interrupt request flag
No interrupt request signal has been issued.
An interrupt request signal has been issued; an interrupt request status.
0
1
Note µPD78E9860A, 78E9861A only
Cautions 1. Bits 5 to 7 must all be set to 0.
2. The TMIF4 flag can be read- and write-accessed only when the watchdog timer is being
used as an interval timer. It must be cleared to 0 if the watchdog timer is used in
watchdog timer mode 1 or 2.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared
and then the interrupt routine is started.
(2) Interrupt mask flag register 0 (MK0)
The interrupt mask flag is used to enable and disable the corresponding maskable interrupts.
MK0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 to FFH.
Figure 14-3. Format of Interrupt Mask Flag Register 0
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FFE4H
After reset
FFH
R/W
R/W
Symbol
MK0
7
0
LVIMK1Note TMMK40
TMMK30
TMMK4
EEMK0Note
××MK×
Interrupt servicing control
0
1
Enables servicing servicing.
Disables servicing servicing.
Note µPD78E9860A, 78E9861A only
Cautions 1. Bits 5 to 7 must all be set to 1.
2. The TMMK4 flag can be read- and write-accessed only when the watchdog timer is
being used as an interval timer.
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(3) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the
interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
RESET input sets PSW to 02H.
Figure 14-4. Program Status Word Configuration
Symbol
PSW
7
6
Z
5
0
4
3
0
2
0
1
1
0
After reset
02H
IE
AC
CY
Used in the execution of ordinary instructions
IE
0
Whether to enable/disable interrupt acknowledgement
Disabled
Enabled
1
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14.4 Interrupt Servicing Operation
14.4.1 Non-maskable interrupt request acknowledgement operation
The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 14-5 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure 14-
6 shows the timing of non-maskable interrupt request acknowledgement. Figure 14-7 shows the acknowledgement
operation if multiple non-maskable interrupts are generated.
Caution The µPD789052 and 789062 Subseries have two non-maskable interrupt sources. Therefore,
during execution of a non-maskable interrupt servicing program, a new non-maskable interrupt
request is not acknowledged until the RETI instruction is executed. Be sure to execute the
RETI instruction after the interrupt servicing program has been executed.
When using the watchdog timer as a non-maskable interrupt, push the address of restore
destination before executing the RETI instruction. If the RETI instruction is executed without
pushing the restore destination, the program will jump to an illegal address. A program
example is shown below.
<Example> Program example in which watchdog timer is used as non-maskable interrupt and
program branches to reset vector when interrupt occurs
XVECT
DW
CSEG
AT 0000H
;(00)
IRESET
IKR
RESET
DW
;(02)
KeyReturn
INTWDT
DW
IWDT
;(04)
:
XRST
CSEG
AT 0080H
IRESET: DI
MOVW AX,#0FEFFH
MOVW SP, AX
:
:
IWDT:
(Interrupt servicing)
MOVW AX,#0080H
PUSH AX
RETI
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Figure 14-5. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement (INTWDT)
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing is started
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 14-6. Timing of Non-Maskable Interrupt Request Acknowledgement
Interrupt servicing
program
Saving PSW and PC, and
jump to interrupt servicing
CPU processing
Instruction
Instruction
Non-maskable
interrupt request
Figure 14-7. Acknowledgement of Non-Maskable Interrupt Request
Main routing
First interrupt servicing
NMI request
(second)
NMI request
(first)
RETI instruction
execution
Second interrupt servicing
RETI instruction
execution
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14.4.2 Maskable interrupt request acknowledgement operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown
in Table 14-3.
See Figures 14-9 and 14-10 for the interrupt request acknowledgement timing.
Table 14-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
9 clocks
Maximum TimeNote
19 clocks
Note The wait time is maximum when an interrupt
request is generated immediately before BT and
BF instruction.
1
fCPU
Remark 1 clock:
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
Figure 14-8 shows the algorithm of interrupt request acknowledgement.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
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Figure 14-8. Interrupt Request Acknowledgement Processing Algorithm
Start
No
××IF = 1 ?
Yes (Interrupt request generated)
No
××MK = 0 ?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1 ?
Yes
Vectored interrupt
servicing
××IF:
Interrupt request flag
××MK: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)
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Figure 14-9. Interrupt Request Acknowledgement Timing (Example of MOV A, r)
8 clocks
Clock
Saving PSW and PC, jump
to interrupt servicing
Interrupt servicing program
CPU
MOV A, r
Interrupt
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
the interrupt is acknowledged after the instruction under execution is complete. Figure 14-9 shows an example of the
interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement
processing is performed after the MOV A, r instruction is executed.
Figure 14-10. Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Set at Last
Clock During Instruction Execution)
8 clocks
Clock
Interrupt
Saving PSW and PC, jump
servicing
CPU
NOP
MOV A, r
to interrupt servicing
program
Interrupt
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgement
processing starts after the next instruction is executed.
Figure 14-10 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set at
the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is
executed, and then the interrupt acknowledgement processing is performed.
Caution Interrupt requests will be held pending while interrupt request flag register 0 (IF0) or interrupt
mask flag register 0 (MK0) is being accessed.
14.4.3 Multiple interrupt servicing
Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be
performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is
performed according to the priority assigned to each interrupt request in advance (see Table 14-1).
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Figure 14-11. Example of Multiple Interrupts
Example 1. A multiple interrupt is acknowledged
INTxx servicing
INTyy servicing
Main processing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
The EI instruction is issued before each interrupt request acknowledgement, and the interrupt request
acknowledgement enable state is set.
Example 2. Multiple interrupts are not generated because interrupts are not enabled
INTxx servicing
INTyy servicing
Main processing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgement disabled
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14.4.4 Interrupt request pending
Some instructions may keep pending the acknowledgement of an instruction request until the completion of the
execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and
external interrupt) is generated during the execution. The following shows such instructions (interrupt request
pending instruction).
• Manipulation instruction for interrupt request flag register 0 (IF0)
• Manipulation instruction for interrupt mask flag register 0 (MK0)
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CHAPTER 15 STANDBY FUNCTION
15.1 Standby Function and Configuration
15.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes:
(1) HALT mode
This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU.
The system clock oscillator continues oscillating. This mode does not reduce the current consumption as
much as STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The current consumption of the CPU can be substantially reduced in
this mode.
The low voltage (VDD = 1.8 V min.) of the data memory can be retained. Therefore, this mode is useful for
retaining the contents of the data memory at an extremely low current consumption.
STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after STOP mode has
been released. If processing must be resumed immediately by using an interrupt request, therefore, use the
HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all
retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.
Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute
the STOP instruction.
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15.1.2 Standby function control register
The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with
the oscillation stabilization time selection register (OSTS)Note
.
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET release is 215/fX in the
µPD789052 and 78E9860A, and 27/fCC in the µPD789062 and 78E9861A independent of OSTS.
Note µPD789052 Subseries only.
There is no oscillation stabilization time selection register in the µPD789062 Subseries. The oscillation
stabilization time of the µPD789062 Subseries is fixed at 27/fCC.
Figure 15-1. Format of Oscillation Stabilization Time Selection Register
6
0
5
0
4
0
3
0
2
1
0
Address
After reset
04H
R/W
R/W
Symbol
OSTS
7
0
OSTS2
OSTS1
OSTS0 FFFAH
OSTS2 OSTS1
OSTS0
Oscillation stabilization time selection
212/f
215/f
217/f
X
0
0
1
0
1
0
0
0
0
µ
(819 s)
X
X
(6.55 ms)
(26.2 ms)
Other than above
Setting prohibited
Caution The wait time after STOP mode is released does not include the time from STOP mode release
to clock oscillation start (“a” in the figure below), regardless of release by RESET input or by
interrupt generation.
STOP Mode Release
X1 Pin Voltage
Waveform
a
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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15.2 Standby Function Operation
15.2.1 HALT mode
(1) HALT mode
HALT mode is set by executing the HALT instruction.
The operation statuses in HALT mode are shown in the following table.
Table 15-1. Operation Statuses in HALT Mode
Item
System clock
HALT Mode Operation Status
System clock oscillation enabled
Clock supply to CPU stopped
CPU
Operation stopped
EEPROMNote 1
Port (output latch)
8-bit timer
Operation enabledNote 2
Remains in the state existing before HALT mode has been set
Operation enabled
TM30
TM40
Operation enabled
Watchdog timer
Operation enabled
Power-on-clear
circuitNote 1
POC
LVI
Operation enabledNote 3
Operation enabled
Bit sequential buffer
Key return circuit
Operation enabled
Operation stopped
Notes 1. µPD78E9860A, 78E9861A only
2. HALT mode can be set after executing a write instruction.
3. When the POC circuit is set to operation enabled by the POC switching circuit in the µPD78E9860A
and 78E9861A.
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(2) Releasing HALT mode
HALT mode can be released by the following three sources:
(a) Releasing by unmasked interrupt request
HALT mode is released by an unmasked interrupt request. In this case, if interrupt request
acknowledgement is enabled, vectored interrupt servicing is performed. If interrupt acknowledgement is
disabled, the instruction at the next address is executed.
Figure 15-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operating
mode
HALT mode
Operating mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that has released standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed:
• When vectored interrupt servicing is not performed:
9 to 10 clocks
1 to 2 clocks
(b) Releasing by non-maskable interrupt request of watchdog timer
HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt
servicing is performed.
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(c) Releasing by RESET input
When HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as the ordinary reset operation, and program execution starts.
Figure 15-3. Releasing HALT Mode by RESET Input
HALT
instruction
WaitNote
RESET
signal
Oscillation
Reset
period
stabilization
wait status
Operating
mode
Operating
mode
HALT mode
Oscillation
stop
Oscillation
Oscillation
Clock
Note
In the µPD789052 and 78E9860A, 215/f
X
: 6.55 ms (@ f
X
= 5.0 MHz operation)
In the µPD789062 and 78E9861A, 27/fCC: 128 µs (@ fCC = 1.0 MHz operation)
Remarks 1. f
X
:
System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
Table 15-2. Operation After Releasing HALT Mode
MK××
Releasing Source
IE
0
Operation
Executes next address instruction.
Executes interrupt servicing.
Retains HALT mode.
Maskable interrupt request
0
0
1
−
1
×
×
Non-maskable interrupt request
of watchdog timer
Executes interrupt servicing.
−
−
RESET input
Reset processing
×: don’t care
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15.2.2 STOP mode
(1) Setting and operation status of STOP mode
STOP mode is set by executing the STOP instruction.
Caution Because standby mode can be released by an interrupt request signal, standby mode is
released as soon as it is set if there is an interrupt source whose interrupt request flag is
set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set
immediately after the STOP instruction has been executed, the wait time set by the
oscillation stabilization time, and then the operation mode is set.
The operation statuses in STOP mode are shown in the following table.
Table 15-3. Operation Statuses in STOP Mode
Item
STOP Mode Operation Status
System clock oscillation stopped
System clock
Clock supply to CPU stopped
CPU
Operation stopped
EEPROMNote 1
Operation stopped
Port (output latch)
8-bit timer
Remains in the state existing before STOP mode has been set
Operation enabledNote 2
TM30
TM40
Operation enabledNote 3
Watchdog timer
Operation stopped
Power-on-clear
circuitNote 1
POC
LVI
Operation enabledNote 4
Operation stopped
Bit sequential buffer
Key return circuit
Operation enabledNote 5
Operation enabled
Notes 1. µPD78E9860A, 78E9861A only
2. Operation enabled only when cascade connected with TM40 (external clock selected for count clock)
3. Operation enabled only when external clock is selected for count clock
4. When the POC circuit is set to operation enabled by the POC switching circuit in the µPD78E9860A
and 78E9861A.
5. Operation enabled only when external clock is selected for TM40 count clock and INTTM40 occurs
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(2) Releasing STOP mode
STOP mode can be released by the following two sources:
(a) Releasing by unmasked interrupt request
STOP mode is released by an unmasked interrupt request. In this case, vectored interrupt servicing is
performed if interrupt acknowledgement is enabled after the oscillation stabilization time has elapsed. If
interrupt acknowledgement is disabled, the instruction at the next address is executed.
Figure 15-4. Releasing STOP Mode by Interrupt
WaitNote
(time set by OSTS)
STOP
instruction
Standby
release signal
Oscillation stabilization
wait status
Operating
mode
Operating
mode
STOP mode
Oscillation
stop
Oscillation
Oscillation
Clock
Note There is no OSTS in the µPD789062 Subseries, and the wait is fixed at 27/fCC
.
Remark The broken lines indicate the case where the interrupt request that has released standby
mode is acknowledged.
(b) Releasing by non-maskable interrupt request of key return
STOP mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt
servicing is performed.
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(b) Releasing by RESET input
When STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 15-5. Releasing STOP Mode by RESET Input
STOP
instruction
WaitNote
RESET
signal
Oscillation
stabilization
wait status
Operating
mode
Reset
period
Operating
mode
STOP mode
Oscillation
Oscillation
stop
Oscillation
Clock
Note
In the µPD789052 and 78E9860A, 215/f
X
: 6.55 ms (@ f
X
= 5.0 MHz operation)
In the µPD789062 and 78E9861A, 27/fCC: 128 µs (@ fCC = 1.0 MHz operation)
Remarks 1. f
X
:
System clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: System clock oscillation frequency (RC oscillation)
Table 15-4. Operation After Releasing STOP Mode
MK××
Releasing Source
IE
0
Operation
Executes next address instruction.
Executes interrupt servicing.
Retains STOP mode.
Maskable interrupt request
0
0
1
−
1
×
×
Non-maskable interrupt request
of key return
Executes interrupt servicing.
−
−
RESET input
Reset processing
×: don’t care
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CHAPTER 16 RESET FUNCTION
The following three operations are available to generate reset signals.
(1) External reset input by RESET signal input
(2) Internal reset by watchdog timer inadvertent program loop time detection
(3) Internal reset by comparison of POC circuit power supply voltage and detection voltageNote
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by reset signal input.
When a low level is input to the RESET pin, the watchdog timer overflows, or POC circuitNote voltage is detected, a
reset is applied and each hardware is set to the status shown in Table 16-1. Each pin is high impedance during reset
input or during the oscillation stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 16-2
through 16-4).
Note
µPD78E9860A, 78E9861A only
Cautions 1. For an external reset, input a low level of 10 µs or more to the RESET pin.
2. When STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pins become high impedance.
Figure 16-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
POC circuitNote
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
Note
µPD78E9860A, 78E9861A only
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CHAPTER 16 RESET FUNCTION
Figure 16-2. Reset Timing by RESET Input
X1, CL1
RESET
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Normal operation
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
X1, CL1
Figure 16-3. Reset Timing by Watchdog Timer Overflow
Reset period
(oscillation
continues)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Normal operation
Watchdog
timer overflow
Internal
reset signal
Hi-Z
Port pin
Figure 16-4. Reset Timing by RESET Input in STOP Mode
X1, CL1
RESET
STOP instruction execution
Oscillation
Stop status
(oscillation
stops)
Reset period
(oscillation
stops)
Normal operation
(reset processing)
stabilization
time wait
Normal operation
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Remark For the reset timing of the power-on-clear circuit, see CHAPTER 11 POWER-ON-CLEAR CIRCUITS
(µPD78E9860A, 78E9861A ONLY).
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CHAPTER 16 RESET FUNCTION
Table 16-1. Status of Hardware After Reset
Hardware
Status After Reset
Program counter (PC)Note 1
The contents of the reset
vector table (0000H, 0001H)
are set
Stack pointer (SP)
Program status word (PSW)
EEPROMNote 2
Undefined
02H
Write control register (EEWC10)
Data memory
08H
RAM
UndefinedNote 3
UndefinedNote 3
00H
General-purpose registers
Ports (P0, P2) (output latch)
Port mode registers (PM0, PM2)
FFH
Processor clock control register (PCC)
02H
Oscillation stabilization time selection register (OSTS)Note 4
04H
8-bit timer
Timer counters (TM30, TM40)
00H
Compare registers (CR30, CR40, CRH40)
Mode control registers (TMC30, TMC40)
Carrier generator output control register (TCA40)
Timer clock selection register (TCL2)
Mode register (WDTM)
Undefined
00H
00H
Watchdog timer
00H
00H
Power-on-clear circuitNote 2
Power-on-clear register (POCF1)
00HNote 5
Low-voltage detection register (LVIF1)
Low-voltage detection level selection register (LVIS1)
Data registers (BSFRL10, BSFRH10)
Output control register (BSFC10)
00H
00H
Bit sequential buffer
Interrupts
Undefined
00H
Request flag register (IF0)
00H
Mask flag register (MK0)
FFH
Notes 1. While a reset signal is being input, and during the oscillation stabilization time wait, the contents of the
PC will be undefined, while the remainder of the hardware will be the same as after the reset.
2. µPD78E9860A, 78E9861A only
3. In standby mode, the RAM enters the hold state after a reset.
4. µPD789052 Subseries only
5. This value is 04H only after a power-on-clear reset.
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CHAPTER 17 µPD78E9860A, 78E9861A
EEPROM versions in the µPD789052, 789062 Subseries include the µPD78E9860A and 78E9861A.
The µPD78E9860A replaces the internal ROM of the µPD789052 with EEPROM. The µPD78E9861A replaces
the internal ROM of the µPD789062 with EEPROM. The differences between the µPD78E9860A, 78E9861A and the
mask ROM versions are shown in Table 17-1.
Table 17-1. Differences Between µPD78E9860A, 78E9861A and Mask ROM Versions
Part Number
EEPROM Versions
Mask ROM Versions
Item
µPD78E9860A
µPD78E9861A
µPD789052
µPD789062
Internal
memory
Program
memory
ROM
EEPROM
Mask ROM
structure
ROM
4 KB
capacity
Data
High-speed
RAM
128 bytes
32 bytes
memory
EEPROM
Not provided
System clock
Ceramic/crystal
oscillation
RC oscillation
Ceramic/crystal
oscillation
RC oscillation
IC pin
Not provided
Provided
Provided
VPP pin
Not provided
Provided
P40 to P43 pull-up resistor by mask
option
Not provided
POC circuit selection by mask option
Not provided
Provided
Oscillation stabilization time after
STOP mode is released by interrupt
request
Can select 212/fX,
215/fX, or 217/fX by
OSTS register
27/fCC
Can select 212/fX,
215/fX, or 217/fX by
OSTS register
27/fCC
Oscillation stabilization time after
STOP mode release by RESET or
reset release via POC circuit
215/fX
27/fCC
215/fX
27/fCC
Power supply voltage
Electrical specifications
VDD = 1.8 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 1.8 to 3.6 V
Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS
Caution There are differences in noise immunity and noise radiation between the EEPROM and mask
ROM versions. When pre-producing an application set with the EEPROM version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
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CHAPTER 17 µPD78E9860A, 78E9861A
17.1 EEPROM (Program Memory)
The on-chip program memory in the µPD78E9860A and 78E9861A is EEPROM.
This chapter describes the functions of the EEPROM incorporated in the program memory area. For the
EEPROM incorporated in data memory, see CHAPTER 5 EEPROM (DATA MEMORY) (µPD78E9860A, 78E9861A
ONLY).
EEPROM can be written with the µPD78E9860A and 78E9861A mounted on the target system (on-board).
Connect the dedicated flash writer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to
the host machine and target system to write to EEPROM.
Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd (TEL +81-45-475-4191).
Programming using EEPROM has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities small-quantity, varied model production
• Easy data adjustment when starting mass production
17.1.1 Programming environment
The following shows the environment required for µPD78E9860A, 78E9861A EEPROM programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between
the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer to the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 17-1. Environment for Writing Program to EEPROM (Program Memory)
VPP
V
DD
SS
RS-232C
USB
V
RESET
Dedicated flash
programmer
µ
µ
PD78E9860A,
PD78E9861A
Pseudo 3-wire
Host machine
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CHAPTER 17 µPD78E9860A, 78E9861A
17.1.2 Communication mode
Use the communication mode shown in Table 17-2 to perform communication between the dedicated flash
programmer and µPD78E9860A, 78E9861A.
Table 17-2. Communication Mode List
Communication
Mode
TYPE SettingNote 1
CPU CLOCKNote 2
Pins Used
Number of
VPP Pulses
COMM
PORT
SIO Clock
Multiple
Rate
In Flashpro
100 Hz to 1, 2, 4, 5
1 kHz
MHzNotes 3, 4
On Target Board
1 to 5 MHzNote 3
Pseudo 3-wire
Port A
1.0
P02 (serial data input)
P01 (serial data output)
P00 (serial clock input)
12
(Pseudo-
3 wire)
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III / Flashpro IV).
2. Be sure to use In Flashpro (system clock is supplied from a dedicated flash writer) with the
µPD78E9861A.
3. The possible setting range differs depending on the voltage. For details, see CHAPTER 20
ELECTRICAL SPECIFICATIONS.
4. 2 or 4 MHz only with Flashpro III
Figure 17-2. Communication Mode Selection Format
10 V
VPP
VDD
1
2
n
VSS
VPP pulse
V
DD
RESET
V
SS
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CHAPTER 17 µPD78E9860A, 78E9861A
Figure 17-3. Example of Connection with Dedicated Flash Programmer
(a) Pseudo 3-wire (µPD78E9860A)
µ
Dedicated flash programmer
PD78E9860A
VPP1
VDD
V
PP
DD
V
RESET
SCK
RESET
P00 (serial clock)
P02 (serial input)
P01 (serial output)
X1
SO
SI
CLKNote
GND
VSS
(b) Pseudo 3-wire (µPD78E9861A)
Dedicated flash programmer PD78E9861A
µ
VPP1
VDD
RESET
SCK
SO
V
V
PP
DD
RESET
P00 (serial clock)
P02 (serial input)
P01 (serial output)
P03
SI
CLK
GND
V
SS
Note When supplying the system clock from a dedicated flash writer, connect the CLK and X1 pins and cut off
the resonator on the board. When using the clock oscillated by the on-board resonator, do not connect the
CLK pin.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. When using the power supply connected to the VDD pin, supply
voltage before starting programming.
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CHAPTER 17 µPD78E9860A, 78E9861A
If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash
programmer, the following signals are generated for the µPD78E9860A, 78E9861A. For details, refer to the manual
of Flashpro III/Flashpro IV.
Table 17-3. Pin Connection List
Signal Name
VPP1
I/O
Output
−
Pin Function
Pin Name
Pseudo 3-Wire
Write voltage
VPP
−
−
×
VPP2
Note
VDD
I/O
VDD voltage generation/voltage monitoring
VDD
VSS
−
GND
Ground
X1 (µPD78E9860A)
CLK
Output
Clock output
P03 (µPD78E9861A)
RESET
SI
Output
Input
Reset signal
RESET
P01
P02
P00
−
Receive signal
Transmit signal
Transfer clock
Handshake signal
SO
Output
Output
Input
SCK
HS
×
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not need to be connected.
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CHAPTER 17 µPD78E9860A, 78E9861A
17.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and EEPROM programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In EEPROM programming mode, a write voltage of 10.0 V
(TYP.) is supplied to the VPP pin, so perform either of the following.
(1) Connect a pull-down resistor RVPP = 10 kΩ to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 17-4. VPP Pin Connection Example
PD78E9860A, 78E9861A
µ
Connection pin of dedicated flash programmer
V
PP
Pull-down resistor (RVPP
)
<Serial interface pins>
The following shows the pins used by the serial interface.
Serial Interface
Pseudo 3-wire
Pins Used
P02, P01, P00
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device on-
board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such
connections.
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CHAPTER 17 µPD78E9860A, 78E9861A
(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device
or set the other device to the output high impedance status.
Figure 17-5. Signal Conflict (Input Pin of Serial Interface)
µ
PD78E9860A, 78E9861A
Connection pin of
dedicated flash
programmer
Signal conflict
Input pin
Other device
Output pin
In the EEPROM programming mode, the signal output by another device
and the signal sent by the dedicated flash programmer conflict; therefore,
isolate the signal of the other device.
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that
is connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
signals input to the other device are ignored.
Figure 17-6. Abnormal Operation of Other Device
PD78E9860A, 78E9861A
µ
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
µ
If the signal output by the PD78E9860A, 78E9861A affects another
device in the EEPROM programming mode, isolate the signals of the other
device.
µ
PD78E9860A, 78E9861A
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the EEPROM programming mode, isolate the signals of the other
device.
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CHAPTER 17 µPD78E9860A, 78E9861A
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the EEPROM programming mode, a normal programming
operation cannot be performed. Therefore, do not input other than reset signals from the dedicated flash
programmer.
Figure 17-7. Signal Conflict (RESET Pin)
µ
PD78E9860A, 78E9861A
Connection pin of
dedicated flash
programmer
Signal conflict
RESET
Reset signal generator
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the EEPROM programming
mode, so isolate the signal of the reset signal generator.
<Port pins>
When the µPD78E9860A and 78E9861A enter the EEPROM programming mode, all the pins other than those
that communicate with the flash programmer are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS via a resistor.
<Oscillator>
• In µPD78E9860A
When using the on-board clock, connect X1 and X2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator
on-board, and leave the X2 pin open.
• In µPD78E9861A
Connect CL1 and CL2 as required in the normal operation mode, and connect the clock output of the flash
programmer to the P03 pin.
<Power supply>
To use the power output from the flash programmer, connect the VDD pin to VDD of the flash programmer, and
the VSS pin to GND of the flash programmer.
To use the on-board power supply, make connections that accord with the normal operation mode. However,
because the voltage is monitored by the flash programmer, be sure to connect VDD of the flash programmer.
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CHAPTER 17 µPD78E9860A, 78E9861A
17.1.4 Connection of adapter for flash memory (EEPROM) writing
The following figures show the examples of recommended connection when the adapter for flash memory
(EEPROM) writing is used.
Figure 17-8. Wiring Example for Flash Memory (EEPROM) Writing Adapter with Pseudo 3-Wire (1/2)
(a) µPD78E9860A
VDD (2.7 to 5.5 V)
GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
µ
7
8
9
10
GND
VDD
VDD2 (LVDD)
SI
SO
SCK CLKOUT RESET VPP RESERVE/HS
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CHAPTER 17 µPD78E9860A, 78E9861A
Figure 17-8. Wiring Example for Flash Memory (EEPROM) Writing Adapter with Pseudo 3-Wire (2/2)
(b) µPD78E9861A
VDD (2.7 to 3.6 V)
GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
µ
7
8
9
10
GND
VDD
VDD2 (LVDD)
SI
SO
SCK CLKOUT RESET VPP RESERVE/HS
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CHAPTER 18 MASK OPTIONS
The µPD789052 and 789062 have the following mask options.
P40 to P43 mask options
•
On-chip pull-up resistors can be selected in bit units.
<1> Specify on-chip pull-up resistors
<2> Do not specify on-chip pull-up resistors
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CHAPTER 19 INSTRUCTION SET OVERVIEW
This chapter lists the instruction set of the µPD789052, 789062 Subseries. For details of the operation and
machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual
(U11047E).
19.1 Operation
19.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !:
Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 19-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark For symbols of special function registers, see Table 4-3 Special Function Registers.
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19.1.2 Description of “Operation” column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS:
( ):
Flag indicating non-maskable interrupt servicing in progress
Memory contents indicated by address or register contents in parentheses
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
×H, ×L:
∧:
∨:
Logical sum (OR)
∨:
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
19.1.3 Description of “Flag” column
(Blank): Unchanged
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is stored
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CHAPTER 19 INSTRUCTION SET OVERVIEW
19.2 Operation List
Mnemonic
MOV
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
r ← byte
r, #byte
saddr, #byte
sfr, #byte
A, r
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r ← A
r, A
A ← (saddr)
(saddr) ← A
A ← sfr
A, saddr
saddr, A
A, sfr
sfr ← A
sfr, A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
×
×
×
×
×
×
[DE], A
A, [HL]
(HL) ← A
[HL], A
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
A, [HL + byte]
[HL + byte], A
A, X
XCH
Note 2
A ↔ r
A, r
A ↔ (saddr)
A ↔ sfr
A, saddr
A, sfr
A ↔ (DE)
A ↔ (HL)
A, [DE]
A, [HL]
A ↔ (HL + byte)
A, [HL, byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 19 INSTRUCTION SET OVERVIEW
Mnemonic
MOVW
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
rp ← word
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
AX ← (saddrp)
AX, saddrp
saddrp, AX
AX, rp
(saddrp) ← AX
Note
Note
Note
AX ← rp
rp ← AX
rp, AX
AX ↔ rp
XCHW
ADD
AX, rp
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, #byte
saddr, #byte
A, r
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, [HL + byte]
A, #byte
saddr, #byte
A, r
ADDC
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (HL + byte)
A, [HL + byte]
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 19 INSTRUCTION SET OVERVIEW
Mnemonic
SUBC
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
saddr, #byte
A, r
A ← A ∧ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (addr16)
A ← A ∧ (HL)
A ← A ∧ (HL + byte)
A ← A ∨ byte
A, [HL + byte]
A, #byte
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
saddr, #byte
A, r
A ← A ∨ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A ∨ byte
A, [HL + byte]
A, #byte
XOR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
saddr, #byte
A, r
A ← A ∨ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A, [HL + byte]
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 19 INSTRUCTION SET OVERVIEW
Mnemonic
CMP
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A − byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
(saddr) − byte
A − r
saddr, #byte
A, r
A − (saddr)
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A − (addr16)
A − (HL)
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
saddr
r
DEC
(saddr) ← (saddr) − 1
rp ← rp + 1
saddr
rp
INCW
DECW
ROR
rp ← rp − 1
rp
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
×
×
×
×
A, 1
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit ← 1
A.bit
PSW.bit ← 1
×
×
×
×
×
PSW.bit
[HL].bit
saddr.bit
sfr.bit
(HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
CLR1
A.bit ← 0
A.bit
PSW.bit ← 0
×
PSW.bit
[HL].bit
CY
(HL).bit ← 0
CY ← 1
SET1
CLR1
NOT1
1
0
×
CY ← 0
CY
CY ← CY
CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
CALLT
PCL ← (00000000, addr5), SP ← SP − 2
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP),
RETI
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
rp
PSW
4
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
rp
6
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
(saddr) ← (saddr) − 1, then
saddr, $addr16
8
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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19.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte
A
r
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
[HL + byte]
A
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
ADD
ADDC
SUB
SUBC
AND
OR
RORC
ROLC
ADDC
SUB
SUBC
XOR
CMP
AND
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL + byte]
Note Except r = A.
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CHAPTER 19 INSTRUCTION SET OVERVIEW
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW SUBW
CMPW
MOVW
XCHW
MOVW
MOVW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
sp
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16
None
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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CHAPTER 19 INSTRUCTION SET OVERVIEW
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol
Supply voltage
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–10
Unit
V
VDD
µPD78E9860A, 78E9861A only, Note
VPP
VI
V
Input voltage
V
Output voltage
Output current, high
VO
IOH
V
Per pin
mA
mA
mA
mA
°C
°C
°C
Total of all pins
Per pin
–30
Output current, low
IOL
30
Total of all pins
80
Operating ambient temperature
Storage temperature
TA
–40 to +85
−65 to +150
–40 to +125
Tstg
Mask ROM version
EEPROM version
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the
EEPROM (program memory) is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
VDD
0 V
a
b
V
PP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum rating are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
the ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
System Clock Oscillator Characteristics
Ceramic or crystal oscillation (µPD789052, 78E9860A)
(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
1.0
TYP.
MAX.
5.0
Unit
VSS X2
X1
Ceramic resonator
Oscillation frequency VDD = Oscillation
(fX)Note 1
MHz
voltage range
Oscillation
stabilization timeNote 2
After VDD reaches
oscillation voltage
range MIN.
4
ms
V
SS X2
X1
Crystal resonator
External clock
Oscillation frequency
(fX)Note 1
1.0
5.0
30
MHz
ms
Oscillation
stabilization timeNote 2
X1 input frequency
(fX)Note 1
1.0
85
5.0
MHz
ns
X1
X2
X1 input high-/low-
level width (tXH, tXL)
500
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Caution When using a ceramic or crystal oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross with other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
Recommended Oscillation Circuit Constants
Ceramic oscillator (TA = −40 to +85°C) (µPD789052)
Manufacturer
Part Number
Frequency Recommended Circuit
Oscillation Voltage
Range (VDD)
Remark
(MHz)
Constant (pF)
C1
100
−
C2
100
−
MIN.
2.0
MAX.
5.5
CSBLA1M00J58-B0Note
CSTCC2M00G56-R0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
CSTCR4M19G53-R0
CSTLS4M19G53-B0
CSTCR4M91G53-R0
CSTLS4M91G53-B0
CSTCR5M00G53-R0
CSTLS5M00G53-B0
1.0
2.0
4.0
Rd = 1.0 kΩ
Murata Mfg.
1.8
5.5
With internal
capacitor
4.194
4.915
5.0
Note When using the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. as the ceramic oscillator, a limiting resistor
(Rd = 1.0 kΩ) is necessary (refer to the figure below). The limiting resistor is not necessary when other
recommended oscillators are used.
X1
X2
Rd
C2
CSBLA1M00J58-B0
C1
Caution The oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer.
If optimization of oscillator characteristics is necessary in the actual application, apply to the
resonator manufacturer for evaluation on the implementation circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use
the µPD789052 so that the internal operating conditions are within the specifications of the DC
and AC characteristics.
Remark For the resonator selection and oscillator constant of the µPD78E9860A, customers are required to
either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
RC oscillation (µPD789062, 78E9861A)
(TA = –40 to +85°C, VDD = 1.8 to 3.6 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
0.85
TYP.
MAX.
1.15
Unit
CL1
CL2
RC oscillator
Oscillation frequency VDD = Oscillation
(fCC)Notes 1,2
MHz
voltage range
External clock
CL1 input frequency
(fCC)Note 1
1.0
85
5.0
MHz
ns
CL1
CL2
CL1 input high-/low-
level width (tXH, tXL)
500
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Variations due to external resistance and external capacitance are not included.
Caution When using an RC oscillator, wire as follows in the area enclosed by the broken lines in the
above figure to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross with other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
DC Characteristics (µPD789052, 78E9860A) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
10
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
µPD789052
µPD78E9860A
µPD789052
µPD78E9860A
P00 to P07
Output current, low
IOL
Per pin
All pins
40
Per pin
3
All pins
7.5
−1
Output current, high
Input voltage, high
IOH
Per pin
−15
All pins
−0.75
−7.5
VDD
Per pin
All pins
2.7 V≤ VDD ≤ 5.5 V
1.8 V≤ VDD < 2.7 V
2.7 V≤ VDD ≤ 5.5 V
1.8 V≤ VDD < 2.7 V
VIH1
VIH2
0.7VDD
0.9VDD
VDD
V
RESET, P20, P21, P40
to P43
0.8VDD
VDD
V
0.9VDD
VDD
V
VIH3
X1, X2
VDD – 0.1
VDD
V
2.7 V≤ VDD ≤ 5.5 V
1.8 V≤ VDD < 2.7 V
2.7 V≤ VDD ≤ 5.5 V
1.8 V≤ VDD < 2.7 V
Input voltage, low
VIL1
P00 to P07
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
RESET, P20, P21, P40
to P43
0
V
0
V
VIL3
X1, X2
0
V
IOH = –100 µA
IOH = –500 µA
IOL = 400 µA
IOL = 2 mA
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
ILIH1
P00 to P07, P20, P21
VDD – 0.5
VDD – 0.7
V
V
P00 to P07, P20, P21
0.5
0.7
1
V
V
µPD789052
µPD78E9860A
µA
µA
Input leakage current, high
VI = VDD
P00 to P07,
P20, P21,
P40 to P43,
RESET
3
µA
µA
µA
X1, X2
20
−1
−3
ILIH2
ILIL1
µPD789052
Input leakage current, low
VI = 0 V
P00 to P07,
P20, P21,
P40 to P43,
RESET
µPD78E9860A
−20
1
µA
µA
µA
µA
µA
kΩ
ILIL2
X1, X2
µPD789052
Output leakage current, high
Output leakage current, low
Mask-option pull-up resistor
ILOH
VO = VDD
VO = 0 V
µPD78E9860A
µPD789052
3
−1
−3
200
ILOL
µPD78E9860A
VIN = 0 V, P40 to P43, µPD789052 only
R
50
100
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
DC Characteristics (µPD789062, 78E9861A) (TA = –40 to +85°C, VDD = 1.8 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
10
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
µPD789062
µPD78E9861A
µPD789062
µPD78E9861A
P00 to P07
Output current, low
IOL
Per pin
All pins
40
Per pin
2
All pins
5.0
−1
Output current, high
Input voltage, high
IOH
Per pin
−15
−0.5
−5.0
VDD
All pins
Per pin
All pins
2.7 V≤ VDD ≤ 3.6 V
1.8 V≤ VDD < 2.7 V
2.7 V≤ VDD ≤ 3.6 V
1.8 V≤ VDD < 2.7 V
VIH1
VIH2
0.7VDD
0.9VDD
VDD
V
RESET, P20, P21, P40
to P43
0.8VDD
VDD
V
0.9VDD
VDD
V
VIH3
CL1, CL2
VDD – 0.1
VDD
V
2.7 V≤ VDD ≤ 3.6 V
1.8 V≤ VDD < 2.7 V
2.7 V≤ VDD ≤ 3.6 V
1.8 V≤ VDD < 2.7 V
Input voltage, low
VIL1
P00 to P07
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
RESET, P20, P21, P40
to P43
0
V
0
V
VIL3
CL1, CL2
0
V
IOH = –100 µA
IOH = –500 µA
IOL = 400 µA
IOL = 2 mA
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
ILIH1
P00 to P07, P20, P21
VDD – 0.5
VDD – 0.7
V
V
P00 to P07, P20, P21
0.5
0.7
1
V
V
µPD789062
µPD78E9861A
µA
µA
Input leakage current, high
VI = VDD
P00 to P07,
P20, P21,
P40 to P43,
RESET
3
µA
µA
µA
ILIH2
CL1, CL2
20
−1
−3
µPD789062
Input leakage current, low
ILIL1
VI = 0 V
P00 to P07,
P20, P21,
P40 to P43,
RESET
µPD78E9861A
−20
1
µA
µA
µA
µA
µA
kΩ
ILIL2
CL1, CL2
µPD789062
Output leakage current, high
Output leakage current, low
Mask-option pull-up resistor
ILOH
VO = VDD
VO = 0 V
µPD78E9861A
µPD789062
3
−1
−3
200
ILOL
µPD78E9861A
VIN = 0 V, P40 to P43, µPD789062 only
R
50
100
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V (for µPD789052), VDD = 1.8 to 3.6 V (for
µPD789062))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
2.6
1.0
0.7
1.8
0.6
0.5
3.0
0.9
0.8
0.8
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply currentNote
Ceramic/crystal oscillation:
µPD789052
IDD1
1.0
5.0 MHz
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 3.0 V 10%
Crystal oscillation
operating mode
C1 = C2 = 22 pF
0.5
0.3
5.0 MHz
IDD2
IDD3
IDD4
0.6
Crystal oscillation
HALT mode
0.25
0.22
0.1
C1 = C2 = 22 pF
STOP mode
µA
0.05
0.05
0.3
µA
Power supply currentNote
mA
1.0 MHz 15%
RC oscillation: µPD789062
RC oscillation
operating mode
R = 24 kΩ, C = 30 pF
VDD = 2.0 V 10%
VDD = 3.0 V 10%
0.26
0.25
0.6
0.6
mA
mA
1.0 MHz 15%
RC oscillation HALT
mode
IDD5
VDD = 2.0 V 10%
0.22
0.5
mA
R = 24 kΩ, C = 30 pF
VDD = 3.0 V 10%
VDD = 2.0 V 10%
µA
µA
IDD6
STOP mode
0.05
0.05
0.9
0.8
Note Port current (including current flowing in on-chip pull-up resistors) is not included.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
DC Characteristics
(TA = –40 to +85°C, VDD = 1.8 to 5.5 V (µPD78E9860A), VDD = 1.8 to 3.6 V (µPD78E9861A))
Parameter
Symbol
Conditions
MIN.
TYP.
2.5
MAX.
5.0
Unit
mA
Power supply currentNote
Ceramic/crystal oscillation:
µPD78E9860A
IDD1
5.0 MHz
VDD = 5.0 V 10%
VDD = 5.0 V 10%
VDD = 5.0 V 10%
crystal oscillation operating
mode (EEPROM halted)
C1 = C2 = 22 pF
IDD2
IDD3
IDD4
5.0 MHz
3.0
1.6
6.0
3.2
mA
mA
crystal oscillation operating
mode (EEPROM operating)
C1 = C2 = 22 pF
5.0 MHz
crystal oscillation HALT mode
(EEPROM halted)
C1 = C2 = 22 pF
µA
µA
µA
µA
µA
µA
µA
mA
STOP mode
(POC operating)
VDD = 5.0 V
TA = −40 to +85°C
1.2
1.0
4.0
2.5
3.0
2.0
3.0
1.5
0.9
1.6
VDD = 3.0 V 10%
TA = −40 to +85°C
VDD = 5.0 V
TA = −20 to +75°C
VDD = 3.0 V 10%
TA = −20 to +75°C
1.0
IDD5
STOP mode
VDD = 5.0 V
TA = −40 to +85°C
(POC operation halted)
VDD = 3.0 V 10%
TA = −40 to +85°C
VDD = 5.0 V
TA = 25°C
Power supply currentNote
RC oscillation:
µPD78E9861A
IDD1
IDD2
IDD3
IDD4
1.0 MHz
0.8
1.0
0.7
VDD = 3.0 V 10%
VDD = 3.0 V 10%
VDD = 3.0 V 10%
RC oscillation operating mode
(EEPROM halted)
R = 24 kΩ, C = 30 pF
1.0 MHz
2.0
1.4
mA
mA
RC oscillation operating mode
(EEPROM operating)
R = 24 kΩ, C = 30 pF
1.0 MHz
RC oscillation HALT mode
(EEPROM halted)
R = 24 kΩ, C = 30 pF
VDD = 3.0 V 10%
TA = −40 to +85°C
µA
µA
µA
STOP mode
(POC operating)
1.0
1.0
2.5
2.0
1.5
VDD = 3.0 V 10%
TA = –20 to +75°C
VDD = 3.0 V 10%
IDD5
STOP mode
(POC operation halted)
Note Port current (including current flowing in on-chip pull-up resistors) is not included. This current will be further
added to when writing to or reading from EEPROM (data memory). For the specific current values, refer to
EEPROM (Data Memory) Characteristics.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
AC Characteristics
(1) µPD789052, 78E9860A (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions
2.7 V ≤ VDD ≤ 5.5 V
MIN.
0.4
TYP.
MAX.
8
Unit
µs
Cycle time
TCY
(minimum instruction execution
time)
1.8 V ≤ VDD < 2.7 V
µs
1.6
8
Ceramic/crystal oscillation
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
KR10 to KR13
TMI input
fTI
0
4.0
MHz
kHz
µs
input frequency
0
500
TMI
tTIH,
0.1
1.0
10
high-/low-level width
tTIL
µs
µs
Key return input pin
low-level width
tKRIL
tRSL
µs
RESET
10
low-level width
TCY vs. VDD (System Clock: Ceramic/Crystal Oscillation)
60
20
10
µ
Guaranteed
operation range
2.0
1.0
0.5
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD (V)
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
(2) µPD789062, 78E9861A (TA = –40 to +85°C, VDD = 1.8 to 3.6 V)
Parameter
Symbol
TCY
Conditions
2.7 V ≤ VDD ≤ 3.6 V
MIN.
0.4
TYP.
MAX.
9.42
Unit
µs
Cycle time
(minimum instruction execution
time)
1.8 V ≤ VDD < 2.7 V
µs
1.6
9.42
RC oscillation
2.7 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.7 V
KR10 to KR13
TMI input
fTI
0
4.0
MHz
kHz
µs
input frequency
0
500
TMI
tTIH,
0.1
1.0
10
high-/low-level width
tTIL
µs
µs
Key return input pin
low-level width
tKRIL
tRSL
µs
RESET
10
low-level width
TCY vs. VDD (System Clock: RC Oscillation)
60
20
10
µ
Guaranteed
operation
range
2.0
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD (V)
(3) RC oscillation frequency characteristics (TA = –40 to +85°C, VDD = 1.8 to 3.6 V) (µPD789062, 78E9861A
only)
Parameter
Symbol
Conditions
R = 24 kΩ, C = 30 pF
MIN.
0.85
TYP.
1.00
MAX.
1.15
Unit
Oscillation frequencyNote
fCC
MHz
Note Variations due to external resistance and external capacitance are not included.
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
AC Timing Measurement Points (Excluding X1, CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Points of measurement
Clock Timing
1/fCLK
t
XL
t
XH
V
IH3 (MIN.)
X1 (CL1) input
VIL3 (MAX.)
Remark fCLK: fX or fCC
TMI Timing
1/fTI
tTIL
tTIH
TMI
Key Return Input Timing
t
KRIL
KR10 to KR13
RESET Input Timing
t
RSL
RESET
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
Power-on-Clear Circuit Characteristics (µPD78E9860A, 78E9861A only)
(1) POC
(a) DC characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V (µPD78E9860A), VDD = 1.8 to 3.6 V
(µPD78E9861A))
Parameter
Detection voltage
Symbol
Conditions
MIN.
TYP.
MAX.
2.0
Unit
V
VPOC
Response timeNote 1: 2 ms
1.8Note 2
1.9Note 2
Notes 1. Time from detecting voltage until output reverses and time until stable operation after transition from
halted state to operating state.
2. Note that the POC detection voltage may be lower than the operating voltage range of these products.
(b) AC characteristics (TA = –40 to +85°C)
Parameter
Power rise time
Symbol
TPth1
Conditions
MIN.
0.01
10
TYP.
MAX.
100
Unit
ms
µs
VDD: 0 → 1.8 V
VDD: 0 → 1.8 V
TA = +25°C
TPth2
(2) LVI
(a) DC characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V (µPD78E9860A), VDD = 1.8 to 3.6 V
(µPD78E9861A))
Parameter
LVI7 detection voltage
LVI6 detection voltage
LVI5 detection voltage
LVI4 detection voltage
LVI3 detection voltage
LVI2 detection voltage
LVI1 detection voltage
LVI0 detection voltage
Symbol
VLVI7
VLVI6
Conditions
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
Response timeNote 1: 2 ms
MIN.
2.4
TYP.
2.6
MAX.
2.8
Unit
V
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
2.0
V
VLVI5
VLVI4
VLVI3
VLVI2
VLVI1
VLVI0
V
V
V
V
V
Note 3
2.2
V
Notes 1. Time from detecting voltage until output reverses and time until stable operation after transition from
halted state to operating state
2. Relative relationship: VLVI7 > VLVI6 > VLVI5 > VLVI4 > VLVI3 > VLVI2 > VLVI1 > VLVI0
3. VPOC < VLVI0
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
EEPROM (Data Memory) Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V (µPD78E9860A),
VDD = 1.8 to 3.6 V (µPD78E9861A))
Parameter
Write timeNote 1
Number of overwrites
Symbol
Conditions
MIN.
3.3
TYP.
MAX.
6.6
Unit
ms
Per 32 bytes
Per 4 KB
10
10,000
times
100
times
Note Write time = T × 145 (T = time of 1 clock cycle selected by EWCS100 to EWCS102)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
µPD789052, 78E9860A
µPD789062, 78E9861A
STOP release by RESET pin
MIN.
1.8
1.8
10
TYP.
MAX.
5.5
Unit
V
Data retention power supply
voltage
VDDDR
3.6
V
µs
Release signal set time
tSREL
Data Retention Timing
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
V
DDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
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CHAPTER 20 ELECTRICAL SPECIFICATIONS
Oscillation Stabilization Wait Time
(a) Ceramic/crystal oscillation (TA = −40 to 85°C, VDD = 1.8 to 5.5 V) (µPD789052, 78E9860A)
Parameter
Symbol
Conditions
MIN.
TYP.
215/fX
MAX.
Unit
s
Oscillation wait timeNote 1
tWAIT
STOP release by RESET or reset
release by POC
Release by interrupt
Note 2
s
Notes 1. Time required to stabilize oscillation after a reset or STOP mode release.
2. 212/fX, 215/fX, or 217/fX can be selected using bits 0 to 2 of the oscillation stabilization time selection
register (OSTS0 to OSTS2).
(b) RC oscillation (TA = −40 to +85°C, VDD = 1.8 to 3.6 V) (µPD789062, 78E9861A)
Parameter
Symbol
Conditions
MIN.
TYP.
27/fCC
MAX.
Unit
s
Oscillation wait timeNote
tWAIT
STOP release by RESET or reset
release by POC
Release by interrupt
27/fCC
s
Note Time required to stabilize oscillation after a reset or STOP mode release.
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CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS
(REFERENCE VALUES)
fCC vs. VDD (RC Oscillation: µPD789062, R = 24 kΩ, C = 30 pF)
(TA = 25˚C)
CL1
CL2
24 kΩ
1.10
1.05
1.0
30 pF
Sample A
Sample B
Sample C
0.95
0.90
1.5
2.0
3.0
4.0
Supply voltage VDD [V]
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User’s Manual U15861EJ3V1UD
CHAPTER 22 PACKAGE DRAWING
20-PIN PLASTIC SSOP (7.62 mm (300))
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
I
J
S
N
S
K
C
B
M
D
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
6.65 0.15
0.475 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
S20MC-65-5A4-2
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User’s Manual U15861EJ3V1UD
CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
The µPD789052, 789062, 78E9860A, and 78E9861A should be soldered and mounted under the following
recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index/html)
Table 23-1. Surface Mounting Type Soldering Conditions (1/2)
µPD789052MC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))
µPD789062MC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-00-3
VP15-00-3
WS60-00-1
−
Count: three times or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: three times or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering method together (except for partial heating).
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CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
Table 23-1. Surface Mounting Type Soldering Conditions (2/2)
µPD78E9860AMC-5A4: 20-pin plastic SSOP (7.62 mm (300))
µPD78E9861AMC-5A4: 20-pin plastic SSOP (7.62 mm (300))
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake
at 125°C for 10 hours)
IR35-103-2
VP15-103-2
WS60-103-1
−
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at
125°C for 10 hours)
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering method together (except for partial heating).
µPD789052MC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))
µPD789062MC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))
µPD78E9860AMC-5A4-A:
µPD78E9861AMC-5A4-A:
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at
125°C for 20 to 72 hours)
Infrared reflow
Wave soldering
IR60-207-3
−
When the pin pitch of the package is 0.65 mm or more, wave soldering can also
be performed.
For details, contact an NEC Electronics sales representative.
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
Partial heating
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by "-A" are lead-free products.
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789052, 789062
Subseries. Figure A-1 shows development tools.
• Compatibility with PC98-NX Series
Unless stated otherwise, products which are supported for IBM PC/ATTM and compatibles can also be used with
the PC98-NX Series. When using the PC98-NX Series, therefore, refer to the explanations for IBM PC/AT and
compatibles.
• WindowsTM
Unless stated otherwise, “Windows” refers to the following operating systems.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Ver. 4.0
• Windows XP
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
·
Software package
Language processing software
Debugging software
·
·
·
·
Assembler package
C compiler package
Device file
·
Integrated debugger
System simulator
·
C library source file Note 1
Control software
Project Manager
(Windows version only)Note 2
·
Host machine
(PC or EWS)
Interface adapter
Power supply unit
EEPROM writing environment
Flash programmer
In-circuit emulator
Emulation board
Flash memory
(EEPROM)
writing adapter
EEPROM
(program memory)
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. C library source file is not included in the software package.
2. Project Manager is included in the assembler package.
Project Manager is used only in the Windows environment.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Software tools for development of the 78K/0S Series are combined in this package.
The following tools are included.
Software package
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the OS used
µS××××SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Media
CD-ROM
PC-9800 series, IBM PC/AT
compatible
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object codes that can be executed
by microcontroller.
Assembler package
In addition, automatic functions to generate symbol table and optimize branch instructions
are also provided.
Used in combination with optional device file (DF789062 or DF789861).
<Caution when used under PC environment>
The assembler package is a DOS-based application but may be used under the Windows
environment by using Project Manager of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed
by microcontroller.
C compiler package
Used in combination with optional assembler package (RA78K0S) and device file
(DF789062 or DF789861).
<Caution when used under PC environment>
The C compiler package is a DOS-based application but may be used under the Windows
environment by using Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789062Note 1
DF789861Note 1
Device file
File containing the information inherent to the device.
• DF789062: For µPD789052, 789062
• DF789861: For µPD78E9860A, 78E9861A
Used in combination with optional RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Part number: µS××××DF789062, µS××××DF789861
CC78K0S-LNote 2
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
C library source file
Part number: µS××××CC78K0S-L
Notes 1. DF789062, 789861 are common files that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machines and operating systems to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
BB13
AB17
BB17
3P17
3K17
Host Machine
PC-9800 series,
OS
Supply Media
3.5” 2HD FD
Japanese Windows
English Windows
IBM PC/AT compatible
Japanese Windows
English Windows
CD-ROM
HP9000 series 700TM
SPARCstationTM
HP-UXTM (Rel. 10.10)
SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
µS××××DF789062
µS××××DF789861
µS××××CC78K0S-L
××××
Host Machine
OS
Supply Media
AB13
BB13
3P16
3K13
3K15
PC-9800 series,
Japanese Windows
Japanese Windows
HP-UXTM (Rel. 10.10)
SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
3.5” 2HD FD
IBM PC/AT compatible
HP9000 series 700
SPARCstation
DAT
3.5” 2HD FD
1/4-inch CGMT
A.3 Control Software
PM plus
Control software created for efficient development of the user program in the Windows
environment. User program development operations such as editor startup, build, and
debugger startup can be performed from the Project Manager.
<Caution>
Project Manager
The Project Manager is included in the assembler package (RA78K0S).
The Project Manager is used only in the Windows environment.
A.4 EEPROM (Program Memory) Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcomputers incorporating flash memory (EEPROM)
FA-20MC
Adapter for writing to flash memory (EEPROM) and connected to Flashpro III or Flashpro IV.
• FA-20MC: For 20-pin plastic shrink SOP (MC-5A4 type)
Flash memory (EEPROM)
writing adapter
Remark The FL-PR3, FL-PR4, and FA-20MC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
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APPENDIX A DEVELOPMENT TOOLS
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging hardware and software of application system using the 78K/0S
Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an AC
adapter, emulation probe, and interface adapter for connecting the host machine.
In-circuit emulator
IE-78K0S-NS-A
In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further
enhanced by adding a coverage function and enhancing the tracer and timer functions.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using PC-9800 series PC (except notebook type) as host machine (C
bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using notebook PC as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter
Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus
supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using personal computer incorporating PCI bus as host machine
IE-789860-NS-EM1
Emulation board
Board for emulating the peripheral hardware inherent to the device. Used in combination with in-
circuit emulator.
NP-20GS
Cable to connect the in-circuit emulator and target system.
Used in combination with the EV-9500GS-20.
Emulation probe
EV-9500GS-20 Conversion adapter to connect the NP-20GS and a target system board on which a 20-pin plastic
Conversion
adapter
SSOP can be mounted.
Remark The NP-20GS is a product made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
Integrated debugger
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing with
the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result.
Used in combination with optional device file (DF789062 or DF789861).
Part number: µS××××ID78K0S-NS
SM78K0S
System simulator
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
It can be used to debug the target system at C source level or assembler level while
simulating the operation of the target system on the host machine.
Using SM78K0S, the logic and performance of the application can be verified independently
of hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used
in combination with optional device file (DF789062 or DF789861).
Part number: µS××××SM78K0S
DF789062Note
DF789861Note
Device file
File containing the information inherent to the device.
• DF789062: For µPD789052, 789062
• DF789861: For µPD78E9860A, 78E9861A
Used in combination with the optional RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Part number: µS××××DF789062, µS××××DF789861
Note DF789062, 789861 are common files that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
Remark ×××× in the part number differs depending on the operating systems and supply medium to be used.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
BB13
AB17
BB17
Host Machine
PC-9800 series
IBM PC/AT compatibles
OS
Japanese Windows
English Windows
Japanese Windows
English Windows
Supply Media
3.5” 2HD FD
CD-ROM
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
The following shows the conditions when connecting the emulation probe to the conversion socket. Follow the
configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Among the products described in this appendix, NP-20GS is a product of Naito Densei Machida Mfg. Co., Ltd.
Table B-1. Distance Between IE System and Conversion Socket
Emulation Probe
NP-20GS
Conversion Socket
EV-9500GS-20
Distance Between IE System and Conversion Socket
185 mm
Figure B-1. Distance Between In-Circuit Emulator and Conversion Socket
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789860-NS-EM1
185 mm
Emulation probe
NP-20GS
CN1
Conversion socket
EV-9500GS-20
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-2. Connection Conditions of Target System
Emulation board
IE-789860-NS-EM1
Conversion socket
EV-9500GS-20
Emulation probe
NP-20GS
15 mm
30 mm
100 mm
Target system
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APPENDIX C REGISTER INDEX
C.1 Register Name Index (in Alphabetical Order)
[B]
Bit sequential buffer 10 data registers L, H (BSFRL10, BSFRH10)......................................................................133
Bit sequential buffer output control register 10 (BSFC10) ....................................................................................134
[C]
[E]
Carrier generator output control register 40 (TCA40) .............................................................................................93
EEPROM write control register 10 (EEWC10)........................................................................................................60
8-bit compare register 30 (CR30) ...........................................................................................................................89
8-bit compare register 40 (CR40) ...........................................................................................................................89
8-bit compare register H40 (CRH40)......................................................................................................................89
8-bit timer counter 30 (TM30).................................................................................................................................89
8-bit timer counter 40 (TM40).................................................................................................................................89
8-bit timer mode control register 30 (TMC30).........................................................................................................91
8-bit timer mode control register 40 (TMC40).........................................................................................................92
[I]
Interrupt mask flag register 0 (MK0) .....................................................................................................................141
Interrupt request flag register 0 (IF0)....................................................................................................................141
[L]
Low-voltage detection level selection register 1 (LVIS1) ......................................................................................129
Low-voltage detection register 1 (LVIF1)..............................................................................................................129
[O]
Oscillation stabilization time selection register (OSTS) ........................................................................................151
[P]
Port 0 (P0)..............................................................................................................................................................66
Port 2 (P2)..............................................................................................................................................................67
Port 4 (P4)..............................................................................................................................................................68
Port mode register 0 (PM0) ....................................................................................................................................69
Port mode register 2 (PM2) ..............................................................................................................................69, 94
Power-on-clear register 1 (POCF1)......................................................................................................................128
Processor clock control register (PCC).............................................................................................................72, 79
[T]
Timer clock selection register 2 (TCL2)................................................................................................................122
[W]
Watchdog timer mode register (WDTM)...............................................................................................................123
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APPENDIX C REGISTER INDEX
C.2 Register Symbol Index (in Alphabetical Order)
[B]
[C]
BSFC10: Bit sequential buffer output control register 10......................................................................................134
BSFRH10: Bit sequential buffer 10 data register H ..............................................................................................133
BSFRL10: Bit sequential buffer 10 data register L................................................................................................133
CR30: 8-bit compare register 30.............................................................................................................................89
CR40: 8-bit compare register 40.............................................................................................................................89
CRH40: 8-bit compare register H40 .......................................................................................................................89
[E]
[I]
EEWC10: EEPROM write control register 10 .........................................................................................................60
IF0: Interrupt request flag register 0 .....................................................................................................................141
[L]
LVIF1: Low-voltage detection register 1 ...............................................................................................................129
LVIS1: Low-voltage detection level selection register 1........................................................................................129
[M]
MK0: Interrupt mask flag register 0.......................................................................................................................141
[O]
OSTS: Oscillation stabilization time selection register..........................................................................................151
[P]
P0: Port 0.... ...........................................................................................................................................................66
P2: Port 2.... ...........................................................................................................................................................67
P4: Port 4.... ...........................................................................................................................................................68
PCC: Processor clock control register..............................................................................................................72, 79
PM0: Port mode register 0......................................................................................................................................69
PM2: Port mode register 2................................................................................................................................69, 94
POCF1: Power-on-clear register 1 .......................................................................................................................128
[T]
TCA40: Carrier generator output control register 40...............................................................................................93
TCL2: Timer clock selection register 2 .................................................................................................................122
TM30: 8-bit timer counter 30...................................................................................................................................89
TM40: 8-bit timer counter 40...................................................................................................................................89
TMC30: 8-bit timer mode control register 30 ..........................................................................................................91
TMC40: 8-bit timer mode control register 40 ..........................................................................................................92
[W]
WDTM: Watchdog timer mode register ................................................................................................................123
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APPENDIX D REVISION HISTORY
Revisions up to this edition are shown below. The “Applied to” column indicates the chapter in each edition to
which the revision was applied.
(1/2)
Edition
2nd
Description
Deletion of µPD78E9860 and 78E9861
Applied to
Throughout
Addition of µPD78E9860A and 78E9861A
Addition of description of pin handling to 3.2.9 VPP (µPD78E9860A, 78E9861A
CHAPTER 3 PIN FUNCTIONS
only)
9.2 8-Bit Timers 30 and 40 Configuration
CHAPTER 9 8-BIT TIMERS 30
AND 40
• Modification of Figure 9-3 Block Diagram of Output Controller (Timer 40)
• Addition of description to (2) 8-bit compare register 40 (CR40)
• Addition of description to (3) 8-bit compare register H40 (CRH40)
Addition of Cautions to Figure 9-6 Format of Carrier Generator Output Control
Register 40
Addition of Cautions and description to 9.4.3 Operation as carrier generator
9.5 Notes on Using 8-Bit Timers 30 and 40
• Modification of description of (1) Error on starting timer
• Addition of (2) Count value if external clock input from TMI pin is selected
Modification of Figure 11-1 Block Diagram of Power-on-Clear Circuit
Modification of Figure 11-2 Block Diagram of Low-Voltage Detection Circuit
Addition of Note to 11.4.1 Power-on-clear (POC) circuit operation
Addition of Caution to 11.4.2 Operation of low-voltage detection (LVI) circuit
CHAPTER 11 POWER-ON-
CLEAR CIRCUITS
(µPD78E9860A, 78E9861A ONLY)
Addition of Caution to Figure 14-2 Format of Interrupt Request Flag Register 0 CHAPTER 14 INTERRUPT
FUNCTIONS
CHAPTER 17 µPD78E9860A,
Total revision of 17.1 EEPROM Features (Program Memory)
78E9861A
Addition of chapter
CHAPTER 20 ELECTRICAL
SPECIFICATIONS
CHAPTER 21 EXAMPLE OF RC
OSCILLATION FREQUENCY
CHARACTERISTICS
(REFERENCE VALUES)
CHAPTER 22 PACKAGE
DRAWING
CHAPTER 23 RECOMMENDED
SOLDERING CONDITIONS
Addition of Flashpro IV to A.4 EEPROM (Program Memory) Writing Tools
Addition of notes on target system design
APPENDIX A DEVELOPMENT
TOOLS
APPENDIX B NOTES ON
TARGET SYSTEM DESIGN
Addition of revision history
APPENDIX D REVISION
HISTORY
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APPENDIX D REVISION HISTORY
(2/2)
Edition
3 rd
Description
Applied to
• Update of 1.5 78K/0S Series Lineup and 2.5 78K/0S Series Lineup to latest
CHAPTER 1 GENERAL
(µPD789052 SUBSERIES)
version
CHAPTER 2 GENERAL
(µPD789062 SUBSERIES)
• Deletion of non-selectable clock settings
CHAPTER 5 EEPROM (DATA
MEMORY) (µPD78E9860A,
78E9861A ONLY)
• Addition of Notes to Figure 5-2 Format of EEPROM Write Control Register
10
• Modification of description of (8) in 5.4 Notes for EEPROM Writing
• Addition of description “output to EEPROM” to Figure 9-2 Block Diagram of
CHAPTER 9 8-BIT TIMERS 30
AND 40
Timer 40
• Modification of a caution in Figure 14-3 Format of Interrupt Mask Flag
CHAPTER 14 INTERRUPT
FUNCTIONS
Register 0
• Modification of a signal name in Figure 14-6 Timing of Non-Maskable
Interrupt Request Acknowledgment
• Specification of non-maskable interruption for HALT release in 15.2.1 HALT
Mode
CHAPTER 15 STANDBY
FUNCTIONS
• Addition of non-maskable interruption for STOP release to 15.2.2 STOP Mode
• Addition of descriptions of oscillation stabilization time in Table 17-1
CHAPTER 17 µPD78E9860A,
Differences Between µPD78E9860A, 78E9861A and Mask ROM Versions
78E9861A
• Modification of description of CLK connection in Table 17-3 Pin Connection
List
• Modification of condition of supply currents of µPD78E9860A in DC
CHAPTER 20 ELECTRICAL
SPECIFICATIONS
Characteristics
• Modification of soldering conditions of µPD789052 and 789062 in Table 23-1
CHAPTER 23 RECOMMENDED
SOLDERING CONDITIONS
Surface Mounting Type Soldering Conditions
• Addition of lead-free products
3 rd
CHAPTER 1 GENERAL
(µPD789052 SUBSERIES)
(modification
version)
CHAPTER 2 GENERAL
(µPD789062 SUBSERIES)
• Addition of soldering conditions of lead-free products in Table 23-1 Surface
CHAPTER 23 RECOMMENDED
SOLDERING CONDITIONS
Mounting Type Soldering Conditions
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User’s Manual U15861EJ3V1UD
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