X9319WS8IT1 [RENESAS]
10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDSO8, PLASTIC, SOIC-8;
| 型号： | X9319WS8IT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDSO8, PLASTIC, SOIC-8 光电二极管 转换器 电阻器 |
| 文件： | 总8页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9319
FN8185
Rev 3.00
July 31, 2014
Digitally Controlled Potentiometer (XDCP™)
The Intersil X9319 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
Features
• Solid-state potentiometer
• 3-wire serial interface
• Terminal voltage, 0 to +10V
• 100 wiper tap points
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 99 resistive elements
- Temperature compensated
- End-to-end resistance range ±20%
• Low power CMOS
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
- V
CC
= 5V
- Active current, 3mA max.
- Standby current, 1mA max.
Applications
• High reliability
• LCD bias control
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• DC bias adjustment
• Gain and offset trim
• Laser diode bias control
• Voltage regulator output control
• R
value = 10kΩ
TOTAL
• Package
- 8 Ld SOIC
• Pb-free (RoHS compliant)
Block Diagram
U/D
INC
R
99
H
UP/DOWN
COUNTER
V
(SUPPLY VOLTAGE)
CC
CS
98
97
96
R
R
UP/DOWN
(U/D)
H
7-BIT
NONVOLATILE
MEMORY
CONTROL
AND
MEMORY
ONE OF
INCREMENT
(INC)
W
ONE
HUNDRED
DECODER
WIPER
SWITCHES
RESISTOR
ARRAY
DEVICE SELECT
(CS)
R
L
2
STORE AND
RECALL
CONTROL
CIRCUITRY
V
(GROUND)
1
0
SS
V
CC
SS
V
GENERAL
R
R
L
W
DETAILED
FN8185 Rev 3.00
July 31, 2014
Page 1 of 8
X9319
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PACKAGE
(Pb-Free)
PART MARKING
R
(kΩ)
TEMP RANGE (°C)
0 to +70
PKG. DWG. #
M8.15E
M8.15E
TOTAL
X9319WS8Z
X9319W Z
X9319W ZI
10
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil)
X9319WS8IZ
NOTES:
-40 to +85
1. Add "T1" suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9319. For more information on MSL, please see tech brief TB363.
Pin Configuration
X9319
(8 LD SOIC)
TOP VIEW
V
INC
U/D
R
1
2
3
4
8
7
6
5
CC
CS
R
L
H
V
R
SS
W
Pin Descriptions
SOIC
SYMBOL
BRIEF DESCRIPTION
1
2
3
4
5
6
7
8
INC
Increment. Toggling INC while CS is low moves the wiper either up or down.
Up/Down. The U/D input controls the direction of the wiper movement.
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
Ground.
U/D
R
H
V
SS
R
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
Chip Select. The device is selected when the CS input is LOW, and deselected when CS is high.
Supply Voltage.
W
R
L
CS
V
CC
FN8185 Rev 3.00
July 31, 2014
Page 2 of 8
X9319
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D and V
with respect to V . . . . -1V to +7V
SS
Junction Temperature under bias . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CC
R , R , R to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V
H
W
L
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Potentiometer Characteristics
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 7) (Note 8) (Note 7)
UNIT
%
End-to-end resistance tolerance
See ordering information for values
-20
+20
10
V
/
R /R terminal voltage
V
= 0V
V
V
RH RL
H
L
SS
SS
Power rating
25
mW
W
R
Wiper resistance
Wiper current (Note 9)
Noise (Note 11)
I
= 1mA
W
40
200
+3.0
W
I
See test circuit
Ref: 1kHz
-3.0
mA
dBV
%
W
-120
1
Resolution
Absolute linearity (Note 4)
V(RH) = 10V,
V(RL) = 0V
-1
+1
MI
(Note 6)
Relative linearity (Note 5)
-0.2
+0.2
MI
(Note 6)
R
temperature coefficient (Note 9)
±300
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric temperature coefficient (Notes 9, 10)
Potentiometer capacitances
-20
4.5
+20
5.5
C /C /C
W
See “Equivalent Circuit” on page 4
10/10/25
H
L
(Note 9)
V
Supply Voltage
V
CC
D.C. Operating Characteristics
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 7) (Note 8) (Note 7) UNIT
I
V
active current (Increment)
CS = V , U/D = V or V and
1
3
mA
µA
CC
CC
IL IL IH
INC = 0.4V/2.4V at min. t
CYC
R , R , R not connected
L
H
W
I
Standby supply current
CS 2.4V, U/D and INC = 0.4V
300
1000
+10
SB
R , R , R not connected
L
H
W
I
CS, INC, U/D input leakage current
CS, INC, U/D input HIGH voltage
CS, INC, U/D input LOW voltage
CS, INC, U/D input capacitance
V
= V to V
SS CC
-10
2
µA
V
LI
IN
V
V
+ 1
IH
CC
0.8
10
V
-1
V
IL
C
V
= 5V, V = V , T = +25°C, f = 1MHz
IN SS
pF
IN
CC
A
(Note 9)
Endurance and Data Retention
PARAMETER
V
= 5V ±10%, T = Full Operating Temperature Range
A
CC
MIN
100,000
100
UNIT
Minimum endurance
Data retention
Data changes per bit
Years
FN8185 Rev 3.00
July 31, 2014
Page 3 of 8
X9319
Test Circuit
Equivalent Circuit
AC Conditions of Test
Input pulse levels
0.8V to 2V
10ns
R
TOTAL
TEST POINT
R
Input rise and fall times
Input reference levels
R
L
H
C
L
C
W
C
1.4V
H
10pF
R
W
FORCE
25pF
CURRENT
10pF
R
W
A.C. Operating Characteristics
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 7)
(Note 8)
(Note 7)
UNIT
ns
t
CS to INC setup
100
100
1
Cl
t
(Note 9) INC HIGH to U/D change
(Note 9) U/D to INC setup
ns
lD
t
µs
DI
t
INC LOW period
1
µs
lL
t
t
INC HIGH period
1
µs
lH
lC
INC inactive to CS inactive
CS deselect time (STORE)
CS deselect time (NO STORE)
1
µs
t
20
1
ms
µs
CPHS
t
CPHNS
(Note 9)
t
(Note 9) INC to R change
100
500
500
µs
µs
µs
IW
W
t
INC cycle time
4
CYC
t
t
INC input rise and fall time
R, F
(Note 9)
t
(Note 9) Power-up to wiper stable
500
50
µs
PU
t
V
V power-up rate
CC
0.2
V/ms
R
CC
(Note 9)
NOTES:
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
) - V(R
)]/MI
W(n)(actual)
W(n)(expected)
V(R
) = n(V(R ) - V(R ))/99 + V(R ), with n from 0 to 99.
H L L
W(n)(expected)
5. Relative linearity is a measure of the error in step size between taps = [V(R
) - (V(R ) - MI)]/MI.
W(n)
W(n+1)
6. 1 Ml = Minimum Increment = [V(R ) - V(R )]/99.
H
L
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Typical values are for T = +25°C and nominal supply voltage.
A
9. Guaranteed by device characterization.
6
10. Ratiometric temperature coefficient = (V(R
0 to 99.
)
- V(R
)
)/[V(R (T1 - T2) x 10 ], with T1 and T2 being 2 temperatures, and n from
)
W T1(n)
W T2(n)
W T1(n)
11. Measured with wiper at tap position 31, R grounded, using test circuit.
L
Power-Up and Down Requirements
In order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS and INC high before or
not fully apply until 1 millisecond after V
reaches its final
CC
ramp spec is always in effect.
value. The V
CC
concurrently with the V
pin on power-up. The potentiometer
CC
voltages must be applied after this sequence is completed.
During power-up, the data sheet parameters for the DCP do
FN8185 Rev 3.00
July 31, 2014
Page 4 of 8
X9319
A.C. Timing
CS
t
CYC
t
CPHNS
t
t
t
t
t
CPHS
CI
IL
IH
IC
90%
90%
INC
U/D
10%
t
t
t
t
R
ID
DI
F
t
IW
(3)
MI
R
W
The contents of the counter can be stored in nonvolatile
memory and retained for future use. The resistor array is
comprised of 99 individual resistors connected in series.
Electronic switches at either end of the array and between
each resistor provide an electrical connection to the wiper pin,
Pin Descriptions
R and R
H
L
The high (R ) and low (R ) terminals of the X9319 are
H
L
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R and R references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
L
H
R .
W
The wiper acts like its mechanical equivalent and does not
move beyond the first or last position. That is, the counter does
not wrap around when clocked to either extreme.
R
W
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions. If the wiper is moved several positions, multiple taps
R
is the wiper terminal and is equivalent to the movable
W
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40Ω.
are connected to the wiper for t (INC to V change). The
IW
W
R
value for the device can temporarily be reduced by a
TOTAL
Up/Down (U/D)
significant amount if the wiper is moved several positions.
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
When the device is powered down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is set to the value last stored.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW, the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH-to-LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) the seven bit counter.
The output of this counter is decoded to select one of one
hundred wiper positions along the resistive array.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete the X9319 will be placed in the low
power standby mode until the device is selected once again.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
Principles of Operation
There are three sections of the X9319: the control section, the
nonvolatile memory, and the resistor array. The control section
operates just like an up/down counter. The output of this
counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
The system may select the X9319, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
FN8185 Rev 3.00
July 31, 2014
Page 5 of 8
X9319
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-up/down cycle recalled the
previously stored data. This procedure allows the system to
always power-up to a preset value stored in nonvolatile
memory; then during system operation minor adjustments
could be made. The adjustments might be based on user
preference, system parameter changes due to temperature
drift, etc.
Mode Selection (Continued)
CS
INC
U/D
MODE
H
X
Store wiper position to
nonvolatile memory
H
X
L
X
X
Standby
No store, return to standby
L
L
H
L
Wiper Up (not recommended)
Wiper Down
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
(not recommended)
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
Mode Selection
CS
INC
U/D
MODE
1. The variability and reliability of a solid-state potentiometer
2. The flexibility of computer-based digital controls
L
H
Wiper up
3. The retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.
L
L
Wiper down
Basic Configurations of Electronic Potentiometers
V
REF
V
REF
R
H
R
W
R
L
I
FIGURE 2. TWO TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
FIGURE 1. THREE TERMINAL POTENTIOMETER; VARIABLE
VOLTAGE DIVIDER
Basic Circuits
+V
+V
+8V
R
R
2
1
R
1
V
S
+V
X
+5V
R
W
R
LMC7101
V
W
-
+
-
V
100k
REF
V
+V
O
OUT
+
+10V
LMC7101
R
W
100k
(a)
(b)
V
= V /R
V = (R /R )V
O 2 1 S
OUT
W
W
FIGURE 3. BUFFERED REFERENCE VOLTAGE
FIGURE 4. CASCADING TECHNIQUES
FIGURE 5. SINGLE SUPPLY
INVERTING AMPLIFIER
FN8185 Rev 3.00
July 31, 2014
Page 6 of 8
X9319
Basic Circuits (Continued)
R
R
2
1
V
S
LT311A
V
V (REG)
O
317
IN
+12V
V
-
S
100kΩ
V
O
-
+
R
1
V
O
+
I
adj
LMC7101
10kΩ
10kΩ
R
2
R
R
1
2
10kΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
+15V
= {R /(R +R )} V (min)
V
(REG) = 1.25V (1+R /R )+I
R
2
1 1 2 O
O
2
1
adj
FIGURE 6. VOLTAGE REGULATOR
FIGURE 7. OFFSET VOLTAGE ADJUSTMENT
FIGURE 8. COMPARATOR WITH
HYSTERESIS
© Copyright Intersil Americas LLC 2005-2014. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8185 Rev 3.00
July 31, 2014
Page 7 of 8
X9319
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN8185 Rev 3.00
July 31, 2014
Page 8 of 8
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