RT6343 [RICHTEK]
暂无描述;型号: | RT6343 |
厂家: | RICHTEK TECHNOLOGY CORPORATION |
描述: | 暂无描述 |
文件: | 总35页 (文件大小:621K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
RT6343
42VIN, 3.5A, Asynchronous Step-Down Converter with Low
Quiescent Current
General Description
Features
Wide Input Voltage Range
The RT6343 is a 3.5A, high-efficiency, peak current mode
control asynchronous step-down converter. The device
operates with input voltages from 4V to 42V. The device
can program the output voltage between 0.8V to VIN. The
low quiescent current design with the integrated low RDS(ON)
of high-side MOSFET achieves high efficiency over the
wide load range. The peak current mode control with simple
external compensation allows the use of small inductors
and results in fast transient response and good loop
stability.
4.5V to 42V
4V to 42V (Soft-start is finished)
Wide Output Voltage Range : 0.8V to VIN
0.8V 1% Reference Accuracy
Peak Current Mode Control
Integrated 80mΩ High-Side MOSFET
Low Quiescent Current : 100μA
Low Shutdown Current : 2.25μA
Adjustable Switching : 100kHz to 2.5MHz
Synchronizable Switching : 300kHz to 2.2MHz
Power Saving Mode (PSM) at Light Load
Low Dropout at Light Loads with Integrated Boot
Recharge FET
The wide switching frequency of 100kHz to 2500kHz allows
for efficiency and size optimization when selecting the
output filter components. The ultra-low minimum on-time
enables constant-frequency operation even at very high
step-down ratios. For switching noise sensitive
applications, it can be externally synchronized from
300kHz to 2200kHz.
Externally Adjustable Soft-Start by Part Number
Option
Power Good Indication by Part Number Option
Enable Control
The RT6343 provides complete protection functions such
as input under-voltage lockout, output under-voltage
protection, output over-voltage protection, over-current
protection, and thermal shutdown. Cycle-by-cycle current
limit provides protection against shorted outputs, and soft-
start eliminates input current surge during start-up. The
RT6343 is available in WDFN-10L 4x4 and SOP-8
(Exposed pad) packages.
Adjustable UVLO Voltage and Hysteresis
Built-In UVLO, UVP, OVP, OCP, OTP
Applications
12V and 24V Power Systems
GPS, Entertainment
Simplified Application Circuit
C
BOOT
C
BOOT
RT6343GSP
RT6343GQW
V
IN
V
IN
VIN
BOOT
SW
VIN
BOOT
SW
L1
L1
C
IN
V
OUT
C
IN
V
OUT
D1
D1
R
R
C
OUT
C
OUT
FB1
R
R
EN
FB1
Enable Signal
PGOOD
EN
Enable Signal
FB
FB
PGOOD
R
RT
FB2
FB2
RT/SYNC
C
COMP1
C
R
COMP
COMP
C
R
COMP
COMP1
C
SS/TR
COMP
GND
R
RT
C
SS
COMP2
COMP2
RT/SYNC
PAD
GND
PAD
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6343-00 October 2019
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1
RT6343
Ordering Information
RT6343
Pin Configuration
(TOP VIEW)
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
8
7
6
5
BOOT
VIN
SW
(WDFN-10L 4x4 only)
2
3
4
GND
COMP
FB
PAD
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
QW : WDFN-10L 4x4 (W-Type)
EN
9
RT/SYNC
Lead Plating System
G : Green (Halogen Free and Pb Free)
SOP-8 (Exposed pad)
Note :
1
2
3
4
5
10
9
BOOT
PGOOD
***Empty means Pin1 orientation is Quadrant 1
Richtek products are :
VIN
EN
SW
8
PAD
GND
COMP
FB
7
SS/TR
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
11
6
RT/SYNC
Suitable for use in SnPb or Pb-free soldering processes.
WDFN-10L 4x4
Marking Information
RT6343GSP
RT6343GSP : Product Number
RT6343
YMDNN : Date Code
GSPYMDNN
RT6343GQW
9W= : Product Code
YMDNN : Date Code
9W=YM
DNN
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DS6343-00 October 2019
RT6343
Functional Pin Description
Pin No.
Pin Name
BOOT
VIN
Pin Function
SOP-8
WDFN-10L 4x4
(Exposed Pad)
Bootstrap capacitor connection node to supply the high-side
gate driver. Connect a 0.1F ceramic capacitor between this
pin and the SW pin.
1
2
3
1
2
3
Power input. The input voltage range is from 4V to 42V.
Connect a suitable input capacitor between this pin and GND,
usually two 2.2F or larger ceramic capacitors with one
typical capacitance 4.7F.
Enable control pin with internal pull-up current source. Float
or provide a logic-high ( 1.2V) enables the converter; a
logic-low forces the device into shutdown mode.
EN
Soft-start and tracking control input. Connect a capacitor from
SS to GND to set the soft-start period. ”Do Not” leave this pin
floating to avoid inrush current during power up. It also can
be used to track and sequence because the SS/TR pin
voltage can override the internal reference voltage.
--
4
SS/TR
Frequency setting and external synchronous signal input.
Connect a resistor from this pin to GND to set the switching
frequency. Tie to a clock source for synchronization to an
external frequency.
4
5
5
6
RT/SYNC
FB
Output voltage sense. Sense the output voltage at the FB pin
through a resistive divider. The feedback reference voltage is
0.8V typically.
Compensation node. Connect external compensation
elements to this pin to stabilize the control loop.
6
7
7
8
COMP
GND
Ground. Provide the ground return path for the control
circuitry.
Switch node. SW is the switching node that supplies power
to the output. Connect the output LC filter from SW to the
output load.
8
9
SW
Open-drain power-good indication output. Once being
started-up, PGOOD will be pulled low to GND if any internal
protection is triggered.
--
10
PGOOD
Exposed pad. The exposed pad is internally unconnected
and must be soldered to a large PCB copper area for
maximum power dissipation.
9 (Exposed Pad)
11 (Exposed Pad) PAD
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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RT6343
Functional Block Diagram
WDFN-10L 4x4 package
VIN
PGOOD
EN
Shutdown
Thermal
Shutdown
UV
UVLO
+
IEN
IEN_Hys
-
Voltage
Reference
OV
+
-
Shutdown
Shutdown
Logic
Logic
+
-
Enable
Threshold
PGOOD
Enable
-
+
Comparator
V
Regulator
CC
Current
Sense
Pulse-Skip
Minimum Clamp
I
SS
BOOT
BOOT
UVLO
PWM
Comparator
-
+
+
FB
EA
-
0.8V
High-Side
MOSFET
Logic
SS/TR
+
SW
Slope
Compenastion
Shutdown
OC
Clamp
COMP
GND
Frequency
Foldback
BOOT
recharge
MOSFET
Oscillator
RT/SYNC
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DS6343-00 October 2019
RT6343
SOP-8 (Exposed pad) package
VIN
EN
Shutdown
Thermal
UVLO
Shutdown
UV
OV
+
-
I
I
EN_Hys
EN
Voltage
Reference
Logic
Shutdown
Shutdown
Logic
+
-
+
-
Enable
Threshold
Enable
Comparator
V
Regulator
CC
Current
Sense
Pulse-Skip
Minimum Clamp
BOOT
BOOT
UVLO
PWM
Comparator
-
+
+
FB
EA
-
0.8V
SS
High-Side
MOSFET
Logic
+
SW
Slope
Compenastion
OC
Clamp
COMP
GND
Frequency
Foldback
BOOT
recharge
MOSFET
Oscillator
RT/SYNC
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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RT6343
Operation
Control Loop
can also be synchronized with an external clock ranging
from 300kHz to 2.2MHz by RT/SYNC pin. The switching
frequency of synchronization should be equal to or higher
than the frequency set by the RT resistor. For example, if
the switching frequency of synchronization is 300kHz or
higher, the RRT/SYNC should be selected for 300kHz.
The RT6343 is a high efficiency asynchronous step-down
converter utilizes the peak current mode control. An
internal oscillator initiates the turn-on of the high-side
MOSFET.At the beginning of each clock cycle, the internal
high-side MOSFET turns on, allowing current to ramp-up
in the inductor. The inductor current is internally monitored
during each switching cycle. The output voltage is sensed
on the FB pin via the resistor divider, R1 and R2, and
compared with the internal reference voltage (VREF) to
generate a compensation signal (VCOMP) on the COMP
pin. A control signal derived from the inductor current is
compared to the voltage at the COMP pin, derived from
the feedback voltage. When the inductor current reaches
its threshold, the high-side MOSFET is turned off and
inductor current ramps down. While the high-side MOSFET
is off, the inductor current is supplied through the external
low-side diode, freewheel diode, connected between the
SW pin and GND. This cycle repeats at the next clock
cycle. In this way, duty-cycle and output voltage are
controlled by regulating inductor current.
The RT6343 implements a frequency foldback function to
protect the device at over-load or short-circuited condition,
especially higher switching frequencies and input voltages.
The switching frequency is divided by 1, 2, 4, and 8 as the
FB pin voltage falls from 0.8 V to 0 V for switching
frequency control by RT resistor setting mode and the
synchronization mode both. The frequency foldback
function increases the switching cycle period and provides
more time for the inductor current to ramp down.
Maximum Duty Cycle Operation
The RT6343 is designed to operate in dropout at the high
duty cycle approaching 100%. If the operational duty cycle
is large and the required off-time becomes smaller than
minimum off-time, the RT6343 starts to enable skip off-
time function and keeps high-side MOSFET on
continuously. The RT6343 implements skip off-time
function to achieve high duty approaching 100%. Therefore,
the maximum output voltage is near the minimum input
supply voltage of the application. The input voltage at which
the devices enter dropout changes depending on the input
voltage, output voltage, switching frequency, load current,
and the efficiency of the design.
Light Load Operation
The RT6343 operates in power saving mode (PSM) at
light load to improve light load efficiency. IC starts to switch
when VFB is lower than PSM threshold ( VREF x 1.005,
typically) and stops switching when VFB is high enough.
During PSM, the peak inductor current (IL_PEAK) is
controlled by the minimum on-time of high-side MOSFET
to ensure the low output voltage ripple. During non-
switching period, most of the internal circuit is shut down,
and the supply current drops to quiescent current (100μA,
typically) to reduce the quiescent power consumption.
With lower output loading, the non-switching period is
longer, so the effective switching frequency becomes lower
to reduce the switching loss and switch driving loss.
BOOT UVLO
The BOOT UVLO circuit is implemented to ensure a
sufficient voltage of BOOT capacitor for turning on the high-
side MOSFET at any conditions. The BOOT UVLO usually
actives at extremely high conversion ratio or the higher
VOUT application operates at very light load. With such
conditions when the BOOT to SW voltage falls below
VBOOT_UVLO_L (2.7V, typically), the device turns on the
internal BOOT recharge FET (150ns, typically) to charge
the BOOT capacitor. The BOOT UVLO is sustained until
the BOOT to SW voltage is higher than VBOOT_UVLO_H
(2.8V, typically).
Switching Frequency Selection and Synchronization
The RT6343 provides an RT/SYNC pin for switching
frequency selection. The switching frequency can be set
by using external resistor RRT/SYNC and the switching
frequency range is from 100kHz to 2.5MHz. The RT6343
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DS6343-00 October 2019
RT6343
Enable Control
and FB pin is larger than 42mV (typically). Only when
this ramp voltage is higher than the feedback voltage VFB,
the switching will be resumed. The FB voltage will track
the SS/TR pin ramp voltage with a SS/TR to FB offset
voltage (42mV, typically) during soft-start interval. The
output voltage can then ramp up smoothly to its targeted
regulation voltage, and the converter can have a monotonic
smooth start-up. For soft-start control, the SS pin should
never be left unconnected. After the FB pin voltage rises
above 94% of VREF (typically), the PGOOD pin will be in
high impedance and the VPGOOD will be held high. The
typical start-up waveform shown in Figure 1 indicates the
sequence and timing between the output voltage and
related voltage.
The RT6343 provides an ENpin, as an external chip enable
control, to enable or disable the device. If VEN is held
below the enable threshold voltage, switching is inhibited
even if the VIN voltage is above VIN under-voltage lockout
threshold (VUVLOH). If VEN is held below 0.4V, the converter
will enter into shutdown mode, that is, the converter is
disabled. During shutdown mode, the supply current can
be reduced to ISHDN (2.25μA, typically). If the EN voltage
rises above the enable threshold voltage while the VIN
voltage is higher than VUVLOH, the device will be turned
on, that is, switching being enabled and soft-start
sequence being initiated. The ENpin has an internal pull-
up current source IEN (1.2μA, typically) that enables
operation of the RT6343 when the EN pin floats. The EN
pin can be used to adjust the under-voltage lockout (UVLO)
threshold and hysteresis by using two external resistors.
The RT6343 implements additional hysteresis current
source IEN_Hys (3.4μA, typically) to adjust the UVLO. The
IEN_Hys is sourced out of the EN pin when VEN is larger
than enable threshold voltage. When the VEN falls below
enable threshold voltage, the IEN_Hys will be stopped
sourcing out of the EN pin.
V
= 4.5V to 42V
IN
VIN
EN
t
SS
540µs
SS
42mV
10% x
94% x V
OUT
90% x V
OUT
VOUT
PGOOD
V
OUT
Soft-Start and Tracking Control
The soft-start function is used to prevent large inrush
currents while the converter is being powered up. The
RT6343GSP provides internal soft-start and the
RT6343GQW provides external soft-start function for inrush
currents control. The RT6343GQW provides an SS/TR pin
so that the soft-start time can be programmed by selecting
the value of the external soft-start capacitor CSS/TR
connected from the SS/TR pin to ground or controlled by
external ramp voltage to SS/TR pin. During the start-up
sequence, the soft-start capacitor is charged by an internal
current source ISS (1.7μA, typically) to generate a soft-
start ramp voltage as a reference voltage to the PWM
comparator. The high-side MOSFET will start switching if
the VSS/TR is larger than 54mV, and then the voltage
difference between SS/TR pin and FB pin is larger than
42mV ( i.e. VSS/TR − VFB > 42mV, typically) during power-
up period. If the output is pre-biased to a certain voltage
during start-up for some reason, the device will not start
switching until the voltage difference between SS/TR pin
Figure 1 Start-Up Sequence for RT6343GQW
Power Good Indication
The RT6343GQW features an open-drain power-good
output (PGOOD) to monitor the output voltage status. The
output delay of comparator prevents false flag operation
for short excursions in the output voltage, such as during
line and load transients. Pull-up PGOOD with a resistor
to an external voltage source and it is recommended to
use pull-up resistance between the values of 1 and 10kΩ
to reduce the switching noise coupling to PGOOD pin.
The PGOOD assertion requires input voltage above 2V.
The power-good function is controlled by a comparator
connected to the feedback signal VFB. If VFB rises above
the power-good high threshold (VTH_PGLH1) (94% of the
reference voltage, typically), the PGOOD pin will be in
high impedance and VPGOOD will be held high after a certain
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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RT6343
delay elapsed. When VFB falls below power-good low
threshold (VTH_PGHL2) (92% of the reference voltage,
typically) or exceeds VTH_PGHL1 (109% of the reference
voltage, typically), the PGOODpin will be pulled low. For
VFB higher than VTH_PGHL1, VPGOOD can be pulled high
again if VFB drops back by a power-good high threshold
(VTH_PGLH2) (106% of the reference voltage, typically).
Once being started-up, if any internal protection is
triggered, PGOODwill be pulled low toGND. The internal
open-drain pull-down device (45Ω, typically) will pull the
PGOODpin low. The power good indication profile is shown
in Figure 2.
certain amount of delay when the high-side MOSFET
being turned on. If an over-current condition occurs, the
converter will immediately turn off the high-side MOSFET
to prevent the inductor current exceeding the high-side
MOSFET peak current limit (ILIM).
Output Under-Voltage Protection
The RT6343 includes output under-voltage protection
(UVP) against over-load or short-circuited condition by
constantly monitoring the feedback voltage VFB. If VFB
drops below the under-voltage protection trip threshold
(50% of the internal reference voltage, typically), the UV
comparator will go high to turn off the internal high-side
switch. If the output under-voltage condition continues for
a period of time, the RT6343 enters output under-voltage
protection with hiccup mode and discharges the CSS/TR
by an internal discharging current source ISS_DIS (0.5μA,
typically). During hiccup mode, the device remains
shutdown. After the SS pin voltage is discharged to less
than 54mV (typically), the RT6343 attempts to re-start up
again, and the internal charging current source ISS (1.7μA,
typically) gradually increases the voltage on CSS/TR. The
high-side MOSFET will start switching when voltage
difference between SS pin and FB pin is larger than 42mV
( i.e. VSS − VFB > 42mV, typically). If the output under-
voltage condition is not removed, the high-side MOSFET
stops switching when the voltage difference between SS
pin and FB pin is 1.2V ( i.e. VSS − VFB = 1.2V, typically)
and then the ISS_DIS discharging current source begins to
discharge CSS/TR. Upon completion of the soft-start
sequence, if the output under-voltage condition is removed,
the converter will resume normal operation; otherwise, such
cycle for auto-recovery will be repeated until the output
under-voltage condition is cleared. Hiccup mode allows
the circuit to operate safely with low input current and
power dissipation, and then resume normal operation as
soon as the over-load or short-circuit condition is removed.
V
TH_PGHL1
V
TH_PGLH2
V
TH_PGLH1
V
TH_PGHL2
V
FB
V
PGOOD
Figure 2. The Logic of PGOOD for RT6343GQW
Input Under-Voltage Lockout
In addition to the EN pin, the RT6343 also provides enable
control through the VIN pin. If VEN rises above VTH_EN first,
the switching will be inhibited until the VIN voltage rises
above VUVLOH. It is to ensure that the internal regulator is
ready so that operation with not-fully-enhanced internal
high-side MOSFET can be prevented. After the device is
powered up, if the input voltage VIN goes below the UVLO
falling threshold voltage (VUVLOL), this switching will be
inhibited; if VIN rises above the UVLO rising threshold
(VUVLOH), the device will resume switching. Note that VIN
= 4V is only design for input voltage momentarily falls
down to the UVLO threshold voltage requirement, and
normal input voltage should be larger than the VUVLOH
.
Since the CSS/TR will be discharged to 54mV when the
RT6343 enters output under-voltage protection, the first
discharging time (tSS_DIS1) can be calculated as below :
High-Side MOSFET Peak Current Limit Protection
The RT6343 includes a cycle-by-cycle high-side MOSFET
peak current-limit protection against the condition that
the inductor current increasing abnormally, even over the
inductor saturation current rating. The inductor current
through the high-side MOSFET will be measured after a
V
0.054
SS
t
= C
SS_DIS1
SS
I
SS_DIS
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DS6343-00 October 2019
RT6343
The equation below assumes that the VFB will be 0 at
short-circuited condition and it can be used to calculate
the CSS/TR discharging time (tSS_DIS2) and charging time
(tSS_CH) during hiccup mode.
1.146
tSS_DIS2 = CSS
ISS_DIS
1.146
tSS_CH = CSS
ISS_CH
Output Over-Voltage Protection
The RT6343 includes an output over-voltage protection
(OVP) circuit to limit output voltage. Since the VFB is lower
than the reference voltage (VREF) at over-load or short-
circuited condition, the COMP voltage will be high to
demand maximum output current. Once the over-load or
short-circuited condition is removed, the COMP voltage
resumes to the normal voltage to regulate the output
voltage. The output voltage leads to the possibility of an
output overshoot if the load transient is faster than the
COMP voltage transient response, especially for small
output capacitance. If the VFB goes above the 109% of
the reference voltage, the high-side MOSFET will be forced
off to limit the output voltage. When the VFB drops lower
than the 106% of the reference voltage, the high-side
MOSFET will be resumed.
Over-Temperature Protection
The RT6343 includes an over-temperature protection (OTP)
circuitry to prevent overheating due to excessive power
dissipation. The OTP will shut down switching operation
when junction temperature exceeds a thermal shutdown
threshold TSD. Once the junction temperature cools down
by a thermal shutdown hysteresis (ΔTSD), the IC will
resume normal operation with a complete soft-start.
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RT6343
Absolute Maximum Ratings (Note 1)
Supplu Voltage, VIN ------------------------------------------------------------------------------------------------------ −0.3V to 45V
Enable Voltage, EN ------------------------------------------------------------------------------------------------------- −0.3V to 45V
Switch Voltage, SW ------------------------------------------------------------------------------------------------------ −0.6V to 45V
SW (t ≤ 100ns) ------------------------------------------------------------------------------------------------------------- −5V to 50V
PowerGood Voltage, PGOOD ----------------------------------------------------------------------------------------- −0.3V to 45V
BOOT to SW (BOOT−SW)---------------------------------------------------------------------------------------------- −0.3V to 6V
All Other Pins -------------------------------------------------------------------------------------------------------------- −0.3V to 6V
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Ratings (Note 2)
ESD Susceptibility
HBM (Human Body Model)---------------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 3)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 4V to 42V
Output Voltage ------------------------------------------------------------------------------------------------------------- 0.8V to VIN
Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C
Thermal Information (Note 4 and Note 5)
SOP-8
(Exposed pad)
Thermal Parameter
WDFN-10L 4x4
Unit
Junction-to-ambient thermal resistance (JEDEC
standard)
JA
31.7
30.4
C/W
JC(Top)
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
46.4
4.1
73.9
3.4
C/W
C/W
JC(Bottom)
Junction-to-ambient thermal resistance (specific
EVB)
JA(EVB)
30.4
30
C/W
JC(Top)
JB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.4
13
5
C/W
C/W
13.2
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DS6343-00 October 2019
RT6343
Electrical Characteristics
(VIN = 12V, TA = TJ = 25°C, unless otherwise specified)
Parameter
Supply Voltage
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Operating Voltage
VIN
After soft-start is finished
VIN rising
4
--
42
4.5
4
V
V
VUVLOH
VUVLOL
ISHDN
4.1
3.8
--
4.3
3.9
2.25
VIN Under-Voltage Lockout
Threshold
VIN falling
Shutdown Current
Quiescent Current
VEN = 0V
5
A
A
VEN = 2V, VFB = 0.83V, not
IQ
--
100
135
switching
Enable Voltage
Enable Threshold Voltage
Enable to COMP Active
VTH_EN
1.1
--
1.2
540
4.6
1.2
3.4
1.3
--
V
VIN = 12V, TA = 25C
VTH_EN + 50mV
s
A
A
A
--
--
Pull-Up Current
IEN
VTH_EN 50mV
0.58
2.2
1.8
4.5
Hysteresis Current
Reference Voltage
Reference Voltage
Internal MOSFET
IEN_Hys
VREF
0.792
--
0.8
80
0.808
150
V
High-Side Switch On-
Resistance
RDS(ON)_H
VIN = 12V, VBOOT VSW = 5V
m
nA
Error Amplifier
Input Current
--
--
50
--
--
Normal operation
2A < ICOMP < 2A
VCOMP = 1V
440
Error Amplifier Trans-
Conductance
gm
A/V
During SS,
2A < ICOMP < 2A
VCOMP = 1V, VFB = 0.4V
--
77
--
10000
2500
30
Error Amplifier DC Gain
Error Amplifier Bandwidth
Source/Sink Current
VFB = 0.8V
--
--
--
--
--
--
V/V
kHz
A
VCOMP = 1V, 100mV overdrive
COMP to Current Sense
Trans-Conductance
gm_cs
ILIM
--
12
--
A/V
Current Limit
f
SW = 500kHz,
Current Limit
4.675
5.5
6.325
A
VOUT = 5V
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11
RT6343
Parameter
Symbol
Test Conditions
Min
Typ Max Unit
On-Time Timer Control
Minimum On-Time
tON_MIN
IOUT = 1A
--
--
135
ns
Timing Resistor and External Clock
Switching Frequency 1
Switching Frequency 2
Switching Frequency 3
SYNC Frequency Range
Minimum Sync Pulse Width
fSW1
fSW2
fSW3
RRT/SYNC = 1M
90
105
500
120
550
kHz
kHz
RRT/SYNC = 200k
RRT/SYNC = 37.4k
External clock
450
2200 2450 2700 kHz
--
0.3
--
2.2
--
MHz
ns
20
--
VIH_SYNC
VIL_SYNC
1.55
1.2
2
SYNC Threshold Voltage
V
0.5
--
RT/SYNC Falling Edge to SW
Rising Edge Delay
--
70
--
ns
Soft-Start and Tracking
Internal Charge Current
SS/TR to FB Offset
ISS
VSS/TR = 0.4V, RT6343GQW
VSS/TR = 0.4V, RT6343GQW
98% nominal, RT6343GQW
VFB = 0V, RT6343GQW
--
--
--
--
1.7
42
--
--
--
--
A
mV
V
SS/TR-to-Reference Crossover
SS/TR Discharge Voltage
Internal Soft-Start Time
Soft-Start Period
1.16
54
mV
10% to 90%, RT6343GSP
1.4
2
2.6
ms
Power Good
V
FB rising, % of VREF, PGOOD
VTH_PGLH1
VTH_PGHL1
VTH_PGHL2
VTH_PGLH2
90
105
88
94
109
92
98
113
96
from low to high, RT6343GQW
VFB rising, % of VREF, PGOOD
from high to low, RT6343GQW
Power Good Threshold
%
VFB falling, % of VREF, PGOOD
from high to low, RT6343GQW
VFB falling, % of VREF, PGOOD
102
--
106
2
110
--
from low to high, RT6343GQW
Power Good Hysteresis
VFB falling, RT6343GQW
%
VPGOOD = 5.5V, TA = 25°C,
RT6343GQW
Power Good Leakage Current
ILK_PGOOD
--
10
500
nA
IPGOOD = 3mA, VFB < 0.79V,
RT6343GQW
On-Resistance
--
--
45
--
2
VPGOOOD < 0.5V, IPGOOD = 100A,
Minimum VIN for defined output
0.9
V
RT6343GQW
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DS6343-00 October 2019
RT6343
Parameter
Thermal Shutdown
Thermal Shutdown
Symbol
Test Conditions
Min
Typ
Max
Unit
TSD
TSD
--
--
175
15
--
--
°C
°C
Thermal Shutdown
Hysteresis
Output Under-Voltage Protection
UVP Trip Threshold VUVP
UVP detect
--
0.4
--
V
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA and θJC are measured or simulated at TA = 25°C based on the JEDEC 51-7 standard.
ψ ψ
(Top) and JB are measured on a high effective-thermal-conductivity four-layer test board which is in size of
JC
Note 5. θJA
,
(EVB)
70mm x 50mm; furthermore, outer layers with 2 oz. Cu and inner layers with 1 oz. Cu. Thermal resistance/parameter
values may vary depending on the PCB material, layout, and test environmental conditions.
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13
RT6343
Typical Application Circuit
300kHz, 3.3V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6343GSP
V
2
3
1
8
L1
10µH
IN
VIN
BOOT
4.5V to 42V
V
OUT
C1
2.2µF
C2
2.2µF
SW
3.3V/3.5A
D1
SS5P6
R1
31.6k
C5
47µF
C6
47µF
EN
Enable Signal
5
FB
C3
10nF
R3
4.99k
R2
10k
6
COMP
C4
270pF
R
332k
RT
4
RT/SYNC
PAD
GND
7
9 (Exposed pad)
f
= 300kHz
SW
L1 = VCHA075D-100MS6
C5/C6 = GRM32ER61C476KE15L
C1/C2 = HMK316AC7225KL-TE
400kHz, 5V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6343GSP
V
IN
2
1
8
L1
VIN
BOOT
SW
8V to 42V
10µH
V
OUT
C1
2.2µF
C2
2.2µF
5V/3.5A
D1
SS5P6
R1
52.3k
3
C5
47µF
C6
47µF
EN
Enable Signal
5
FB
R2
10k
C5
8.2nF
R3
10k
6
COMP
C6
100pF
R
249k
RT
4
RT/SYNC
PAD
GND
7
f
= 400kHz
SW
9 (Exposed pad)
L1 = VCHA075D-100MS6
C5/C6 = GRM32ER61C476KE15L
C1/C2 = HMK316AC7225KL-TE
400kHz, 12V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6343GSP
V
2
3
1
9
IN
L1
22µH
VIN
BOOT
14V to 42V
V
OUT
C1
2.2µF
C2
2.2µF
SW
12V/3.5A
D1
SS5P6
R1
140k
C5
10µF
C6
10µF
C7
10µF
EN
Enable Signal
8
FB
R2
10k
C3
8.2nF
R3
6.34k
6
COMP
R
249k
RT
C4
150pF
4
RT/SYNC
PAD
GND
7
9 (Exposed pad)
f
= 400kHz
SW
L1 = 7443551221
C6/C7/C8 = UMK325AB7106KM
C1/C2 = HMK316AC7225KL-TE
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14
DS6343-00 October 2019
RT6343
300kHz, 3.3V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6343GQW
V
IN
2
1
9
L1
VIN
BOOT
4.5V to 42V
10µH
V
OUT
C1
2.2µF
C2
2.2µF
SW
3.3V/3.5A
D1
SS5P6
R1
31.6k
3
C5
47µF
C6
47µF
EN
Enable Signal
PWRGD
10
6
4
FB
PGOOD
R
RT
R2
10k
332k
R3
4.99k
5
7
RT/SYNC
COMP
C3
SS/TR
C
SS
0.01µF
C4
270pF
10nF
GND
8
PAD
11 (Exposed pad)
f
= 300kHz
SW
L1 = VCHA075D-100MS6
C5/C6 = GRM32ER61C476KE15L
C1/C2 = HMK316AC7225KL-TE
400kHz, 5V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6343GQW
V
2
1
9
IN
L1
10µH
VIN
BOOT
8V to 42V
V
OUT
C1
2.2µF
C2
2.2µF
SW
5V/3.5A
D1
SS5P6
R1
52.3k
3
C5
47µF
C6
47µF
EN
Enable Signal
PWRGD
10
6
4
FB
PGOOD
R
RT
R2
10k
249k
R3
10k
5
7
RT/SYNC
COMP
C3
SS/TR
C
SS
0.01µF
C4
8.2nF
GND
8
PAD
11 (Exposed pad)
100pF
f
= 400kHz
SW
L1 = VCHA075D-100MS6
C5/C6 = GRM32ER61C476KE15L
C1/C2 = HMK316AC7225KL-TE
400kHz, 12V, 3.5A Step-Down Converter
C
0.1µF
BOOT
RT6363GQW
V
2
1
9
IN
L1
22µH
VIN
BOOT
14V to 42V
V
OUT
C1
2.2µF
C2
2.2µF
SW
12V/3.5A
D1
SS5P6
R1
140k
3
C5
10µF
C6
10µF
C7
10µF
EN
Enable Signal
PWRGD
10
6
4
FB
PGOOD
R
RT
R2
10k
249k
R3
6.34k
5
7
RT/SYNC
COMP
C3
SS/TR
C
SS
0.01µF
C4
8.2nF
GND
8
PAD
11 (Exposed pad)
150pF
f
= 400kHz
SW
L1 = 7443551221
C6/C7/C8 = UMK325AB7106KM
C1/C2 = HMK316AC7225KL-TE
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15
RT6343
Typical Operating Characteristics
Efficiency vs. Output Current
Efficiency vs. Output Current
100
100
90
80
70
60
50
40
30
20
10
0
90
VIN = 14V
VIN = 24V
VIN = 36V
VIN = 42V
80
70
60
50
40
30
20
10
0
Freq = 100k
Freq = 500k
Freq = 1M
Freq = 2.5M
VIN = 12V, VOUT = 5V
fSW = 2.5MHz, L = VCMT053T-1R5MN5, 1.5μH
f
SW = 1MHz, VCMT063T-4R7MN5, 4.7μH
VOUT = 12V, fsw = 400kHz
f
SW = 400kHz, L = VCHA075D-100MS6, 10μH
fSW = 100kHz, L = 74435573300, 33μH
L = 7443551221, 22μH
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
Efficiency vs. Output Current
Efficiency vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 8V
VIN = 4.5V
VIN = 8V
VIN = 12V
VIN = 13.5V
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 42V
VIN = 12V
VIN = 13.5V
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 42V
VOUT = 5V, fSW = 400kHz
L = VCHA075D-100MS6, 10μH
VOUT = 3.3V, fsw = 300kHz
L = VCHA075D-100MS6 10μH
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
Output Voltage vs. Output Current
Output Voltage vs. Input Voltage
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
VIN = 12V, VOUT = 5V
2.5 3.5
IOUT = 3.5A, VOUT = 5V
27 32 37 42
0
0.5
1
1.5
2
3
7
12
17
22
Input Voltage (V)
Output Current (A)
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DS6343-00 October 2019
RT6343
Current Limit vs. Input Voltage
Switching Frequency vs. Temperature
7.0
6.5
6.0
5.5
5.0
4.5
4.0
120
115
110
105
100
95
VIN = 12V, VOUT = 5V
VOUT = 5V, fSW = 500kHz, L = 7.8μH
I
OUT = 2.5A, RRT/SYNC = 1MΩ
90
7
12
17
22
27
32
37
42
-50
-25
0
25 50 75 100 125
Input Voltage (V)
Temperature (°C)
Switching Frequency vs. Temperature
Switching Frequency vs. Temperature
550
530
510
490
470
450
2700
2600
2500
2400
2300
2200
VIN = 12V, VOUT = 5V
IOUT = 2.5A, RRT/SYNC = 37.4kΩ
V
= 12V, V
= 5V
OUT
IN
I
= 2.5A, R
= 200kΩ
OUT
25
RT/SYNC
-50
-25
0
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Quiescent Current vs. Temperature
Shutdown Current vs. Temperature
135
125
115
105
95
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
85
75
VIN = 12V
VIN = 12V
100 125
65
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
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RT6343
UVLO Threshold vs. Temperature
Enable Threshold vs. Temperature
5.0
4.6
4.2
3.8
3.4
3.0
1.30
1.26
1.22
1.18
1.14
1.10
Rising
Falling
VOUT = 1V
100 125
VOUT = 1V
-50
-25
0
25
50
75
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Output Voltage vs. Temperature
Current Limit vs. Temperature
5.10
5.05
5.00
4.95
4.90
4.85
4.80
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
High-Side MOSFET
VIN = 12V, VOUT = 5V
fSW = 500kHz, L= 7.8μH
VIN = 12V, VOUT = 5V, IOUT = 2.5A
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Output Ripple Voltage
Load Transient Response
VOUT
(10mV/Div)
IOUT
(1A/Div)
VIN = 12V, VOUT = 5V
IOUT = 1.75A to 3.5A, fSW = 400kHz
COUT = 47μF x 2, L = 10μH
VOUT
(200mV/Div)
VSW
(5V/Div)
VIN = 12V, VOUT = 5V, IOUT = 3mA, fSW = 400kHz
Time (50μs/Div)
Time (100μs/Div)
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DS6343-00 October 2019
RT6343
Output Ripple Voltage
Power On from EN
VIN = 12V, VOUT = 5V, IOUT = 3.5A, fSW = 400kHz
VEN
(2V/Div)
VOUT
(10mV/Div)
VSS/TR
(1V/Div)
VIN = 12V, VOUT = 5V
IOUT = 3.5A, fSW = 400kHz
VOUT
(2V/Div)
VSW
(5V/Div)
VPGOOD
(5V/Div)
Time (2ms/Div)
Time (5μs/Div)
Power Off from EN
Power On from VIN
VEN
(2V/Div)
VSS/TR
(5V/Div)
VIN
(4V/Div)
VSS/TR
(2V/Div)
VOUT
(2V/Div)
VIN = 12V, VOUT = 5V
VIN = 12V, VOUT = 5V
IOUT = 3.5A, fSW = 400kHz
IOUT = 3.5A, fSW = 400kHz
VOUT
(2V/Div)
VPGOOD
(5V/Div)
VPGOOD
(5V/Div)
Time (200μs/Div)
Time (4ms/Div)
Start-Up Dropout Performance
Power Off from VIN
VIN
(4V/Div)
VIN
VSS/TR
(5V/Div)
VOUT
(2V/Div)
VOUT
VIN = 12V, VOUT = 5V
VIN
IOUT = 3.5A, fSW = 400kHz
(2V/Div)
VPGOOD
(5V/Div)
VOUT
(2V/Div)
VOUT = 5V, IOUT = 0.1A, 50Ω, EN pin floats
Time (100ms/Div)
Time (4ms/Div)
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RT6343
Start-Up Dropout Performance
VIN
VOUT
VIN
(2V/Div)
VOUT
(2V/Div)
VOUT = 5V, IOUT = 1A, 5Ω, EN pin floats
Time (100ms/Div)
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DS6343-00 October 2019
RT6343
Application Information
A general RT6343 application circuit is shown in typical
application circuit section. External component selection
is largely driven by the load requirement and begins with
the switching frequency selection by using external resistor
RRT/SYNC. Next, the inductor L, the input capacitor CIN,
the output capacitor COUT and freewheel diode are chosen.
Next, feedback resistors and compensation circuit are
selected to set the desired output voltage and crossover
frequency, and the bootstrap capacitor CBOOT can be
selected. Finally, the remaining optional external
components can be selected for functions such as the
EN, external soft-start, PGOOD, and synchronization.
shows minimum off-time calculation with loss terms
consideration :
V
+ I
R + V
OUT
OUT_MAX
L
D
1
V
I
R
V
D
IN_MIN
OUT_MAX
DS(ON)_H
t
OFF_MIN
f
SW
where RDS(ON)_H is the on-resistance of the high-side
MOSFET; VD is the forward conduction voltage of the
freewheel diode; RL is the DC resistance of inductor.
The switching frequency fSW is set by the external resistor
RRT/SYNC connected between the RT/SYNC pin and
ground. The failure mode and effects analysis (FMEA)
consideration is applied to the RT/SYNC pin setting to
avoid abnormal switching frequency operation at failure
conditions. It includes failure scenarios of short-circuit to
ground and the pin is left open. The switching frequency
will be 900kHz (typically) when the RT/SYNC pin is
shorted to ground, and 240kHz (typically) when the pin is
left open. The equation below shows the relation between
setting frequency and the RRT/SYNC value.
Switching Frequency Setting
The RT6343 offers adjustable switching frequency setting
and the switching frequency can be set by using external
resistor RRT/SYNC. The switching frequency range is from
100kHz to 2.5MHz. The selection of the operating
frequency is a trade-off between efficiency and component
size. High frequency operation allows the use of smaller
inductor and capacitor values. Operation at lower
frequencies improves efficiency by reducing internal gate
charge and transition losses, but requires larger inductance
values and/or capacitance to maintain low output ripple
voltage. The additional constraints on operating frequency
are the minimum on-time and minimum off-time. The
minimum on-time, tON_MIN, is the smallest duration of time
in which the high-side switch can be in its “on” state.
The minimum on-time of the RT6343 is 100ns (typically).
In continuous mode operation, the maximum operating
frequency, fSW_MAX, can be derived from the minimum on-
time according to the formula below :
120279
R
=
RT/SYNC (k)
1.033
f
SW
where fSW (kHz) is the desired setting frequency. It is
recommended to use 1% tolerance or better, and the
temperature coefficient of 100 ppm or less resistors. Figure
3 shows the relationship between switching frequency and
the RRT/SYNC resistor.
1200
1000
800
600
400
200
0
V
OUT
f
=
SW_MAX
t
V
IN_MAX
ON_MIN
where VIN_MAX is the maximum operating input voltage.
The minimum off-time, tOFF_MIN, is the smallest amount of
time that the RT6343 is capable of tripping the current
comparator and turning the high-side MOSFET back off.
The minimum off-time of the RT6343 is 130ns (typically).
If the switching frequency should be constant, the required
off-time needs to be larger than minimum off-time. Below
0
500
1000
1500
2000
2500
fSW (kHz)
Figure 3. Switching Frequency vs. RRT/SYNC
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21
RT6343
Inductor Selection
The current flowing through the inductor is the inductor
ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current
can increase above the calculated peak inductor current
level calculated above . In transient conditions, the inductor
current can increase up to the switch current limit of the
device. For this reason, the most conservative approach
is to specify an inductor with a saturation current rating
which is equal to or greater than the switch current limit
rather than the peak inductor current. It is recommended
to use shielded inductors for good EMI performance.
The inductor selection trade-offs among size, cost,
efficiency, and transient response requirements.Generally,
three key inductor parameters are specified for operation
with the device: inductance value (L), inductor saturation
current (ISAT), andDC resistance (DCR).
Agood compromise between size and loss is a 30% peak-
to-peak ripple current to the IC rated current. The switching
frequency, input voltage, output voltage, and selected
inductor ripple current determines the inductor value as
follows :
V
(V V
)
OUT
IN
OUT
Input Capacitor Selection
L =
V f
I
IN SW
L
Input capacitance, CIN, is needed to filter the pulsating
current at the drain of the high-side MOSFET. The CIN
should be sized to do this without causing a large variation
in input voltage. The peak-to-peak voltage ripple on input
capacitor can be estimated as equation below :
Larger inductance values result in lower output ripple
voltage and higher efficiency, but a slightly degraded
transient response. This results in additional phase lag in
the loop and reduces the crossover frequency.As the ratio
of the slope-compensation ramp to the sensed-current
ramp increases, the current-mode system tilts towards
voltage-mode control. Lower inductance values allow for
smaller case size, but the increased ripple lowers the
effective current limit threshold and increases the AC
losses in the inductor. It also causes insufficient slope
compensation and ultimately loop instability as duty cycle
approaches or exceeds 50%. When duty cycle exceeds
50%, below condition needs to be satisfied :
1D
IN SW
V
where
D =
= DI
+ ESRI
OUT
CIN
OUT
C
f
V
OUT
V
IN
Figure 4 shows the CIN ripple current flowing through the
input capacitors and the resulting voltage ripple across
the capacitors.
For ceramic capacitors, the equivalent series resistance
(ESR) is very low, the ripple which is caused by ESR can
be ignored, and the minimum value of effective input
capacitance can be estimated as equation below :
D 1D
VOUT
L
2.9fSW
Agood compromise among size, efficiency, and transient
response can be achieved by setting an inductor current
ripple (ΔIL) with about 10% to 50% of the maximum rated
output current (3.5A).
C
IN_MIN
= I
OUT_MAX
V
f
CIN_MAX SW
where ΔVCIN_MAX is maximum input ripple voltage.
To enhance the efficiency, choose a low-loss inductor
having the lowest possible DC resistance that fits in the
allotted dimensions. The inductor value determines not
only the ripple current but also the load-current value at
whichDCM/CCM switchover occurs. The selected inductor
should have a saturation current rating greater than the
peak current limit of the device. The core must be large
enough not to saturate at the peak inductor current (IL_PEAK) :
V
CIN
C
Ripple Voltage
IN
V
ESR
= I
OUT
x ESR
(1-D) x I
OUT
C
Ripple Current
IN
D x I
OUT
V
OUT
(V V
OUT
)
IN
I =
L
V f
L
IN SW
1
2
D x tSW
(1-D) x tSW
IL_PEAK = IOUT_MAX
+
IL
Figure 4. CIN Ripple Voltage and Ripple Current
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RT6343
In addition, the input capacitor needs to have a very low
ESR and must be rated to handle the worst-case RMS
input current. The RMS ripple current (IRMS) of the regulator
can be determined by the input voltage (VIN), output voltage
(VOUT), and rated output current (IOUT) as the following
equation :
frequency noise, an additional small 0.1μF capacitor should
be placed close to the part and the capacitor should be
0402 or 0603 in size. X7R capacitors are recommended
for best performance across temperature and input voltage
variations.
Output Capacitor Selection
V
V
V
IN
V
OUT
OUT
I
I
1
RMS
OUT_MAX
IN
The selection of COUT is determined by considering to
satisfy the voltage ripple and the transient loads. The peak-
to-peak output ripple, ΔVOUT, is determined by :
From the above, the maximum RMS input ripple current
occurs at maximum output load, which will be used as
the requirements to consider the current capabilities of
the input capacitors. The maximum ripple voltage usually
occurs at 50% duty cycle, that is, VIN = 2 x VOUT. It is
common to use the worse IRMS ≅ 0.5 x IOUT_MAX at VIN = 2
x VOUT for design. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further de-rate
the capacitor, or choose a capacitor rated at a higher
temperature than required.
1
VOUT = IL ESR +
8fSW COUT
Where the ΔIL is the peak-to-peak inductor ripple current.
The highest output ripple is at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements.
Regarding to the transient loads, the VSAG and VSOAR
requirement should be taken into consideration for
choosing the effective output capacitance value. The
amount of output sag/soar is a function of the crossover
frequency factor at PWM, and can be calculated from
Several capacitors may also be paralleled to meet size,
height and thermal requirements in the design. For low
input voltage applications, sufficient bulk input capacitance
is needed to minimize transient effects during output load
changes.
below equation :
IOUT
2 COUT fC
VSAG = VSOAR
=
Ceramic capacitors are ideal for switching regulator
applications because of its small size, robustness, and
very low ESR. However, care must be taken when these
capacitors are used at the input.Aceramic input capacitor
combined with trace or cable inductance forms a high
quality (under damped) tank circuit. If the RT6343 circuit
is plugged into a live supply, the input voltage can ring to
twice its nominal value, possibly exceeding the device's
rating. This situation is easily avoided by placing the low
ESR ceramic input capacitor in parallel with a bulk
capacitor with higher ESR to damp the voltage ringing.
Ceramic capacitors have very low equivalent series
resistance (ESR) and provide the best ripple performance.
The X7R dielectric capacitor is recommended for the best
performance across temperature and input voltage
variations. The variation of the capacitance value with
temperature, DC bias voltage and switching frequency
needs to be taken into consideration. For example, the
capacitance value of a capacitor decreases as theDC bias
across the capacitor increases. Be careful to consider the
voltage coefficient of ceramic capacitors when choosing
the value and case size. Most ceramic capacitors lose
50% or more of their rated values when used near their
rated voltage.
The input capacitor should be placed as close as possible
to the VIN pin with a low inductance connection to the
GND of the IC. The VIN pin must be bypassed to ground
with a minimum value of effective capacitance 3μF. For
400kHz switching frequency application, two 4.7μF, X7R
capacitors can be connected between the VINpin and the
GNDpin. The larger input capacitance is required when a
lower switching frequency is used. For filtering high
Transient performance can be improved with a higher value
output capacitor. Increasing the output capacitance will
also decrease the output voltage ripple.
Freewheel Diode Selection
When the high-side MOSFET turns off, inductor current
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RT6343
is supplied through the external low-side diode, freewheel
diode, connected between the SW pin and GND.
output voltage is set according to the following equation :
R1
R2
V
= V
1 +
OUT
REF
The reverse voltage rating of freewheel diode should be
equal to or greater than the VIN_MAX. The maximum average
forward rectified current of freewheel diode should be equal
to or greater than the maximum load current. Considering
the efficiency performance, the diode must have a
minimum forward voltage and reverse recovery time. So
SchottkyDiodes are recommended to be freewheel diode.
where the reference voltage VREF, is 0.8V (typically).
V
OUT
R1
FB
RT6343
R2
GND
The select forward voltage of SchottkyDiode must be less
than the restriction of forward voltage in Figure 5 at
operating temperature range to avoid the IC malfunction.
1.15
Figure 6. Output Voltage Setting
The placement of the resistive divider should be within
5mm of the FB pin. The resistance of R2 should not be
larger than 80kΩ for noise immunity consideration. The
resistance of R1 can then be obtained as below :
1.10
1.05
1.00
0.95
0.90
0.85
0.80
R2(VOUT VREF
)
R1 =
VREF
For better output voltage accuracy, the divider resistors
(R1 and R2) with 1% tolerance or better should be used.
Compensation Network Design
The purpose of loop compensation is to ensure stable
operation while maximizing the dynamic performance.An
undercompensated system may result in unstable
operation. Typical symptoms of an unstable power supply
include: audible noise from the magnetic components or
ceramic capacitors, jittering in the switching waveforms,
oscillation of output voltage, overheating of power MOSFET
and so on.
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
Figure 5. Restriction of Forward Voltage vs. Temperature
The losses of freewheel diode must be considered in order
to ensure sufficient power rating for diode selection. The
conduction loss in the diode is determined by the forward
voltage of the diode, and the switching loss in the diode
can be determined by the junction capacitor of the diode.
The power dissipation of the diode can be calculated as
following formula
In most cases, the peak current mode control architecture
used in the RT6343 only requires two external components
to achieve a stable design as shown in Figure 7. The
compensation can be selected to accommodate any
capacitor type or value. The external compensation also
allows the user to set the crossover frequency and optimize
the transient performance of the device. At around the
crossover frequency, the peak current mode control
(PCMC) equivalent circuit of Buck converter can be
simplified as shown in Figure 8. The method presented
here is easy to calculate and ignore the effects of the
internal slope compensation. Since the slope
compensation is ignored, the actual crossover frequency
VOUT
V
PD = PD_CON + PD_SW = IOUT V 1
D
IN
1
+
C V + VD 2 fSW
J IN
2
where CJ is the junction capacitance of the freewheel diode.
Output Voltage Programming
The output voltage can be programmed by a resistive divider
from the output to ground with the midpoint connected to
the FB pin. The resistive divider allows the FB pin to sense
a fraction of the output voltage as shown in Figure 6. The
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DS6343-00 October 2019
RT6343
is usually lower than the crossover frequency used in the
calculations. It is always necessary to make a
measurement before releasing the design for final
production. Though the models of power supplies are
theoretically correct, they cannot take full account of the
circuit parasitic and component nonlinearity, such as the
ESR variations of output capacitors, the nonlinearity of
inductors and capacitors, etc.Also, circuit PCB noise and
limited measurement accuracy may also cause
measurement errors.ABode plot is ideally measured with
a network analyzer while Richtek application noteAN038
provides an alternative way to check the stability quickly
and easily. Generally, follow the steps below to calculate
the compensation components :
4. The compensation pole is set to the frequency at the
ESR zero or 1/2 of the operating frequency. Output
capacitor and its ESR provide a zero, and optional
CCOMP2 can be used to cancel this zero.
R
C
COMP
ESR
R
OUT
C
COMP2
=
If 1/2 of the operating frequency is lower than the ESR
zero, the compensation pole is set at 1/2 of the
operating frequency.
1
C
COMP2
=
fsw
2
2
R
COMP
Note: Generally, CCOMP2 is an optional component used
to enhance noise immunity.
COMP
1. Set up the crossover frequency, fC. For stability
purposes, the target is to have a loop gain slope that
is −20dB/decade from a very low frequency to beyond
the crossover frequency. In general, one-twentieth to
one-tenth of the switching frequency (5% to 10% of
fsw) is recommended to be the crossover frequency.
Do “NOT” design the crossover frequency over 80kHz
with the RT6343. For dynamic purposes, the higher
the bandwidth, the faster the load transient response.
The downside of the high bandwidth is that it increases
the susceptibility of the regulators to board noise which
ultimately leads to excessive falling edge jitter of the
switch node voltage.
R
COMP
C
COMP2
RT6343
(option)
C
COMP
GND
Figure 7. External Compensation Components
V
OUT
R
ESR
gm_cs
R
L
C
OUT
R1
R2
V
FB
-
V
2. RCOMP can be determi ned by :
COMP
EA
+
V
REF
2 fC VOUT COUT
gm VREF gm_cs
2 fC COUT
gmgm_cs
RCOMP
=
=
R
COMP
C
COMP2
(option)
C
R1 + R2
R2
COMP
where gm is the error amplifier gain of trans-
conductance (440μA/V) ; gm_cs is COMP to current
sense trans-conductance (12A/V)
Figure 8. Simplified Equivalent Circuit of Buck with
PCMC
Bootstrap Driver Supply
3. A compensation zero can be placed at or before the
dominant pole of buck which is provided by output
capacitor and maximum output loading (RL). Calculate
The bootstrap capacitor (CBOOT) between the BOOT pin
and the SW pin is used to create a voltage rail above the
applied input voltage, VIN. Specifically, the bootstrap
capacitor is charged through an internal diode to an internal
voltage source each time when the low-side freewheel
diode conducts. The charge on this capacitor is then used
to supply the required current during the remainder of the
switching cycle. For most applications, a 0.1μF, 0603
CCOMP
:
R C
L
OUT
C
COMP
=
R
COMP
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RT6343
ceramic capacitor with X7R is recommended, and the
capacitor should have a 6.3 V or higher voltage rating.
External Bootstrap Resistor (Option)
The gate driver of an internal high-side MOSFET, utilized
as a high-side switch, is optimized for turning on the
switch. The gate driver is not only fast enough for reducing
switching power loss, but also slow enough for minimizing
EMI. The EMI issue is worse when the switch is turned
on rapidly due to induced high di/dt noises. When the
high-side MOSFET is turned off, the SW node will be
discharged relatively slow by the inductor current because
the presence of the dead time when both the high-side
MOSFET and low-side freewheel diode are turned off.
External Bootstrap Diode
It has to add an external bootstrap diode between an
external 5V voltage supply and the BOOT pin to improve
enhancement of the high-side MOSFET and improve
efficiency when the input voltage is below 5.5V or duty
ratio is higher than 65%. The recommended application
circuit is shown in Figure 9. The bootstrap diode can be a
low-cost one, such as 1N4148. The external 5V can be a
fixed 5V voltage supply from the system, or a 5V output
voltage generated by the RT6343.Note that the VBOOT−SW
must be lower than 5.5V. Figure 10 shows efficiency
comparison between with and without bootstrap diode.
5V
In some cases, it is desirable to reduce EMI further, even
at the expense of some additional power dissipation. The
turn-on rate of the high-side MOSFET can be slowed by
placing a small bootstrap resistor RBOOT between the
BOOT pin and the external bootstrap capacitor as shown
in Figure 11. The recommended range for the RBOOT is
several ohms to 10 ohms, and it could be 0402 or 0603 in
size.
D
BOOT
BOOT
RT6343
SW
C
0.1µF
BOOT
This will slow down the rates of the high-side switch turn-
on and the rise of VSW. In order to improve EMI performance
and enhancement of the internal high-side MOSFET, the
recommended application circuit is shown in Figure 12,
which includes an external bootstrap diode for charging
the bootstrap capacitor and a bootstrap resistor RBOOT
placed between the BOOT pin and the capacitor/diode
connection.
Figure 9. External Bootstrap Diode
100
98
96
94
92
90
88
86
84
82
80
VIN = 4.5V, VOUT = 3.3V
L = VCHA075D-100MS6, 10μH
f
= 300kHz
SW
With Bootstrap Diod
R
BOOT
Without Bootstrap Diode
BOOT
SW
C
BOOT
RT6343
Figure 11. External Bootstrap Resistor at the BOOT Pin
0
0.5
1
1.5
2
2.5
3
3.5
5V
Output Current (A)
D
BOOT
Figure 10. Efficiency Comparison between with and
without BootstrapDiode
R
BOOT
BOOT
SW
C
RT6343
BOOT
Figure 12. External Bootstrap Diode and Resistor at the
BOOT Pin
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RT6343
EN Pin for Start-Up and UVLO Adjustment
typically) charges an external capacitor to build a soft-
start ramp voltage. The internal charging current source
ISS gradually increases the voltage on CSS/TR, and the high-
side MOSFET will start switching if voltage difference
between SS/TR pin and FB pin is larger than 42mV ( i.e.
VSS/TR − VFB > 42mV, typically) during power-up period.
The FB voltage will track the SS/TR pin ramp voltage with
a SS/TR to FB offset voltage (42mV, typically) during soft-
start interval. The typical soft-start time (tSS) which is the
duration of VOUT rises from 10% to 90% of setting value is
calculated as follows :
For automatic start-up, the ENpin has an internal pull-up
current source IEN (1.2μA, typically) that enables operation
of the RT6343 when the EN pin floats. If the EN voltage
rises above the VTH_EN (1.2V, typically) and the VINvoltage
is higher than VUVLOH (4.3V, typically), the device will be
turned on, that is, switching is enabled and soft-start
sequence is initiated. If the high UVLO is required, the
EN pin can be used to adjust the under-voltage lockout
(UVLO) threshold and hysteresis. There is an additional
hysteresis current source IEN_Hys (3.4μA, typically) which
is sourced out of the EN pin when the EN pin voltage
VREF 0.8
tSS = CSS/TR
ISS
exceeds VTH_EN. When the EN pin drops below VTH_EN
,
If a heavy load is added to the output with large
capacitance, the output voltage will never enter regulation
because of UVP. Thus, the device remains in hiccup
operation. The CSS/TR should be large enough to ensure
soft-start period ends after COUT is fully charged.
the IEN_Hys is removed. Therefore, the EN pin can be
externally connected to VIN by adding two resistors, RENH
and RENL to achieve UVLO adjustment as shown in Figure
13.
According to the desired start and stop input voltage, the
resistance of REN1 and REN2 can be obtained as below :
ISS V
OUT
C
C
SS/TR
OUT
0.8I
COUT_CHG
VStart VStop
REN1
REN2
=
=
where ICOUT_CHG is the COUT charge current which is
related to the switching frequency, inductance, high-side
MOSFET peak current limit and load current.
IEN_Hys
VTH_EN
VStart VTH_EN
+ IEN
REN1
Power-Good Output
The EN pin, with high-voltage rating, supports wide input
voltage range to adjust the VIN UVLO.
The RT6343GQW features an open-drain power-good
output (PGOOD) to monitor the output voltage status. The
PGOODpin is an open-drain power-good indication output
and is to be connected to an external voltage source
through a pull-up resistor.
R
EN1
V
IN
EN
R
RT6343
GND
EN2
It is recommended to use pull-up resistance between the
values of 1 and 10kΩ to reduce the switching noise
coupling to PGOOD pin.
Figure 13. ResistiveDivider for Under-Voltage Lockout
Threshold Setting
Synchronization
Soft-Start and Tracking Control
The RT6343 can be synchronized with an external clock
ranging from 300kHz to 2.2MHz which is applied to the
RT/SYNC pin. The minimum synchronous pulse width of
the external clock must be larger than 20ns and the
amplitude should have valleys that are below 0.5V and
peaks above 2V (up to 6V). The rising edge of the SW will
be synchronized to the falling edge of the RT/SYNC pin
signal.
The RT6343GQW provides adjustable soft-start function.
The soft-start function is used to prevent large inrush
current while converter is being powered-up. The
RT6343GQW provides an SS/TR pin so that the soft-start
time can be programmed by selecting the value of the
external soft-start capacitor CSS/TR connected from the
SS/TR pin to ground or controlled by external ramp voltage
to SS/TR pin. An internal current source ISS (1.7μA,
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RT6343
The switching frequency control of the RT6343 will switch
from the RT resistor setting mode to the synchronization
mode when the external clock is applied to the RT/SYNC
pin. The RT6343 transitions from the RT resistor setting
mode to the synchronization mode within 60
microseconds. Figure 14 and Figure 15 show the device
synchronized to an external system clock in power saving
mode (PSM) and continuous conduction mode (CCM).
Thermal Considerations
In many applications, the RT6343 does not generate much
heat due to its high efficiency and low thermal resistance
of its WDFN-10L4x4 and SOP-8 (Exposed pad) packages.
However, in applications which the RT6343 runs at a high
ambient temperature and high input voltage or high
switching frequency, the generated heat may exceed the
maximum junction temperature of the part.
The switching frequency of synchronization should be
equal to or higher than the frequency set with the RT
resistor. For example, if the switching frequency of
synchronization will be 300kHz and higher, the RRT/SYNC
should be selected for 300kHz. Be careful to design the
compensation network and inductance for switching
frequency controlled by both RT resistor setting mode
and the synchronization mode.
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. If the junction temperature reaches
approximately 175°C, the RT6343 stops switching the high-
side MOSFET until the temperature cools down by 15°C.
The maximum power dissipation can be calculated by
the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA(EFFECTIVE)
where TJ(MAX) is the maximum allowed junction temperature
of the die. For recommended operating condition
specifications, the maximum junction temperature is
150°C. TA is the ambient operating temperature,
θJA(EFFECTIVE) is the system-level junction to ambient
thermal resistance. It can be estimated from thermal
modeling or measurements in the system.
The thermal resistance of the device strongly depends on
the surrounding PCB layout and can be improved by
providing a heat sink of surrounding copper ground. The
addition of backside copper with thermal vias, stiffeners,
and other enhancements can also help reduce thermal
resistance.
Figure 14. Synchronization Mode in PSM
Experiments in the Richtek thermal lab show that simply
set θJA(EFFECTIVE) as 110% to 120% of the θJA is reasonable
to obtain the allowed PD(MAX)
.
If the application calls for a higher ambient temperature
and may exceed the recommended maximum junction
temperature of 150°C, care should be taken to reduce the
temperature rise of the part by using a heat sink or air
flow.
Figure 15. Synchronization Mode in CCM
Note that the over-temperature protection is intended to
protect the device during momentary overload conditions.
The protection is activated outside of the absolute
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DS6343-00 October 2019
RT6343
maximum range of operation as a secondary fail-safe and
therefore should not be relied upon operationally.
Continuous operation above the specified absolute
maximum operating junction temperature may impair
device reliability or permanently damage the device.
The RT/SYNC resistor, RRT/SYNC, should be placed as
close to the IC as possible because to the RT/SYNC
pin is sensitive to noise.
Figure 16 and Figure 17 are the RT6343GQW layout
examples.
Layout Guidelines
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the RT6343 :
Four-layer or six-layer PCB with maximum ground plane
is strongly recommended for good thermal performance.
Keep the traces of the main current paths wide and
short.
Place high frequency decoupling capacitor CIN5 as close
to the IC as possible to reduce the loop impedance and
minimize switch node ringing.
Place bootstrap capacitor, CBOOT, as close to the IC as
possible. Routing the trace with width of 20mil or wider.
Place multiple vias under the device near VINandGND,
and close to input capacitors to reduce parasitic
inductance and improve thermal performance. To keep
thermal resistance low, extend the ground plane as much
as possible. Add thermal vias under and near the
RT6343 to additional ground planes within the circuit
board and on the bottom side.
The high frequency switching nodes, SW and BOOT,
should be as small as possible. Keep analog
components away from the SW and BOOT nodes.
Place freewheel diode,D1, and inductor, L1, as close to
the IC as possible to reduce the area size of the SW
exposed copper to reduce the electrically coupling from
this voltage.
Connect the feedback sense network behind via of output
capacitor.
Place the feedback components RFB1 / RFB2 / CFF near
the IC.
Place the compensation components RCP1 / CCP1 / CCP2
near the IC.
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RT6343
L1
COUT2
COUT3
COUT1
SW should be connected to
inductor / diode by wide and
short trace. Keep sensitive
components away from this
trace. Reducing area of SW
trace as possible.
D1
CIN5
CIN1 CIN2
CIN3
CIN4
REN1
REN2
CCP2
CCP1
Input capacitors must be
placed as close to IC
VIN-GND as possible.
RCP1
RRT
RFB2
RFB1
CFF
CSS
The feedback and compensation
components must be connected
as close to the device as possible.
The exposed pad must be soldered to a large
GND plane and add 6 thermal vias with
0.25mm diameter on exposed pad for thermal
dissipation.
Top Layer
Figure 16. LayoutGuide for RT6343GQW (Top Layer)
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DS6343-00 October 2019
RT6343
Place the CBOOT on another layer and
connect by short trace. Keep sensitive
components away from this trace.
Bottom Layer
Figure 17. LayoutGuide for RT6343GQW (Bottom Layer)
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RT6343
Outline Dimension
H
A
Y
M
EXPOSED THERMAL PAD
(Bottom of Package)
J
B
X
F
C
I
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.000
5.791
0.406
2.000
2.000
2.100
3.000
5.004
4.000
1.753
0.510
1.346
0.254
0.152
6.200
1.270
2.300
2.300
2.500
3.500
0.189
0.150
0.053
0.013
0.047
0.007
0.000
0.228
0.016
0.079
0.079
0.083
0.118
0.197
0.157
0.069
0.020
0.053
0.010
0.006
0.244
0.050
0.091
0.091
0.098
0.138
J
M
X
Y
X
Y
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
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RT6343
2
1
2
1
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
0.700
0.000
0.175
0.250
3.900
3.250
3.900
2.550
Max
0.800
0.050
0.250
0.350
4.100
3.350
4.100
2.650
Min
0.028
0.000
0.007
0.010
0.154
0.128
0.154
0.100
Max
0.031
0.002
0.010
0.014
0.161
0.132
0.161
0.104
A
A1
A3
b
D
D2
E
E2
e
0.800
0.031
L
0.350
0.450
0.014
0.018
W-Type 10L DFN 4x4 Package
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RT6343
Footprint Information
Footprint Dimension (mm)
Package
Number of Pin
Tolerance
±0.10
P
A
B
C
D
Sx
2.30
3.40
Sy
2.30
2.40
M
Option1
Option2
PSOP-8
8
1.27
6.80
4.20
1.30
0.70
4.51
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
34
DS6343-00 October 2019
RT6343
Footprint Dimension (mm)
Number of
Pin
Package
Tolerance
M
P
A
B
C
D
Sx
Sy
V/W/U/XDFN4x4-10
10
0.80
4.80
3.10
0.85
0.40
3.40
2.70
3.60
±0.05
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
DS6343-00 October 2019
www.richtek.com
35
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