RT6543B_技术文档

®

RT6543A/B

High Efficiency Single Synchronous Buck PWM Controller

for INTEL VCCIN AUX ICL and TGL

General Description

Features

^A High Efficiency Step-Down DC-DC Controller

The RT6543A/B PWM controller provides high efficiency,

excellent transient response, and highDC output accuracy

for stepping down high voltage batteries to generate low

voltage CPU core, I/O, and chipset RAM.

^Built-in 1% Reference Voltage

^2-Bit Programmable Output Voltage with Integrated

^Adjustable Switching Frequency

^Input Voltage Range : 3V to 24V

^Internal Soft-Start to Reduce Inrush Current

^Capability of Driving Large Synchronous Rectifier

MOSFETs

The RT6543A/B supports on chip voltage programming

function between 0V and 1.8V by controlling VID1/VID0

inputs.

Compared with conventional current-mode PWMs, the

RT6543A/B achieves high efficiency without any current

sensing resistors. Furthermore, the RT6543A/B has ability

to drive synchronous rectifier MOSFETs and enters diode

emulation mode at light load condition that also save lots

of power consumption. Besides, the RT6543A/B equips

with UVLO, OVP, UVP, OTP and current limit protection.

All above functions are integrated in a WQFN-20L-3x3

package.

^Power Good Indicator

^Cycle-by-Cycle Current Limit

^Over-/Under-Voltage Protection

 Thermal Shutdown

 RT6543A : Slew Down Mode as VID Change

 RT6543B : Decay Down Mode as VID Change

Pin Configuration

(TOP VIEW)

Applications

20 19 18 17 16

 Notebook Computers

1

2

3

4

5

15

14

13

12

11

CS_DIS

ISENSEP

ISENSEN

PGOOD

COMP

PVCC

PGND

LGATE

PH

 CPU/GPU Core Supply

 Chipset/RAM Supply

AGND

21

UGATE

 GenericDC-DC Power Regulator

6

7

8

9 10

WQFN-20L 3x3

Simplified Application Circuit

RT6543A/B

BOOT

VSYS

PVCC

VSYS

PVCC

V

OUT

BUCK

LGATE

VCC

PH

UGATE

PGOOD

ISENSEP

ISENSEN

FSWSEL

EN

VEN

CS_DIS

VID0

VOUT

FB

VID0

VID1

PGND

AGND

COMP

RGND

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RT6543A/B

Ordering Information

RT6543A/B

Marking Information

RT6543AGQW

Package Type

ML= : Product Code

QW : WQFN-20L 3x3 (W-Type)

YMDNN : Date Code

ML=YM

DNN

Lead Plating System

G : Green (Halogen Free and Pb Free)

Mode when VID changes to lower set point

A : Slew down

B : Decay down

RT6543BGQW

P7= : Product Code

YMDNN : Date Code

Note :

P7=YM

DNN

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Functional Pin Description

Pin No.

Pin Name

Pin Function

Current limit setting. Connect a resistor from CS pin to AGND for overcurrent

protection. CS pin sources a CS current which is 6A (typ) at T_A= 25^oC to

define maximum allowable output current. CS terminal voltage VCS is

limited from 0.5V to 2.8V over all operation temperature.

1

CS_DIS

Positive input pin for current sense of buck.(for load line setting, in zero load

line condition is short this pin with ISENSEN)

2

3

ISENSEP

ISENSEN

Negative input pin for current sense of buck.(for load line setting, in zero

load line condition is short this pin with ISENSEP)

Power good indicator output for VCCIN_AUX. This open-drain is pulled low

as UVP, OVP, OTP, EN low and output voltage is not regulated (such as

before soft-start). An external pull-up resistor to VCC or other external rail is

required, in which the pull-up resistor is recommended from 10k to 100k.

4

PGOOD

5

6

7

8

COMP

FB

Internal error amplifier output. For loop compensator application.

Internal error amplifier input. For loop compensator application.

Return ground for VCCIN_AUX from CPU side.

RGND

VOUT

VCCIN_AUX feedback input. This pin is unit feedback for AUX regulation

VCCIN_AUX setting pin. Use this pin to adjust AUX rail frequency setting for

different LC combination. (High state: Direct pull high to VCC, Hi-Z state:

Floating, Low state: Direct connect to GND). Default switching frequency is

floating, 600KHz. Anytime, make sure FSWSEL  VCC < 0.5V.

9

FSWSEL

BOOT

Supply bootstrap capacitor output pin. The bootstrap capacitor is charged by

this pin while the low-side MOSFET is turned on. Therefore, the bootstrap

capacitor can provide the energy to turn on the high-side MOSFET. Connect

this pin through the bootstrap capacitor to the PH pin.

10

Upper gate driver with sink and source output. Connect to the gate of the

high-side MOSFET through a short and low inductance path.

11

12

UGATE

PH

Switch node of AUX. Connect to the power inductor. For the high-side gate

driver return path, connect a capacitor from PH to BOOT. Beside, this pin is

noisy, keep the sensitive trace or signal away from PH.

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DS6543A/B-01 March 2020

RT6543A/B

Pin No.

Pin Name

Pin Function

Low-side gate driver output pin. Connect this pin to the gate of low-side

MOSFET. Notice, DO NOT connect the resistor RG_EXT between LGATE

and gate terminal of low-side MOSFET, otherwise it might cause undesired

shoot-through since the LGATE voltage is monitored for shoot-through

protection.

13

LGATE

Power GND. AGND and PGND are connected with a short trace and at only

one point to reduce circulating currents.

14

15

PGND

PVCC

Bias voltage for internal gate driver. The required bias voltage for PVCC is

5V typ. For avoiding noise disturbance, the supplied bias voltage must be

stable, Beside, a RC filter (R = 2.2/0603 and C = 1F/0603) from bias

voltage to PVCC pin is necessary which should be placed as close as

physically possible to PVCC pin.

Bias voltage for control logic. The required bias voltage for VCC is 5V typ.

For avoiding noise disturbance, the supplied bias voltage must be stable,

Beside, a RC filter (R = 2.2/0603 and C = 1F/0603) from bias voltage to

VCC pin is necessary which should be placed as close as physically

possible to VCC pin.

16

VCC

VCCIN_AUX VID control signal. Adjust AUX output voltage(0V, 1.1V, 1.65V

and 1.8V)

17

18

AUX_VID0

AUX_VID1

VCCIN_AUX VID control signal. Adjust AUX output voltage(0V, 1.1V, 1.65V

and 1.8V)

Enable control input. As voltage is lower than 0.3V, RT6543A/B is in

shutdown mode and all power rails are disabled. As RT6543A/B is higher

than 1V, RT6543A/B is woken up.

19

20

EN

System voltage sense. Connect this pin to input voltage for UVLO monitor

and controller’s on-time setting. For avoiding any noise to disturb on-time

setting, a RC filter (R = 2.2/0603 and C = 0.1F/0603) is required from

input voltage to VSYS.

VSYS

Exposed pad for package. Electrically isolated. Directly solder to the large

PGND plane and use thermal vias to connect PGND of other layers for

thermal resistor reduction

21 (Exposed pad) GND

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RT6543A/B

Functional Block Diagram

VID1

VID0

Enable

Logic

To driver Logic

Reference

Output Gen.

EN

To Power on Reset

RGND

VCC

VOUT

OV

Power On Reset

&Central Logic

+

-

2.2V

PGOOD

UV

60% V

+

-

REF

Control & Protection Logic

PGOOD

90% V

PVCC

+

REF

V

REF

-

BOOT

UGATE

PH

Soft-Start &

Slew Rate

Control

HIZ

Driver

Logic

TON

Gen.

VREF_

DROOP

+

PWM

LGATE

PGND

-

+

ISENSEP

ISENSEN

Droop

-

PWM

CMP

EA

FB

-

Zero Current

Detction

COMP

VSYS

+

To Power

on Reset

V

IN

-

+

Current

Limit

Detection

Frequency

Lock and

Selection

6µA

FSWSEL

AGND

CS_DIS

X(-1/12)

Operation

The RT6543A/B is a constant on-time synchronous step-

down controller. In normal operation, the high-side N-

MOSFET is turned on when the output voltage is lower

than V_REF, and is turned off after the internal one-shot

timer expires. While the high-side N-MOSFET is turned

off, the low-side N-MOSFET is turned on to conduct the

inductor current until next cycle begins.

Current Limit

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle. The current

limit threshold can be set with an external voltage setting

resistor on the CS_DIS pin.

Soft-Start (SS)

Over-Voltage Protection (OVP) & Under-Voltage

Protection (UVP)

For internal soft-start function, an internal current source

charges an internal capacitor to build the soft-start ramp

voltage. The output voltage will track the internal ramp

voltage during soft-start interval.

The output voltage is continuously monitored for over-

voltage and under-voltage protection. When the output

voltage exceeds 2.2V (Typ.), UGATE goes low and LGATE

is forced high. When the feedback voltage is less than

60% of output voltage, under-voltage protection is triggered

and then both UGATE and LGATE gate drivers are forced

low. The controller is latched until VCC is re-supplied and

exceeds the POR rising threshold voltage or EN is reset.

PGOOD

The power good output is an open-drain architecture. When

the soft-start is finished, the PGOOD open-drain output

will be high impedance.

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DS6543A/B-01 March 2020

RT6543A/B

Absolute Maximum Ratings (Note 1)

 VSYS to PGND ----------------------------------------------------------------------------------------------------------- −0.3V to 28V

 VCC to PGND ------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V

 RGND to PGND ----------------------------------------------------------------------------------------------------------- −0.3V to 0.3V

 BOOT to PH --------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V

 LGATE to PGND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V

<100ns ----------------------------------------------------------------------------------------------------------------------- −2V to 7.5V

 PH to PGND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 30V

<100ns ----------------------------------------------------------------------------------------------------------------------- −10V to 35V

 UGATE to PGND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 36.8V

<100ns ----------------------------------------------------------------------------------------------------------------------- −10V to 41.8V

 Other Pins------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V

 Power Dissipation, P_D@ T_A= 25°C

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------ 3.33W

 Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θ_JA------------------------------------------------------------------------------------------------------- 30°C/W

WQFN-20L 3x3, θ_JC------------------------------------------------------------------------------------------------------ 7.5°C/W

 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C

 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 VCC Input Voltage--------------------------------------------------------------------------------------------------------- 4.5V to 5.5V

 VSYS Input Voltage ------------------------------------------------------------------------------------------------------ 3V to 24V

 Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C

Electrical Characteristics

(V_CC= 5V, V_SYS= 7.4V, T_A= 25°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Supply Voltage VCC

Supply Voltage

V_CC

4.5

--

5

5.5

--

V

I_SHDN

I_DACOFF

I_VCC

V_EN= 0V

A

mA

Supply Current

V_EN= 5V, VID = 00

40

0.3

--

V_EN= 5V, no switching

--

0.55

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RT6543A/B

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

VCC POR/UVLO Threshold

POR Threshold

V_{CC_POR}

4

4.2

3.9

4.4

4.1

V

UVLO Threshold

V_{VCC_UVLO}

3.7

Logic Threshold

VID0/VID1 Input Low

Voltage

V_{ID_IL}

V_{ID_IH}

Falling edge, V_CC= 5V

Rising edge, V_CC= 5V

--

1

0.3

--

V

--

VID0/VID1 Input High

Voltage

EN Input Low Voltage

V_{EN_IL}

Falling edge, V_CC= 5V

Rising edge, V_CC= 5V

Falling edge, V_CC= 5V

--

1

0.3

--

V

EN Input High Voltage

FSWSEL Input High Level

FSWSEL Input Low Level

V_{EN_IH}

V_{FSWSEL_H}

V_{FSWSEL_L}

4.5

--

0.4

FSWSEL Input Floating

Level

V_{FSWSEL_HIZ}Floating, V_CC= 5V

2

2.5

3

V

VSYS UVLO

VSYS UVLO Threshold

UVLO Hysteresis

V_{SYS_UVLO}

--

2.7

200

2

--

V

V_{SYS_HYS}

mV

A

V_SYS= 19V, V_CC= 5V

Input Current

I_VSYS

V_SYS= 8.4V, V_CC= 5V

V_CC< V_{CC_UVLO}

0.9

0

Thermal Shutdown

Threshold

T_SD

--

160

20

--

C

Thermal Shutdown

Hysteresis

T_SD

Power Good Indicator (upper side threshold decide by OV threshold)

PGOOD High Threshold

PGOOD Low Threshold

PGOOD Leakage Current

V_{PGOOD_IH}

V_{PGOOD_IL}

I_{LK_PGOOD}

Rising edge

86

80

90

84

94

88

1

%V_OUT

A

Falling edge

High state, V_PGOOD= 5V

--

PGOOD Output Low

Voltage

V_{PGOOD_LOW}I_{PGOOD_LOW}= 10mA

0.3

V

Input Supply Voltage

Supply Voltage

V_IN

3

--

24

V

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DS6543A/B-01 March 2020

RT6543A/B

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Reference and Soft-Start

VID[1:0] = 11

1.782

1.6335

1.089

0.01

1.8

1.65

1.1

0

1.818

1.666

1.111

0.01

VID[1:0] = 10

VID[1:0] = 01

VID[1:0] = 00

Output Voltage Scaling

V

Dynamic Voltage Scale

Slew Rate

SR_DVS

12

--

60

mV/s

Current Limit

I_LIM

5.4

0.4

6

6.6

2.8

A

Current Limit Setting

Range

V_CS

Voltage of pin CS_DIS

--

V

GND PHASE = VCS / 12

0.5V  VCS  2.8V

15

7

VCS / 12

4700

+15

+7

--

%

Current Limit Voltage

V_{_PHASW_OC}

GND PHASE = VCS / 12

0.4V  VCS  0.5V

mV

Current Limit Temperature

Coefficient

--

ppm/C

Switching Frequency and Minimum Off Timer

FSWSEL = 5V

--

0.8

0.6

0.4

--

FSWSEL = HIZ

FSWSEL = 0V

Switching Frequency

f_SW

MHz

KHz

Switching Frequency

Programmable Step

--

200

--

Switching Frequency

Accuracy

f_SW

FSWSEL = HIZ

0.51

--

0.6

0.69

--

MHz

ns

Minimum Off-Time

t_{OFF_MIN}

130

Protections

OVP Trip Threshold

OVP Propagation Delay

UVP Trip Threshold

UVP Propagation Delay

V_OVP

OVP detect

UVP detect

--

2.2

5

--

V

T_{DELAY_OVP}

V_UVP

s

%

s

60

5

t_{DELAY_UVP}

Zero Current Crossing

Threshold

V_{PH_ZC}

4

--

4

mV

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RT6543A/B

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Driver

UGATE Driver Source

UGATE Driver Sink

LGATE Driver Source

LGATE Driver Sink

R_UGATEsr

R_UGATEsk

R_LGATEsr

R_LGATEsk

BOOT  LX = 5V

--

2

1

4

2

3



BOOT  LX = 5V

LGATE, high state, V_CC= 5V

LGATE, low state, V_CC= 5V

1.5

0.7

From LGATE falling to UGATE

rising

t_{D_LU}

30

20

40

ns



--

Dead Time

From UGATE falling to LGATE

rising

t_{D_UL}

Internal Boost Diode

Resistance

R_BOOT

VCC to BOOT, I_BOOT= 10mA

80

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ_JAis measured under natural convection (still air) at T_A= 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θ_JCis measured at the

exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

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DL6543A/B

RT6543A/B

Typical Application Circuit

VSYS

RT6543A/B

1

20

10

CS_DIS

VSYS

BOOT

0.1µF

11

12

13

14

UGATE

PH

2.2

15

0.22µH

PVCC

VCC

5V

V

OUT

C

OUT

1µF

2.2

1µF

LGATE

PGND

16

2

3

8

100

ISENSEP

ISENSEN

VOUT

100

10k

4

AUX_SENSE

PGOOD

EN

820P

0.22µF

19

18

17

9

16.9k

1.4k

EN

5

COMP

VID0

VID1

VID0

VID1

15P

6

7

16.9k

FB

AUX_VSSSENSE

Refer to Table 1

FSWSEL set up

FSWSEL

RGND

AGND

21 (Exposed pad)

C_OUT

ICL

Y-Line (PCS)

U-Line (PCS)

17

19

22

20

TGL

C_OUTtype : 22F/6.3V

Table 1. FSWSEL set up

Frequency setting

800kHz

FSWSEL

High (>4.5V)

Floating (2~3V)

Low (<0.4V)

Suggestion

Connect to VCC

Floating

600kHz

400kHz

Connect to GND

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RT6543A/B

Typical Operating Characteristics

Power On from EN

V_OUT

(1V/Div)

V_OUT

(1V/Div)

PH

(20V/Div)

PH

(20V/Div)

EN

(2V/Div)

EN

(2V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

V_SYS= 12V, V_CC= 5V, V_OUT= 1.8V, I_OUT= 32A

V_SYS= 12V, V_CC= 5V, V_OUT= 1.65V, I_OUT= 24A

Time (200μs/Div)

Over-Current Limit

V_OUT

(600mV/Div)

V_OUT

(600mV/Div)

I_L

(10A/Div)

PH

(20V/Div)

PH

(20V/Div)

PGOOD

(6V/Div)

PGOOD

(6V/Div)

V_IN= 12V, V_CC= 5V, V_OUT= 1.8V

V_IN= 12V, V_CC= 5V, V_OUT= 1.65V

Time (50μs/Div)

VID Change

V_OUT

offset 1.65V

(80mV/Div)

V_OUT

offset 1.65V

(80mV/Div)

PH

(10V/Div)

PH

(10V/Div)

VID0

(10V/Div)

VID0

(5V/Div)

VID1

(5V/Div)

VID1

(5V/Div)

V_IN= 12V, V_CC= 5V

V_OUT= 1.65V to 1.8V, I_OUT= 5A

V_OUT= 1.8V to 1.65V, I_OUT= 5A

Time (10μs/Div)

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DS6543A/B-01 March 2020

RT6543A/B

VID Change

V_OUT

offset 1.1V

(300mV/Div)

V_OUT

offset 1.1V

(300mV/Div)

PH

(20V/Div)

PH

(20V/Div)

VID0

(5V/Div)

VID0

(5V/Div)

V_IN= 12V, V_CC= 5V

V_OUT= 1.65V to 1.1V, I_OUT= 5A

VID1

(5V/Div)

VID1

(5V/Div)

V_IN= 12V, V_CC= 5V

V_OUT= 1.1V to 1.65V, I_OUT= 5A

Time (10μs/Div)

Load Transient Response

V_OUT

offset 1.65V

offset 1.8V

(50mV/Div)

PH

(10V/Div)

PH

(10V/Div)

I_OUT

offset 12A

(12A/Div)

I_OUT

offset 12A

(12A/Div)

V_IN= 12V, V_OUT= 1.65V

V_IN= 12V, V_OUT= 1.8V

V_CC= 5V, Load = 7.2A to 24A

Slew rate = 16.8A/μs

V_CC= 5V, Load = 12.8A to 32A

Slew rate = 19.2A/μs

Time (10μs/Div)

Over-Voltage Protection

V_OUT

(600mV/Div)

V_OUT

(600mV/Div)

PH

(3V/Div)

PH

(3V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

V_IN= 12V, V_CC= 5V, V_OUT= 1.8V, OVP = 2.2V

V_IN= 12V, V_CC= 5V, V_OUT= 1.65V, OVP = 2.2V

Time (20μs/Div)

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RT6543A/B

V1P8 Efficiency vs. Output Current

V1P65 Efficiency vs. Output Current

95

93

91

89

87

85

83

81

79

77

75

95

93

91

89

87

85

83

81

79

77

75

V_IN= 7V

V_IN= 12V

V_IN= 24V

V_IN= 7V

V

_IN= 12V

_IN= 24V

V_CC= 5V, V_OUT= 1.8V

V_CC= 5V, V_OUT= 1.65V

12 16 20 24

0

4

8

12

16

20

24

28

32

0

4

8

Output Current (A)

Output Voltage vs. Output Current

1.670

1.830

1.825

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.665

1.660

1.655

1.650

1.645

V_IN= 7V

V_IN= 12V

V_IN= 24V

V_CC= 5V, V_OUT= 1.65V

12 16 20 24

V_CC= 5V, V_OUT= 1.8V

16 20 24 28 32

0

4

8

0

4

8

12

Output Current (A)

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DS6543A/B-01 March 2020

RT6543A/B

Application Information

The RT6543A/B is a constant on-time PWM controller

which supports on chip voltage programming function (0V,

1.1V, 1.65V and 1.8V) by controlling VID1/VID0 inputs.

The control scheme uses in the RT6543A/B is called

FCOT^TM(Fixed Constant On-Time) which easy handles

wide input/output ratios and provides fast response to load

steps while maintains a relatively constant operating

frequency.

discontinuous conduction mode, for emulating the behavior

of diode, the few negative current is allowed to flow through

the low-side MOSFET when inductor's free-wheeling

current is in negative status. On the other hand, as the

load current increasing from light load to heavy load, the

switching frequency raises to the expected value where

inductor current is in continuous conduction mode. Figure

1 shows the behavior of inductor current in boundary

conduction mode and the load current can be expressed

as below :

FCOT^TMis provided a solution to solve a problem of poor

load transient timing in current mode PWM, and performs

excellent noise immunity for suiting comprehensive

applications.

I

L

Slope = (V -V

) / L

IN OUT

I

PEAK

LOAD

PWM Operation

I

= I

PEAK

/2

FCOT^TMcontrol scheme relies on the output filter

capacitor's Effective Series Resistance (ESR) to act as a

current-sense resistor, so the output ripple voltage provides

the PWM ramp signal. Referring to the function block

diagrams of the RT6543A/B, the synchronous high-side

MOSFET is turned on at the beginning of each cycle.

After the internal one-shot timer expires, the high-side

MOSFET is turned off. The pulse width of this one-shot is

determined by the converter's input and output voltages

for keeping the frequency fairly constant with entire input

voltage range. Besides, the pulse width of low-side one-

shot is set as 130ns(typ.) minimum off-time.

t

0

t

ON

Figure 1. Boundary Condition of CCM/DEM

(V_IN V_OUT

)

I_LOAD(SKIP)



t_ON

2L

where t_ONis the on-time.

Output Voltage Transition Operation

Through controlling the digital pins VID0 and VID1, V_OUT

can be changed to setting output voltage. During the

downward transition (V_OUTfrom high to low condition),

internal V_REFis adjusted to a new V_REFby converting

VIDx signal. During this period, the low-side MOSFET is

turned on to pull down the output voltage V_OUT. LGATE is

remained high until V_FBfalls to the new internal V_REFand

UGATE goes high to start a new cycle, as shown in Figure

2.

On-Time Control (t_ON

)

There are two inputs on on-time one-shot comparator. One

input is used to detect input voltage and then transfer to

proportional current. The transferred current is applied to

charge to on-time capacitor till threshold V_OUTconnected

to the other input of comparator. Further, the on-time is

determined, relating to V_INand V_OUT. This implementation

results in a nearly constant switching frequency without

any clock generators.

Diode Emulation Mode (DEM)

In diode emulation mode, the RT6543A/B automatically

reduces switching frequency at light load conditions to

maintain high efficiency. Therefore, during period of

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13

RT6543A/B

VIDx

If the V_OUTchange is too significant, UGATE continues to

output several cycle with minimum off-time. At the same

time, inductor current is rapidly increase which leads to

storage energy LI²of inductor flowing to output capacitor

after V_FBachieving new V_REF. This causes an enormous

overshoot on V_OUT, as shown in Figure 4.

V

REF

Initial V

REF

New V

REF

V

FB

UGATE

LGATE

VIDx

New V

REF

V

REF

Initial V

REF

Initial V

OUT

UGATE

V

OUT

New V

OUT

Figure 2. Down Transition of Output Voltage

During the upward transition (V_OUTfrom low to high),

internal V_REFis raised to the new level V_REFthrough VIDx

LGATE

New V

OUT

change. At this moment, V_FBis increased to new V_REF

.

However, for handling fast transition of output voltage, the

switching frequency is speeded up and the minimum off-

time is limited as 130ns (typ.) till V_FBis over the new

V

OUT

Initial V

OUT

Figure 4. Overshoot of Output VoltageDuring Upward

Transition

V_REF

.

The overshoot voltage can be approximately calculated in

following expression, where I_CLis the current limit level

VIDx

New V

REF

and V_FINALis the desired set point of final V_OUT

.

I_CL²L

C_OUT

V

REF

2

V_MAX

=

+ V_FINAL

Initial V

REF

V

FB

Droop Setting and Thermal Compensation

The RT6543A/B provide droop setting viaDCR network as

Figure 5. Due to the cooper wire of inductor has a positive

temperature coefficient.

UGATE

And hence, temperature compensation is necessary for

the lossless inductor current sense. For thermal

compensation, an NTC Thermistor is put in the current

sense network and it can be used to compensation DCR

variation from temperature is changed.

LGATE

New V

OUT

V

OUT

The DCR network equation is as follows :

Initial V

OUT

Figure 3. Upward Transition of Output Voltage

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14

DS6543A/B-01 March 2020

RT6543A/B

L

The CS_DIS pin is connected toGNDthrough a trip voltage

setting resistor R_CS. The RT6543A/B sources a 6μA

current I_CSto R_CS, and current limit level V_CScan be defined

as follows :

1 +

s

R

EQ

+ R

DCR

V

= I DCR



ISENSEP-ISENSEN

L

R

X

R

C

R

EQ

X

EQ

1 +

s

R

+ R

EQ

X

R

R

NTC

P

Let R

EQ

= R

+

S

R

+ R

V_CS= R_CS 6μA

P

NTC

According to current sense network, the corresponding

equation is represented as follows :

The inductor valley current detection is completed by

monitor low-side MOSFET voltage during period of UGATE

in low status. Hence, the relationship between current

limit level V_CSand over current setting point I_OCPcan be

defined as follows :

R

R C

EQ

L

X

=

,

DCR

R

+ R

X

EQ

R

EQ

+ R

then V

ISENSEP-ISENSEN

= I DCR

L

R

X

EQ

I_{L_ripple}

V_CS

I_OCP

=

+

If DCR network time constant matches inductor time

constant, L/DCR, an expected load transient waveform

can be designed.

12R_{DS(ON)_LS}

2

V_CS

12R_{DS(ON)_LS}

(V_IN V_OUT)V_OUT

1

=

+

2Lf_sw

V

IN

The droop set equation as follows :

As over current condition is triggered, the duty cycle is

limited, and, further, V_OUTstarts to drop. If V_OUTdrops to

under-voltage protection level, the RT6543A/B is into latch

mode. Only EN or V_CCbeing reset, the RT6543A/B can

be released from latch mode.





R

EQ

+ R

V

=

I

DCR

8





DROOP

L

R

X

EQ

R





V

EQ

DROOP

R

=

= DCR

8

DCLL

I

R

+ R

L

X EQ

Where, 8 is internal parameter of RT6543A/B.

Note that the VCS should be set from 0.4V to 2.8V.

For detailDCR network calculation, Richtek provide design

for customer in order to simplify design.

I

L





R

EQ

+ R

Note :

I

DCR

must be < 25mV





L

R

X

EQ





I

L_peak

VOUT

I

L

I

LOAD

L

DCR

C

RT6543A/B

ISENSEP

R

X

I

LIM

+

GM

R

t

S

R

NTC

-

0

ISENSEN

Figure 6. “Valley” Current Limit

R

P

MOSFET Gate Driver (UGATE, LGATE)

Figure 5.DCR Sense Circuit and Thermal Compensation

The high-side driver is designed to drive high current and

low R_DS(ON)N-MOSFET(s). When configured as a floating

driver, 5V bias voltage is delivered from V_CC. The average

Current Limit Setting

The RT6543A/B provides a cycle-by-cycle current limiting

function that is implemented by a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at the CS_DIS pin is above the current limit

threshold, the PWM is not allowed to initiate a new cycle

as shown in Figure 6. In order to provide both good accuracy

and a cost effective solution, the RT6543A/B supports

temperature compensation for MOSFET R_DS(ON)sensing.

driving current is proportional to the gate charge at V_GS

=

5V and is supplied from a flying capacitor connected

between BOOT and PH pins. On the other hand, the low-

side driver is used to drive high current and low R_DS(ON)N-

MOSFET, which is relied on V_CCsupplies 5V bias voltage.

Due to the instantaneous driving current sourced from V_CC,

V_CCmust connect a fly capacitor to GND. Besides, for

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15

RT6543A/B

preventing short through occurrence within the region of

high and low-side MOSFETs transition, there is a dead

time between UGATE and LGATE.

Over-Temperature Protection

The RT6543A/B includes an over-temperature protection

(OTP) circuitry to prevent overheating caused by excessive

power dissipation. As junction temperature is over 160°C,

OTP circuitry will be triggered and then shuts down the

RT6543A/B into latch mode. Only toggle EN or re-power

on V_CCagain, the RT6543A/B can relief protection

situation and restart.

Power Good Output (PGOOD)

The power good output is an open drain output that requires

a pull-up resistor. As output voltage is lower than 16%

(typ.) setting voltage, PGOODwill be pulled low. In other

words, if output voltage is higher than 90% (typ.) setting

voltage, PGOOD will be pulled high. In soft-start period,

PGOODis held low till soft-start function is over and output

voltage reaches 90% setting voltage.

For continuous operation and adequate cooling, the

junction temperature does not exceed 160°C.

External Bootstrap Capacitor (C_BOOT

)

Connect a 0.1μF low ESR ceramic capacitor between

BOOT pin and PH pin. This bootstrap capacitor provides

energy to drive high-sideN-channel MOSFET. If high-side

MOSFET is turned too fast to pass EMI, a small resistor

(<10Ω) can be added between BOOT and the external

bootstrap capacitor. This move will slow high-side MOSFET

turn-on and then improve EMI ability.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VCC rises above

4.2V (typ). After POR is triggered, the RT6543A/B resets

the fault latch and starts a new operation cycle. If V_CCis

below 3.9V, the RT6543A/B is into under-voltage lockout

(UVLO), which is forced UGATE and LGATE in low status.

Furthermore, the RT6543A/B provides an internal soft-start

function for preventing great inrush current and output

overshoot during converter turn-on period. After EN is

enable, the RT6543A/B operating in soft-start period, ramp

of internal reference voltage is clamped to compare with

FB signal that, further, limits converter's turn-on time.

Inductor Selection

Selecting an inductor involves specifying its inductance

and also its required peak current. The exact inductor value

is generally flexible and is ultimately chosen to obtain the

best mix of cost, physical size, and circuit efficiency.

Lower inductance benefits from reduced size and cost

and improves the circuit’s transient response. However,

lower inductance also leads to greater inductor ripple

current and output ripple voltage, while efficiency is

reduced. Conversely, higher inductance might gains more

efficiency, but inductor's size and resistance will be

physically larger because of more turns of wire required.

As well, higher inductance slows transient response,

because inductor needs more time to achieve volt-second

balance.

Output Over-Voltage Protection and Under-Voltage

Protection

For preventing output voltage raising above regulation level

to damage next stage components, the RT6543A/B

provides output over-voltage protection (OVP). If output

voltage is over OVP level, UGATE remains low status. At

the same time, LGATE is pulled high till the inductor current

reaches zero or next on-time one-shot is triggered. As

output voltage upon OVP threshold lasts over 20μs

(typical), OVP function is triggered.. In addition, the

RT6543A/B also supplies output under-voltage protection

(UVP). If output voltage below UVP threshold continues

over 20μs (typical), UVP function is triggered. Both of

protection functions are behaved latch-off mode in the

RT6543A/B. Once the protection is triggered, the

RT6543A/B goes to shut-down and stops switch. Only

toggle EN or re-power on V_CC, the RT6543A/B can relief

protection situation and work.

For designing a good compromise between size, efficiency

and transient response, inductor ripple current (ΔI_L) is

considered which is specified from 20% to 50% of the

desired full output load current. Calculate the approximate

inductance by selecting the input and output voltages,

the switching frequency (f_SW), the maximum output current

(I_OUT(MAX)) and estimating the percentage current of

I_OUT(MAX)with ΔI_L.

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16

DS6543A/B-01 March 2020

RT6543A/B

V_OUT(V_IN V_OUT

)

I_OUTV

C_INf_SWV_OUT

V_OUT

)

IN

L =

V

=

(1

IN

V_INf_SW ∆I_L

V

IN

The typical operating circuit is recommended to use four

Once an inductance is chosen, the ripple current (ΔI_L) can

be calculated to determine the required peak inductor

current.

10μF and low ESR ceramic capacitors on the input.

Output Capacitor Selection

V_OUT(V_IN V_OUT

)

I_L=

and

The RT6543A/B are optimized for ceramic output capacitors

and best performance. The total output capacitance value

is usually determined by the desired output voltage ripple

level and transient response requirements for sag

(undershoot on positive load steps) and soar (overshoot

on negative load steps).

V_INf_SWL

I_L

2

I_L(PEAK)= I_OUT(MAX)

+

To guarantee the required output current, saturation

current rating and thermal rating of selected inductor must

exceed I_L(PEAK), where are minimum requirements. To

maintain control of inductor current in overload and short-

circuit conditions, some applications may design current

rating up to the current limit value. However, the IC's output

under-voltage shutdown feature makes this unnecessary

for most applications.

Output ripple is made up of output capacitor's ESR and

stored charge. These two ripple components are called

ESR ripple and capacitive ripple. Since ceramic capacitors

have extremely low ESR and relatively little capacitance,

both components are similar in amplitude and have to be

considered.

For best efficiency, choose an inductor with a low DC

resistance that meets the cost and size requirements.

V

= V

+ V

RIPPLE

RIPPLE(ESR) RIPPLE(C)

V

= I R

L ESR

RIPPLE(ESR)

Input Capacitor Selection

I_L

8C_OUTf_SW

V_RIPPLE(C)

=

High quality ceramic capacitor, such as X5R or X7R, with

values greater than 20μF are recommended for input

capacitor. The X5R and X7R ceramic capacitors are usually

selected for power regulator capacitors because the

dielectric material behaves less capacitance variation and

more temperature stability. Voltage and current rating are

the key parameters to select an input capacitor. Generally,

selecting an input capacitor with voltage rating 1.5 times

greater than the maximum input voltage is a conservatively

safe design. The input capacitor is used to supply the

input RMS current, which can be approximately calculated

using the following equation :

In addition to voltage ripple at the switching frequency,

the output capacitor and its ESR also affect the voltage

sag (undershoot) and soar (overshoot) when the load steps

up and down abruptly. FCOT^TMtransient response is very

quick and output transients are usually small. The

amplitude of the ESR step up or down is a function of the

load step and the ESR of the output capacitor :

V

= I

R

ESR_STEP

OUT ESR

The amplitude of the capacitive sag is related to load step,

output capacitor value, inductor value, input-to-output

voltage differential, and the maximum duty cycle. Hence,

the approximate on-time (neglecting parasitic) and

maximum duty cycle can be calculated from given input

and output voltages, as follows :



²



V_OUT

I_L

12

2

I_RMS

=

 (1

)I_OUT+



V









IN

The next step is to select a proper capacitor for RMS

current rating. One good design uses more than one

capacitor with low Equivalent Series Resistance (ESR) in

parallel to form a capacitor bank. The input capacitance

value determines the input ripple voltage of the regulator.

The input voltage ripple can be approximately calculated

by using following equation :

V

t

ON

OUT

t

=

and D

=

ON

MAX

V f

t

+ t

ON OFF_MIN

IN SW

According to calculatedD_MAX, the output sag voltage can

be obtain. As follows :

2

L(I

)

OUT

V

=

SAG

2C

(V

D

 V

)

OUT

IN(MIN)

MAX

OUT

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RT6543A/B

The amplitude of the capacitive soar is related to the load

step, the output capacitor value, the inductor value and

the output voltage. Therefore, output soar voltage can be

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Four-Layer PCB

determined, as below :

2

L(I_OUT

)

V_SOAR

=

2C_OUT V_OUT

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature T_J(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 7.Derating Curve of Maximum PowerDissipation

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125°C. The junction-to-ambient thermal

resistance, θ_JA, is highly package dependent. For a

WQFN-20L 3x3 package, the thermal resistance, θ_JA, is

30°C/W on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at T_A= 25°C can be calculated as below :

P_D(MAX)= (125°C − 25°C) / (30°C/W) = 3.33W for a

WQFN-20L 3x3 package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed T_J(MAX)and the thermal

resistance, θ_JA. The derating curves in Figure 7 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

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DS6543A/B-01 March 2020

RT6543A/B

Layout Considerations

Layout is very important in high frequency switching

converter design. If the design is improper, the PCB could

radiate excessive noise and contribute instability in

converter. For the best performance of the RT6543A/B,

the following guidelines should be strictly followed.

 Connect a RC low-pass filter from V_CC, (1μF and 10 are

recommended). Place the filter capacitor close to the

IC.

 Keep current limit setting network as close as possible

to the IC. Routing of the network should be kept away

from high voltage switching nodes to prevent it from

coupling.

 Connecting between the drivers and the respective gate

of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance.

 All the sensitive analog traces and components, such

as FB, GND, EN, PGOOD, CS and VCC, should be

placed away from high voltage switching nodes (PHASE,

LGATE, UGATE, or BOOT) nodes to prevent coupling.

Use internal layer(s) as ground plane(s) and shield the

feedback trace from power traces and components.

 Current sense connections must always be made by

Kelvin connections to ensure an accurate signal.

 Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses.

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RT6543A/B

Outline Dimension

1

2

1

2

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

2.900

1.650

2.900

1.650

0.800

0.050

0.250

3.100

1.750

3.100

1.750

0.028

0.000

0.007

0.006

0.114

0.065

0.114

0.065

0.031

0.002

0.010

0.122

0.069

0.122

0.069

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 20L QFN 3x3 Package

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20

DS6543A/B-01 March 2020

RT6543A/B

Footprint Information

Footprint Dimension (mm)

Number of

Package

Tolerance

P

Ax

Ay

Bx

By

C

D

Sx

Sy

V/W/U/XQFN3*3-20

20

0.40

3.80

2.10

0.85

0.20

1.70

±0.05

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify

that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek

product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;

nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of Richtek or its subsidiaries.

DS6543A/B-01 March 2020

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21


型号：	RT6543B
厂家：	RICHTEK TECHNOLOGY CORPORATION
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文件：	总21页 (文件大小：337K)
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