RT6550A [RICHTEK]
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| 型号： | RT6550A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
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®
RT6550A
Synchronous DC-DC Step-Down Controller with 5V LDO
General Description
Features
Support Connected Shutdown Mode for Ultrabook
CCRCOT Control with 100ns Load Step Response
PWM Maximum Duty Ratio > 98%
5V to 25V Input Voltage Range
The RT6550A is a step-down, controller generating supply
voltages for battery-powered systems. It includes Pulse-
Width Modulation (PWM) controller adjustable from 2V
to 5.5V, and a 5V linear regulator which provides up to
100mA output current. Other features include on-board
power-up sequencing, internal soft-start, and soft-
discharge output that prevents negative voltage during
shutdown.
2V to 5.5V Output Voltage Range
5V LDO with 100mA Output Current
Internal Frequency Setting with 300kHz @ VIN =12V
Internal Soft-Start and Soft-Discharge
4700ppm/°C RDS(ON) Current Sensing
Independent Switcher Enable Control
Built-In OVP/UVP/OCP/OTP
A constant current ripple PWM control scheme operates
without sense resistors and provides 100ns response to
load transient. The RT6550A is available in the WDFN-
10L 3x3 package.
Non-Latch UVLO
Applications
Notebook and Sub-Notebook Computers
Ordering Information
RT6550A
System Power Supplies
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
3-Cell and 4-Cell Li+ Battery-PoweredDevices
Package Type
QW : WDFN-10L 3x3 (W-Type)
Pin Configuration
(TOP VIEW)
Lead Plating System
G : Green (Halogen Free and Pb Free)
10
9
1
2
3
EN
CS
FB
LGATE
PHASE
UGATE
BOOT
VIN
8
7
6
4
5
VO_DIS
LDO5
Note :
11
***Empty means Pin1 orientation is Quadrant 1
Richtek products are :
WDFN-10L 3x3
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Marking Information
6W= : Product Code
Suitable for use in SnPb or Pb-free soldering processes.
YMDNN : Date Code
6W=YM
DNN
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
1
RT6550A
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
EN
Enable control input.
Current limit setting. Connect a resistor to GND to set the threshold for
synchronous RDS(ON) sense. The GND - PHASE current limit threshold is 1/8th the
voltage seen at CS over a 0.2V to 2V range. There is an internal 10A current
source from LDO5 to CS.
2
CS
Feedback voltage input. Connect FB to a resistive voltage divider from VOUT to
GND to adjust output from 2V to 5.5V.
3
4
5
6
7
8
9
FB
VO_DIS
LDO5
VIN
Output discharge function.
5V linear regulator output. LDO5 is also the supply voltage for the low-side
MOSFET and analog supply voltage for the device.
Power input for 5V LDO regulator and buck controller.
Bootstrap supply for high-side gate driver. Connect to an external capacitor
according to the typical application circuit.
BOOT
UGATE
PHASE
High-side gate driver output. UGATE swings between PHASE and BOOT.
Switch node of MOSFETs. PHASE is the internal lower supply rail for the UGATE
high-side gate driver. PHASE is also the current sense input.
10
LGATE
GND
Low-side gate driver output. LGATE swings between GND and LDO5.
11
Ground. The exposed pad must be soldered to a large PCB and connected to GND
for maximum power dissipation.
(Exposed Pad)
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS6550A-00 September 2016
RT6550A
Functional Block Diagram
VO_DIS
VIN
Shutdown
Discharge
Power On
Reset
LDO5
LDO5
113%
VREF
OVP
UVP
+
VREF
-
Over-
Temperature
Protection
Control & Protection Logic
52%
VREF
+
-
Soft
Start &
Slew
Rate
Control
BOOT
UGATE
PHASE
+
-
TON
Generator
PWM
PWM
CMP
Driver
Logic
FB
EN
LDO5
Enable
Logic
LGATE
GND
10µA
-
+
Current
limit
Short during CCM
CS
X(1/8)
Operation
current to the load exceeds the average output inductor
current, the output voltage falls and eventually crosses
the under-voltage protection threshold, inducing IC
shutdown.
The RT6550Aincludes constant on-time synchronou step-
down controller and linear regulator.
Buck Controller
In normal operation, the high-side N-MOSFET is turned
on when the output is lower than VREF, and is turned off
after the internal one-shot timer expires. While the high-
sideN-MOSFET is turned off, the low-sideN-MOSFET is
turned on to conduct the inductor current until next cycle
begins.
Over-Voltage Protection (OVP) and Under-Voltage
Protection (UVP)
The channel output voltage is continuously monitored for
over-voltage and under-voltage conditions. When the
output voltage exceeds over-voltage threshold (113% of
VOUT), UGATE goes low and LGATE is forced high; when
it is less than 52% of reference voltage, under-voltage
protection is triggered and then both UGATE and LGATE
gate drivers are forced low. The controller is latched until
EN is reset or LDO5 is re-supplied.
Soft-Start
For internal soft-start function, an internal current source
charges an internal capacitor to build the soft-start ramp
voltage. The output voltage will track the internal ramp
voltage during soft-start interval.
LDO5
Current Limit
The LDO5 can be power on by EN. The linear regulator
LDO5 provides 5V regulated output.
The current limit circuit employs an unique “valley” current
sensing algorithm. If the magnitude of the current sense
signal at PHASE is above the current limit threshold, the
PWM is not allowed to initiate a new cycle. Thus, the
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
3
RT6550A
Absolute Maximum Ratings (Note 1)
VINtoGND--------------------------------------------------------------------------------------------------------- −0.3V to 30V
BOOT toGND
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to 36V
<100ns -------------------------------------------------------------------------------------------------------------- −5V to 42V
BOOT to PHASE
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns -------------------------------------------------------------------------------------------------------------- −5V to 7.5V
PHASE to GND
DC-------------------------------------------------------------------------------------------------------------------- −5V to 30V
<100ns -------------------------------------------------------------------------------------------------------------- −10V to 42V
UGATE toGND
DC-------------------------------------------------------------------------------------------------------------------- −5V to 36V
<100ns -------------------------------------------------------------------------------------------------------------- −10V to 42V
UGATE to PHASE
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns -------------------------------------------------------------------------------------------------------------- −5V to 7.5V
LGATE toGND
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns -------------------------------------------------------------------------------------------------------------- −5V to 7.5V
Other Pins---------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ---------------------------------------------------------------------------------------------------- 3.27W
Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ---------------------------------------------------------------------------------------------- 30.5°C/W
WDFN-10L 3x3, θJC ---------------------------------------------------------------------------------------------- 7.5°C/W
Junction Temperature -------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------- 260°C
Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model)------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
Supply Voltage, VIN --------------------------------------------------------------------------------------------- 5V to 25V
Junction Temperature Range----------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range----------------------------------------------------------------------------------- −40°C to 85°C
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS6550A-00 September 2016
RT6550A
Electrical Characteristics
(VIN = 12V, VEN = 3.3V, VCS = 2V, No Load, TA = 25°C, unless otherwise specified)
Parameter
Input Supply
Symbol
Test Conditions
Min
Typ
Max
Unit
Rising Threshold
--
4.6
3.7
4.9
--
VIN Power On Reset
VIN_POR
V
Falling Threshold
3.2
VIN Shutdown Supply
Current
IVIN_SBY
IVIN
Buck Controller Off, VEN = GND
--
--
20
35
A
A
UGATE / LGATE Floating,
VIN = 12V, No Switching
VIN Quiescent Current
420
750
Buck Controllers Output and FB Voltage
FB Valley Trip Voltage
VFB
CCM Operation
VVO_DIS = 0.5V
1.98
10
2
2.02
--
V
VO_DIS Discharge
Current
IDCHG
45
mA
PHASE Discharge
Current
IDCHG_LX
VPHASE = 0.5V
5
8
--
mA
Switching Frequency
Switching Frequency
Minimum Off-Time
Soft-Start
fSW
VIN = 12V, VOUT = 5V
VFB = 1.9V
240
--
300
200
360
275
kHz
ns
tOFF(MIN)
Soft-Start Time
tSS
VOUT Ramp-up Time
--
0.9
--
ms
Current Sense
CS Source Current
ICS
VCS = 1V
9
10
11
--
A
CS Current Temperature
Coefficient
TCICS
In Comparison with 25°C
--
4700
ppm/C
Internal Regulator
VIN = 12V, No Load
4.9
4.8
4.8
4.5
100
5
5
5.1
5.1
5.1
5.1
--
VIN > 7V, ILDO5 < 100mA
VIN > 5.5V, ILDO5 < 35mA
VIN > 5V, ILDO5 < 20mA
VLDO5 = 4.5V, VIN = 7.4V
LDO5 Output Voltage
VLDO5
V
mA
V
5
4.75
175
LDO5 Output Current
ILDO5
UVLO
Rising Edge
Falling Edge
--
4.3
3.9
4.6
4.1
LDO5 UVLO Threshold
VUVLO5
3.7
Fault Detection
OVP Trip Threshold
OVP Propagation Delay
UVP Trip Threshold
VOVP
FB with Respect to Internal Reference 109
--
113
1
117
--
%
s
%
VUVP
UVP Detect, FB Falling Edge
47
52
57
UVP Shutdown Blanking
Time
tSHDN_UVP From EN Enable
--
1.3
--
ms
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
5
RT6550A
Parameter
Thermal Shutdown
Thermal Shutdown
Logic Inputs
Symbol
Test Conditions
Min
Typ Max Unit
TSD
--
150
--
°C
V
VEN_H
VEN_L
SMPS On
SMPS Off
1.6
--
--
--
--
EN Threshold Voltage
0.4
Internal Boost Switch
Internal Boost Switch
On-Resistance
RBOOST
LDO5 to BOOT
--
80
--
Power MOSFET Drivers
High State, VBOOT VUGATE = 0.25V,
VBOOT VPHASE = 5V
--
--
--
3
2
3
--
--
--
UGATE On-Resistance
RUGATE
Low State, VUGATE VPAHSE = 0.25V,
VBOOT VPHASE = 5V
High State, VLDO5 VLGATE = 0.25V,
VLDO5 = 5V
LGATE On-Resistance
Dead-Time
RLGATE
Low State, VLGATE GND = 0.25V
LGATE Rising
--
--
--
1
--
--
--
20
30
tD
ns
UGATE Rising
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS6550A-00 September 2016
RT6550A
Typical Application Circuit
V
IN
5.2V to 25V
R1
0
C1
10µF
RT6550A
UGATE
C3
C4
10µF
R3 0
R4 0
Q2
BSC0909
NS
10µF
8
7
6
1
VIN
EN
BOOT
C4
0.1µF
L
3.3µH
R5*
C5*
Enable
On
9
V
5V
OUT
PHASE
LGATE
C6
220µF
Q4
BSC0909
NS
10
Off
5
2
5V
LDO5
C2
1µF
4
3
VO_DIS
R6
15k
C8*
R2
FB
82k
R7
10k
11 (Exposed Pad)
CS
GND
* : Optional
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
7
RT6550A
Typical Operating Characteristics
Efficiency vs. Output current
Switching Frequency vs. Output Current
100
450
400
350
300
250
200
150
100
50
95
IN
V
V
V
V
= 7.4V
IN
V
= 19V
90
85
80
75
70
65
60
IN
IN
IN
= 11.1V
= 14.8V
= 20.5V
IN
V
= 11.1V
IN
V
= 7.4V
VEN = 1/4 VIN
VEN = 1/4 VIN
0
0
1
2
3
4
5
6
7
8
9
0.001
0.01
0.1
1
10
Output current (A)
Output current (A)
Switching Frequency vs. Input Voltage
Output Voltage vs. Output Current
500
400
300
200
100
0
5.02
5.01
5.00
4.99
4.98
4.97
4.96
IN
V
V
V
V
= 20.5V
= 14.8V
= 11.1V
= 7.4V
IN
IN
IN
VEN = 1/4 VIN
IOUT = 6A
VEN = 1/4 VIN
5
9
13
17
21
25
0.001
0.01
0.1
1
10
Input Voltage (V)
Output Current (A)
Quiescent Current vs. Input Voltage
VLDO5 vs. ILDO5
300
290
280
270
260
250
240
230
220
210
200
5.030
5.025
5.020
5.015
5.010
5.005
5.000
VEN = 1/4 VIN,
VFB = 2.2V,
No Switching
VEN = 1/4 VIN,
VIN = 12V
5
9
13
17
21
25
0
20
40
60
80
100
Input Voltage (V)
ILDO5 (mA)
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS6550A-00 September 2016
RT6550A
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(5V/Div)
VOUT
(5V/Div)
VLDO5
(5V/Div)
VLDO5
(5V/Div)
VIN = 12V, VEN = 5V, No Load
VIN = 12V, VEN = 5V, No Load
Time (400μs/Div)
Time (2ms/Div)
Load Transient Response
OVP
EN
IN
IN
V
V
= 1/4 V ,
= 12V,
VOUT
(100mV/Div)
No Load
UGATE
(20V/Div)
VOUT
(2V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
IOUT
(5A/Div)
LGATE
(5V/Div)
VEN = 1/4 VIN, VIN = 12V, IOUT = 0A to 6A
Time (40μs/Div)
Time (40μs/Div)
UVP
EN
IN
IN
V
V
= 1/4 V ,
= 12V,
No Load
IOUT
(5A/Div)
IOUT
VOUT
VOUT
(2V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
Time (400μs/Div)
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
9
RT6550A
Application Information
The RT6550Ais a low quiescent, Mach ResponseTM DRVTM
mode synchronous Buck controller targeted for Ultrabook
system power supply solutions. Richtek's Mach
ResponseTM technology provides fast response to load
steps. The topology solves the poor load transient
response timing problems of fixed frequency current mode
PWMs, and avoids the problems caused by widely varying
switching frequencies in CCR (constant current ripple)
constant on-time PWM schemes. A special adaptive on-
time control trades off the performance and efficiency over
wide input voltage range. The RT6550Aincludes 5V (LDO5)
linear regulators. The LDO5 linear regulator steps down
the battery voltage to supply internal circuitry and gate
drivers. The synchronous switch gate drivers are directly
powered by LDO5.
and predictable output voltage ripple.
The RT6550Aadaptively changes the operation frequency
according to the input voltage. Higher input voltage usually
comes from an external adapter, so the RT6550Aoperates
with higher frequency to have better performance. Lower
input voltage usually comes from a battery, so the
RT6550A operates with lower switching frequency for
lower switching losses. For a specific input voltage range,
the switching cycle period is given by :
For 5V VOUT,
V
IN 2.025
IN 3.79
Period (usec.) =
V
where the VIN is in volt.
The on-time guaranteed in the Electrical Characteristics
table is influenced by switching delays in the external
high-side power MOSFET.
PWM Operation
The Mach ResponseTM DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current sense resistor, so that the output
ripple voltage provides the PWM ramp signal. Referring to
the RT6550A's Function BlockDiagram, the synchronous
high-side MOSFET is turned on at the beginning of each
cycle. After the internal one-shot timer expires, the
MOSFET will be turned off. The pulse width of this one-
shot is determined by the converter's input output voltages
to keep the frequency fairly constant over the entire input
voltage range. Another one-shot sets a minimum off-time
(200ns typ.). The on-time one-shot will be triggered if the
error comparator is high, the low-side switch current is
below the current limit threshold, and the minimum off-
time one-shot has timed out.
Forced-CCM Mode
The low noise, forced-CCM mode disables the zero-
crossing comparator, which controls the low side switch
on-time. This causes the low side gate-drive waveform to
become the complement of the high side gate-drive
waveform. This in turn causes the inductor current to
reverse at ligt loads as the PWM loop to maintain a duty
ratio VOUT/VIN. The benefit of forced-CCM mode is to keep
the switching frequency fairly constant, but it comes at a
cost : The no-load battery current can be up to 10mA,
depending on the external MOSFETs.
Linear Regulators (LDO5)
The RT6550A includes 5V (LDO5) linear regulators. The
regulator can supply up to 100mA for external loads.
Bypass LDO with 1μF (min) to 4.7μF (max), and the
recommended value is 1μF ceramic capacitor.
PWM Frequency and On-time Control
For each specific input voltage range, the Mach
ResponseTM control architecture runs with pseudo constant
frequency by feed forwarding the input and output voltage
into the on-time one-shot timer. The high-side switch
on-time is inversely proportional to the input voltage as
measured by VIN and proportional to the output voltage.
The inductor ripple current operating point remains
relatively constant, resulting in easy design methodology
Current Limit Setting
The RT6550Ahas cycle-by-cycle current limit control and
the OCP function only operation at CCM , it is disabled at
FCCM in order to reduce quiescent current. The current
limit circuit employs an unique “valley” current sensing
algorithm. If the magnitude of the current sense signal at
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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10
DS6550A-00 September 2016
RT6550A
PHASE is above the current limit threshold, the PWM is
not allowed to initiate a new cycle (Figure 2). The actual
peak current is greater than the current limit threshold by
an amount equal to the inductor ripple current. Therefore,
the exact current limit characteristic and maximum load
capability are a function of the sense resistance, inductor
value, battery and output voltage.
MOSFET Gate Driver (UGATE, LGATE)
The high-side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating driver,
5V bias voltage is delivered from the LDO5 supply. The
average drive current is also calculated by the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins.Adead-time to prevent shoot
through is internally generated from high-side MOSFET
off to low-side MOSFET on and low-side MOSFET off to
high-side MOSFET on.
I
L
I
I
PEAK
LOAD
The low-side driver is designed to drive high current low
RDS(ON) N-MOSFET(s). The internal pull down transistor
that drives LGATE low is robust, with a 1Ω typical on-
resistance. A 5V bias voltage is delivered from the LDO5
supply. The instantaneous drive current is supplied by an
input capacitor connected between LDO5 andGND.
I
t
LIMIT
Figure 2. “Valley” Current Limit
The RT6550Auses the on resistance of the synchronous
rectifier as the current sense element and supports
temperature compensated MOSFET RDS(ON) sensing. The
RILIM resistor between the CS pin andGNDsets the current
limit threshold. The resistor RILIM is connected to a current
source from CS which is 10μA (typ.) at room temperature.
The current source has a 4700ppm/°C temperature slope
to compensate the temperature dependency of the
RDS(ON). When the voltage drop across the sense resistor
or low-side MOSFET equals 1/8 the voltage across the
RILIM resistor, positive current limit will be activated. The
high-side MOSFET will not be turned on until the voltage
drop across the MOSFET falls below 1/8 the voltage across
the RILIM resistor.
For high current applications, some combinations of high
and low-side MOSFETs may cause excessive gate drain
coupling, which leads to efficiency killing, EMI producing,
and shoot through currents. This is often remedied by
adding a resistor in series with BOOT, which increases
the turn-on time of the high-side MOSFET without
degrading the turn-off time. See Figure 3.
V
IN
UGATE
BOOT
R
BOOT
PHASE
Figure 3. Increasing the UGATE Rise Time
Soft-Start
Choose a current limit resistor according to the following
equation :
The RT6550A provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled.During soft-
start, it clamps the ramping of internal reference voltage
which is compared with FB signal. The typical soft-start
duration is 0.9ms. An unique PWM duty limit control that
prevents output over-voltage during soft-start period is
designed specifically for FB floating.
VLIMIT = (RLIMIT x 10μA) / 8 = ILIMIT x RDS(ON)
RLIMIT = (ILIMIT x RDS(ON)) x 8 / 10μA
Carefully observe the PC board layout guidelines to ensure
that noise andDC errors do not corrupt the current sense
signal at PHASE and GND. Mount or place the IC close
to the low-side MOSFET.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
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11
RT6550A
UVLO Protection
Thermal Protection
The RT6550Ahas LDO5 under-voltage lock out protection
(UVLO). When the LDO5 voltage is lower than 3.9V (typ.),
both switch power supply is shut off. This is a non-latch
protection.
The RT6550A features thermal shutdown to prevent
damage from excessive heat dissipation. Thermal
shutdown occurs when the die temperature exceeds
150°C.All internal circuitries are turned off during thermal
shutdown. The RT6550A triggers thermal shutdown while
input voltage on VIN and drawing current from LDO5 are
too high.
Output Over-Voltage Protection (OVP)
The output voltage can be continuously monitored for over-
voltage condition. If the output voltage exceeds 13% of
its set voltage threshold, the over-voltage protection is
triggered and the LGATE low-side gate drivers is forced
high. This activates the low-side MOSFET switch, which
rapidly discharges the output capacitor and pulls the output
voltage downward.
Discharge Mode (Soft Discharge)
When EN is low the output under-voltage fault latch is
set, the output discharge mode will be triggered. During
discharge mode, an internal switch creates a path for
discharging the output capacitors' residual charge toGND.
The RT6550A is latched once OVP is triggered and can
only be released by either toggling EN or cycling VIN.
There is a 1μs delay built into the over-voltage protection
circuit to prevent false transition.
Shutdown Mode
When VIN exceeds POR threshold and EN < 0.4V, the
RT6550Aoperate in shutdown mode, and PWM contoller
is OFF state. For the RT6550A, LDO5 is OFF and
approximately consumes 17μA of input current.
Note that latching LGATE high will cause the output voltage
to dip slightly negative due to previously stored energy in
the LC tank circuit. For loads that cannot tolerate a negative
voltage, place a power Schottky diode across the output
to act as a reverse polarity clamp.
Power-Up Sequencing and On/Off Controls (EN)
EN controls the power-up sequencing of the Buck
converter. The 0.4V falling edge threshold on EN can be
used to detect a specific analog voltage level and to
shutdown the device. Once in shutdown, the 1.6V rising
edge threshold activates, providing sufficient hysteresis
for most applications.
If the over-voltage condition is caused by a shorted in
high-side switch, turning the low-side MOSFET on 100%
will create an electrical shorted circuit between the battery
and GND to blow the fuse and disconnecting the battery
from the output.
Output Under-Voltage Protection (UVP)
The output voltage can be continuously monitored for under-
voltage condition. If the output is less than 52% (typ.) of
its set voltage threshold, the under-voltage protection will
be triggered and then both UGATE and LGATE gate drivers
will be forced low. The UVP is ignored for at least 1.3ms
(typ.) after a start-up or a rising edge on EN. Toggle ENor
cycle VIN to reset the UVP fault latch and restart the
controller.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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12
DS6550A-00 September 2016
RT6550A
Table 1. Operation Mode Truth Table
Condition
LDO < UVLO threshold
Mode
Comment
LDO Over
Current Limit
Transitions to discharge mode after VIN POR. LDO5
remains active.
Run
EN = high, VOUT is enabled
Normal Operation.
Over-Voltage
Protection
LGATE is forced high. LDO5 is active. Exit by VIN
POR or by toggling EN.
Either output >113% of the nominal level.
Either output < 52% of the nominal level Both UGATE and LGATE are forced low and enter
after 1.3ms time-out expires and output is discharge mode. LDO5 is active. Exit by VIN POR or
Under-Voltage
Protection
enabled
by toggling EN.
During discharge mode, there is one path to
discharge the output capacitors’ residual charge to
GND via an internal switch.
Either output is still high in shutdown
mode
Discharge
Shutdown
VIN > POR, VEN < 0.4V
TJ > 150°C
LDO5 and VO_DIS discharge
Thermal
Shutdown
All circuitries are off. Exit by VIN POR.
Table 2. Enabling State (RT6550A)
EN
OFF
ON
LDO5
OFF
ON
PWM Controller (5VOUT)
OFF
ON
VIN POR threshold
EN threshold
VIN
EN
LDO5
VREG5 UVLO threshold
Start-Up Time
Soft-Start Time
5V VOUT
Figure 4. Timing
V
Output Voltage Setting (FB)
IN
Connect a resistive voltage divider at the FB pin between
VOUT and GND to adjust the output voltage between 2V
and 5.5V (Figure 5). The recommended R2 is between
10kΩ to 20kΩ, and solve for R1 using the equation below:
UGATE
VOUT
PHASE
LGATE
R1
R2
R1
R2
FB
V
V 1 +
FB
OUT (valley)
GND
where VFB is 2V (typ.).
Figure 5. Setting VOUT with a resistive voltage divider
Copyright 2016 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
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13
RT6550A
Output Inductor Selection
Thermal Considerations
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as shown
below :
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
tON (VIN VOUT
LIRILOAD(MAX)
)
L
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
current, IPEAK
:
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WDFN-10L 3x3 package, the thermal resistance, θJA, is
30.5°C/Won a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
IPEAK = ILOAD(MAX) + [ (LIR / 2) x ILOAD(MAX)
]
The calculation above shall serve as a general reference.
To further improve transient response, the output
inductance can be further reduced. Of course, besides
the inductor, the output capacitor should also be
considered when improving transient response.
Output Capacitor Selection
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for a
The capacitor value and ESR determine the amount of
output voltage ripple and load transient response. Thus,
the capacitor value must be greater than the largest value
calculated from the equations below :
WDFN-10L 3x3 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 6 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
(ILOAD)2 L(tON + tOFF(MIN)
)
VSAG
)
2COUT V tON VOUTx(tON + tOFF(MIN)
IN
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
(ILOAD)2 L
2COUT VOUTx
VSOAR
1
VPP LIRILOAD(MAX) ESR +
8COUT f
where VSAG and VSOAR are the allowable amount of
undershoot and overshoot voltage during load transient,
Vp-p is the output ripple voltage, and tOFF(MIN) is the
minimum off-time.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum PowerDissipation
Copyright 2016 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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14
DS6550A-00 September 2016
RT6550A
Layout Considerations
Layout is very important in high frequency switching converter design. Improper PCB layout can radiate excessive noise
and contribute to the converter’s instability. Certain points must be considered before starting a layout with the RT6550A.
Place the filter capacitor close to the IC, within 12mm (0.5 inch) if possible.
Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high-
voltage switching node.
Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as
possible to reduce stray inductance. Use 0.65mm (25 mils) or wider trace.
All sensitive analog traces and components such as FB, PGOOD, and should be placed away from high voltage
switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground
plane(s) and shield the feedback trace from power traces and components.
Place ground terminal of VINcapacitor(s), VOUT capacitor(s), and Source of low-side MOSFETs as close to each other
as possible. The PCB trace of PHASE node, which connects to Source of high-side MOSFET, Drain of low-side
MOSFET and high voltage side of the inductor, should be as short and wide as possible.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6550A-00 September 2016
www.richtek.com
15
RT6550A
Outline Dimension
D2
D
L
E
E2
SEE DETAIL A
1
e
b
2
1
2
1
A
A3
DETAILA
Pin #1 ID and Tie Bar Mark Options
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
0.800
0.050
0.250
0.300
3.050
2.650
3.050
1.750
Min
Max
0.031
0.002
0.010
0.012
0.120
0.104
0.120
0.069
A
A1
A3
b
0.700
0.000
0.175
0.180
2.950
2.300
2.950
1.500
0.028
0.000
0.007
0.007
0.116
0.091
0.116
0.059
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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16
DS6550A-00 September 2016
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