RT8162A [RICHTEK]
暂无描述;
| 型号： | RT8162A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 |
| 文件： | 总40页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT8162A
Dual Single-Phase PWM Controller for CPU and GPU Core
Power Supply
General Description
The RT8162Ais a dual single-phase PWM controller with
integrated MOSFET drivers, compliant with Intel IMVP7
Pulse Width Modulation Specification to support both
CPU core andGPU core power. This part adoptsG-NAVPTM
(Green-NativeAVP), which is Richtek's proprietary topology
derived from finite DC gain compensator in constant on-
time control mode. The G-NAVPTM makes this part an
easy setting PWM controller to meet all Intel AVP (Active
Voltage Positioning) mobile CPU/GPU requirements. The
RT8162A uses SVID interface to control an 8-bit DAC for
output voltage programming. The built-in high accuracy
DAC converts the received VID code into a voltage value
ranging from 0V to 1.52V with 5mV step voltage. The
system accuracy of the controller can reach 0.8%. The
RT8162A operates in continuous conduction mode or
diode emulation mode, according to the SVIDcommand.
The maximum efficiency can reach up to 90% in different
operating modes according to different load conditions.
The droop function (load line) can be easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance.
The RT8162A is available in the WQFN-40L 5x5 small
footprint package.
Features
Dual Single-Phase PWM Controller for CPU Core
and GPU Core Power
IMVP7 Compatible Power Management States
Serial VID Interface
G-NAVPTM Topology
AVP for CPU VR Only
0.5% DAC Accuracy
0.8% System Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
SETINI/SETINIA for CPU/GPU Core VR Initial
Startup Voltage
TMPMAX to Set Platform Maximum Temperature
ICCMAX/ICCMAXA for CPU/GPU Core VR
Maximum Current
Power Good Indicator : VR_READY/VRA_READY for
CPU/GPU Core Power
Thermal Throttling Indicator : VRHOT
Diode Emulation Mode at Light Load Condition
Fast Line/Load Transient Response
Switching Frequency up to 1MHz per Phase
OVP, UVP, NVP, OTP, UVLO, OCP
RoHS Compliant and Halogen Free
The output voltage transition slew rate is set via the SVID
interface. The RT8162A supports both DCR and sense
resistor current sensing. The RT8162A provides
VR_READY and thermal throttling output signals for
IMVP7 CPU and GPU core. This part also features
complete fault protection functions including over-voltage,
under-voltage, negative-voltage, over-current and thermal
shutdown.
Simplified Application Circuit
RT8162A
VR_READY
VRA_READY
VRHOT
VR_READY
VRA_READY
VRHOT
PHASE
MOSFET
MOSFET
V
V
CORE
GPU
VCLK
VDIO
VCLK
PHASEA
VDIO
ALERT
ALERT
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
www.richtek.com
1
RT8162A
Applications
IMVP7 Intel CPU/GPU Core Power Supply
Pin Configurations
(TOP VIEW)
Laptop Computers
AVP Step-Down Converter
40 39 38 37 36 35 34 33 32 31
30
29
28
27
26
25
1
2
ISENAP
ISENAN
COMPA
FBA
RGNDA
VCLK
VDIO
ALERT
VRA_READY
VR_READY
Ordering Information
RT8162A
BOOT1
TONSET
ISEN1P
ISEN1N
COMP
FB
RGND
GFXPS2
VCC
3
Package Type
QW : WQFN-40L 5x5 (W-Type)
4
5
GND
6
Lead Plating System
G : Green (Halogen Free and Pb Free)
24
23
22
21
7
8
41
9
Note :
10
SETINI
Richtek products are :
11 12 13 14 15 16 17 18 19 20
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
WQFN-40L 5x5
Marking Information
RT8162AGQW : Product Number
RT8162A
GQW
YMDNN : Date Code
YMDNN
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS8162A-00 November 2013
RT8162A
Table 1. IMVP7/VR12 Compliant VID Table
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
H1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
H0
0
VDAC Voltage
0.000
0.250
0.255
0.260
0.265
0.270
0.275
0.280
0.285
0.290
0.295
0.300
0.305
0.310
0.315
0.320
0.325
0.330
0.335
0.340
0.345
0.350
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
0.400
0.405
0.410
0.415
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
www.richtek.com
3
RT8162A
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID3
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H1
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
H0
3
DAC Voltage
0.420
0.425
0.430
0.435
0.440
0.445
0.450
0.455
0.460
0.465
0.470
0.475
0.480
0.485
0.490
0.495
0.500
0.505
0.510
0.515
0.520
0.525
0.530
0.535
0.540
0.545
0.550
0.555
0.560
0.565
0.570
0.575
0.580
0.585
0.590
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8162A-00 November 2013
RT8162A
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
VID3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H1
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
H0
6
DAC Voltage
0.595
0.600
0.605
0.610
0.615
0.620
0.625
0.630
0.635
0.640
0.645
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0.715
0.720
0.725
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
www.richtek.com
5
RT8162A
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H1
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
H0
A
B
C
D
E
F
0
DAC Voltage
0.775
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
0.825
0.830
0.835
0.840
0.845
0.850
0.855
0.860
0.865
0.870
0.875
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.935
0.940
0.945
0.950
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS8162A-00 November 2013
RT8162A
VID7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID3
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H1
8
H0
E
F
0
DAC Voltage
0.955
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
1.025
1.030
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
1.125
1.130
8
9
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
9
A
B
C
D
E
F
0
9
9
9
9
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
www.richtek.com
7
RT8162A
VID7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H1
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
H0
2
DAC Voltage
1.135
1.140
1.145
1.150
1.155
1.160
1.165
1.170
1.175
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
1.280
1.285
1.290
1.295
1.300
1.305
1.310
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS8162A-00 November 2013
RT8162A
VID7
1
VID6
1
VID5
0
VID4
1
VID3
0
VID2
1
VID1
1
VID0
0
H1
D
D
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
H0
6
DAC Voltage
1.315
1.320
1.325
1.330
1.335
1.340
1.345
1.350
1.355
1.360
1.365
1.370
1.375
1.380
1.385
1.390
1.395
1.400
1.405
1.410
1.415
1.420
1.425
1.430
1.435
1
1
0
1
0
1
1
1
7
1
1
0
1
1
0
0
0
8
1
1
0
1
1
0
0
1
9
1
1
0
1
1
0
1
0
A
B
C
D
E
F
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
0
2
1
1
1
0
0
0
1
1
3
1
1
1
0
0
1
0
0
4
1
1
1
0
0
1
0
1
5
1
1
1
0
0
1
1
0
6
1
1
1
0
0
1
1
1
7
1
1
1
0
1
0
0
0
8
1
1
1
0
1
0
0
1
9
1
1
1
0
1
0
1
0
A
B
C
D
E
1
1
1
0
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
E
F
F
F
F
F
F
F
F
F
F
0
1
2
3
4
5
6
7
8
1.440
1.445
1.450
1.455
1.460
1.465
1.470
1.475
1.480
1.485
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
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9
RT8162A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
H1
F
H0
9
DAC Voltage
1.490
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
F
A
1.495
F
B
1.500
F
C
D
E
1.505
F
1.510
F
1.515
F
F
1.520
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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10
DS8162A-00 November 2013
RT8162A
Functional Pin Description
Pin No.
Pin Name
Pin Function
CPU VR Bootstrap Supply for High-Side Gate Driver. This pin powers the
high-side MOSFET drivers. Connect this pin to the PHASE1 pin with a bootstrap
capacitor.
1
BOOT1
Single-Phase CPU VR On-Time Setting Pin. Connect this pin to VIN with a
resistor to set ripple size in PWM mode.
2
TONSET
3
4
5
ISEN1P
ISEN1N
COMP
Positive Current Sense Input of CPU VR.
Negative Current Sense Input of CPU VR.
CPU VR Compensation Node. This pin is the output of the error amplifier.
CPU VR Feedback Voltage Input. This pin is the inverting input node of the error
amplifier.
6
7
8
9
FB
Return Ground for CPU VR. This pin is the inverting input node for differential
remote voltage sensing.
RGND
GFXPS2
VCC
Set Pin for GPU VR Operation Mode. Logic-high on this pin will force the GPU VR
to enter DCM.
Controller Power Supply Input. Connect this pin to GND via a ceramic capacitor
larger than 1F.
10
11
12
13
14
15
SETINI
ADC Input for Single-Phase CPU VR VBOOT Voltage Setting.
ADC Input for Single-Phase GPU VR VBOOT Voltage Setting.
ADC Input for Single-Phase CPU VR Maximum Temperature Setting.
ADC Input for Single-Phase CPU VR Maximum Current Setting.
ADC Input for Single-Phase GPU VR Maximum Current Setting.
Thermal Monitor Sense Input Pin for CPU VR.
SETINIA
TMPMAX
ICCMAX
ICCMAXA
TSEN
Single-Phase CPU VR Over-Current Protection Threshold Setting.
Connect a resistive voltage divider from VCC to ground, and connect the joint of
the voltage divider to the OCSET pin. The voltage, VOCSET, at this pin sets the
over-current threshold, ILIMIT, for CPU VR.
16
17
18
OCSET
TSENA
OCSETA
Thermal Monitor Sense Input for GPU VR.
Single-Phase GPU VR Over-Current Protection Threshold Setting.
Connect a resistive voltage divider from VCC to ground, and connect the joint of
the voltage divider to the OCSETA pin. The voltage, VOCSETA, at this pin sets the
over-current threshold, ILIMIT, for GPU VR.
Internal Bias Current Setting. Connect a 53.6k resistor from this pin to GND to
set the internal bias current.
19
IBIAS
20
21
22
23
24
25
Thermal Monitor Output (Active-Low).
VRHOT
VR_READY
CPU VR Voltage Ready Indicator. This pin has an open-drain output.
VRA_READY GPU VR Voltage Ready Indicator. This pin has an open-drain output.
Alert Line of SVID Interface (active low). This pin has an open-drain output.
Data Transmission Line of SVID Interface.
ALERT
VDIO
VCLK
Clock Signal Line of SVID Interface.
Return Ground for Single-Phase GPU VR.
This pin is the inverting input node for differential remote voltage sensing.
26
RGNDA
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11
RT8162A
Pin No.
Pin Name
Pin Function
GPU VR Feedback Voltage Input. This pin is the inverting input node of the
error amplifier.
27
FBA
Single-Phase GPU VR Compensation Node. This pin is the output of the error
amplifier.
28
COMPA
29
30
ISENAN
ISENAP
Negative Current Sense Input of Single-Phase GPU VR.
Positive Current Sense Input of Single-Phase GPU VR.
Single-Phase GPU VR On-Time Setting. Connect this pin to VIN with a resistor
to set ripple size in PWM mode.
31
32
TONSETA
EN
Voltage Regulator Enable Signal Input Pin.
GPU VR Bootstrap Supply for High-Side Gate Driver. This pin powers the high
side MOSFET drivers. Connect this pin to the PHASEA pin with a bootstrap
capacitor.
33
34
35
BOOTA
High-Side Gate Driver of GPU VR. This pin drives the high-side MOSFET of
GPU VR.
UGATEA
PHASEA
Switch Node of GPU VR. This pin is the return node of the high side MOSFET
driver for GPU VR. Connect this pin to the joint of the source of high-side
MOSFET, Drain of the low-side MOSFET, and the output inductor.
Low-Side Gate Driver of GPU VR. This pin drives the low-side MOSFET of
GPU VR.
36
37
38
LGATEA
PVCC
MOSFET Driver Power Supply Pin. Connect this pin to GND via a ceramic
capacitor larger than 1F.
Low-Side Gate Driver of CPU VR. This pin drives the low-side MOSFET of CPU
VR.
LGATE1
Switch Node of CPU VR. This pin is the return node of the high-side driver for
CPU VR. Connect this pin to the joint of the Source of high-side MOSFET,
Drain of the low side MOSFET, and the output inductor.
39
40
PHASE1
UGATE1
High-Side Gate Driver of CPU VR. This pin drives the high-side MOSFET of
CPU VR.
Ground of Low-Side MOSFET Driver. The exposed pad must be soldered to a
large PCB and connected to GND for maximum power dissipation.
41 (Exposed Pad) GND
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12
DS8162A-00 November 2013
RT8162A
Function Block Diagram
UVLO
Control & Protection Logic
PWM CMP
MUX
ADC
From Control Logic
SVID XCVR
GFXPS2
DAC
RGNDA
TON Time
Generator
TONSETA
ERROR
AMP
Soft-Start & Slew
Rate Control
V
REFA
+
-
Offset
Cancellation
+
-
FBA
BOOTA
COMPA
UGATEA
PHASEA
PVCC
Driver Logic
Control
IBIAS
LGATEA
From Control Logic
DAC
To Protection Logic
ISENAP
ISENAN
+
10
-
RGND
OVP/UVP/NVP
OCP
OCSETA
TONSET
ERROR
AMP
Soft-Start & Slew
Rate Control
V
REF
TON Time
Generator
PWM CMP
+
-
Offset
Cancellation
+
-
FB
COMP
BOOT1
UGATE1
PHASE1
LGATE1
Driver Logic
Control
To Protection Logic
ISEN1P
ISEN1N
+
OCP
OVP/UVP/NVP
10
-
OCSET
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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13
RT8162A
Operation
The RT8162Aadopts theG-NAVPTM (GreenNativeAVP)
which is Richtek's proprietary topology derived from finite
DC gain of EAamplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
Control & Protection Logic
The registers that save the pin setting data from ADC
output
The control logic also generate the digital code of the
VID that relative to VSET.
The RT8162A adopts the G-NAVPTM controller, which is
one type of current mode constant on-time control with
DC offset cancellation. The approach not only can improve
Control the on phase of PWM and the on time interval
of PWM according to PWMCMP output.
Control the power on sequence.
Control the protection behavior.
Control the operational phase number.
DC offset problem for increasing system accuracy but also
can have fast transient response for saving BOM. For the
RT8162A, when current feedback signal reaches comp
signal to generate an on-time width to achieve PWM
modulation.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
TON GEN
Generate the UGATEx pulse according to the phase control
signal from the loop control protection logic.
UVLO
Detect the VCC voltage and issue POR signal as VCC is
high enough.
SVID XCVR Interface
The interface that receive the SVID signal from CPU
and sent the relative signals to Loop Control Protection
logic to execute the action by CPU.
DAC
Generate a analog signal according the digital code
generated by Control Logic.
The SVID logic that control the ADC timing.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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14
DS8162A-00 November 2013
RT8162A
Absolute Maximum Ratings (Note 1)
PVCC, VCC to GND ------------------------------------------------------------------------------------- −0.3V to 6.5V
RGNDx toGND ------------------------------------------------------------------------------------------- −0.3V to 0.3V
TONSETx toGND ---------------------------------------------------------------------------------------- −0.3V to 28V
Other Pins-------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
BOOTx to PHASEx -------------------------------------------------------------------------------------- −0.3V to 6.5V
PHASEx to GND
DC------------------------------------------------------------------------------------------------------------ −3V to 28V
<20ns ------------------------------------------------------------------------------------------------------- −8V to 32V
UGATEx to PHASEx
DC------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx)
<20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V
LGATEx toGND
DC------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC + 0.3V)
<20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
Power Dissipation, PD @ TA = 25°C
WQFN−40L 5x5 ------------------------------------------------------------------------------------------- 3.63W
Package Thermal Resistance (Note 2)
WQFN−40L 5x5, θJA ------------------------------------------------------------------------------------- 27.5°C/W
WQFN−40L 5x5, θJC ------------------------------------------------------------------------------------- 6°C/W
Junction Temperature ------------------------------------------------------------------------------------ 150°C
Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C
Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model)----------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions (Note 4)
Supply Voltage, VCC ------------------------------------------------------------------------------------- 4.5V to 5.5V
Input Voltage, VIN ----------------------------------------------------------------------------------------- 5V to 25V
Junction Temperature Range--------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range--------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Supply Input
Symbol
Test Conditions
Min
Typ Max Unit
VCC/VPVCC
VIN
VCC + IPVCC
VEN = 1.05V, Not Switching
Battery Input Voltage
4.5
5
5
5.5
25
Input Voltage Range
V
--
Supply Current
(VCC + PVCC)
Supply Current
(TONSETx)
I
VEN = 1.05V, Not Switching
--
--
12
20
--
mA
ITONSETx
VFB =1V, VIN = 12V, RTON = 100k
110
A
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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DS8162A-00 November 2013
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15
RT8162A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Shutdown Current
IVCC_SHDN
+ IPVCC_SHDN
VEN = 0V
--
--
5
A
(PVCC + VCC
)
Shutdown Current
(TONSETx)
ITONSETx_SHDN VEN = 0V
--
--
5
A
TON Setting
TONSETx Voltage
On-Time
VTONSETx
tON
IRTON = 80A, VFBx = 1V
IRTON = 80A, VFBx = 1V
0.95
315
1.075
350
1.2
V
385
ns
TONSETx Input
Current Range
IRTON
VFBx = 1.1V
25
--
--
280
--
A
Minimum Off-Time
TOFF_MIN
350
ns
GFX VR Forced DEM
GFXPS2x Enable
Threshold
GFXPS2x Disable
Threshold
VGFXPS
VGFXPS
4.3
--
--
--
--
V
V
0.7
References and System Output Voltage
VIDSVID Setting = 1.000V to 1.520V
OFSSVID Setting = 0V
0.5
5
0
0
0
0
0
0.5
5
%VID
mV
VIDSVID Setting = 0.800V to 1.000V
OFSSVID Setting = 0V
DAC Accuracy
(PS0/PS1)
VIDSVID Setting = 0.500V to 0.800V
OFSSVID Setting = 0V
VFBx
8
8
VIDSVID Setting = 0.250V to 0.500V
OFSSVID Setting = 0V
8
8
VIDSVID Setting = 1.100V
OFSSVID Setting =0.640V to 0.635V
10
10
VINI_CORE = 0V, VINI_GFX = 0V
VINI_CORE = 0.9V, VINI_GFX = 0.9V
VINI_CORE = 1V, VINI_GFX = 1V
0
0.3125 0.5125
0.7375 0.9375 1.1375
1.3625 1.5625 1.7625
SETINIx Voltage
IBIAS Pin Voltage
VSETINIx
V
VINI_CORE = 1.1V, VINI_GFX = 1.1V
2.6125
2.09
2.5
--
5
VIBIAS
RIBIAS = 53.6k
SetVID Slow
SetVID Fast
2.14
3.125
12.5
2.19
3.75
15
V
Dynamic VID Slew
Rate
SRDVID
mV/s
10
Error Amplifier
DC Gain
ADC
RL = 47k (Note5)
70
--
80
10
--
--
dB
Gain-Bandwidth
Product
GBW
CLOAD = 5pF (Note5)
MHz
C
LOAD = 10pF
Slew Rate
SRCOMP
(Gain = 4, RLOAD_COMP = 47k,
--
5
--
V/s
VCOMPx = 0.5V to 3V)
Output Voltage
Range
VCOMP
ICOMP
RL = 47k
0.5
--
--
3.6
--
V
MAX Source/Sink
Current
VCOMP = 2V
250
A
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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16
DS8162A-00 November 2013
RT8162A
Parameter
Symbol
Test Conditions
Min
Typ
Max Unit
Impedance of FBx
R
V
1
--
--
M
FBx
Current Sense Amplifier
Input Offset Voltage
1
1
--
--
--
1
mV
M
M
OFS_CSA
Impedance of Neg. Input
Impedance of Pos. Input
R
--
--
ISENxN
ISENxP
R
1
Current Sense
Differential Input Range
V
V
= 1.1V,
= V
FBx
V
50
--
100
mV
CSDIx
V
ISENxN
CSDIx
ISENxP
Current Sense DC Gain
(Loop)
A
V
V
V
= 1.1V, 30mV < V
= 1.1V 30mV < V
< 50mV
< 50mV
ISEN_IN
--
10
--
--
1
V/V
%
I
FBx
CSDIx
V
Linearity
1
ISEN
ISEN_ACC
DAC
Gate Driver
V
V
BOOTx V
BOOTx V
= 5V
= 0.1V
PHASEx
UGATEx
High-Side Driver Source
R
--
1
--
UGATEx_sr
High-Side Driver Sink
Low-Side Driver Source
Low-Side Driver Sink
R
R
R
V
= 0.1V
UGATEx
--
--
--
1
1
--
--
--
UGATEx_sk
LGATEx_sr
PVCC = 5V, PVCC V
= 0.1V
LGATEx
V
= 0.1V
LGATEx
0.5
LGATEx_sk
BOOTx
Internal Boot Charging
Switch On-Resistance
R
V
PVCC to BOOTx
= GND V
--
--
30
10
--
--
Zero Current Detection
Threshold
V
mV
ZCD_TH
ZCD_TH
PHASEx
Protection
Under-Voltage Lockout
Threshold
V
VCC Falling edge
4.04 4.24
--
--
V
UVLO
Under-Voltage Lockout
Hysteresis
V
--
100
150
mV
mV
mV
mV
V/V
UVLO
Over-Voltage Protection
Threshold
Respect to VOUT_MAX
filter time
, with 1s
SVID
V
V
V
A
100
200
OVP
Under-Voltage Protection
Threshold
V
= V
V
, 0.8V < V
REFx REFx
UVP
ISENxN
350 300 250
UVP
NVP
OC
<1.52V, with 3s filter time
Negative-Voltage
Protection Threshold
V
= VISENxN GND
100 50
--
--
NVP
Current Sense Gain for
Over-Current Protection
V
V
= 2.4V
OCSET
ISENxP
--
48
V
= 50mV
ISENxN
Logic Inputs
Logic-High
EN Input
V
V
With respect to 1V, 70%
With respect to 1V, 30%
0.7
--
--
--
--
--
0.3
1
IH
V
Voltage
Logic-Low
IL
Leakage Current of EN
1
A
V
V
With respect to Intel Spec.
With respect to Intel Spec.
0.65
--
--
--
--
IH
IL
VCLK, VDIO Input
Threshold Voltage
V
0.45
Leakage Current of
VCLK, VDIO
I
1
--
1
A
LEAK_IN
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17
RT8162A
Parameter
ALERT
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.4
V
ALERT Low Voltage
VR Ready
VALERT
IALERT_ SINK = 4mA
VRx_READY Low Voltage VVRx_READY IVRx_READY_ SINK = 4mA
--
--
0.4
V
VRx_READY Delay
tVRx_READY VISENxN = VBOOT to VVRx_READY high
70
100
160
s
Thermal Throttling
VVRHOT
IVRHOT_SINK = 40mA
--
0.4
--
--
1
V
VRHOT Output Voltage
High Impedance Output
ALERT, VRx_READY,
VRHOT
ILEAK_OUT
1
A
Temperature Zone
TSEN Threshold for
Tmp_Zone [7] transition
100°C
97°C
94°C
91°C
88°C
85°C
82°C
75°C
--
--
--
--
--
--
--
1.8725
1.8175
1.7625
1.7075
1.6525
1.5975
1.5425
--
--
--
--
--
--
--
V
V
V
V
V
V
V
TSEN Threshold for
Tmp_Zone [6] transition
TSEN Threshold for
Tmp_Zone [5] transition
VTSENx
TSEN Threshold for
Tmp_Zone [4] transition
TSEN Threshold for
Tmp_Zone [3] transition
TSEN Threshold for
Tmp_Zone [2] transition
TSEN Threshold for
Tmp_Zone [1] transition
VTSENx
TSEN Threshold for
Tmp_Zone [0] transition
--
--
1.4875
1600
--
--
V
Update Period
ADC
tTSEN
s
Latency
tLAT
--
29
61
125
5
--
32
400
s
CICCMAX1
CICCMAX2
CICCMAX3
VICCMAX = 0.637V
VICCMAX = 1.2642V
VICCMAX = 2.5186V
35 decimal
67 decimal
131 decimal
11 decimal
19 decimal
35 decimal
88 decimal
103 decimal
128 decimal
Digital Code of ICCMAX
Digital Code of ICCMAXA
Digital Code of TMPMAX
64
128
8
CICCMAXA1 VICCMAXA = 0.1666V
CICCMAXA2 VICCMAXA = 0.3234V
CICCMAXA3 VICCMAXA = 0.637V
13
29
82
97
122
16
32
CTMPMAX1
CTMPMAX2
CTMPMAX3
VTMPMAX = 1.6758V
VTMPMAX = 1.9698V
VTMPMAX = 2.4598V
85
100
125
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18
DS8162A-00 November 2013
RT8162A
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
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19
RT8162A
Typical Application Circuit
RT8162A
TONSET
R3
5.1
R2
R1
2.2
V
CC
130k
V
2
IN
9
5V to 25V
VCC
5V
C2
0.1µF
C1
1µF
C3
10µF
R4
0
Q1
40
UGATE1
V
CCP
DCR = 7.6m
V
CORE
C4
0.1µF
0
R5
1
L1
R6 R7 R8 R9 R10 R11
130 130 150 10k 10k 75
BOOT1
Optional
1µH
39
PHASE1
C26
330µF
/9m
C5
R12
25
24
23
22
21
20
0
Q2
38
37
R13
C7
VCLK
VDIO
ALERT
VRA_READY
VR_READY
VRHOT
VCLK
VDIO
ALERT
330µF
/9m
C6
68µF
LGATE1
PVCC
R14
3.9k
0.0
5V
VRA_READ
VR_READY
VRHOT
Y
NTC
C8
1µF
1
R15
4.7k
4.7k
R16
2.4k
ß = 3500
3
4
ISEN1P
ISEN1N
Optional
C10
C9
Optional
V
CC
O
ption
al
6
FB
C11
R17
27k
R18
R19 R20
NSE
CORE V SE
8.7k 10k 10k
CC
18
R23
100
R22
10k
R55
R21
71k
5
OCSETA
OCSETA
OCSET
SETINI
COMP
V
CORE
16
10
11
OCSET
SETINI
SETINIA
C21
SETINIA
Optional
R24
10k
R25
10k
R26
NC
R27
NC
7
RGND
CORE V SENSE
SS
R28
100
R34
5.1
R33
130k
V
31
IN
TONSETA
V
CC
5V to 25V
C12
0.1µF
Q3
R29
51k
R30
R31
R32
NC
150k 100k
0
0
R35
R36
C14
34
33
UGATEA
BOOTA
10µF
12
13
14
TMPMAX
ICCMAX
ICCMAXA
GFXPS2
TMPMAX
ICCMAX
ICCMAXA
GFXPS2
C13
0.1µF
DCR = 14.6m
V
GFX
L2
2µH
Optional
8
35
36
PHASEA
C27
330µF
/15m
C17
C16
R43
11k
330µF
/15m
R42
C15
R37 R38
33k
R39 R40
1.6k 10k
0.1µF
R41
0
Q4
5.1k
LGATEA
NTC
A
R44
1k
R45
1.2k
1k
ß = 3650
30
29
ISENAP
ISENAN
V
CC
NTC
TA
R46
12k
NTC
R47
12k
C18
T1
10k
Optional
Optional
C19
Optional
C20
10k
ß = 3380
27
28
26
FBA
ß = 3380
SE
GFX V SEN
CC
R71
750
R72
750
17
15
19
TSENA
TSEN
IBIAS
R48
42k
R49
10k
R50
100
COMPA
V
GFX
R52
1k
C22
R53
1k
R56
R54
53.6k
Optional
RGNDA
GND
NSE
GFX V SE
SS
32
Enable
EN
R51
100
41 (Exposed
Pad)
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DS8162A-00 November 2013
RT8162A
Typical Operating Characteristics
CORE VR Power Off from EN
CORE VR Power On from EN
VCORE
(500mV/Div)
VCORE
(500mV/Div)
EN
(2V/Div)
EN
(2V/Div)
VR_READY
(2V/Div)
VR_READY
(2V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Boot VID = 1V
Boot VID = 1V
Time (100μs/Div)
Time (100μs/Div)
CORE VR OCP
CORE VR OVP and NVP
VCORE
VCORE
(1V/Div)
(1V/Div)
ILOAD
LGATE
(10A/Div)
(10V/Div)
VR_READY
(1V/Div)
VR_READY
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
VID = 1.1V
VID = 1.1V
Time (100μs/Div)
Time (40μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Down
VCORE
VCORE
(500mV/Div)
(500mV/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VDIO
(2V/Div)
ALERT
ALERT
(2V/Div)
(2V/Div)
0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A
1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A
Time (40μs/Div)
Time (40μs/Div)
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21
RT8162A
CORE VR Dynamic VID Down
CORE VR Dynamic VID Up
VCORE
VCORE
(500mV/Div)
(500mV/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VDIO
(2V/Div)
ALERT
ALERT
(2V/Div)
(2V/Div)
0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A
1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A
Time (10μs/Div)
Time (10μs/Div)
CORE VR Load Transient
CORE VR Load Transient
VCORE
VCORE
(20mV/Div)
(20mV/Div)
8
8
ILOAD
ILOAD
(A/Div)
(A/Div)
1
1
VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns
VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns
Time (100μs/Div)
Time (100μs/Div)
CORE VR Mode Transition
CORE VR Mode Transition
VCORE
VCORE
(20mV/Div)
(20mV/Div)
VCLK
(1V/Div)
VCLK
(1V/Div)
LGATE
LGATE
(10V/Div)
(10V/Div)
UGATE
UGATE
(20V/Div)
(20V/Div)
VID = 1.1V, PS0 to PS2, ILOAD = 0.2A
VID = 1.1V, PS2 to PS0, ILOAD = 0.2A
Time (100μs/Div)
Time (100μs/Div)
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DS8162A-00 November 2013
RT8162A
CORE VR Thermal Monitoring
CORE VR VREF vs. Temperature
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.9
1.7
TSEN
(V/Div)
VRHOT
(500mV/Div)
TSEN Sweep from 1.7V to 1.9V
Time (10ms/Div)
-50
-25
0
25
50
75
100
125
Temperature (°C)
GFX VR Power On from EN
GFX VR Power Off from EN
VGFX
(500mV/Div)
VGFX
(500mV/Div)
EN
(2V/Div)
EN
(2V/Div)
VRA_READY
(2V/Div)
VRA_READY
(2V/Div)
UGATEA
(20V/Div)
UGATEA
(20V/Div)
Boot VID = 1V
Boot VID = 1V
Time (100μs/Div)
Time (100μs/Div)
GFX VR OCP
GFX VR OVP and NVP
VGFX
VGFX
(1V/Div)
(1V/Div)
VRA_READY
(1V/Div)
ILOAD
(5A/Div)
LGATEA
(10V/Div)
VRA_READY
(1V/Div)
UGATEA
(20V/Div)
UGATEA
(20V/Div)
VID = 1.1V
Time (100μs/Div)
Time (40μs/Div)
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RT8162A
GFX VR Dynamic VID
GFX VR Dynamic VID
VGFX
VGFX
(500mV/Div)
(500mV/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VDIO
(2V/Div)
ALERT
ALERT
(2V/Div)
(2V/Div)
0.7V to 1.2V, Slew Rate = Slow, ILOAD = 1.25A
1.2V to 0.7V, Slew Rate = Slow, ILOAD = 1.25A
Time (40μs/Div)
Time (40μs/Div)
GFX VR Dynamic VID
GFX VR Dynamic VID
VGFX
VGFX
(500mV/Div)
(500mV/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VDIO
(2V/Div)
ALERT
ALERT
(2V/Div)
(2V/Div)
0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A
1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A
Time (10μs/Div)
Time (10μs/Div)
GFX VR Load Transient
GFX VR Load Transient
VGFX
VGFX
(20mV/Div)
(20mV/Div)
4
4
ILOAD
ILOAD
(A/Div)
(A/Div)
1
1
VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns
VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns
Time (100μs/Div)
Time (100μs/Div)
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DS8162A-00 November 2013
RT8162A
GFX VR Mode Transition
GFX VR Mode Transition
VGFX
VGFX
(20mV/Div)
(20mV/Div)
VCLK
(1V/Div)
VCLK
(1V/Div)
LGATEA
(10V/Div)
LGATEA
(10V/Div)
UGATEA
(20V/Div)
UGATEA
(20V/Div)
VID = 1.1V, PS0 to PS2, ILOAD = 0.1A
VID = 1.1V, PS2 to PS0, ILOAD = 0.1A
Time (100μs/Div)
Time (100μs/Div)
GFX VR VREF vs. Temperature
GFX VR Thermal Monitoring
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
0.988
1.9
TSENA
(V/Div)
1.7
VRHOT
(500mV/Div)
TSENA Sweep from 1.7V to 1.9V
Time (10ms/Div)
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT8162A
Application Information
The RT8162A is a VR12/IMVP7 compliant, dual single-
phase synchronous Buck PWM controller for the CPU
CORE VR and GFX VR. The gate drivers are embedded
to facilitate PCB design and reduce the total BOM cost. A
serial VID (SVID) interface is built-in in the RT8162A to
communicate with Intel VR12/IMVP7 compliant CPU.
Design Tool
To help users reduce efforts and errors caused by manual
calculations, a user-friendly design tool is now available
on request. This design tool calculates all necessary
design parameters by entering user's requirements.
Please contact Richtek's representatives for details.
The RT8162AadoptsG-NAVPTM (GreenNativeAVP), which
is Richtek's proprietary topology derived from finite DC
gain compensator, making it an easy setting PWM
controller to meet AVP requirements. The load-line can
be easily programmed by setting the DC gain of the error
amplifier. The RT8162Ahas fast transient response due to
theG-NAVPTM commanding variable switching frequency.
Serial VID (SVID) Interface
SVIDis a three-wire serial synchronous interface defined
by Intel. The three wire bus includes VDIO, VCLK and
ALERT signals. The master (Intel's VR12/IMVP7 CPU)
initiates and terminates SVIDtransactions and drives the
VDIO, VCLK, andALERT during a transaction. The slave
(RT8162A) receives the SVID transactions and acts
accordingly.
TheG-NAVPTM topology also represents a high efficiency
system with green power concept. With the G-NAVPTM
topology, the RT8162Abecomes a green power controller
with high efficiency under heavy load, light load, and very
light load conditions. The RT8162A supports mode
transition function between CCM andDEM. These different
operating states allow the overall power system to have
low power loss. By utilizing the G-NAVPTM topology, the
operating frequency of RT8162A varies with output voltage,
load and VINto further enhance the efficiency even in CCM.
The built-in high accuracy DAC converts the SVID code
ranging from 0.25V to 1.52V with 5mV per step. The
differential remote output voltage sense and high accuracy
DAC allow the system to have high output voltage accuracy.
The RT8162A supports VR12/IMVP7 compatible power
management states and VIDon-the-fly function. The power
management states includeDEM in PS2/PS3 and Forced-
CCM in PS1/PS0. The VID on-the-fly function has three
different slew rates : Fast, Slow andDecay. The RT8162A
integrates a high accuracy ADC for platform setting
functions, such as no-load offset and over current level.
The controller supports both DCR and sense-resistor
current sensing. The RT8162A provides VR ready output
signals of both CORE VR and GFX VR. It also features
complete fault protection functions including over-voltage,
under-voltage, negative-voltage, over-current and under-
voltage lockout. The RT8162A is available in the WQFN-
40L 5x5 small foot print package.
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26
DS8162A-00 November 2013
RT8162A
Standard Serial VID Command
Master Payload
Slave Payload
Contents
Code
00h
Commands
Description
Contents
not supported
N/A
N/A
N/A
Set new target VID code, VR jumps to new VID
target with controlled default “fast” slew rate
12.5mV/s.
Set new target VID code, VR jumps to new VID
target with controlled default “slow” slew rate
3.125mV/s.
Set new target VID code, VR jumps to new VID
target, but does not control the slew rate. The
output voltage decays at a rate proportional to
the load current
01h
02h
SetVID_Fast
SetVID_Slow
VID code
VID code
N/A
N/A
N/A
03h
SetVID_Decay
VID code
Byte indicating
power states
04h
05h
06h
SetPS
N/A
N/A
N/A
Set power state
Pointer of registers
in data table
SetRegADR
SetReg DAT
Set the pointer of the data register
Write the contents to the data register
New data register
content
Specified
Register
Contents
Pointer of registers
in data table
Slave returns the contents of the specified
register as the payload
07h
GetReg
08h
-
not supported
N/A
N/A
N/A
1Fh
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27
RT8162A
Data and Configuration Register
Description
Index Register Name
Access
Default
1Eh
00h
01h
02h
05h
Vendor ID
Vendor ID, default 1Eh.
RO, Vendor
RO, Vendor
RO, Vendor
RO, Vendor
Product ID
Product ID.
65h
Product Revision
Protocol ID
Product Revision.
SVID Protocol ID.
01h
01h
Bit mapped register, identifies the SVID VR capabilities
and which of the optional telemetry register are
supported.
06h
VR_Capability
RO, Vendor
81h
10h
11h
Status_1
Status-2
Data register containing the status of VR.
R-M, W-PWM
R-M, W-PWM
00h
00h
Data register containing the status of transmission.
Temperature
Zone
Data register showing temperature zone that have been
entered.
12h
R-M, W-PWM
00h
Data register showing direct ADC conversion of averaged
output current.
15h
1Ch
Output_Current
R-M, W-PWM
R-M, W-PWM
00h
00h
Status_2_lastread The register contains a copy of the status_2.
Data register containing the maximum ICC of platform
21h
22h
24h
ICC_Max
Temp_Max
SR-Fast
supports.
RO, Platform
RO, Platform
RO
--
--
Binary format in Amp, IE 64h = 100A.
Data register containing the temperature max the platform
supports.
Binary format in °C, IE 64h = 100°C
Only for CORE VR
Data register containing the capability of fast slew rate the
platform can sustains. Binary format in mV/s, IE 0Ah =
10mV/s.
0Ah
Data register containing the capability of slow slew rate.
Binary format in mV/s IE 02h = 2.5mV/s.
25h
30h
SR-Slow
RO
02h
The register is programmed by the master and sets the
maximum VID.
VOUT_Max
RW, Master
FBh
31h
32h
33h
VID Setting
Power State
Offset
Data register containing currently programmed VID.
Register containing the current programmed power state.
Set offset in VID steps.
RW, Master
RW, Master
RW, Master
00h
00h
00h
Bit mapped data register which configures multiple VRs
behavior on the same bus.
34h
Multi VR Config
Pointer
RW, Master
RW, Master
00h
30h
Scratch pad register for temporary storage of the
SetRegADR pointer register.
35h
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM only
Vendor = hard coded by VR vendor
Platform = programmed by platform
Master = programmed by the master
PWM = programmed by the VR control IC
Copyright 2013 Richtek Technology Corporation. All rights reserved.
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28
DS8162A-00 November 2013
RT8162A
Power Ready Detection and Power On Reset (POR)
ICCMAX, ICCMAXA and TMPMAX
During start-up, the RT8162A detects the voltage on the
The RT8162Aprovides ICCMAX, ICCMAXAand TMPMAX
pins for platform users to set the maximum level of output
current or VR temperature: ICCMAX for CORE VR
maximum current, ICCMAXA for GFX VR maximum
current, and TMPMAX for CORE VR maximum
temperature.
voltage input pins : VCC and EN. When VCC > VUVLO
,
the RT8162A will recognize the power state of system to
be ready (POR = high) and wait for enable command at
EN pin. After POR = high and EN > VENTH, the RT8162A
will enter start-up sequence for both CORE VR and GFX
VR. If the voltage on any voltage pin drops below POR
threshold (POR = low), the RT8162A will enter power down
sequence and all the functions will be disabled. SVIDwill
be invalid within 300μs after chip becomes enabled. All
the protection latches (OVP, OCP, UVP, OTP) will be
cleared only after POR = low. EN = low will not clear
these latches.
To set ICCMAX, ICCMAXA and TMPMAX, platform
designers should use resistive voltage dividers on these
three pins. The current of the divider should be several
milli-Amps to avoid noise effect. The three items share
the same algorithms : theADC divides 5V into 255 levels.
Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV
applied to ICCMAX pin equals to 1Asetting. For example,
if a platform designer wants to set TMPMAX to 120°C, the
voltage applied to TMPMAX should be 120 x 19.6mV =
2.352V. The ADC circuit inside these three pins will
decode the voltage applied and store the maximum current/
temperature setting into ICC_MAX and Temp_Max
registers. The ADC monitors and decodes the voltage at
these three pins only after EN = high. If EN = low, the
RT8162Awill not take any action even when the VR output
current or temperature exceeds its maximum setting at
these ADC pins. The maximum level settings at these
ADC pins are different from over-current protection or over-
temperature protection. That means, these maximum level
setting pins are only for platform users to define their
system operating conditions and these messages will only
be utilized by the CPU.
VCC
+
-
POR
V
UVLO
ENTH
EN
+
-
Chip EN
V
Figure 3. Power Ready Detection and Power On Reset
(POR)
Precise Reference Current Generation
The RT8162A includes extensive analog circuits inside
the controller. These analog circuits need very precise
reference voltage/current to drive these analog devices.
The RT8162A will auto-generate a 2.14V voltage source
at IBIAS pin, and a 53.6kΩ resistor is required to be
connected between IBIAS and analog ground. Through
this connection, the RT8162A generates a 40μA current
from IBIAS pin to analog ground and this 40μAcurrent will
be mirrored inside the RT8162A for internal use. Other
types of connection or other values of resistance applied
at the IBIAS pin may cause failure of the RT8162A's analog
circuits. Thus a 53.6kΩ resistor is the only recommended
component to be connected to the IBIAS pin. The
resistance accuracy of this resistor is recommended to
be at least 1%.
V
CC
ICCMAX
A/D
Converter
ICCMAXA
TMPMAX
Current
Mirror
2.14V
Figure 5. ADC Pins Setting
+
-
53.6k
IBIAS
Figure 4. IBIAS Setting
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29
RT8162A
VCC (5V)
VINI_CORE
Recommended
V
=
=
1.1V
1.1V
INI_CORE
VINI_GFX SETINI/SETINIA Pin Voltage
V
INI_GFX
5
8
1.1V
1V
x VCC≒3.125V or VCC
3
8
1/2 VCC
x VCC≒1.875V
V
= 1V
= 1V
INI_CORE
INI_GFX
3
V
0.9V
0V
x VCC≒0.9375V
16
1/4 VCC
1/8 VCC
GND
V
= 0.9V
= 0.9
V
INI_CORE
1
16
x VCC≒0.3125V or GND
V
INI_GFX
V
= 0V
= 0V
INI_CORE
INI_GFX
V
Figure 6. SETINI and SETINIA Pin Voltage Setting
After the output voltage reaches the target voltage, the
VINI_CORE and VINI_GFX Setting
RT8162A will send out VR_READY signal to indicate the
power state of the RT8162A is ready. The VR_READY
circuit is an open-drain structure so a pull-up resistor is
recommended for connecting to a voltage source.
The initial start-up voltage (VINI_CORE, VINI_GFX) of the
RT8162A can be set by platform users through SETINI
and SETINIApins. Voltage divider circuit is recommended
to be applied to the SETINI and SETINIA pins. The
VINI_CORE/VINI_GFX relate to SETINI/SETINIA pin voltage
setting as shown in Figure 6. Recommended voltage
setting at the SETINI and SETINIApins are also shown in
Figure 6.
Power Down Sequence
Similar to the start up sequence, the RT8162A also utilizes
a soft shutdown mechanism during turn-off. After POR =
low, the internal reference voltage (positive terminal of
compensation EA) starts ramping down with 3.125mV/μs
slew rate, and output voltage will follow the reference
voltage to 0V. After output voltage drops below 0.2V, the
RT8162Ashuts down and all functions are disabled. The
VR_READY will be pulled down immediately after POR =
low.
Start Up Sequence
The RT8162A utilizes internal soft-start sequence which
strictly follows Intel VR12/IMVP7 start-up sequence
specifications. After POR = high and EN = high, a 300μs
delay is needed for the controller to determine whether all
the power inputs are ready for entering start-up sequence.
If pin voltage of SETINI/SETINIA is zero, the output voltage
of CORE/GFX VR is programmed to stay at 0V. If pin
voltage of SETINI/SETINIA is not zero, VR output voltage
will ramp up to initial boot voltage (VINI_CORE,VINI_GFX) after
both POR = high and EN = high. After the output voltage
of CORE/GFX VR reaches target initial boot voltage, the
controller will keep the output voltage at the initial boot
voltage and wait for the next SVID commands. After the
RT8162A receives valid VID code (typically SetVID_Slow
command), the output voltage will ramp up/down to the
target voltage with specified slew rate.
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30
DS8162A-00 November 2013
RT8162A
VCC
POR
EN
EN Chip
(Internal Signal)
SVID
Valid
xx
XX
300µs
0.2V
Off
V
GFX
GFX VR
Operation Mode
Off
Off
CCM
CCM
CCM
SVID defined
V
CORE
0.2V
Off
CORE VR
Operation Mode
CCM
SVID defined
100µs
VRA_READY
VR_READY
100µs
Figure 7 (a). Power Sequence for RT8162A (VINI_CORE = VINI_GFX = 0V)
VCC
POR
EN
EN Chip
(Internal Signal)
300µs
SVID
xx
Valid
XX
250µs
V
INI_CORE
0.2V
Off
V
GFX
GFX VR
Operation Mode
Off
CCM
CCM
SVID defined
100µs
V
VRA_READY
70µs
INI_GFX
V
CORE
0.2V
Off
CORE VR
Operation Mode
Off
CCM
SVID defined
CCM
100µs
VR_READY
Figure 7 (b). Power Sequence for RT8162A (VINI_CORE 0, V
0V)
INI_GFX
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RT8162A
Disable GFX VR : Before EN = High
Similar to the valley current mode control with finite
compensator gain, the high side MOSFET on-time is
determined by the CCRCOT PWM generator. When load
current increases, VCS increases, the steady state COMP
voltage also increases which makes the output voltage
decrease, thus achieving AVP.
GFX VR enable or disable is determined by the internal
circuitry that monitors the ISENAN voltage during start
up. Before EN= high,GFX VR detects whether the voltage
of ISENAN is higher than “VCC − 1V” to disable GFX
VR. The unused driver pins can be connected to GND or
left floating.
Droop Setting (with Temperature Compensation)
GFX VR Forced-DEM Function Enable : After
VRA_Ready = High
It's very easy to achieve the Active Voltage Positioning
(AVP) by properly setting the error amplifier gain due to
the native droop characteristics. The target is to have
The GFX VR's forced-DEM function can be enabled or
disabled with GFXPS2 pin. The RT8162A detects the
voltage ofGFXPS2 for forced-DEM function. If the voltage
atGFXPS2 pin is higher than 4.3V, theGFX VR operates
in forced-DEM. If this voltage is lower than 0.7V, theGFX
VR follows SVID power state command.
VOUT = VREFx − ILOAD x RDROOP
(1)
Then solving the switching condition VCOMPx = VCSx in
Figure 8 yields the desired error amplifier gain as
A R
R
R2
R1
I
SENSE
DROOP
(2)
A
V
where AI is the internal current sense amplifier gain and
RSENSE is the current sense resistance. If no external sense
resistor is present, the DCR of the inductor will act as
RSENSE. RDROOP is the resistive slope value of the converter
output and is the desired static output impedance.
Loop Control
Both CORE and GFX VR adopt Richtek's proprietary G-
NAVPTM topology. G-NAVPTM is based on the finite-gain
valley current mode with CCRCOT (Constant Current
Ripple Constant On Time) topology. The output voltage,
VCORE or VGFX, will decrease with increasing output load
current. The control loop consists of PWM modulator with
power stage, current sense amplifier and error amplifier
as shown in Figure 8.
V
OUT
A
> A
V1
V2
A
A
V2
V1
V
IN
V
OUT
/V
High Side
MOSFET
UGATEx
PHASEx
(V
)
CORE GFX
GFX/CORE VR
CCRCOT
Driver
Logic
L
0
Load Current
PWM Generator
Control
Figure 9. ErrorAmplifierGain (AV) Influence on VOUT
Accuracy
R
C
LGATEx
Low Side
MOSFET
R
X
C
X
C
CMP
Since the DCR of inductor is temperature dependent, it
affects the output accuracy in high temperature conditions.
Temperature compensation is recommended for the
lossless inductor DCR current sense method. Figure 10
shows a simple but effective way of compensating the
temperature variations of the sense resistor using anNTC
thermistor placed in the feedback path.
ISENxP
ISENxN
V
CSx
+
Ai
-
C
Byp
C2
R2
C1
R1
CORE/GFX VR
COMPx
FBx
V
CC_SENSE
-
C2
C1
EA
CORE/GFX VR
RGNDx
+
V
SS_SENSE
VREFx
R2
R1a
NTC
R1b
COMPx
V
CC_SENSE
FBx
-
EA
RGNDx
V
Figure 8. Simplified Schematic for Droop and Remote
Sense in CCM
+
SS_SENSE
VREFx
Figure 10. Loop Setting with Temperature Compensation
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RT8162A
Usually, R1a is set to equal RNTC (25°C), while R1b is
selected to linearize theNTC's temperature characteristic.
For a given NTC, the design would be to obtain R1b and
R2 and then C1 and C2. According to (2), to compensate
the temperature variations of the sense resistor, the error
amplifier gain (AV) should have the same temperature
coefficient with RSENSE. Hence
Loop Compensation
Optimized compensation of the CORE VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for a proper compensation. Figure 10 shows the
compensation circuit. It was previously mentioned that to
determine the resistive feedback components of error
amplifier gain, C1 and C2 must be calculated for the
compensation. The target is to achieve constant resistive
output impedance over the widest possible frequency
range.
A
R
SENSE, HOT
V, HOT
(3)
A
R
SENSE, COLD
V, COLD
From (2), we can haveAv at any temperature (T) as
R2
A
(4)
V, T
The pole frequency of the compensator must be set to
R1a / /R
R1b
NTC, T
compensate the output capacitor ESR zero :
1
The standard formula for the resistance ofNTC thermistor
as a function of temperature is given by :
(9)
fP
2 CRC
where C is the capacitance of the output capacitor and RC
is the ESR of the output capacitor. C2 can be calculated
as follows :
1
1
298
T+273
(5)
RNTC, T RNTC, 25
e
where RNTC, 25 is the thermistor's nominal resistance at
room temperature, β (beta) is the thermistor's material
constant in Kelvins, and T is the thermistor's actual
temperature in Celsius.
CR
R2
C
(10)
C2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching-related noise.
Such that,
TheDCR value at different temperatures can be calculated
using the equation below :
1
C1
(11)
R1b R1a // R
f
SW
NTC, 25C
DCRT = DCR25 x [1+0.00393 x (T-25)]
(6)
TON Setting
where 0.00393 is the temperature coefficient of copper.
For a givenNTC thermistor, solving (4) at room temperature
(25°C) yields
High frequency operation optimizes the application by
trading off efficiency due to higher switching losses with
smaller component size. This may be acceptable in ultra-
portable devices where the load currents are lower and
the controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
11 shows the on-time setting circuit. Connect a resistor
(RTONSETx) between VIN and TONSETx to set the on-time
of UGATEx :
R2 = AV, 25 x (R1b + R1a // RNTC, 25
)
(7)
whereAV, 25°C is the error amplifier gain at room temperature
obtained from (2). R1b can be obtained by substituting
(7) to (3),
R1b
RSENSE, HOT
(R1a //RNTC, HOT ) (R1a//RNTC, COLD
)
RSENSE, COLD
RSENSE, HOT
-12
2810 R
1
TONSETx
(12)
t
(V
REFx
1.2V)
RSENSE, COLD
(8)
ONx
V
V
REFx
IN
where tONx is the UGATEx turn on period, VINis the input
voltage of converter, and VREFx is the internal reference
voltage.
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RT8162A
When VREFx is larger than 1.2V, the equivalent switching
frequency may be over the maximum design range, making
it unacceptable. Therefore, the VR implements a pseudo-
constant-frequency technology to avoid this disadvantage
of CCRCOT topology. When VREFx is larger than 1.2V,
the on-time equation will be modified to :
Differential Remote Sense Setting
The CORE/GFX VR includes differential, remote-sense
inputs to eliminate the effects of voltage drops along the
PC board traces, CPU internal power routes and socket
contacts. The CPU contains on-die sense pins CORE/
GFX VCC_SENSE and VSS_SENSE. Connect RGNDx to CORE/
GFX VSS_SENSE. Connect FBx to CORE/GFX VCC_SENSE
with a resistor to build the negative input path of the error
amplifier. The precision voltage reference VREFx is referred
to RGND for accurate remote sensing.
tONx (VREFx 1.2V)
23.3310-12 RTONSETx VREFx
(13)
VIN VREFx
On-time translates roughly to switching frequencies. The
on-times guaranteed in the Electrical Characteristics are
influenced by switching delays in external high side
MOSFET.Also, the dead-time effect increases the effective
on-time, reducing the switching frequency. It occurs only
in CCM during dynamic output voltage transitions when
the inductor current reverses at light or negative load
currents. With reversed inductor current, PHASEx goes
high earlier than normal, extending the on-time by a period
equal to the high side MOSFET rising dead time.
Current Sense Setting
The current sense topology of the CORE/GFX VR is
continuous inductor current sensing. Therefore, the
controller can be less noise sensitive. Low offset amplifiers
are used for loop control and over current detection. The
internal current sense amplifier gain (AI) is fixed to be 10.
The ISENxP and ISENxNdenote the positive and negative
input of the current sense amplifier.
Users can either use a current sense resistor or the
inductor'sDCR for current sensing. Using inductor'sDCR
allows higher efficiency as shown in Figure 12. To let
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX)(kHz)
(15)
L
DCR
tON tHSDelay
R C
X
X
VREFx(MAX) ILOAD(MAX) RON_LSFET DCR RDROOP then the transient performance will be optimum. For
example, choose L = 0.36μH with 1mΩ DCR and
CX = 100nF, to yields for RX :
0.36H
V
ILOAD(MAX) RON_LSFET RON_HSFET
IN(MAX)
(14)
R
3.6k
X
(16)
1m 10 0nF
where fS(MAX) is the maximum switching frequency, tHS-
Delay is the turn on delay of high side MOSFET, VREFx(MAX)
is the maximum application DAC voltage of application,
VIN(MAX) is the maximum application input voltage,
ILOAD(MAX) is the maximum load of application, RON_LS-FET
is the low side MOSFET RDS(ON), RON_HS-FET is the high
side MOSFET RDS(ON), DCRL is the inductor DCR, and
RDROOP is the load line setting.
V
OUT
(V
/V
)
CORE GFX
L
DCR
PHASEx
C
X
R
X
ISENxP
ISENxN
+
V
CSx
A
I
-
C
Byp
Figure 12. Lossless Inductor Sensing
R
R1
C1
TONSETx
TONSETx
VREFx
GFX/CORE
VR CCRCOT
PWM
V
IN
Generator
On-Time
Figure 11. On-Time Setting with RC Filter
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DS8162A-00 November 2013
RT8162A
V
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is too small. Vice versa, if the resistance is too large the
output voltage transient will only have a small initial dip
and the recovery will be too fast, causing a ring-back.
CC
R
1
R
NTC
R
2
TSENx
R
3
Using current-sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, a RC filter is recommended. The RC filter
calculation method is similar to the above-mentioned
inductorDCR sensing method.
Figure 13. Thermal Monitoring Circuit
To meet Intel's VR12/IMVP7 specification, platform users
have to set the TSEN voltage to meet the temperature
variation of VR from 75% to 100% VR max temperature.
For example, if the VR max temperature is 100°C, platform
users have to set the TSEN voltage to be 1.4875V when
VR temperature reaches 75°C and 1.8725V when VR
temperature reaches 100°C. Detailed voltage setting
versus temperature variation is shown in Table 2.
Thermometer code is implemented in the Temperature
Zone register.
Operation Mode Transition
The RT8162Asupports operation mode transition function
in CORE/GFX VR for the SetPS command of Intel's VR12/
IMVP7 CPU. The default operation mode of the RT8162A's
CORE/GFX VR is PS0, which is CCM operation. The other
operation mode is PS2 (DEM operation).
After receiving SetPS command, the CORE/GFX VR will
immediately change to the new operation state. When
VR receives SetPS command of PS2 operation mode,
the VR operates as a DEM controller.
Table 2. Temperature Zone Register
Comparator Trip Points
SVID Temperatures Scaled to maximum =
Thermal 100%
VRHOT
Alert Voltage Represents Assert bit
Minimum Level
If VR receives dynamic VID change command (SetVID),
VR will automatically enter PS0 operation mode. After
output voltage reaches target voltage, VR will stay at PS0
state and ignore former SetPS command. Only by
re-sending SetPS command after SetVID command will
VR be forced into PS2 operation state again.
b7
100%
b6
b5
b4
b3
b2
b1
b0
97% 94% 91% 88% 85% 82% 75%
1.745 1.69 1.635 1.58 1.52 1.47
1.855V 1.8V
V
V
V
V
5V
V
Temperature_Zone
Register Content
1111_1111
TSEN Pin Voltage
1.855 VTSEN
Thermal Monitoring and Temperature Reporting
1.800 VTSEN 1.835
1.745 VTSEN 1.780
1.690 VTSEN 1.725
1.635 VTSEN 1.670
1.580 VTSEN 1.615
1.525 VTSEN 1.560
1.470 VTSEN 1.505
VTSEN 1.470
0111_1111
CORE/GFX VR provides thermal monitoring function via
sensing TSEN pin voltage. Through the voltage divider
resistors R1, R2, R3 and RNTC, the voltage of TSEN will
be proportional to VR temperature. When VR temperature
rises, the TSENx voltage also rises. The ADC circuit of
VR monitors the voltage variation at TSENx pin from 1.47V
to 1.89V with 55mV resolution, and this voltage is decoded
into digital format and stored into the Temperature Zone
register.
0011_1111
0001_1111
0000_1111
0000_0111
0000_0011
0000_0001
0000_0000
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RT8162A
V
CC
The RT8162A supports two temperature reporting,
VRHOT(hardware reporting) and ALERT(software
reporting), to fulfill VR12/IMVP7 specification. VRHOT is
an open-drain structure which sends out active-low VRHOT
signals. When TSEN voltage rises above 1.855V (100%
of VR temperature), the VRHOT signal will be set to low.
When TSEN voltage drops below 1.8V (97% of VR
temperature), the VRHOT signal will be reset to high. When
TSEN voltage rises above 1.8V (97% of VR temperature),
The RT8162A will update the bit1 data from 0 to 1 in the
Status_1 register and assertALERT. When TSENvoltage
drops below 1.745V (94% of VR temperature), VR will
update the bit1 data from 1 to 0 in the Status_1 register
and assertALERT.
R
OC1
OCSETx
R
OC2
Figure 14. OCP Setting without Temperature
Compensation
The current limit is triggered when inductor current
exceeds the current limit threshold ILIMIT, defined by
VOCSET. The driver will be forced to turn off UGATE until
the over-current condition is cleared. If the over-current
condition remains valid for 15 PWM cycles, VR will trigger
OCP latch. Latched OCP forces both UGATE and LGATE
to go low. When OCP is triggered in one of VRs, the
other VR will enter into soft shutdown sequence. The OCP
latch mechanism will be masked when VRx_READY =
low, which means that only the current limit will be active
when VOUT is ramping up to initial voltage (or VREFx).
The temperature reporting function for theGFX VR can be
disabled by pulling TSENA pin to VCC in case the
temperature reporting function for theGFX VR is not used
or the GFX VR is disabled. When the GFX VR's
temperature reporting function is disabled, the RT8162A
will reject the SVID command of getting the
Temperature_Zone register content of the GFX VR.
However, note that the temperature reporting function for
the CORE VR is always active. CORE VR's temperature
reporting function can not be disabled by pulling TSEN
pin to VCC.
If inductorDCR is used as the current sense component,
then temperature compensation is recommended for
protection under all conditions. Figure 15 shows a typical
OCP setting with temperature compensation.
V
CC
R
OC1a
NTC
OC1b
Over-Current Protection
The CORE/GFX VR compares a programmable current
limit set point to the voltage from the current sense amplifier
output for Over-Current Protection (OCP). The voltage
applied to OCSETx pin defines the desired peak current
R
OCSETx
R
OC2
limit threshold ILIMIT
:
Figure 15. OCP Setting with Temperature Compensation
VOCSET = 48 x ILIMIT x RSENSE
(17)
Connect a resistive voltage divider from VCC toGND, with
the joint of the resistive divider connected to OCSET pin
as shown in Figure 14. For a given ROC2, then
Usually, ROC1a is selected to be equal to the thermistor's
nominal resistance at room temperature. Ideally, VOCSET
is assumed to have the same temperature coefficient as
RSENSE (InductorDCR) :
V
CC
(18)
R
R
OC2
1
OC1
V
OCSET
V
R
SENSE, HOT
OCSET, HOT
(19)
V
R
SENSE, COLD
OCSET, COLD
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According to the basic circuit calculation, VOCSET can be
obtained at any temperature :
Negative-Voltage Protection (NVP)
During OVP latch state, both CORE/GFX VRs also monitor
ISENxN pin for negative-voltage protection. Since the OVP
latch will continuously turn on low-side MOSFET of VR,
VR may suffer negative output voltage. Therefore, when
the voltage of ISENxN drops below −0.05V after triggering
OVP, VR will turn off low-side MOSFETs while high-side
MOSFETs remain off. TheNVP function will be active only
after OVP is triggered.
ROC2
VOCSET, T VCC
ROC1a / /RNTC, T ROC1b ROC2
(20)
Re-write (19) from (20), to get VOCSET at room temperature
R
//R
R
R
R
R
R
SENSE, HOT
OC1a
NTC, COLD
OC1b
OC2
R
//R
R
SENSE, COLD
OC1a
NTC, HOT
OC1b
OC2
(21)
Under-Voltage Protection (UVP)
VOCSET, 25
VCC
ROC2
Both CORE/GFX VR implement Under-Voltage Protection
(22)
ROC1a / /RNTC, 25 ROC1b ROC2
(UVP). If ISENxNis less than VREFx by 300mV + VOFFSET
,
VR will trigger UVP latch. The UVP latch will turn off both
high-side and low-side MOSFETs. When UVP is triggered
by one of the VRs, the other VR will enter into soft
shutdown sequence. The UVP mechanism is masked
when VRx_READY = low.
Solving (21) and (22) yields ROC1b and ROC2
ROC2
REQU, HOT REQU, COLD (1 )REQU, 25
VCC
VOCSET, 25
(1 )
(23)
(24)
ROC1b
Under-Voltage Lockout (UVLO)
( 1)R2 REQU, HOT REQU, COLD
(1 )
During normal operation, if the voltage at the VCC pin
drops below UVLO falling edge threshold, both VR will
trigger UVLO. The UVLO protection forces all high-side
MOSFETs and low-side MOSFETs off to turn off.
where
RSENSE, HOT
DCR25 [1 0.00393(THOT 25)]
RSENSE, COLD DCR25 [1 0.00393(TCOLD 25)]
(25)
(26)
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
REQU, T = ROC1a // RNTC, T
V
IN VOUT
LMIN
tON
(27)
IRipple(MAX)
Over-Voltage Protection (OVP)
where tON is the UGATE turn on period.
The over-voltage protection circuit of CORE/GFX VR
monitors the output voltage via the ISENxN pin. The
supported maximum operating VID of VR (V(MAX)) is stored
in the Vout_Max register. Once VISENxN exceeds “V(MAX)
+ 200mV”, OVP is triggered and latched. VR will try to
turn on low-side MOSFETs and turn off high-side
MOSFETs to protect CPU. When OVP is triggered by
the one of the VRs, the other VR will enter soft shutdown
sequence. A 1μs delay is used in OVP detection circuit
to prevent false trigger.
Higher inductance induces less ripple current and hence
higher efficiency. However, the tradeoff is a slower transient
response of the power stage to load transients. This might
increase the need for more output capacitors, thus driving
up the cost. Find a low-loss inductor having the lowest
possibleDC resistance that fits in the allotted dimensions.
The core must be large enough not to be saturated at the
peak inductor current.
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is a registered trademark of Richtek Technology Corporation.
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RT8162A
Output Capacitor Selection
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Four-Layer PCB
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors can be found, bulk capacitors closely located
to the inductors and ceramic output capacitors in close
proximity to the load. Latter ones are for mid-frequency
decoupling with very small ESR and ESL values while the
bulk capacitors have to provide enough stored energy to
overcome the low-frequency bandwidth gap between the
regulator and the CPU.
0
25
50
75
100
125
Ambient Temperature (°C)
Thermal Considerations
Figure 16.Derating Curve of Maximum Power
Dissipation
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Layout Consideration
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board with their ground terminals flushed
against one another. Follow these guidelines for optimum
PC board layout :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
Keep the high current paths short, especially at the
ground terminals.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-40L 5x5 packages, the thermal resistance, θJA, is
27.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
Keep the power traces and load connections short. This
is essential for high efficiency.
When trade-offs in trace lengths must be made, it's
preferable to allow the inductor charging path to be made
longer than the discharging path.
Place the current sense component close to the
controller. ISENxP and ISENxNconnections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee the current sense
accuracy. The PCB trace from the sense nodes should
be parallel to the controller.
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.63W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 16 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Route high-speed switching nodes away from sensitive
analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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38
DS8162A-00 November 2013
RT8162A
Special attention should be paid in placing the DCR
current sensing components. TheDCR current sensing
capacitor and resistors must be placed close to the
controller.
The capacitor connected to the ISEN1N/ISENANfor noise
decoupling is optional and it should also be placed close
to the ISEN1N/ISENAN pin.
The NTC thermistor should be placed physically close
to the inductor for better DCR thermal compensation.
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8162A-00 November 2013
www.richtek.com
39
RT8162A
Outline Dimension
SEE DETAIL A
D
D2
L
1
E2
E
1
2
1
2
e
b
DETAILA
A
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.700
0.000
0.175
0.150
4.950
3.250
4.950
3.250
0.800
0.050
0.250
0.250
5.050
3.500
5.050
3.500
0.028
0.000
0.007
0.006
0.195
0.128
0.195
0.128
0.031
0.002
0.010
0.010
0.199
0.138
0.199
0.138
D
D2
E
E2
e
0.400
0.016
L
0.350
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8162A-00 November 2013
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