RT8249D_技术文档

®

RT8249D

Dual-Channel Synchronous DC-DC Step-Down Controller

with 5V/3.3V LDOs

General Description

Features

^Support Connected Standby Mode for Ultrabook

^CCRCOT Control with 100ns Load Step Response

^PWM Maximum Duty Ratio > 98%

^5V to 25V Input Voltage Range

^Dual Adjustable Output :

The RT8249D is a dual-channel step-down, controller

generating supply voltages for battery-powered systems.

It includes two Pulse-Width Modulation (PWM) controllers

adjustable from 2V to 5.5V, and two fixed 5V/3.3V linear

regulators. Each linear regulator provides up to 100mA

output current and 3.3V linear regulator provides 1%

accuracy under 35mA. The RT8249D provides a mode

selection pin, SKIPSEL, to selectDiode-Emulation Mode

(DEM) or Audio Skipping Mode (ASM). Other features

include on-board power-up sequencing, a power-good

output, internal soft-start, and soft-discharge output that

prevents negative voltage during shutdown.

 CH1 : 2V to 5.5V

 CH2 : 2V to 4V

^5V/3.3V LDOs with 100mA Output Current

^1% Accuracy on 3.3V LDO Output

^Oscillator Driving Output for Charge Pump

Application

 Internal Frequency Setting

^500kHz/600kHz (CH1/CH2)

A constant current ripple PWM control scheme operates

without sense resistors and provides 100ns response to

load transient. For maximizing power efficiency, the

RT8249D automatically switches to the diode-emulation

mode in light load applications. The RT8249Dis available

in the WQFN-20L 3x3 package.

 Internal Soft-Start and Soft-Discharge

 4700ppm/°C R_DS(ON)Current Sensing

 Independent Switcher Enable Control

 Built in OVP/UVP/OCP/OTP

 Non-latch UVLO

 Power Good Indicator

 20-Lead WQFN Package

 RoHS Compliant and Halogen Free

Simplified Application Circuit

V

IN

UGATE2

VIN

RT8249D

BOOT2

UGATE1

BOOT1

V

PHASE2

LGATE2

OUT2

V

OUT1

PHASE1

LGATE1

FB2

CS1

CS2

BYP1

LDO5

5V

FB1

EN1

EN2

Channel 1 Enable

Channel 2 Enable

PGOOD

LDO3

icator

PGOOD Ind

3.3V

On

Off

GND

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RT8249D

Pin Configuration

Applications

 Notebook and Sub-Notebook Computers

(TOP VIEW)

 System Power Supplies

 3-Cell and 4-Cell Li+ Battery-PoweredDevices

20 19 18 17 16

Ordering Information

RT8249D

1

2

3

4

5

15

14

13

12

11

CS1

FB1

LDO3

FB2

LGATE1

BYP1

LDO5

VIN

LGATE2

GND

Pin 1 Orientation***

(2) : Quadrant 2, Follow EIA-481-D

21

CS2

6

7

8

9 10

Package Type

QW : WQFN-20L 3x3 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

WQFN-20L 3x3

Note :

Marking Information

RT8249DGQW

***Empty means Pin1 orientation is Quadrant 1

Richtek products are :

9N= : Product Code

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

YMDNN : Date Code

9N=YM

DNN

 Suitable for use in SnPb or Pb-free soldering processes.

Functional Pin Description

Pin No.

Pin Name

Pin Function

Current limit setting. Connect a resistor to GND to set the threshold for channel 1

synchronous R_DS(ON)sense. The GND  PHASE1 current limit threshold is 1/8th

the voltage seen at CS1 over a 0.2V to 2V range. There is an internal 50A

current source from LDO5 to CS1.

1

CS1

Feedback voltage input for channel 1. Connect FB1 to a resistive voltage divider

from VOUT1 to GND to adjust output from 2V to 5.5V.

2

3

4

FB1

3.3V linear regulator output. It is always on when VIN is higher than VINPOR

threshold.

LDO3

FB2

Feedback voltage input for channel 2. Connect FB2 to a resistive voltage divider

from VOUT2 to GND to adjust output from 2V to 4V.

Current limit setting. Connect a resistor to GND to set the threshold for channel 2

synchronous R_DS(ON)sense. The GND  PHASE2 current limit threshold is 1/8th

the voltage seen at CS2 over a 0.2V to 2V range. There is an internal 50A

current source from LDO5 to CS2.

5

CS2

6

7

EN2

Enable control input for channel 2.

PGOOD

Power good indicator output for channel 1 and channel 2. (Logical AND)

Switch node of channel 2 MOSFETs. PHASE2 is the internal lower supply rail for

the UGATE2 high-side gate driver. PHASE2 is also the current-sense input for the

channel 2.

8

PHASE2

Bootstrap supply for channel 2 high-side gate driver. Connect to an external

capacitor according to the typical application circuits.

9

BOOT2

High-side gate driver output for channel 2. UGATE2 swings between PHASE2

and BOOT2.

10

UGATE2

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DS8249D-02 January 2020

RT8249D

Pin No.

11

Pin Name

LGATE2

VIN

Pin Function

Low-side gate driver output for channel 2. LGATE2 swings between GND and

LDO5.

12

Power input for 5V and 3.3V LDO regulators and buck controllers.

5V linear regulator output. LDO5 is also the supply voltage for the low-side

MOSFET and analog supply voltage for the device.

13

LDO5

14

BYP1

Switch-over source voltage input for LDO5.

Low-side gate driver output for channel 1. LGATE1 swings between GND and

LDO5.

15

LGATE1

High-side gate driver output for channel 1. UGATE1 swings between PHASE1

and BOOT1.

16

17

UGATE1

BOOT1

Bootstrap supply for channel 1 high-side gate driver. Connect to an external

capacitor according to the typical application circuits.

Switch node of channel 1 MOSFETs. PHASE1 is the internal lower supply rail for

the UGATE1 high-side gate driver. PHASE1 is also the current sense input for the

Channel 1.

18

PHASE1

SKIPSEL

PWM operating mode selection.

Diode-emulation mode : connect to LDO5

Audio skipping mode : short to GND

19

20

EN1

Enable control input for channel 1.

21

Ground. The exposed pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

GND

(Exposed Pad)

Functional Block Diagram

BOOT1

BOOT2

UGATE1

UGATE2

PHASE2

PHASE1

LDO5

Channel 1

Buck

Channel 2

Buck

Controller

LGATE1

LGATE2

FB1

CS1

FB2

CS2

PGOOD

GND

SKIPSEL

SW5 Threshold

BYP1

Power-On

Sequence

Clear Fault Latch

EN1

EN2

REF

LDO3

BYP1

LDO3

LDO5

VIN

LDO5

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RT8249D

Operation

current to the load exceeds the average output inductor

current, the output voltage falls and eventually crosses

the under-voltage protection threshold, inducing IC

shutdown.

The RT8249Dincludes two constant on-time synchronous

step-down controllers and two linear regulators.

Buck Controller

In normal operation, the high-side N-MOSFET is turned

on when the output is lower than VREF, and is turned off

after the internal one-shot timer expires. While the high-

sideN-MOSFET is turned off, the low-sideN-MOSFET is

turned on to conduct the inductor current until next cycle

begins.

Over-Voltage Protection (OVP) & Under-Voltage

Protection (UVP)

The two channel output voltages are continuously

monitored for over-voltage and under-voltage conditions.

When the output voltage exceeds over-voltage threshold

(113% of VOUT), UGATE goes low and LGATE is forced

high. When it is less than 52% of reference voltage, under-

voltage protection is triggered and then both UGATE and

LGATE gate drivers are forced low. The controller is latched

until ENx is reset or LDO5 is re-supplied.

Soft-Start

For internal soft-start function, an internal current source

charges an internal capacitor to build the soft-start ramp

voltage. The output voltage will track the internal ramp

voltage during soft-start interval.

LDO5 and LDO3

PGOOD

When the VIN voltage exceeds the POR rising threshold,

LDO3 will default turn-on. The LDO5 can be power on by

ENx. The linear regulator LDO5 and LDO3 provide 5V and

3.3V regulated output.

The power good output is an open-drain architecture. When

the two channels soft-start are both finished, the PGOOD

open-drain output will be high impedance.

Current Limit

Switching Over

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle. Thus, the

The BYP1 is connected to the Channel 1 output. After the

Channel 1 output voltage exceeds the set threshold

(4.66V), the output will be bypassed to the LDO5 output

to maximize the efficiency.

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RT8249D

Absolute Maximum Ratings (Note 1)

 VINtoGND----------------------------------------------------------------------------------------------------------------- −0.3V to 30V

 BOOTx toGND

DC---------------------------------------------------------------------------------------------------------------------------- −0.3V to 36V

<100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 42V

 BOOTx to PHASEx

DC---------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

<100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 PHASEx to GND

DC---------------------------------------------------------------------------------------------------------------------------- −5V to 30V

<100ns ---------------------------------------------------------------------------------------------------------------------- −10V to 42V

 UGATEx toGND

DC---------------------------------------------------------------------------------------------------------------------------- −5V to 36V

<100ns ---------------------------------------------------------------------------------------------------------------------- −10V to 42V

 UGATEx to PHASEx

DC---------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

<100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGATEx toGND

DC---------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

<100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 Other Pins------------------------------------------------------------------------------------------------------------------ −0.3V to 6.5V

 Power Dissipation, P_D@ T_A= 25°C

WQFN-20L 3x3 ----------------------------------------------------------------------------------------------------------- 3.33W

 Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θ_JA------------------------------------------------------------------------------------------------------ 30°C/W

WQFN-20L 3x3, θ_JC----------------------------------------------------------------------------------------------------- 7.5°C/W

 Junction Temperature ---------------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------ 260°C

 Storage Temperature Range ------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Supply Voltage, VIN ----------------------------------------------------------------------------------------------------- 5V to 25V

 Junction Temperature Range------------------------------------------------------------------------------------------- −40°C to 125°C

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RT8249D

Electrical Characteristics

(V_IN= 12V, V_EN1= V_EN2= 3.3V, V_CS1= V_CS2= 2V, No Load, T_A= 25°C, unless otherwise specified)

Parameter

Input Supply

Symbol

Test Conditions

Min

Typ

Max

Unit

Rising threshold

--

4.6

3.7

4.9

--

VIN Power On Reset

V_{IN_POR}

V

Falling threshold

3.2

VIN Standby Supply

Current

Both buck controllers off,

V_EN1= V_EN2= GND

I_{VIN_SBY}

--

20

15

35

25

A

Both buck controllers on,

V_FBx= 2.05V, V_BYP1= 5.05V

VIN Quiescent Current

BYP1 Supply Current

I_{VIN_nosw}

I_{BYP1_nosw}

Both buck controllers on,

V_FBx= 2.05V, V_BYP1= 5.05V

120

180

Soft-Start

Soft-Start Time

t_SSx

V_OUTramp-up time

--

0.9

--

ms

Buck Controllers Output and FB Voltage

FBx Valley Trip Voltage

BYP1 Discharge Current

V_FBx

CCM operation

1.98

10

2

2.02

--

V

I_{DCHG_BYP1}V_BYP1= 0.5V

45

mA

PHASEx Discharge

Current

I_{DCHG_LX}

V_PHASEx= 0.5V

5

8

--

mA

Switching Frequency

V_IN= 20V, V_OUT1= 5V

V_IN= 20V, V_OUT2= 3.33V

V_FBx= 1.9V

400

480

--

500

600

200

600

720

275

Switching Frequency

f_SWx

kHz

ns

Minimum Off-Time

Current Sense

t_OFF(MIN)

CSx Source Current

I_CSx

V_CSx= 1V

47

--

50

4700

1

53

--

A

ppm/C

mV

CSx Current Temperature

Coefficient

TCI_CSx

V_ZC

In comparison with 25°C

V_FBx= 2.05V, GND  PHASEx

Zero-Current Threshold

--

Internal Regulator

V_IN= 12V, no load

4.9

4.8

5

5.1

V_IN> 7V, I_LDO5< 100mA

V_IN> 5.5V, I_LDO5< 35mA

V_IN> 5V, I_LDO5< 20mA

V_IN= 12V, no load

LDO5 Output Voltage

LDO3 Output Voltage

V_LDO5

V

4.8

5

5.1

4.5

4.75

3.3

5.1

3.267

3.217

3.267

3.217

3.333

3.383

3.333

3.383

V_IN> 7V, I_LDO3< 100mA

V_IN> 5.5V, I_LDO3< 35mA

V_IN> 5V, I_LDO3< 20mA

V_LDO3

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RT8249D

Parameter

Symbol

I_LDO5

Test Conditions

Min

100

--

Typ

175

4.66

Max

--

Unit

mA

V

_LDO5= 4.5V, V_BYP1= GND,

LDO5 Output Current

LDO3 Output Current

V_IN= 7.4V

I_LDO3

V_LDO3= 3V, V_IN= 7.4V

--

LDO5 Switch-over

Threshold to BYP1

V_SWTH

Rising edge at BYP1 regulation point

LDO5 to BYP1, 10mA

--

LDO5 Switch-over

Equivalent Resistance

R_SW

--

1.5

3



SKIP Mode Selection

SKIPSEL Input Voltage

UVLO

ASM operation

DEM operation

--

0.8

--

V

V_SKIPSEL

1.2

Rising edge

Falling edge

Channel x off

--

3.7

--

4.3

3.9

2.5

4.6

4.1

--

V

LDO5 UVLO Threshold

V_UVLO5

V_UVLO3

LDO3 UVLO Threshold

Power Good

PGOOD detect, V_FBxrising edge

Hysteresis

84

--

88

8

92

--

PGOOD Threshold

V_PGxTH

%

PGOOD Leakage

Current

High state, V_PGOOD= 5.5V

I_SINK= 4mA

--

1

A

PGOOD Output Low

Voltage

0.3

V

Fault Detection

OVP Trip Threshold

OVP Propagation Delay

UVP Trip Threshold

V_OVP

FBx with respect to internal reference

UVP detect, FBx falling edge

109

--

113

1

117

--

%

s

%

V_UVP

47

52

57

UVP Shutdown Blanking

Time

t_{SHDN_UVP}From ENx enable

--

1.3

--

ms

Thermal Shutdown

Threshold

T_SD

150

°C

Logic Inputs

V_{ENx_H}

V_{ENx_L}

SMPS on

SMPS off

1.6

--

ENx Threshold Voltage

V

0.4

Internal Boost Switch

On-Resistance

R_BST

LDO5 to BOOTx

--

80

--



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RT8249D

Parameter

Symbol

Test Conditions

Min

Typ

Max Unit

Power MOSFET Drivers

High state, V_BOOTx V_UGATEx= 0.25V,

V_BOOTx V_PHASEx= 5V

--

3

2

3

--



--

UGATEx On-Resistance

R_UG

Low state, V_UGATEx V_PAHSEx= 0.25V,

V_BOOTx V_PHASEx= 5V

High state, V_LDO5 V_LGATEx= 0.25V,

V_LDO5= 5V

--

LGATEx On-Resistance

Dead-Time

R_LG



Low state, V_LGATEx GND = 0.25V

LGATEx rising

--

1

--

20

30

--

t_d

ns

--

UGATEx rising

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

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RT8249D

Typical Application Circuit

V

IN

5.2V to 25V

R8

0

C1

10µF

RT8249D

UGATE2

C13

C12

R10 0

R9 0

Q2

BSC0909

NS

10µF

10

9

12

VIN

C10

0.1µF

BOOT2

Q1

BSC0909

NS

R4 0

16

17

C11

0.1µF

L2

2.2µH

UGATE1

BOOT1

8

V

OUT2

R3 0

PHASE2

LGATE2

3.3V

C17

220µF

Q4

BSC0909

NS

11

L1

3.3µH

C2

0.1µF

R11*

C14*

18

15

V

OUT1

5V

PHASE1

LGATE1

Q3

BSC0909

NS

C3

220µF

R5*

C4*

R14

130k

C21*

4

FB2

14

2

R15

200k

BYP1

FB1

C23

R12

150k

13

0.1µF

C18*

LDO5

5V

C9

1µF

R13

100k

7

3

PGOOD

LDO3

PGOOD Indicator

3.3V Always On

DEM : 5V

ASM : GND

19

SKIPSEL

C16

1µF

20

6

R1

Channel 1 Enable

EN1

EN2

16k

1

5

CS1

CS2

Channel 2 Enable

R2

16k

On

Off

21 (Exposed Pad)

GND

* : Optional

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RT8249D

Typical Operating Characteristics

V_OUT1Efficiency vs. Output Current

V_OUT2Efficiency vs. Output Current

100

95

90

85

80

75

70

65

60

55

50

45

40

35

100

95

90

V_IN= 7.4V

V_IN= 11.1V

V_IN= 14.8V

V_IN= 20.5V

V_IN= 7.4V

V_IN= 11.1V

V_IN= 14.8V

V_IN= 20.5V

85

80

75

70

DEM, EN1 = 0V, EN2 = LDO3, BYP1 on

DEM, EN1 = LDO3, EN2 = 0V, BYP1 on

65

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT1Switching Frequency vs. Output Current

V_OUT2Switching Frequency vs. Output Current

600

700

DEM, EN1 = 0V, EN2 = LDO3, BYP1 on

DEM, EN1 = LDO3, EN2 = 0V, BYP1 on

600

500

V_IN= 19V

V_IN= 11.1V

V_IN= 7.4V

V_IN= 19V

V_IN= 11.1V

V_IN= 7.4V

500

400

300

200

100

0

300

200

100

0

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT1Switching Frequency vs. Input Voltage

600

V_OUT2Switching Frequency vs. Input Voltage

700

600

500

400

300

200

100

500

400

300

200

100

DEM, EN1 = 0V, EN2 = LDO3, I_OUT2= 6A, BYP1 on

0

DEM, EN1 = LDO3, EN2 = 0V, I_OUT1= 6A, BYP1 on

0

5

7

9

11 13 15 17 19 21 23 25

5

7

9

11 13 15 17 19 21 23 25

Input Voltage (V)

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RT8249D

V_OUT1Output Voltage vs. Output Current

V_OUT2Output Voltage vs. Output Current

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

3.33

3.32

3.31

3.30

3.29

3.28

V_IN= 20.5V

V_IN= 14.8V

V_IN= 11.1V

V_IN= 7.4V

V_IN= 20.5V

V_IN= 14.8V

V_IN= 11.1V

V_IN= 7.4V

DEM, EN1 = 0V, EN2 = LDO3, BYP1 on

DEM, EN1 = LDO3, EN2 = 0V, BYP1 on

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

VLDO5 vs. ILDO5

VLDO3 vs. ILDO3

3.300

5.020

5.018

5.016

5.014

5.012

5.010

5.008

5.006

5.004

5.002

5.000

3.298

3.296

3.294

3.292

3.290

3.288

3.286

3.284

3.282

3.280

DEM, V_IN= 12V, EN1 = LDO3, EN2 = 0V, BYP1 off

DEM, V_IN= 12V, EN1 = 0V, EN2 = LDO3, BYP1 off

0

10 20 30 40 50 60 70 80 90 100

ILDO5 (mA)

0

10 20 30 40 50 60 70 80 90 100

ILDO3 (mA)

Quiescent Current vs. Input Voltage

BYP1 Supply Current vs. Input Voltage

30

25

20

15

10

5

160

150

140

130

120

110

100

DEM, EN1 = EN2 = LDO3, BYP1 on

0

5

7

9

11 13 15 17 19 21 23 25

Input Voltage (V)

5

7

9

11 13 15 17 19 21 23 25

Input Voltage (V)

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RT8249D

Power On from EN

Power Off from EN

EN

(5V/Div)

V_OUT1

(5V/Div)

V_OUT2

V_OUT1

(5V/Div)

V_OUT2

(5V/Div)

LDO5

(5V/Div)

LDO5

(5V/Div)

DEM, EN1 = EN2 = LDO3, V_IN= 12V , No Load

Time (20ms/Div)

DEM, EN1 = EN2 = LDO3, V_IN= 12V , No Load

Time (400μs/Div)

V_OUT1Load Transient Response at DEM

V_OUT1Load Transient Response at ASM

EN1 = LDO3, EN2 = 0V, V_IN= 12V, I_OUT1= 0A to 6A

UGATE1

(20V/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

LGATE1

(5V/Div)

I_OUT1

(5A/Div)

I_OUT1

(5A/Div)

V_OUT1

(50mV/Div)

Time (40μs/Div)

V_OUT2Load Transient Response at DEM

V_OUT2Load Transient Response at ASM

EN1 = 0V, EN2 = LDO3, V_IN= 12V, I_OUT1= 0A to 6A

UGATE1

(20V/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

LGATE1

(5V/Div)

I_OUT1

(5A/Div)

I_OUT1

(5A/Div)

V_OUT1

(50mV/Div)

Time (40μs/Div)

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DS8249D-02 January 2020

RT8249D

V_OUT1OVP

V_OUT1UVP

V_OUT1

(5V/Div)

I_L1

(10A/Div)

V_OUT1

(2V/Div)

UGATE1

(20V/Div)

PGOOD

(5V/Div)

LGATE1

(5V/Div)

LGATE1

(5V/Div)

DEM, EN1 = EN2 = LDO3, V_IN= 12V, No Load

DEM, EN1 = EN2 = LDO3, V_IN= 12V

Time (100μs/Div)

Time (400μs/Div)

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RT8249D

Application Information

on-time is inversely proportional to the input voltage as

measured by V_INand proportional to the output voltage.

The inductor ripple current operating point remains

relatively constant, resulting in easy design methodology

and predictable output voltage ripple. The frequency of 3V

output controller is set higher than the frequency of 5V

output controller. This is done to prevent audio frequency

“beating” between the two sides, which switch

asynchronously for each side.

The RT8249D is a dual-channel, low quiescent, Mach

Response^TMDRV^TMmode synchronous Buck controller

targeted for Ultrabook system power supply solutions.

Richtek's Mach Response^TMtechnology provides fast

response to load steps. The topology solves the poor load

transient response timing problems of fixed frequency

current mode PWMs, and avoids the problems caused

by widely varying switching frequencies in CCR (constant

current ripple) constant on-time and constant off-time

PWM schemes. Aspecial adaptive on-time control trades

off the performance and efficiency over wide input voltage

range. The RT8249Dincludes 5V (LDO5) and 3.3V (LDO3)

linear regulators. The LDO5 linear regulator steps down

the battery voltage to supply both internal circuitry and

gate drivers. The synchronous switch gate drivers are

directly powered by LDO5. When V_OUT1rises above 4.66V,

an automatic circuit disconnects the linear regulator and

allows the device to be powered by V_OUT1via the BYP1

pin.

The RT8249Dadaptively changes the operation frequency

according to the input voltage. Higher input voltage usually

comes from an external adapter, so the RT8249Doperates

with higher frequency to have better performance. Lower

input voltage usually comes from a battery, so the

RT8249D operates with lower switching frequency for

lower switching losses. For a specific input voltage range,

the switching cycle period is given by :

For 5V VOUT,

V

_IN1.62

Period (μsec.) =

For 3.3V VOUT,

Period (μsec.) =

V_IN3.79

PWM Operation

The Mach Response^TMDRV^TMmode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current sense resistor, so that the output

ripple voltage provides the PWM ramp signal. Referring to

the RT8249D's Function BlockDiagram, the synchronous

high-side MOSFET is turned on at the beginning of each

cycle. After the internal one-shot timer expires, the

MOSFET will be turned off. The pulse width of this one-

shot is determined by the converter's input output voltages

to keep the frequency fairly constant over the entire input

voltage range. Another one-shot sets a minimum off-time

(200ns typ.). The on-time one-shot will be triggered if the

error comparator is high, the low-side switch current is

below the current limit threshold, and the minimum off-

time one-shot has timed out.

V_IN1.45

V_IN 2.59

where the VIN is in volt.

The on-time guaranteed in the Electrical Characteristics

table is influenced by switching delays in the external

high-side power MOSFET.

Operation Mode Selection

The RT8249D supports two operation modes : diode

emulation mode (DEM) and ultrasonic mode (ASM). The

operation mode can be set via the SKIPSEL pin. When

the SKIPSELpin voltage is higher than 1.2V, the RT8249D

operates inDEM. When the SKIPSEL pin Voltage is lower

than 0.8V, the RT8249D operates in ASM.

PWM Frequency and On-time Control

Diode Emulation Mode

For each specific input voltage range, the Mach

Response^TMcontrol architecture runs with pseudo constant

frequency by feed forwarding the input and output voltage

into the on-time one-shot timer. The high-side switch

In diode emulation mode, the RT8249D automatically

reduces switching frequency at light load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly. As the output current decreases from

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14

DS8249D-02 January 2020

RT8249D

heavy load condition, the inductor current is also reduced,

and eventually comes to the point that its current valley

touches zero, which is the boundary between continuous

conduction and discontinuous conduction modes. To

emulate the behavior of diodes, the low-side MOSFET

allows only partial negative current to flow when the

inductor free wheeling current becomes negative. As the

load current is further decreased, it takes longer and longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. The on-time is kept the

same as that in the heavy load condition. In reverse, when

the output current increases from light load to heavy load,

the switching frequency increases to the preset value as

the inductor current reaches the continuous conduction.

The transition load point to the light load operation is shown

in Figure 1. and can be calculated as follows :

Ultrasonic Mode (ASM)

The RT8249Dactivates a unique type of diode emulation

mode with a minimum switching frequency of 25kHz,

called ultrasonic mode. This mode eliminates audio-

frequency modulation that would otherwise be present

when a lightly loaded controller automatically skips

pulses. In ultrasonic mode, the low-side switch gate driver

signal is “OR”ed with an internal oscillator (>25kHz).

Once the internal oscillator is triggered, the controller will

turn on UGATE and give it shorter on-time.

When the on-time expired, LGATE turns on until the

inductor current goes to zero crossing threshold and keep

both high-side and low-side MOSFET off to wait for the

next trigger. Because shorter on-time causes a smaller

pulse of the inductor current, the controller can keep output

voltage and switching frequency simultaneously.

I

L

The on-time decreasing has a limitation and the output

voltage will be lifted up under the slight load condition.

The controller will turn on LGATE first to pull down the

output voltage. When the output voltage is pulled down to

the balance point of the output load current, the controller

will proceed the short on-time sequence as the above

description.

Slope = (V - V

) / L

IN

OUT

I

t

PEAK

I

/ 2

LOAD = PEAK

0

t

ON

Linear Regulators (LDOx)

Figure 1. Boundary Condition of CCM/DEM

The RT8249Dincludes 5V (LDO5) and 3.3V (LDO3) linear

regulators. The regulators can supply up to 100mA for

external loads. Bypass LDOx with 1μF(min) to 4.7μF

(max), and the recommended value is 1μF. ceramic

capacitor. When V_OUT1is higher than the switch over

threshold (4.66V), an internal 1.5Ω P-MOSFET switch

connects BYP1 to the LDO5 pin while simultaneously

disconnects the internal linear regulator.

(V_IN V_OUT

)

I_LOAD(SKIP)



t_ON

2L

where t_ONis the on-time.

The switching waveforms may appear noisy and

asynchronous when light load causes diode emulation

operation. This is normal and results in high efficiency.

Trade offs in PFM noise vs. light load efficiency is made

by varying the inductor value.Generally, low inductor values

produce a broader efficiency vs. load curve, while higher

values result in higher full load efficiency (assuming that

the coil resistance remains fixed) and less output voltage

ripple. Penalties for using higher inductor values include

larger physical size and degraded load transient response

(especially at low input voltage levels).

Current Limit Setting

The RT8249Dhas cycle-by-cycle current limit control and

the OCP function only operation at CCM, it is disabled at

DEM in order to reduce quiescent current. The current

limit circuit employs a unique “valley” current sensing

algorithm. If the magnitude of the current sense signal at

PHASEx is above the current limit threshold, the PWM

is not allowed to initiate a new cycle (Figure 2). The actual

peak current is greater than the current limit threshold by

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15

RT8249D

an amount equal to the inductor ripple current. Therefore,

the exact current limit characteristic and maximum load

capability are a function of the sense resistance, inductor

value, battery and output voltage.

drive current is supplied by the flying capacitor between

the BOOTx and PHASEx pins. A dead-time to prevent

shoot through is internally generated from high-side

MOSFET off to low-side MOSFET on and low-side

MOSFET off to high-side MOSFET on.

I

L

The low-side driver is designed to drive high current low

R_DS(ON)N-MOSFET(s). The internal pull down transistor

that drives LGATEx low is robust, with a 1Ω typical on-

resistance. A 5V bias voltage is delivered from the LDO5

supply. The instantaneous drive current is supplied by an

input capacitor connected between LDO5 andGND.

I

PEAK

LOAD

I

t

LIMIT

For high current applications, some combinations of high

and low-side MOSFETs may cause excessive gate drain

coupling, which leads to efficiency killing, EMI producing,

and shoot through currents. This is often remedied by

adding a resistor in series with BOOTx, which increases

the turn-on time of the high-side MOSFET without

degrading the turn-off time. See Figure 3.

Figure 2. “Valley” Current Limit

The RT8249Duses the on resistance of the synchronous

rectifier as the current sense element and supports

temperature compensated MOSFET R_DS(ON)sensing. The

R_ILIMresistor between the CSx pin andGNDsets the current

limit threshold. The resistor R_ILIMis connected to a current

source from CSxwhich is 50μA (typ.) at room temperature.

The current source has a 4700ppm/°C temperature slope

to compensate the temperature dependency of the

R_DS(ON). When the voltage drop across the sense resistor

or low-side MOSFET equals 1/8 the voltage across the

R_ILIMresistor, positive current limit will be activated. The

high-side MOSFET will not be turned on until the voltage

drop across the MOSFET falls below 1/8 the voltage across

the R_ILIMresistor.

V

IN

UGATEx

BOOTx

R

BOOT

PHASEx

Figure 3. Increasing the UGATEx Rise Time

Soft-Start

Choose a current limit resistor according to the following

equation :

The RT8249D provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled.During soft-

start, it clamps the ramping of internal reference voltage

which is compared with FBx signal. The typical soft-start

duration is 0.9ms. An unique PWM duty limit control that

prevents output over-voltage during soft-start period is

designed specifically for FBx floating.

V_LIMIT= (R_LIMITx 50μA) / 8 = I_LIMITx R_DS(ON)

R_LIMIT= (I_LIMITx R_DS(ON)) x 8 / 50μA

Carefully observe the PC board layout guidelines to ensure

that noise andDC errors do not corrupt the current sense

signal at PHASEx and GND. Mount or place the IC close

to the low-side MOSFET.

MOSFET Gate Driver (UGATEx, LGATEx)

UVLO Protection

The high-side driver is designed to drive high current, low

R_DS(ON)N-MOSFET(s). When configured as a floating driver,

5V bias voltage is delivered from the LDO5 supply. The

average drive current is also calculated by the gate charge

at V_GS= 5V times switching frequency. The instantaneous

The RT8249Dhas LDO5 under-voltage lock out protection

(UVLO). When the LDO5 voltage is lower than 3.9V (typ.)

and the LDO3 voltage is lower than 2.5V (typ.), both switch

power supplies are shut off. This is a non-latch protection.

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DS8249D-02 January 2020

RT8249D

Power Good Output (PGOOD)

Thermal Protection

PGOOD is an open-drain output and requires a pull-up

resistor. PGOODis actively held low in soft-start, standby,

and shutdown. For RT8249D, PGOOD is released when

both output voltages are above 88% of nominal regulation

point. The PGOOD signal goes low if either output turns

off or is 20% below or 13% over its nominal regulation

point.

The RT8249D features thermal shutdown to prevent

damage from excessive heat dissipation. Thermal

shutdown occurs when the die temperature exceeds

150°C.All internal circuitries are turned off during thermal

shutdown. The RT8249D triggers thermal shutdown if LDO5

is not supplied from V_OUT1, while input voltage on VINand

drawing current from LDO5 are too high. Nevertheless,

even if LDO5 is supplied from V_OUT1, overloading LDO5

can cause large power dissipation on automatic switches,

which may still result in thermal shutdown.

Output Over-Voltage Protection (OVP)

The output voltage can be continuously monitored for over-

voltage condition. If the output voltage exceeds 13% of

its set voltage threshold, the over-voltage protection is

triggered and the LGATEx low-side gate drivers are forced

high. This activates the low-side MOSFET switch, which

rapidly discharges the output capacitor and pulls the output

voltage downward.

Discharge Mode (Soft Discharge)

When ENx is low the output under-voltage fault latch is

set, the output discharge mode will be triggered. During

discharge mode, an internal switch creates a path for

discharging the output capacitors' residual charge toGND.

The RT8249D is latched once OVP is triggered and can

only be released by either toggling ENx or cycling VIN.

There is a 1μs delay built into the over-voltage protection

circuit to prevent false transition.

Standby Mode

When VINrises POR threshold and ENx < 0.4V, RT8249D

operate in standby mode, CH1 and CH2 is OFF state. For

RT8249D, LDO5 is OFF and LDO3 is ON state and

approximately consumes 17μA of input current.

Note that latching LGATEx high will cause the output

voltage to dip slightly negative due to previously stored

energy in the LC tank circuit. For loads that cannot tolerate

a negative voltage, place a power Schottky diode across

the output to act as a reverse polarity clamp.

Power-Up Sequencing and On/Off Controls (ENx)

EN1 and EN2 control the power-up sequencing of the two

channels of the Buck converter. The 0.4V falling edge

threshold on ENx can be used to detect a specific analog

voltage level and to shutdown the device. Once in

shutdown, the 1.6V rising edge threshold activates,

providing sufficient hysteresis for most applications.

If the over-voltage condition is caused by a shorted in

high-side switch, turning the low-side MOSFET on 100%

will create an electrical shorted circuit between the battery

and GND to blow the fuse and disconnecting the battery

from the output.

Output Under-Voltage Protection (UVP)

The output voltage can be continuously monitored for under-

voltage condition. If the output is less than 52% (typ.) of

its set voltage threshold, the under-voltage protection will

be triggered and then both UGATEx and LGATEx gate

drivers will be forced low. The UVP is ignored for at least

1.3ms (typ.) after a start-up or a rising edge on ENx. Toggle

ENx or cycle VIN to reset the UVP fault latch and restart

the controller.

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RT8249D

Table 1. Operation Mode Truth Table

Condition

Mode

Comment

LDO Over

Current Limit

Transitions to discharge mode after VIN POR. LDO5

and LDO3 remain active.

LDOx < UVLO threshold

Run

ENx = high, V_OUT1or V_OUT2are enabled Normal Operation.

Over-Voltage

Protection

LGATEx is forced high. LDO3 and LDO5 are active.

Exit by VIN POR or by toggling ENx.

Either output >113% of the nominal level.

Either output < 52% of the nominal level Both UGATEx and LGATEx are forced low and enter

after 1.3ms time-out expires and output is discharge mode. LDO3 and LDO5 are active. Exit by

Under-Voltage

Protection

enabled

VIN POR or by toggling ENx.

During discharge mode, there is one path to

Discharge

Standby

Either output is still high in standby mode discharge the output capacitors’ residual charge to

GND via an internal switch.

VIN > POR ENx < 0.4V

LDO3 is active

Thermal

Shutdown

T_J> 150C

All circuitries are off. Exit by VIN POR.

Table 2. Enabling/PGOOD State

EN1

OFF

ON

EN2

OFF

ON

LDO5

OFF

ON

LDO3

ON

CH1 (5VOUT) CH2 (3.3VOUT)

PGOOD

Low

OFF

ON

OFF

ON

Low

OFF

ON

OFF

ON

Low

ON

High

VIN POR threshold

VIN

LDO3

EN1

EN threshold

VREG5 UVLO threshold

Start-Up Time

LDO5

Soft-Start Time

5V VOUT

EN2

EN threshold

Start-Up Time

3.3V VOUT

PGOOD

Soft-Start Time

Delay

Figure 4. RT8249D Timing

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DS8249D-02 January 2020

RT8249D

Output Voltage Setting (FBx)

Output Capacitor Selection

Connect a resistive voltage divider at the FBx pin between

V_OUTxand GND to adjust the output voltage from 2V to

5.5V for CH1 and 2V to 4V for CH2, as shown in Figure 5.

The recommended R2 is between 100kΩ to 200kΩ, V_OUT

(vally) and solve for R1 using the equation below :

The capacitor value and ESR determine the amount of

output voltage ripple and load transient response. Thus,

the capacitor value must be greater than the largest value

calculated from the equations below :

(I_LOAD)²L(t_ON+ t_OFF(MIN)

)

V_SAG





R1 









)

2C_OUT V t_ON V_OUTx(t_ON+ t_OFF(MIN)

IN





V

 V

 1 +

OUT(Valley)

FBx







R2



(I_LOAD)²L





V_SOAR



where V_FBxis 2V (typ.).

2C_OUT V_OUTx

V

IN









1

V_PP LIRI_LOAD(MAX) ESR +



8C_OUTf



UGATEx

where V_SAGand V_SOARare the allowable amount of

undershoot and overshoot voltage during load transient,

V_p-pis the output ripple voltage, and t_OFF(MIN)is the

minimum off-time.

VOUTx

PHASEx

LGATEx

R1

R2

FBx

Thermal Considerations

GND

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

Figure 5. Setting V_OUTxwith a resistive voltage divider

Output Inductor Selection

The switching frequency (on-time) and operating point

(% ripple or LIR) determine the inductor value as shown

below :

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

t

(V  V

)

ON

IN

OUTx

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction to ambient

thermal resistance.

L 

LIRI

LOAD(MAX)

where LIR is the ratio of the peak-to-peak ripple current to

the average inductor current.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

WQFN-20L 3x3 package, the thermal resistance, θ_JA, is

30°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at T_A= 25°C can

be calculated by the following formula :

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor

current, I_PEAK

:

I_PEAK= I_LOAD(MAX)+ [ (LIR / 2) x I_LOAD(MAX)

]

P_D(MAX)= (125°C − 25°C) / (30°C/W) = 3.33W for

WQFN-20L 3x3 package

The calculation above shall serve as a general reference.

To further improve transient response, the output

inductance can be further reduced. Of course, besides

the inductor, the output capacitor should also be

considered when improving transient response.

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curve in Figure 6 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

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RT8249D

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

 Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high-voltage switching node.

Four-Layer PCB

 Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.

 All sensitive analog traces and components such as

FBx, PGOOD, and should be placed away from high

voltage switching nodes such as PHASEx, LGATEx,

UGATEx, or BOOTx nodes to avoid coupling. Use

internal layer(s) as ground plane(s) and shield the

feedback trace from power traces and components.

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 6.Derating Curve of Maximum PowerDissipation

 Place ground terminal of VIN capacitor(s), V_OUTx

capacitor(s), and Source of low-side MOSFETs as close

to each other as possible. The PCB trace of PHASEx

node, which connects to Source of high-side MOSFET,

Drain of low-side MOSFET and high voltage side of the

inductor, should be as short and wide as possible.

Layout Considerations

Layout is very important in high frequency switching

converter design. Improper PCB layout can radiate

excessive noise and contribute to the converter’s

instability. Certain points must be considered before

starting a layout with the RT8249D.

 Place the filter capacitor close to the IC, within 12mm

(0.5 inch) if possible.

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DS8249D-02 January 2020

RT8249D

Outline Dimension

1

2

1

2

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

2.900

1.650

2.900

1.650

0.800

0.050

0.250

3.100

1.750

3.100

1.750

0.028

0.000

0.007

0.006

0.114

0.065

0.114

0.065

0.031

0.002

0.010

0.122

0.069

0.122

0.069

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify

that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek

product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;

nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of Richtek or its subsidiaries.

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21


型号：	RT8249D
厂家：	RICHTEK TECHNOLOGY CORPORATION
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文件：	总21页 (文件大小：305K)
中文：	中文翻译
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