RT9210PC [RICHTEK]
Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination; 5V双路同步降压DC-DC PWM控制器，用于DDR内存VDDQ和VTT终端
| 型号： | RT9210PC |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination |
| 文件： | 总17页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT9210
Dual 5V Synchronous Buck DC-DC PWM Controller
for DDR Memory VDDQ and VTT Termination
General Description
Features
z Operating with Single 5V Supply Voltage
z High Power VDDQ, VTT and VREF for DDR Memory
z VTT Tracks (VDDQ/2) to ±30mV
The RT9210 is a dual high power, high efficiency
synchronous buck DC-DC controller optimized for high
performance double data rate (DDR) memory applications.
It is designed to convert voltage supplies ranging from
4.5V to 5.5V into efficiently 2.5VDDQ for powering DDR
memory, VTT for signal termination and a buffered amplifier
for VREF reference. VTT tracks (VDDQ/2) to ±30mV, and
VTT accurately tracks VREF. The RT9210 integrates all of
the control, output adjustment, monitoring and protection
functions into a single package.
z VTT Regulator Internally Compensated
z Support “S3” Sleep Mode
z Drives All Low Cost N-MOSFETs
z Voltage Mode PWM Control
z 300kHz Fixed Frequency Oscillator
z Fast Transient Response :
Full 0% to 100% Duty Ratio
z Internal Soft-Start
The VTT supply can be turned off independently of VDDQ
during S3 sleep mode, the VTT output is maintained by a
low power window regulator when V2_SD pin being
triggered high.
z Adaptive Non-Overlapping Gate Driver
z Over-Current Fault Monitor on VCC, No Current
Sense Resistor Required
z RoHS Compliant and 100% Lead (Pb)-Free
The RT9210 provides simple, single feedback loop, voltage
mode control with fast transient response for VDDQ
regulator. The VTT regulator features internal compensation
that eases the circuitry design. It includes two phase-
locked 300kHz sawtooth-wave oscillators which are placed
90° to minimize interference between the two PWM
regulators.
Applications
z DDR Memory Termination Supply
z SSTL_2 and SSTL_3 Interfaces
z Graph Card, Motherboard,Desktop Servers
z High Power TrackingDC-DC Regulators
Pin Configurations
The RT9210 protects against over-current conditions by
inhibiting PWM operation. It also monitors the current in
the VDDQ regulator by using the RDS(ON) of the upper
MOSFET which eliminates the need for a current sensing
resistor.
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
PGND1
LGATE1
UGATE1
BOOT1
PHASE1
VREF
2
3
4
5
6
PVCC1
OCSET/SD
V2_SD
PGOOD
NC
SENSE2
NC
VCC
FB1
Ordering Information
RT9210
COMP1
SENSE1
VREF_IN
GNDA
7
8
9
Package Type
C : TSSOP-24
S : SOP-24
10
11
12
NC
BOOT2
UGATE2
LGATE2
PGND2
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
TSSOP-24 & SOP-24
cial Standard)
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
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1
Preliminary
RT9210
Typical AppIication Circuit
V
CC
5V
V
IN
2.5V/3.3V/5V
V
IN (>V
)
DDQ
2.5V/3.3V/5V
C10
470uF
C2
1uF
R6
10k
D1
1N4148
R1
3.48k
C1
1nF
RT9210
C9
0.1uF
PHKD6N02LT
Q5
RESET
15
19
2
VCC
Q1
PGOOD
C12 to C15
150uF (x 4)
1uH
L1
V
DDQ
21
7
OCSET/SD
SENSE1
BOOT1
1.8V
1
UGATE1
Q2
20
8
3
VTT_SD
V2_SD
VREF_IN
VREF
PHASE1
PVCC1
LGATE1
PGND1
22
23
VREF_IN
C3 100pF
4
V
24
C4
CC
5V
D2
1N4148
6
COMP1
0.1uF
11
12
10
14
13
17
C5
BOOT2
UGATE2
PHASE2
LGATE2
5.6nF
C6
C11
0.1uF
PHKD6N02LT
VREF_OUT
100pF
R4
6.34k
Q3
5
C16 to C17
150uF (x 2)
1uH
FB1
L2
C7
V
TT
PGND2
0.1uF
0.9V
SENSE2
R2
1k
C8
Q4
GNDA
15nF
9
R3
1.25k
R5
100
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DS9210-05 March 2007
Preliminary
RT9210
Functional Pin Description
UGATE1 (Pin 1)
VREF_IN (Pin 8)
VDDQ upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
This pin is used as an option to overdrive the internal
resistor divider network that sets the voltage for both VREF
and the reference voltage for the VTT supply. A 100pF
capacitor between VREF_INand ground is recommended
for proper operation.
BOOT1 (Pin 2)
GNDA (Pin 9)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT1 pin and the
PHASE1 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Ties the pin directly to ground
plane with the lowest impedance.
PHASE1 (Pin 3)
BOOT2 (Pin 11)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. PHASE1 is used to
monitor the voltage drop across the upper MOSFET of
the VDDQ regulator for over-current protection.
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT2 pin and the
PHASE2 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
VREF (Pin 4)
UGATE2 (Pin 12)
Buffered internal reference voltage of VDDQ / 2. This output
should be used to provide the reference voltage for the
Northbridge chipset andDDR memory.
VTT upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
FB1 (Pin 5)
PGND2 (Pin 13)
VDDQ feedback voltage. This pin is the inverting input of
the error amplifier. FB1 senses the VDDQ through an
external resistor divider network.
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
COMP1 (Pin 6)
LGATE2 (Pin 14)
VDDQ external compensation. This pin internally connects
to the output of the error amplifier and input of the PWM
comparator. Use a RC + C network at this pin to
compensate the feedback loop to provide optimum
transient response.
VTT lower gate driver output. Connect to gate of the low-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
SENSE1 (Pin 7)
VCC (Pin 15)
This pin is connected directly to the regulated output of
VDDQ supply. This pin is also used as an input to create
the voltage at VREF.
Connect this pin to a well-decoupled 5V bias supply. It is
also the positive supply for the lower gate driver, LGATE2.
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3
Preliminary
RT9210
NC (Pin 10 , 16 , 18)
LGATE1 (Pin 23)
No internal connection.
VDDQ lower gate drive output. Connect to gate of the low-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
SENSE2 (Pin 17)
This pin is connected directly to the regulated output of
VTT supply. This pin is also used as the feedback pin of
the VTT regulator and as the regulation point for the window
regulator that is enable in V2_SD mode.
PGND1 (Pin 24)
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
PGOOD (Pin 19)
PGOODis an open-drain output used to indicate that both
the VDDQ and VTT regulators are within normal operating
voltage ranges.
V2_SD (Pin 20)
A TTL compatible high level at this pin puts the VTT
controller into“sleep”mode. In sleep mode, both UGATE2
and LGATE2 are driven low, effectively floating the VTT
supply. While the VTT supply “floats”, it is held to about
50% of VDDQ via a low current window regulator which
drivers VTT via the SENSE2 pin. The window regulator
can overcome up to at least 10mA of leakage on VTT.
While V2_SD is high, PGOOD is low.
OCSET/SD (Pin 21)
Connect a resistor (ROCSET) from this pin to the drain of
the upper MOSFET of the VDDQ regulator sets the over-
current trip point. ROCSET, an internal 40μAcurrent source
, and the upper MOSFET on-resistance, RDS(ON), set the
VDDQ converter over-current trip point (IOCSET) according
to the following equation:
40uA × ROCSET
IOCSET =
RDS(ON) of the upper MOSFET
An over-current trip cycles the soft-start function. Pulling
the pin to ground resets the device and all external
MOSFETs are turned off allowing the two output voltage
power rails to float.
PVCC1 (Pin 22)
Connect this pin to a well-decoupled 5V supply. It is also
the positive supply for the lower gate driver, LGATE1.
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DS9210-05 March 2007
Preliminary
RT9210
Function Block Diagram
VCC
Thermal
SHDN
+
Bias
OC
137.5%
62.5%
0.8V
Ref.
Power
On
Reset
OCSET/SD
POR
OV
UV
40uA
-
OVP
&
UVP
0.8V
FB1
Soft-
Start
1
Power
Good
BOOT1
PGOOD
+
EA
+
PWM1
+
-
-
UGATE1
COMP1
VREF
OC
Control
Logic
PHASE1
PVCC1
LGATE1
PGND1
OV
UV
Thermal
SHDN
-
+
200k
200k
300kHz
Oscillator
VREE_IN
SENSE1
PGND2
PWM2
-
LGATE2
+
+
EA
-
Control
Logic
Zf
OC
OV
UV
SENSE2
V2_SD
FB2
VCC
90 deg
shift
Window
Regulator
Zc
Thermal
UGATE2
BOOT2
SHDN
GNDA
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5
Preliminary
RT9210
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC -------------------------------------------------------------------------------------------------- 7V
7V
z BOOT, VBOOT - VPHASE------------------------------------------------------------------------------------------------
z
Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V
z Package Thermal Resistance
TSSOP-24, θJA --------------------------------------------------------------------------------------------------------- 100°C/W
SOP-24, θJA ------------------------------------------------------------------------------------------------------------ 90°C/W
z Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------- 260°C
z Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode)-------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
z Supply Voltage, VCC -------------------------------------------------------------------------------------------------- 5V 5%
z Ambient Temperature Range---------------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range---------------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Supply Current
Symbol
Test Conditions
Min
Typ Max
Units
V
CC
OCSET/SD = V , UGATE1 & 2
LGATE1 & 2 Open
CC
Nominal Supply Current
--
--
5
3
--
--
mA
mA
I
I
CC
Shutdown Supply
Power-On Reset
POR Threshold
Hysteresis
OCSET/SD = 0V
CCSD
3.7
--
4.1
0.5
4.5
--
V
V
V
V
V
V
= 4.5V, V Rising
CCRTH
OCSET/SD
CC
= 4.5V
CCHYS
OCSET/SD
Reference (for V1 and V2 Error Amp)
Reference Voltage
%
Sense1
Sense1 = 2.5V
49.0 50.0 51.0
-- --
0.784 0.8 0.816
V
REF2
(V2 Error Amp Reference)
V1 Error Amp Reference Voltage
Tolerance
2
%
V
ΔV
1EAR
Error Amp Reference
Oscillator
V
REF
V
V
= 5V
= 5V
CC
Free Running Frequency
Ramp Amplitude
Error Amplifier
DC Gain
275
--
300
1.9
325
--
kHz
f
OSC
CC
ΔV
V
P-P
OSC
--
--
--
90
10
6
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
To be continued
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DS9210-05 March 2007
Preliminary
RT9210
Parameter
Window Regulator
Symbol
Test Conditions
Min
Typ
Max Units
Load Current
--
--
--
--
mA
%
I
±10
± 7
LOAD
V2_SD = V
±10mA load on V2
,
CC
Output Voltage Error
ΔV
OUT
PWM Controller Gate Drivers
Upper Gate Source (UGATE1 and 2)
BOOT = 10V
--
7
--
R
UGATE
Ω
BOOT − V
= 1V
UGATE
Upper Gate Sink (UGATE1 and 2)
Lower Gate Source (LGATE1 and 2)
Lower Gate Sink (LGATE1 and 2)
Upper Gate Rising Time (UGATE1 and 2)
Upper Gate Falling Time (UGATE1 and 2)
Lower Gate Rising Time (LGATE1 and 2)
Lower Gate Falling Time (LGATE1 and 2)
Dead Time
--
--
--
--
--
--
--
--
5
4
--
--
R
R
R
V
V
V
= 1V
Ω
Ω
UGATE
UGATE
− V
= 1V
LGATE
CC
LGATE
2
--
= 1V
Ω
LGATE
LGATE
70
50
50
32
--
--
ns
ns
ns
ns
ns
T
T
T
T
T
C
C
C
C
= 3.3nF
= 3.3nF
= 3.3nF
= 3.3nF
R_UGATE
F_UGATE
R_LGATE
F_LGATE
DT
Load
Load
Load
Load
--
--
--
100
Protection
FB1 Over-Voltage Trip
FB1 Rising
FB1 Falling
125
--
137.5
62.5
40
--
%
%
ΔFB
ΔFB
I
1OVT
FB1 Under-Voltage Trip
75
1UVT
OCSET/SD Current Source
OCP Blocking Time
34
--
46
V
= 4.5V
μA
ns
OCSET
OCSET/ SD
320
--
540
0.2
Logic-Low Voltage
OCSET/SD
Shutdown
Enable
--
V
IL
V
Logic-High Voltage
2.0
--
--
4
--
--
V
IH
Soft-Start Interval
ms
T
SS
Power Good
Upper Threshold
Lower Threshold
FB1 & Sense2 Rising
FB1 & Sense2 Rising
110
80
115
85
120
90
%
%
V
V
PGOOD+
PGOOD-
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
DS9210-05 March 2007
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7
Preliminary
RT9210
Typical Operating Characteristics
POR ( Start Up)
OCSET/SD ( Start Up)
Vocset/sd
VCC
5V/Div
1V/Div
VDDQ
VTT
VDDQ
VTT
1V/Div
Time (5ms/Div)
Time (5ms/Div)
Power Good Rising
Power Good Falling
5V/Div
5V/Div
5V/Div
5V/Div
VCC
VCC
PGOOD
PGOOD
2V/Div
2V/Div
VDDQ
VDDQ
Time (5ms/Div)
Time (5ms/Div)
Power Off
Power On
IDDQ = 10A, ITT = 5A
IDDQ = ITT = 5A
1V/Div
VCC
VDDQ
VTT
1V/Div
VCC
2V/Div
VDDQ
500mV/Div
1V/Div
VTT
UGATE1
5V/Div
UGATE
10V/Div
Time (5ms/Div)
Time (200μs/Div)
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8
Preliminary
RT9210
UGATE Phase Shift
LGATE Phase Shift
5V/Div
5V/Div
5V/Div
LGATE1
UGATE1
UGATE2
5V/Div
LGATE2
Time (1μs/Div)
Time (1μs/Div)
VTT Sleep Mode
VTT Return from Sleep Mode
5V/Div
5V/Div
Vvs_sd
Vvs_sd
2V/Div
2V/Div
VDDQ
VTT
VDDQ
VTT
20mV/Div
20mV/Div
5V/Div
5V/Div
UGATE2
UGATE2
Time (5μs/Div)
Time (5μs/Div)
VTT Short
VDDQ Short
500mV/Div
500mV/Div
1V/Div
VTT
VDDQ
500mV/Div
VFB1
VFB1
10V/Div
10V/Div
UGATE1
UGATE2
Time (10ms/Div)
Time (10ms/Div)
DS9210-05 March 2007
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9
Preliminary
RT9210
VDDQ Transient
VTT Transient
50mV/Div
VDDQ
50mV/Div
VDDQ
50mV/Div
VTT
50mV/Div
5A/Div
VTT
5A/Div
IDDQ
ITT
VIN = 5V, VDDQ = 2.5V, COUT = 2000μF
Time (250μs/Div)
VIN = 5V, VTT = 1.25V, COUT = 2000μF
Time (250μs/Div)
IOCSET vs. Temperature
VTT Sink & Source
55
100mV/Div
VDDQ
50
45
40
35
30
100mV/Div
VTT
COUT = 2000μF
VIN = 5V,
VDDQ = 2.5V,
VTT = 1.25V
ITT
5A/Div
-40
-10
20
50
80
110
140
Time (100μs/Div)
Temperature
(°C)
Reference Voltage vs. Temperature
Frequency vs. Temperature
0.802
0.801
0.8
350
300
250
200
150
100
50
0.799
0.798
0.797
0.796
0.795
0.794
0.793
0.792
0.791
-40
-10
20
50
80
110
140
-40
-10
20
50
80
110
140
Temperature
Temperature
(°C)
(°C)
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DS9210-05 March 2007
Preliminary
RT9210
POR vs. Temperature
4.4
4.2
4
Rising
Falling
3.8
3.6
3.4
3.2
3
-40
-10
20
50
80
110
140
Temperature
(°C)
DS9210-05 March 2007
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11
Preliminary
RT9210
Applications Information
Inductor
The response time is the time required to slew the inductor
current from an initial current value to the transient current
level. The inductor limit input current slew rate during
the load transient. Minimizing the transient response time
can minimize the output capacitance required. The
response time is different for application of load and removal
of load to a transient. The following equations give the
approximate response time for application and removal of
a transient load :
The inductor is required to supply constant current to the
output load. The inductor is selected to meet the output
voltage ripple requirements and minimize the converter's
response time to the load transient.
A larger value of inductance reduces ripple current and
voltage. However, the larger value of inductance has a larger
physical size, lower output capacitor and slower transient
response time.
L× ΔIOUT
L × ΔIOUT
VIN − VOUT
Agood rule for determining the inductance is to allow the
peak-to-peak ripple current in the inductor to be
approximately 30% of the maximum output current. The
inductance value can be calculated by the following
equation :
TFall =
TRise =
VOUT
Where
TRise is the response time to the application of load,
TFall is the response time to the removal of load,
(VIN − VOUT)× VOUT
L =
VIN ×FS × ΔIOUT
I
OUT is the transient load current step.
Δ
Where
Input Capacitor
VIN is the input voltage,
The input capacitor is required to supply theAC current to
the Buck converter while maintaining theDC input voltage.
The capacitor should be chosen to provide acceptable ripple
on the input supply lines. Use a mix of input bypass
capacitors to control the voltage overshoot across the
MOSFETs. Use small ceramic capacitors for high
frequency decoupling and bulk capacitors to supply the
current. Place the small ceramic capacitors close to the
MOSFETs and between the drain of Q1/Q3 and the source
of Q2/Q4.
VOUT is the output voltage,
FS is the switching frequency,
ΔIOUT is the peak-to-peak inductor ripple current.
The inductance value determines the converter's ripple
current and the ripple current. The ripple voltage is
calculated by the following equation :
(VIN − VOUT)× VOUT
ΔI =
VIN ×Fs×L
Increasing the value of inductance reduces the ripple
current and voltage. However, the large inductance value
raise the converter's response time to a load transient.
The key specifications for input capacitor are the voltage
rating and the RMS current rating. For reliable operation,
select the bulk capacitor with voltage and current ratings
above the maximum input voltage and largest RMS current.
The capacitor voltage rating should be at least 1.25 times
greater than the maximum input voltage and voltage rating
of 1.5 times is a conservative guideline. The RMS current
rating for the input capacitor of a buck regulator should be
greater than approximately 0.5 the DC load current.
One of the parameters limiting the converter's response
to a load transient is the time required to change the
inductor current. Given a sufficiently fast control loop
design, the RT9210 will provide 0% to 100% duty cycle in
response to a load transient.
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DS9210-05 March 2007
Preliminary
RT9210
Output Capacitor
For the Buck converter the average inductor current is
equal to the output load current. The conduction loss is
defined as :
The output capacitor is required to maintain theDC output
voltage and supply the load transient current. The capacitor
must be selected and placed carefully to yield optimal
results and should be chosen to provide acceptable ripple
on the output voltage.
PCD (high side switch) = IO2 * RDS(ON) * D
PCD (low side switch) = IO2 * RDS(ON) * (1-D)
The switching loss is more difficult to calculate. The reason
is the effect of the parasitic components and switching
times during the switching procedures such as turn-on /
turn-off delays and rise and fall times. With a linear
approximation, the switching loss can be expressed as :
The key specification for output capacitor is its ESR. Low
ESR capacitors are preferred to keep the output voltage
ripple low. The bulk capacitor's ESR will determine the
output ripple voltage and the initial voltage drop after a
high slew-rate transient. For transient response, a
combination of low value, high frequency and bulk
capacitors placed close to the load will be required. High
frequency decoupling capacitors should be placed as close
to the power pins of the load as possible. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor.
PSW = 0.5 * VDS(OFF) * IO * (TRise + TFall) * F
Where
VDS(OFF) is drain to source voltage at off time,
T
Rise
is rise time,
TFall is fall time,
F is switching frequency.
The capacitor value must be high enough to absorb the
inductor's ripple current. The output ripple is calculated
The total power dissipation in the switching MOSFET can
be calculate as :
as :
ΔVOUT = ΔIOUT ×ESR
PHigh Side Switch
=
Another concern is high ESR induced output voltage ripple
may trigger UV or OV protections will cause IC shutdown.
IO2 * RDS(ON) D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F
PLow Side Switch = IO2 * RDS(ON) * (1-D)
*
MOSFET
In RT9210, the VDDQ only sources current but the VTT
can sink and source current. When sourcing current, the
upper MOSFET supports most of the switching losses.
On the contrary, the lower MOSFET supports most of the
switching losses when VTT is sinking.
The MOSFET should be selected to meet power transfer
requirements is based on maximum drain-source voltage
(VDS), gate-source drive voltage (VGS), maximum output
current, minimum on-resistance (RDS(ON)) and thermal
management.
Losses while Sourcing Current
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The losses can be divided into
conduction and switching losses.
PHigh Side Switch = IO2 * RDS(ON)* D + 0.5 * VDS(OFF)* IO* (TRise
+ TFall)* F
PLow Side Switch = IO2 * RDS(ON) * (1-D)
Conduction losses are related to the on resistance of
MOSFET, and increase with the load current. Switching
losses occur on each ON/OFF transition. The conduction
losses are the largest component of power dissipation for
both the upper and the lower MOSFETs.
Losses while Sinking Current
PHigh Side = IO2 * RDS(ON) * D
PLow Side = IO2 * RDS(ON)* (1-D) + 0.5 * VDS(OFF)* IO* (TRise
TFall)* F
+
For input voltages of 3.3V and 5V, conduction losses often
dominate switching losses. Therefore, lowering the RDS(ON)
of the MOSFETs always improves efficiency.
DS9210-05 March 2007
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13
Preliminary
RT9210
Feedback Compensation
The output LC filter introduces a double pole,−40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The Resonant
frequency of the LC filter expressed as follows :
The RT9210 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to
achieve fast transient response and accurate output
regulation, a adequate compensator design is necessary.
The goal of the compensation network is to provide
adequate phase margin (greater than 45 degrees) and the
highest 0dB crossing frequency. And to manipulate loop
frequency response that its gain crosses over 0dB at a
slope of -20dB/dec.
1
FP(LC) =
2π × LO ×CO
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
Vin
1
FZ(ESR) =
2π × CO ×ESR
Lo
Vout
PWM
Compensation Frequency Equations
Co
The compensation network consists of the error amplifier
and the impedance networks ZC and ZF as Figure 2 shows.
ESR
Zf
Zf
-
C1
Zc
Zc
+
-
PWM
Comparator
+
R1
VREF
VOUT
R2
C2
Compensator
VRAMP
FB1
-
EA
+
COMP1
Rf
Figure 1
RT9210
VREF
Modulator Frequency Equations
Figure 2
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This transfer function is dominated
by a DC gain and the output filter (LO and CO), with a
double pole
FP1 = 0
FZ1
1
=
2π ×R2 × C2
1
FP1 =
frequency at FLC and a zero at FESR. The DC gain of the
modulator is the input voltage (VIN) divided by the peak-
2π ×R2(C1// C2)
Figure 3 shows theDC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop.
to-peak oscillator voltage VRAMP
.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
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14
DS9210-05 March 2007
Preliminary
RT9210
High crossover frequency is desirable for fast transient
response, but often jeopardize the system stability. In
order to cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency. In the experience,
place the zero at 75% LC filter resonant
frequency.Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching frequency.
3. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces with
heavy copper to keep the parasitic resistance low. Place
the output capacitors as close to the load as possible.
4. The inductor, output capacitor and the MOSFET should
be as close to each other as possible. This helps to reduce
the EMI radiated.
The second pole be place at half the switching frequency.
5. Place the switching MOSFET as close to the input
capacitors as possible. The MOSFET gate traces to the
IC must be as short, straight, and wide as possible. Use
copper filled polygons on the top and bottom layers for
the PHASE nodes.
80
Loop Gain
60
40
Compensation
Gain
20
6. Place the CBOOT as close as possible to the BOOT and
PHASE pins.
0
Modulator
Gain
7. The feedback part of the system should be kept away
from the inductor and other noise sources, and be placed
close to the IC. Connect to the GND pin with a single
trace, and connect this local GND trace to the output
capacitorGND.
-20
-40
-60
100k
1M
10
100
1k
10k
Frequency (Hz)
Figure 3
8. Minimize the leakage current paths on the OCSET/SD
pin and locate the resistor as close to the OCSET/SD pin
as possible because the internal current source isonly
40μA.
Layout Consideration
The layout is very important when designing high frequency
switching converters. Layout will affect noise pickup and
can cause a good design to perform with less than
expected results.
9. In multilayer PCB, use one layer as ground plane and
have a control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current path to a separate loop that does not interfere
with the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
1. Even though double-sided PCB is usually sufficient for
a good layout, four-layer PCB is the optimum approach to
reducing the noise. Use the two internal layers as the
power andGNDplanes, the top layer for power connections
with wide, copper filled areas, and the bottom layer for the
noise sensitive traces.
2. There are two sets of critical components in a DC-DC
converter. The switching components are the most critical
because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. The
others are the small signal components that connect to
sensitive nodes or supply critical bypass current and signal
coupling. Make all critical component ground connections
with vias toGNDplane.
DS9210-05 March 2007
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15
Preliminary
RT9210
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
0.047
0.006
0.041
0.012
0.311
A
A1
A2
b
0.850
0.050
0.800
0.190
7.700
1.200
0.150
1.050
0.300
7.900
0.033
0.002
0.031
0.007
0.303
D
e
0.650
0.026
E
6.300
4.300
0.450
6.500
4.500
0.750
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
24-Lead TSSOP Plastic Package
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16
DS9210-05 March 2007
Preliminary
RT9210
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
15.189
7.391
2.362
0.330
1.194
0.229
0.102
10.008
0.381
Max
15.596
7.595
2.642
0.508
1.346
0.330
0.305
10.643
1.270
Min
Max
A
B
C
D
F
H
I
0.598
0.291
0.093
0.013
0.047
0.009
0.004
0.394
0.015
0.614
0.299
0.104
0.020
0.053
0.013
0.012
0.419
0.050
J
M
24-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9210-05 March 2007
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17
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