RT9610C_技术文档

®

RT9610C

High Voltage Synchronous Rectified Buck MOSFET Driver

for Notebook Computer

General Description

Features

^Drives Two N-MOSFETs

The RT9610C is a high frequency, dual MOSFET driver

specifically designed to drive two power N-MOSFETS in

a synchronous-rectified buck converter topology. It is

especially suited for mobile computing applications that

require high efficiency and excellent thermal performance.

This driver, combined with Richtek's series of multi-phase

Buck PWM controllers, provides a complete core voltage

regulator solution for advanced microprocessors.

^Adaptive Shoot-Through Protection

^0.5Ω On-Resistance, 4A Sink Current Capability

^Supports High Switching Frequency

^Tri-State PWM Input for Power Stage Shutdown

^Output Disable Function

^Integrated Boost Switch

^Low Bias Supply Current

^VCC POR Feature Integrated

The drivers are capable of driving a 3nF load with fast

rising/falling time and fast propagation delay. This device

implements bootstrapping on the upper gates with only a

single external capacitor. This reduces implementation

complexity and allows the use of higher performance, cost

effective,N-MOSFETs.Adaptive shoot through protection

is integrated to prevent both MOSFETs from conducting

simultaneously.

Applications

 Core Voltage Supplies for Intel^®/ AMD^®Mobile

Microprocessors

 High Frequency Low ProfileDC/DC Converters

 High Current Low Output VoltageDC/DC Converters

 High Input VoltageDC/DC Converters

The RT9610C is available in WDFN-8L 2x2 Package.

Ordering Information

RT9610C

Package Type

QW : WDFN-8L 2x2 (W-Type)

Marking Information

2Q : Product Code

Lead Plating System

G : Green (Halogen Free and Pb Free)

W : Date Code

2QW

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Simplified Application Circuit

V

IN

RT9610C

VCC

V

UGATE

BOOT

CC

PHASE

V

CORE

Enable

PWM

EN

PWM

LGATE

GND

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DS9610C-01 April 2016

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RT9610C

Pin Configurations

(TOP VIEW)

1

2

3

4

8

7

6

5

EN

PHASE

UGATE

BOOT

VCC

LGATE

GND

PWM

9

WDFN-8L 2x2

Functional Pin Description

Pin No.

Pin Name

Pin Function

Enable Pin. When low, both UGATE and LGATE are driven low and the normal

operation is disabled.

1

EN

Switch Node. Connect this pin to the source of the upper MOSFET and the drain

of the lower MOSFET. This pin provides a return path for the upper gate driver.

2

3

PHASE

UGATE

Upper Gate Drive Output. Connect to the gate of high side power N-MOSFET.

Floating Bootstrap Supply Pin for Upper Gate Drive. Connect the bootstrap

capacitor between this pin and the PHASE pin. The bootstrap capacitor

provides the charge to turn on the upper MOSFET.

4

BOOT

Control Input for Driver. The PWM signal can enter three distinct states during

operation. Connect this pin to the PWM output of the controller.

5

PWM

GND

6,

Ground. The exposed pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

9 (Exposed Pad)

Lower Gate Drive Output. Connect to the gate of the low side power

N-MOSFET.

7

8

LGATE

VCC

Input Supply Pin. Connect this pin to a 5V bias supply. Place a high quality

bypass capacitor from this pin to GND.

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DS9610C-01 April 2016

RT9610C

Functional Block Diagram

VCC

BOOT

POR

UGATE

PHASE

Control

Logic

Shoot-Through

Protection

EN

VCC

LGATE

GND

R

Tri-State

PWM

Detect

R

Operation

POR (Power On Reset)

Control Logic

POR block detects the voltage at the VCC pin. When the

VCC pin voltage is higher than POR rising threshold, the

POR pin output voltage (POR output) is high. POR output

is low when VCC is not higher than POR rising threshold.

When the POR pin voltage is high, UGATE and LGATE

can be controlled by PWM input voltage. If the POR pin

voltage is low, both UGATE and LGATE will be pulled to

low.

Control logic block detects whether high side MOSFET

is turned off by monitoring (UGATE - PHASE) voltages

below 1.1V or PHASE voltage below 2V. To prevent the

overlap of the gate drives during the UGATE pulls low and

the LGATE pulls high, low side MOSFET can be turned

on only after high side MOSFET is effectively turned off.

Shoot-Through Protection

Shoot-through protection block implements the dead-time

when both high side and low side MOSFETs are turned

off. With shoot-through protection block, high side and

low side MOSFETs are never turned on simultaneously.

Thus, shoot-through between high side and low side

MOSFETs is prevented.

Tri-State Detect

When both POR output and EN pin voltages are high,

UGATE and LGATE can be controlled by PWM input. There

are three PWM input modes which are high, low, and

shutdown state. If PWM input is within the shutdown

window, both UGATE and LGATE outputs are low. When

PWM input is higher than its rising threshold, UGATE is

high and LGATE is low. When PWM input is lower than

its falling threshold, UGATE is low and LGATE is high.

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RT9610C

Absolute Maximum Ratings (Note 1)

 Supply Voltage, VCC ------------------------------------------------------------------------------------------------------- −0.3V to 6V

 BOOT to PHASE ------------------------------------------------------------------------------------------------------------ −0.3V to 6V

 PHASE to GND

DC------------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V

< 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V

 UGATE to PHASE

DC------------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGATE toGND

DC------------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 PWM, EN to GND ---------------------------------------------------------------------------------------------------------- −0.3V to 6V

 PowerDissipation, P_D@ T_A= 25°C

WDFN-8L 2x2 ---------------------------------------------------------------------------------------------------------------- 2.19W

 Package Thermal Resistance (Note 2)

WDFN-8L 2x2, θ_JA----------------------------------------------------------------------------------------------------------- 45.5°C/W

WDFN-8L 2x2, θ_JC---------------------------------------------------------------------------------------------------------- 11.5°C/W

 Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------------- 260°C

 Storage Temperature Range ---------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)------------------------------------------------------------------------------------------------ 2kV

Recommended Operating Conditions (Note 4)

 Input Voltage, VIN ----------------------------------------------------------------------------------------------------------- 4.5V to 26V

 Control Voltage, VCC------------------------------------------------------------------------------------------------------- 4.5V to 5.5V

 Ambient Temperature Range---------------------------------------------------------------------------------------------- −40°C to 85°C

 Junction Temperature Range---------------------------------------------------------------------------------------------- −40°C to 125°C

Electrical Characteristics

(V_CC= 5V, T_A= 25°C, unless otherwise specified)

Parameter

VCC Supply Current

Quiescent Current

Shutdown Current

Symbol

Test Conditions

Min

Typ

Max

Unit

I

PWM Pin Floating, V = 3.3V

--

80

0

--

5

A

V

Q

EN

V

EN

= 0V, PWM = 0V, V = 5V

CC

SHDN

V

PORH

VCC POR Rising

VCC POR Falling

Hysteresis

--

4.2

3.84

360

4.5

--

VCC Power On Reset (POR) V

3.5

--

V

PORL

V

--

mV

PORHYS

Internal BOOT Switch

Internal Boost Switch On

Resistance

R

BOOT

VCC to BOOT, 10mA

--

80



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DS9610C-01 April 2016

RT9610C

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

PWM Input

V_PWM= 5V

--

174

174

3.8

1

--

Input Current

I_PWM

A

V_PWM= 0V

V_CC= 5V

PWM Tri-State Rising Threshold

PWM Tri-State Falling Threshold

EN Input

V_PWMH

V_PWML

3.5

0.7

4.1

1.3

V

Logic-High

EN Input Voltage

V_ENH

V_ENL

V_CC= 5V

1.4

--

V

Logic-Low

0.48

Switching Time

UGATE Rise Time

UGATE Fall Time

LGATE Rise Time

LGATE Fall Time

t_UGATEr

t_UGATEf

t_LGATEr

t_LGATEf

V_CC= 5V, 3nF Load

V_CC= 5V, Outputs Unloaded

--

8

--

ns

8

4

UGATE Turn-Off Propagation Delay t_PDLU

LGATE Turn-Off Propagation Delay t_PDLL

UGATE Turn-On Propagation Delay t_PDHU

LGATE Turn-On Propagation Delay t_PDHL

35

V_CC= 5V, Outputs Unloaded

--

35

20

--

ns

UGATE/LGATE Tri-State

t_PTS

V_CC= 5V, Outputs Unloaded

--

35

--

ns

Propagation Delay

Output

UGATE Driver Source Resistance

R_UGATEsr

100mA Source Current

--

1

--



UGATE Driver Source Current

UGATE Driver Sink Resistance

UGATE Driver Sink Current

I_UGATEsr

R_UGATEsk

I_UGATEsk

V_UGATEV_PHASE= 2.5V

100mA Sink Current

--

2

1

2

--

A



A

V_UGATEV_PHASE= 2.5V

LGATE Driver Source Resistance

R_LGATEsr

100mA Source Current

--

1

--



LGATE Driver Source Current

LGATE Driver Sink Resistance

LGATE Driver Sink Current

I_LGATEsr

R_LGATEsk

I_LGATEsk

V_LGATE= 2.5V

--

2

0.5

4

--

A



A

100mA Sink Current

V_LGATE= 2.5V

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body mode is a 100pF capacitor is

charged through a 1.5kΩ resistor into each pin.

Note 4. The device is not guaranteed to function outside its operating conditions.

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RT9610C

Typical Application Circuit

L1

2.2µH

V

IN

V

BAT

C12

C8

C9

C10

C11

C13

C14

C2

1µF

R2

BOOT

R3

R4

R1

VCC

Q1

Q2

V

UGATE

CC

C1

1µF

L2

RT9610C

V

CORE

1µH

PHASE

C3

Enable

PWM

EN

3.3nF

C4

C5

C6

C7

PWM

LGATE

R5

2.2

GND

Timing Diagram

PWM

t

PDLL

90%

t

PDLU

LGATE

1.5V

90%

1.5V

t

UGATE

t

PDHL

PDHU

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DS9610C-01 April 2016

®

RT9610C

Typical Operating Characteristics

Driver Enable

Driver Disable

UGATE

(20V/Div)

PHASE

(20V/Div)

LGATE

(5V/Div)

EN

(5V/Div)

V_IN= 19V, No Load

Time (1μs/Div)

PWM Rising Edge

PWM Falling Edge

V_IN= 19V, No Load

UGATE

(20V/Div)

UGATE

(20V/Div)

PHASE

(20V/Div)

PHASE

(20V/Div)

LGATE

(5V/Div)

LGATE

(5V/Div)

PWM

(5V/Div)

PWM

(5V/Div)

V_IN= 19V, No Load

Time (20ns/Div)

Dead Time

UGATE

PHASE

UGATE - PHASE

(5V/Div)

LGATE

V_IN= 19V, PWM Rising, No Load

Time (20ns/Div)

V_IN= 19V, PWM Falling, No Load

Time (20ns/Div)

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RT9610C

Dead Time

UGATE

PHASE

UGATE

PHASE

UGATE - PHASE

(5V/Div)

LGATE

V_IN= 19V, PWM Falling, Full Load

V_IN= 19V, PWM Rising, Full Load

Time (20ns/Div)

Short Pulse

UGATE

PHASE

UGATE - PHASE

(5V/Div)

LGATE

V_IN= 19V, Start Up

Time (20ns/Div)

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DS9610C-01 April 2016

RT9610C

Application Information

Supply Voltage and Power On Reset

below their threshold, the non-overlap protection circuit

ensures that UGATE is low before LGATE pulls high.

The RT9610C is designed to drive both high side and low

sideN-MOSFETs through an externally input PWM control

signal. Connect 5V to VCC to power on the RT9610C. A

minimum 1μF ceramic capacitor is recommended to

bypass the supply voltage. Place the bypassing capacitor

physically near the IC. The power on reset (POR) circuit

monitors the supply voltage at the VCC pin. If VCC

exceeds the POR rising threshold voltage, the controller

resets and prepares for operation. UGATE and LGATE

are held low before VCC is above the POR rising threshold.

Also to prevent the overlap of the gate drives during LGATE

pull low and UGATE pull high, the non-overlap circuit

monitors the LGATE voltage. When LGATE go below 1.1V,

UGATE is allowed to go high.

Driving Power MOSFETs

The DC input impedance of the power MOSFET is

extremely high. The gate draws the current only for few

nano-amperes. Thus once the gate has been driven up to

“ON” level, the current could be negligible.

Enable and Disable

However, the capacitance at the gate to source terminal

should be considered. It requires relatively large currents

to drive the gate up and down rapidly. It is also required to

switch drain current on and off with the required speed.

The required gate drive currents are calculated as follows.

The RT9610C includes an EN pin for sequence control.

When the EN pin rises above the V_ENHtrip point, the

RT9610C begins a new initialization and follows the PWM

command to control the UGATE and LGATE. When the

EN pin falls below the V_ENLtrip point, the RT9610C shuts

down and keeps UGATE and LGATE low.

D1

Three State PWM Input

L

d1

s1

V

OUT

IN

After initialization, the PWM signal takes over the control.

The rising PWM signal first forces the LGATE signal low

and then allows the UGATE signal to go high right after a

non-overlapping time to avoid shoot through current. In

contrast, the falling PWM signal first forces UGATE to go

low. When the UGATE or PHASE signal reach a

predetermined low level, LGATE signal is then allowed to

go high.

Cgs1

Cgd1

Cgd2

Cgs2

d2

Igs1

Igd1

Ig1

_Ig2Igd2

Igs2

g1

g2

D2

s2

GND

V

g1

Non-overlap Control

V

+5V

PHASE

To prevent the overlap of the gate drives during the UGATE

pull low and the LGATE pull high, the non-overlap circuit

monitors the voltages at the PHASE node and high side

gate drive (UGATE-PHASE). When the PWM input signal

goes low, UGATE begins to pull low (after propagation

delay). Before LGATE can pull high, the non-overlap

protection circuit ensures that the monitored (UGATE-

PHASE) voltages have gone below 1.1V or phase voltage

is below 2V. Once the monitored voltages fall below the

threshold, LGATE begins to turn high. By waiting for the

voltages of the PHASE pin and high side gate drive to fall

t

V

g2

5V

Figure1. Equivalent Circuit andAssociated Waveforms

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RT9610C

380 x 10^-12x 5

14 x 10^-9

In Figure 1, the current I_g1and I_g2are required to move the

I_gd1



 0.136 (A)

(7)

(8)

gate up to 5V. The operation consists of charging C_gd1

,

C_gd2, C_gs1and C_gs2. C_gs1and C_gs2are the capacitors from

gate to source of the high side and the low side power

MOSFETs, respectively. In general data sheets, the C_gs1

and C_gs2are referred as “C_iss” which are the input

capacitors. C_gd1and C_gd2are the capacitors from gate to

drain of the high side and the low side power MOSFETs,

respectively and referred to the data sheets as “C_rss” the

reverse transfer capacitance. For example, t_r1and t_r2are

the rising time of the high side and the low side power

500 x 10^-12x 12+5





I_gd2

 0.283 (A)

30 x 10^-9

the total current required from the gate driving source can

be calculated as following equations :

(9)

I_g1 I_gs1 I_gd1 0.593  0.136  0.729 (A)





(10)

I_g2 I_gs2 I_gd2 0.367  0.283  0.65 (A)





MOSFETs respectively, the required current I_gs1and I_gs2

,

By a similar calculation, we can also get the sink current

required from the turned off MOSFET.

are shown as below :

dV

C

x 5

g1

gs1

(1)

(2)

I

 C



gs1

Select the Bootstrap Capacitor

dt

dV

t

r1

Figure 2 shows part of the bootstrap circuit of the

RT9610C. The V_CB(the voltage difference between BOOT

and PHASE on RT9610C) provides a voltage to the gate

of the high side power MOSFET. This supply needs to be

ensured that the MOSFET can be driven. For this, the

capacitance C_Bhas to be selected properly. It is

determined by following constraints.

C

g2

gs1

I

 C



gs2

gs1

dt

t

r2

Before driving the gate of the high side MOSFET up to

5V, the low side MOSFET has to be off; and the high side

MOSFET is turned off before the low side is turned on.

From Figure 1, the body diode “D₂” had been turned on

before high side MOSFETs turned on.

V

IN

dV

5

I

 C

gd1

(3)

gd1

BOOT

dt

t

r1

+

C

B

Before the low side MOSFET is turned on, the C_gd2have

been charged to V_IN. Thus, as C_gd2reverses its polarity

and g₂is charged up to 5V, the required current is :

UGATE

PHASE

V

CB

-

V

CC

dV

dt

Vi  5

I

 C

gd2

(4)

gd2

LGATE

GND

t

r2

It is helpful to calculate these currents in a typical case.

Assume a synchronous rectified buck converter, input

voltage V_IN= 12V, V_g1= V_g2= 5V. The high side MOSFET

is PHB83N03LT whose C_iss= 1660pF, C_rss= 380pF, and

t_r= 14ns. The low side MOSFET is PHB95N03LT whose

C_iss= 2200pF, C_rss= 500pF and t_r= 30ns, from the

equation (1) and (2) we can obtain :

Figure 2. Part of Bootstrap Circuit of RT9610C

In practice, a low value capacitor C_Bwill lead to the over

charging that could damage the IC. Therefore, to minimize

the risk of overcharging and to reduce the ripple on V_CB,

the bootstrap capacitor should not be smaller than 0.1μF,

and the larger the better. In general design, using 1μF can

provide better performance.At least one low ESR capacitor

should be used to provide good local de-coupling. It is

recommended to adopt a ceramic or tantalum capacitor.

-12

1660 x 10 x 5

(5)

(6)

I



 0.593 (A)

 0.367 (A)

gs1

-9

14 x 10

-12

2200 x 10 x 5

I

gs2

-9

30 x 10

from equation. (3) and (4)

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DS9610C-01 April 2016

RT9610C

Thermal Considerations

Layout Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

Figure 4 shows the schematic circuit of a synchronous

buck converter to implement the RT9610C.

L1

5V

V

IN

12V

C2

1

C1

R1

C4

BOOT

5

2

VCC

CB

RT9610C

8

7

Q1

UGATE

PWM

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

PWM

5V

L2

V

PHASE

LGATE

CORE

6

3

PHB83N03LT

PHB95N03LT

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction to ambient

thermal resistance.

EN

C3

GND

4

Q2

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

WDFN-8L 2x2 packages, the thermal resistance, θ_JA, is

45.5°C/W on a standard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at T_A= 25°C

can be calculated by the following formula :

Figure 4. Synchronous Buck Converter Circuit

When layout the PCB, it should be very careful. The power

circuit section is the most critical one. If not configured

properly, it will generate a large amount of EMI. The

junction of Q1, Q2, L2 should be very close.

Next, the trace from UGATE, and LGATE should also be

short to decrease the noise of the driver output signals.

PHASE signals from the junction of the power MOSFET,

carrying the large gate drive current pulses, should be as

heavy as the gate drive trace. The bypass capacitor C4

should be connected to GND directly. Furthermore, the

bootstrap capacitors (C_B) should always be placed as close

to the pins of the IC as possible.

P_D(MAX)= (125°C − 25°C) / (45.5°C/W) = 2.19W for

WDFN-8L 2x2 package

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curves in Figure 3 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

2.5

Four-Layer PCB

2.0

1.5

1.0

0.5

0.0

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 3.Derating Curve of Maximum PowerDissipation

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RT9610C

Outline Dimension

D2

D

L

E

E2

SEE DETAIL A

1

e

b

2

1

2

1

A

A3

DETAILA

Pin #1 ID and Tie Bar Mark Options

A1

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

0.800

0.050

0.250

0.300

2.050

1.250

2.050

0.650

Min

Max

0.031

0.002

0.010

0.012

0.081

0.049

0.081

0.026

A

A1

A3

b

0.700

0.000

0.175

0.200

1.950

1.000

1.950

0.400

0.028

0.000

0.007

0.008

0.077

0.039

0.077

0.016

D

D2

E

E2

e

0.500

0.020

L

0.300

0.400

0.012

0.016

W-Type 8L DFN 2x2 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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DS9610C-01 April 2016


型号：	RT9610C
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总12页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT9610C [RICHTEK]

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