RTQ2532WGQV [RICHTEK]
2A, 6.5V, Ultra Low Noise, Ultra Low Dropout Linear Regulator;
| 型号： | RTQ2532WGQV |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 2A, 6.5V, Ultra Low Noise, Ultra Low Dropout Linear Regulator |
| 文件： | 总20页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RTQ2532W
2A, 6.5V, Ultra Low Noise, Ultra Low Dropout Linear Regulator
General Description
Features
Input Voltage Range : 1.1V to 6.5V
The RTQ2532W is a high-current (2A), low-noise
(6.8μVRMS), high accuracy (1% over line, load, and
temperature), low-dropout linear regulator (LDO) capable
of sourcing 2A with extremely low dropout (max. 125mV).
The device output voltage is pin-selectable (up to 3.95V)
using a PCB layout without the need of external resistors,
thus reducing overall component count. Designers can
achieve higher output voltage with the use of external
resistor divider. The device supports single input supply
voltage as low to 1.1V that makes it easy to use.
Two Output Voltage Modes
0.8 V to 5.5V (Set by a Resistive Divider)
0.8 V to 3.95V (Set via PCB Layout, No External
Resistor Required)
Accurate Output Voltage Accuracy (1%) Over Line,
Load and Temperature
Ultra High PSRR : 40dB at 500kHz
Excellent Noise Immunity
6.8μVRMS at 0.8V Output
10μVRMS at 3.3V Output
Ultra Low Dropout Voltage : 125mV at 2A
Enable Control
The low noise, high PSRR and high output current capability
makes the RTQ2532W ideal to power noise-sensitive
devices such as analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and RF components.
With very high accuracy, remote sensing, and soft-start
capabilities to reduce inrush current, the RTQ2532W is
ideal for powering digital loads such as FPGAs, DSPs,
andASICs.
Programmable Soft-Start Output
Stable with a 22μF or Larger Ceramic Output
Capacitor
Support Power-Good Indicator Function
RoHS Compliant and Halogen Free
The external enable control and power good indicator
function makes the control sequence easier. The output
noise immunity is enhanced by adding external bypass
capacitor on theNR/SS pin. The device is fully specified
over the temperature range of TJ = −40°C to 125°C and is
offered in a VQFN-20L 5x5 package.
Applications
Portable ElectronicDevices
Wireless Infrastructures : SerDes, FPGA, DSP
RF, IF Components : VCO, ADC, DAC, LVDS
Pin Configuration
(TOP VIEW)
Ordering Information
RTQ2532W
20
19
18
17
16
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
1
2
3
4
15
14
13
12
VOUT
SNS
VIN
Package Type
QV : VQFN-20L 5x5 (V-Type)
EN
FB
NR/SS
NC
GND
Lead Plating System
G : Green (Halogen Free and Pb Free)
PGOOD
50mV
5
11
Note :
1.6V
21
***Empty means Pin1 orientation is Quadrant 1
Richtek products are :
6
7
8
9
10
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
VQFN-20L 5x5
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2532W-00 July 2019
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1
RTQ2532W
Marking Information
RTQ2532WGQV : Product Number
RTQ2532W
GQV
YMDNN : Date Code
YMDNN
Functional Pin Description
Pin No.
Pin Name
Pin Function
LDO output pins. A 22F or larger ceramic capacitor (10F or greater
effective capacitance) is required for stability. Place the output capacitor as
close to the device as possible and minimize the impedance between VOUT
pin and load.
1, 19, 20
VOUT
Output voltage sense input pin. Connect this pin only if using the
configuration without external resistors. Keep the SNS pin floating if the
VOUT voltage is set by external resistor.
2
3
SNS
FB
Feedback voltage input. This pin is used to set the desired output voltage
via an external resistive divider. The feedback reference voltage is 0.8V
typically.
Power good indicator output. An open-drain output and active high when the
output voltage reaches 88% of the target. The pin is pulled to ground when
the output voltage is lower than its specified thresholds, including EN
shutdown, OCP and OTP.
4
PGOOD
Output voltage setting pins. Connect these pins to ground or leave floating.
50mV, 100mV, Connecting these pins to ground increases the output voltage by the value
5, 6, 7, 9, 10, 11 200mV, 400mV, of the pin name; multiple pins can be simultaneously connected to GND to
800mV, 1.6V
select the desired output voltage. Leave these pins floating (open) if the
VOUT voltage is set by external resistor.
8, 18,
21 (Exposed Pad)
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
GND
No internal connection. Leaving these pins floating does not affect the
functionality of the chip. By connecting these pins to GND, design engineers
could extend the GND copper coverage on the PCB top layer to enhance
the thermal convection.
12
13
NC
Noise-reduction and soft-start pin. Decouple this pin to GND with an external
capacitor CNR/SS can not only reduce output noise to very low levels but also
slow down the rising of VOUT, providing a soft-start behavior. For low noise
applications, a 10nF to 1F CNR/SS is suggested.
NR/SS
Enable control input. Connecting this pin to logic-high enables the regulator,
and driving this pin low puts it into shutdown mode. The device can have VIN
and VEN sequenced in any order without causing damage to the device.
However, to ensure the soft-start function works as intended, certain
sequencing rules must be applied. Enabling the device after VIN is present
is preferred.
14
EN
Supply input. A general 22F ceramic capacitor should be placed as close
as possible to this pin for better noise rejection.
15, 16, 17
VIN
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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2
DSQ2532W-00 July 2019
RTQ2532W
Functional Block Diagram
VOUT
VIN
Charge
Pump
Active
Discharge
Current
Limit
Gate
Driver
Thermal
Protection
PGOOD
0.72V
UVLO
+
-
Enable
Control
Logic
UVLO
-
EN
SNS
FB
Bandgap
Reference
2R
32R 16R
8R
4R
2R
1R
INR/SS
NR/SS GND
50mV 100mV 200mV 400mV 800mV 1.6V
Operation
The RTQ2532W operates with single supply input ranging
from 1.1V to 6.5V and is capable of delivering up to 2A
current to the output. The device features high PSRR and
low noise to provide a clean supply to the application.
If not used, connect the EN pin as close as possible to
the largest capacitance on the input to prevent voltage
droops on the VIN line from triggering the enable circuit.
VOUT Programming Pins
A low-noise reference and error amplifier are included to
reduce device noise. TheNR/SS capacitor filters the noise
from the reference, and the feed-forward capacitor filters
the noise from the error amplifier. The high power-supply
rejection ratio (PSRR) of the RTQ2532W minimizes the
coupling of input supply noise to the output.
The built-in matched feedback resistor network of the
RTQ2532W can set the output voltage. The output voltage
can be programmed from 0.8V to 3.95V in 50mV steps
when tying these programming pins (Pins 5 to 11) to
ground. Tying any of the VOUT programming pins to SNS
can lower the value of the upper resistor divider. Hence,
the VOUT programming resolution is increased.
Enable and Shutdown
The RTQ2532W provides an EN pin, as an external chip
enable control, to enable or disable the device. VEN below
0.5 V turns the regulator off and enters the shutdown mode,
while VEN above 1.1V turns the regulator on. When the
regulator is shutdown, the ground current is reduced to a
maximum of 25μA. The enable circuitry has hysteresis
(typically 50mV) for use with relatively slowly ramping
analog signals.
Programmable Soft-Start
The noise-reduction capacitor (CNR/SS) reduces noise and
programs the soft-start ramp time during turn-on. When
EN and UVLO exceed the respective threshold voltage,
the RTQ2532W activates a quick-start circuit to charge
the noise reduction capacitor (CNR/SS) and then the output
voltage ramps up.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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3
RTQ2532W
Power Good
Over-Temperature Protection (OTP)
The power-good circuit monitors the feedback pin voltage
to indicate the status of the output voltage. The open-
drain PGOOD pin requires an external pull-up resistor to
an external supply, and any downstream device can receive
power-good as a logic signal that can be used for
sequencing. A pull-up resistor from 10kΩ to 100kΩ is
recommended. Make sure that the external pull-up supply
voltage results in a valid logic signal for the receiving device
or devices.
The RTQ2532W implements thermal shutdown protection.
The device is disabled when the junction temperature (TJ)
exceeds 160°C (typical). The LDO automatically turns
on again when the temperature falls below 140°C (typical).
For reliable operation, limit the junction temperature to a
maximum of 125°C. Continuously running the RTQ2532W
into thermal shutdown or above a junction temperature of
125°C reduces long-term reliability.
Output Active Discharge
After start-up, the PGOODpin becomes high impedance
when the feedback voltage exceeds VPGOOD_HYS (typically
90% of 0.8V reference voltage level). The PGOOD is pulled
to GND when the feedback pin voltage falls below the
VIT_PGOOD, when EN is low, or the current limit or OTP
levels are reached.
When the device is disabled, the RTQ2532W discharges
the LDO output (via VOUT pins) through an internal current
sink to ground. Do not rely on the active discharge circuit
for discharging a large amount of output capacitance after
the input supply collapses because reverse current can
possibly flow from the output to the input. External current
protection should be added if the device work at reverse
voltage state.
Under-Voltage Lockout (UVLO)
The UVLO circuit monitors the input voltage to prevent
the device from turning on before VIN rises above the VUVLO
threshold. The UVLO circuit also disables the output of
the device when VIN falls below the lockout voltage
(VUVLO − ΔVUVLO). The UVLO circuit responds quickly to
glitches on VIN and attempts to disable the output of the
device if VINcollapses.
Internal Current Limit (ILIM
)
The RTQ2532W continuously monitors the output current
to protect the device against high load current faults or
short events. The current limit circuitry is not intended to
allow operation above the rated current of the device.
Continuously running the RTQ2532W above the rated
current degrades the reliability of the device.
During current limit, the output voltage falls when load
impedance decreases. If the output voltage is low,
excessive power may cause the output thermal shutdown.
Afoldback feature limits the short-circuit current to protect
the regulator from damage under all load conditions. If the
load current demand exceeds the foldback current limit
before EN goes high, the device does not turn on.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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DSQ2532W-00 July 2019
RTQ2532W
Absolute Maximum Ratings (Note 1)
VIN, PGOOD, EN -------------------------------------------------------------------------------------------------- −0.3V to 7V
VOUT ------------------------------------------------------------------------------------------------------------------ −0.3V to 7V
NR/SS, FB ----------------------------------------------------------------------------------------------------------- −0.3V to 3.6V
Power Dissipation, PD @ TA = 25°C
VQFN-20L5x5 ------------------------------------------------------------------------------------------------------ 2.79W
Package Thermal Resistance (Note 2)
VQFN-20L 5x5, θJA ------------------------------------------------------------------------------------------------- 35.8°C/W
VQFN-20L 5x5, θJC ------------------------------------------------------------------------------------------------ 4.28°C/W
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model)--------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 1.1V to 6.5V
Junction Temperature Range------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
Over operating temperature range (TJ = −40°C to 125°C), (1.1V ≤ VIN < 6.5V and VIN ≥ VOUT(TARGET) + 0.3 V, VOUT(TARGET) = 0.8V,
VOUT connected to 50Ω to GND, VEN = 1.1 V, CIN = 10μF, COUT = 22μF, CNR/SS = 0nF, CFF = 0nF, and PGOOD pin pulled up to
VIN with 100 kΩ, unless otherwise noted. (Note 5)
Parameter
Symbol
VIN
Test Conditions
Min
Typ
Max Unit
Operating Input
Voltage Range
1.1
--
6.5
V
V
Feedback Reference
Voltage
VREF
--
0.8
0.8
--
NR/SS Pin Voltage
VNR/SS
VUVLO
--
--
--
---
V
V
VIN increasing
Hysteresis
1.02 1.085
Under-Voltage
Lockout
VUVLO
100
--
--
mV
Using voltage setting pins (50mV, 100mV, 0.8V
200mV, 400mV, 800mV, and 1.6V)
3.95V
+ 1%
V
V
1%
Output Voltage Range
Output Voltage
0.8V
1%
5V +
1%
Using external resistors
--
--
V
IN = VOUT + 0.3V, 0.8V VOUT 5.2V,
1mA IOUT 2A
VOUT
1
1
%
Accuracy
(Note 6)
Line Regulation
Load Regulation
VOUT/VIN IOUT = 1mA, 1.1V VIN 6.5 V
VOUT/IOUT 1mA IOUT 2A
--
--
0.05
0.08
--
--
%/V
%/A
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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RTQ2532W
Parameter
Symbol
VDROP
ILIM
ISC
Test Conditions
Min
Typ
Max
Unit
V
IN = 1.1V to 6.5V, IOUT = 2A,
Dropout Voltage
--
--
125
mV
VFB = 0.8V 3%
OUT = 90% VOUT(TARGET),
VIN = VOUT(TARGET) + 400mV
LOAD = 20m, under foldback
V
Output Current Limit
2.2
--
3.3
1
3.8
--
A
A
Short-Circuit Current
Limit
R
operation
Minimum load, VIN = 6.5V,
IOUT = 5mA
--
2.8
3.7
4
mA
Maximum load, VIN = 1.1V,
IOUT = 2A
Ground Pin Current
EN Pin Current
IGND
--
5.5
Shutdown, PGOOD = Open,
VIN = 6.5V, VEN = 0.5V
--
--
--
25
0.1
6.5
A
A
IEN
VIN = 6.5V, VEN = 0V and 6.5V
0.1
1.1
EN Pin High-Level
Input Voltage
--
--
VEN_H
Enable device
V
EN Pin Low-Level
Input Voltage
VEN_L
Disable device
0
0.5
PGOOD Pin
Threshold
For the direction PGOOD signal
falling with decreasing VOUT
0.82 x 0.883 x 0.93 x
VIT_PGOOD
V
V
VOUT
VOUT
VOUT
PGOOD Pin
Hysteresis
2% x
VOUT
VPGOOD_HYS For PGOOD signal rising
--
--
PGOOD Pin Low-
Level Output Voltage
V
OUT < VIT_PGOOD
,
VPGOOD_L
--
--
0.4
V
IPGOOD = 1mA (current into device)
PGOOD Pin Leakage
Current
V
OUT > VIT_PGOOD
,
IPGOOD_LK
INR/SS
IFB
--
4
--
--
1
9
A
A
nA
VPGOOD = 6.5V
NR/SS Pin Charging
Current
VNR/SS = GND, VIN = 6.5V
VIN = 6.5V
FB Pin Leakage
Current
100
--
--
100
--
f = 10kHz,
VOUT = 0.8V
42
39
40
25
VIN VOUT = 0.4V,
IOUT = 2A,
CNR/SS = 100nF,
CFF = 10nF,
f = 500kHz,
VOUT = 0.8V
--
--
Power Supply
Rejection Ratio
PSRR
dB
f = 10kHz,
VOUT = 5V
--
--
COUT = 22F
f = 500kHz,
VOUT = 5V
--
--
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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DSQ2532W-00 July 2019
RTQ2532W
Parameter
Symbol
Test Conditions
Min Typ Max
Unit
VIN = 1.1V,
VOUT = 0.8V
BW = 10Hz to 100kHz,
OUT = 2A,
CNR/SS = 100nF,
CFF = 10nF,
6.8
10
--
--
--
--
I
Output Noise
Voltage
VIN = 3.6V,
VOUT = 3.3V
eNO
VRMS
COUT = 22μF
16
VOUT = 5 V
--
--
--
--
--
--
Temperature increasing
Temperature decreasing
160
140
Thermal Shutdown
Threshold
TSD
°C
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C on a high effective-thermal-conductivity four-layer test
board in size of 70mm x 50mm with 1oz copper thickness. θJC is measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. VOUT(TARGET) is the expected VOUT value set by the external feedback resistors. The 50Ω load is disconnected when the
test conditions specify an IOUT value.
Note 6. External resistor tolerance is not taken into account.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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RTQ2532W
Typical Application Circuit
RTQ2532W
15, 16, 17
1, 19, 20
3
V
OUT
V
VIN
IN
VOUT
C
22µF
1.2V/2A
IN
C
22µF
C
10nF
OUT
FF
R1
12.4k
Power Good
FB
R3 100k
4
V
R2
24.9k
OUT
PGOOD
14
13
Enable
EN
NR/SS
C
10nF
NR/SS
GND
8, 18, 21 (Exposed Pad)
R1
R2
12.4k
24.9k
VOUT = VREF 1 +
= 0.8V 1 +
= 1.2V
Figure 1. Configuration Circuit for VOUT Adjusted by a ResistiveDivider
Table 1. Recommended Feedback-Resistor Values
External Restive Divider Combinations
Output Voltage (V)
R1 (k)
12.4
12.4
12.4
12.4
12.4
12.4
11.8
11.8
12.4
R2 (k)
100
0.9
1
49.9
24.9
14.3
10
1.2
1.5
1.8
2.5
3.3
4.5
5
5.9
3.74
2.55
2.37
Table 2. Recommended External Components
Component
Description
Vendor P/N
CFF, CNR/SS
*COUT, CIN
10nF, 50V, X7R, 0603
22F, 16V, X5R, 0805
GCD188R71H103KA01 (Murata)
GRM21BR61C226ME44 (Murata)
* : Considering the effective capacitance derated with biased voltage level, the COUT component needs to
satisfy the effective capacitance at least 10F or above at targeted output level for stable and normal
operation.
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DSQ2532W-00 July 2019
RTQ2532W
RTQ2532W
15, 16, 17
1, 19, 20
V
OUT
V
VIN
IN
VOUT
C
IN
1.25V/2A
2
C
22µF
C
10nF
OUT
FF
22µF
SNS
3
Power Good
FB
R3 100k
11
10
9
4
V
1.6V
800mV
400mV
OUT
PGOOD
14
13
Enable
EN
7
NR/SS
200mV
100mV
C
NR/SS
6
10nF
5
50mV
GND
8, 18, 21 (Exposed Pad)
VOUT = VREF + 50mV + 400mV = 0.8V + 50mV + 400mV = 1.25V
(Table 3. provides a full list for different VOUT targets and the corresponding pin settings.)
Figure 2. Configuration Circuit for Adjusted VOUT via PCB Layout
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RTQ2532W
Table 3. VOUT Select Pin Settings for Different Targets
VOUT (V) 50mV 100mV 200mV 400mV 800mV 1.6V VOUT (V) 50mV 100mV 200mV 400mV 800mV 1.6V
0.8
0.85
0.9
Open Open Open
GND Open Open
Open GND Open
GND GND Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
2.4
2.45
2.5
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0.95
1
2.55
2.6
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.05
1.1
2.65
2.7
1.15
1.2
2.75
2.8
Open Open Open
GND Open Open
Open GND Open
GND GND Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.25
1.3
2.85
2.9
1.35
1.4
2.95
3
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.45
1.5
3.05
3.1
1.55
1.6
3.15
3.2
Open Open Open
GND Open Open
Open GND Open
GND GND Open
1.65
1.7
3.25
3.3
1.75
1.8
3.35
3.4
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.85
1.9
3.45
3.5
1.95
2
3.55
3.6
Open Open Open
GND Open Open
Open GND Open
GND GND Open
2.05
2.1
3.65
3.7
2.15
2.2
3.75
3.8
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
2.25
2.3
3.85
3.9
2.35
3.95
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RTQ2532W
Typical Operating Characteristics
PSRR vs. Frequency and VOUT
PSRR vs. Frequency and VIN
100
100
80
60
40
20
0
VOUT = 0.8V
VOUT = 1.2V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
80
VIN = 1.4V
VIN = 1.3V
VIN = 1.2V
VIN = 1.1V
60
40
20
0
VOUT = 0.8V, IOUT = 2A, COUT = 22μF
VIN = VOUT + 0.3V, IOUT = 2A, COUT = 22μF,
CNR/SS = 10nF, CFF = 10nF
CNR/SS = 10nF, CFF = 10nF
10
100
1K
10K 100K 1M
10
100
1K
10K 100K 1M
Frequency (Hz)
Frequency (Hz)
Output Noise vs. Frequency and Output Voltage
10
PSRR vs. Frequency and IOUT
100
80
60
40
20
0
VOUT = 5V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 0.8V
IOUT = 0.1A
1
I
I
OUT = 0.5A
OUT = 1A
IOUT = 1.5A
OUT = 2A
I
0.1
0.01
VIN = VOUT + 0.3V, IOUT = 2A, COUT = 22μF
VIN = 1.1V, VOUT = 0.8V, COUT = 22μF
NR/SS = 10nF, CFF = 10nF
CNR/SS = 10nF, CFF = 10nF
C
0.001
10
100
1K
10K 100K 1M
10
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
Output Noise vs. Frequency and CNR/SS
Output Noise vs. Frequency and CFF
10
1
10
1
CNR/SS = 0nF
CNR/SS = 1nF
CFF = 100nF
CFF = 10nF
CFF = 1nF
CNR/SS = 10nF
CNR/SS = 100nF
CFF = 0nF
CFF = 0.1nF
0.1
0.1
0.01
0.001
0.01
0.001
VIN =1.1V, VOUT = 0.8V, IOUT = 2A
VIN = 1.1V, VOUT = 0.8V, IOUT = 2A
COUT = 22μF, CFF = 10nF
COUT = 22μF, CNR/SS = 10nF
10
100
1K
10K 100K 1M
10
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
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RTQ2532W
Power Up Response
Load Transient Response
VIN = VOUT + 0.3V, VOUT = 3.3V,
VIN = 3.7V, VOUT = 3.3V, IOUT = 0.2A to 2A (1A/μs),
COUT = 22μF, CNR/SS = CFF = 10nF
IOUT = 2A, COUT = 22μF, CFF = 10nF
VOUT
(40mV/Div)
offset 3.3V
VEN
VEN
(1V/Div)
VOUT, CNR/SS = 1nF
VOUT, CNR/SS = 10nF
VOUT, CNR/SS = 47nF
VOUT, CNR/SS = 100nF
IOUT
(1A/Div)
VOUT
(1V/Div)
Time (4ms/Div)
Time (50μs/Div)
Load Transient Response vs. Load Slew Rate
Enable Voltage vs. Temperature
1.50
1.25
1.00
0.75
0.50
0.25
0.00
VOUT
(40mV/Div)
Rising
Falling
offset 3.3V
VIN = 3.7V, VOUT = 3.3V
OUT = 0.2A to 2A
COUT = 22μF, CNR/SS = CFF = 10nF
I
VOUT
(40mV/Div)
offset 3.3V
VOUT, Load S. R. = 0.5A/μs
VOUT, Load S. R. = 1A/μs
VOUT, Load S. R. = 2A/μs
VOUT
(40mV/Div)
offset 3.3V
VIN = 1.8V, VOUT = 0.8V, IOUT = 10mA
-50
-25
0
25
50
75
100
125
Time (50μs/Div)
Temperature (°C)
Dropout Voltage vs. Input Voltage
Dropout Voltage vs. Output Current
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
125°C
85°C
25°C
0°C
−40°C
125°C
85°C
25°C
0°C
−40°C
IOUT = 2A
VIN = 1.1V
1.6 2
0
0.4
0.8
1.2
0
1
2
3
4
5
6
Output Current (A)
Input Voltage (V)
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RTQ2532W
Dropout Voltage vs. Output Current
120
100
80
60
40
20
0
125°C
85°C
25°C
0°C
−40°C
VIN = 5.4V
0
0.4
0.8
1.2
1.6
2
Output Current (A)
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RTQ2532W
Application Information
The RTQ2532W is a high current, low-noise, high
accuracy, low-dropout linear regulator which is capable of
sourcing 2A with maximum dropout of 125mV . The input
voltage operating range is 1.1V to 6.5V, and the adjustable
output voltage is 0.8V to (VIN − VDROP ) according to the
external resistor setting or 0.8V to 3.95V via PCB Layout
to short specific pins and get the required output target.
RTQ2532W
V
OUT
OUT
VIN
V
VOUT
IN
C
C
SNS
IN
C
FF
EN
FB
1.6V
800mV
400mV
200mV
100mV
Output Voltage Setting
50mV
The output voltage of the RTQ2532W can be set by external
resistors or by using the output voltage setting pins (50mV,
100mV, 200mV, 400mV, 800mV and 1.6V) to achieve
different output targets.
GND
EX :
V
= 0.8V + ( Output setting pins to Ground)
= 0.8V + (0.8V + 0.2V + 0.05V) = 1.85V
OUT
Figure 4. Output Setting without External Resistors
By using external resistors, the output voltage is
determined by the values of R1 and R2 as shown in Figure
3. The values of R1 and R2 can be calculated for any
voltage value using the following formula :
Table 2 summarizes these voltage values associated with
each active pin setting for reference. By leaving all
programming pins open, or floating, the output is thereby
programmed to the minimum possible output voltage which
equals to VREF (0.8V). The maximum output target can
be supported up to 3.95V after all pins 5, 6, 7, 9, 10 are
shorted with ground at the same time.
R1 + R2
VOUT = 0.8
R2
RTQ2532W
V
OUT
V
VIN
VOUT
SNS
IN
C
OUT
Dropout Voltage
C
IN
R1
R2
EN
C
FF
The dropout voltage refers to the voltage difference between
the VINand VOUT pins while operating at a specific output
current. The dropout voltage VDROP also can be expressed
as the voltage drop on the pass-FET at a specific output
current (IRATED) while the pass-FET is fully operating in
the ohmic region and the pass-FET can be characterized
as a resistance RDS(ON). Thus, the dropout voltage can be
defined as (VDROP = VIN − VOUT = RDS(ON) x IRATED). For
normal operation, the suggested LDO operating range is
(VIN > VOUT + VDROP) for good transient response and
PSRR performance. However, operation in the ohmic
region will degrade the performance severely.
FB
GND
Figure 3. Output Voltage Set by External Resistors
The RTQ2532W can also short pins 5, 6, 7, 9, 10, and 11
to ground and program the regulated output voltage level
without external resistors after the SNS pin is connected
to the VOUT. Pins 5, 6, 7, 9, 10, and 11 are connected
with internal resistor pairs. Each pin is either connected
to ground (active) or left open (floating).
CIN and COUT Selection
Voltage programming is set as the sum of the internal
reference voltage (VREF = 0.8V) plus the accumulated sum
of the respective voltages assigned to each active pin as
illustrated in figure 4.
The RTQ2532W is designed to support low-series-
resistance (ESR) ceramic capacitors. X7R, X5R, and COG-
rated ceramic capacitors are recommended due to its good
capacitive stability across differenet temperatures, whereas
the use of Y5V-rated capacitors is not recommended
because of large capacitance variations.
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RTQ2532W
However, the capacitance of ceramic capacitors varies with
operating voltage and temperature, and the design engineer
must be aware of these characteristics. Ceramic
capacitors are usually recommended to be derated by
50%. A22μF or greater output ceramic capacitor (or 10μF
effective capacitance) is suggested to ensure stability.
Input capacitance is selected to minimize transient input
drop during load current steps. For general applications,
an input capacitor of at least 22μF is highly recommended
for minimal input impedance. If the trace inductance
between the RTQ2532W input pin and power supply is
high, a fast load transient can cause VIN voltage level
ringing above the absolute maximum voltage rating which
damages the device. Adding more input capacitors is
available to restrict the ringing and keep it below the device
absolute maximum ratings.
For noise-reduction, CNR/SS in conjunction with an internal
noise-reduction resistor forms a low-pass filter (LPF) and
filters out the noise from the internal bandgap reference
before being amplified via the error amplifier, thus reducing
the total device noise floor.
Input Inrush Current
During start-up, the input Inrush current into the VIN pin
consists of the sum of load current and the charging
current of the output capacitor. The inrush current is difficult
to measure because the input capacitor must be removed,
which is not recommended.Generally, the soft-start inrush
current can be estimated by Equation b1, where VOUT(t)
is the instantaneous output voltage of the power-on ramp,
dVOUT(t) / dt is the slope of the VOUT ramp and RLOAD is
the resistive load impedance.
COUT dVOUT
t
VOUT
t
+
IOUT t =
b1
Feed-Forward Capacitor (CFF)
dt
RLOAD
The RTQ2532W is designed to be stable without the
external feed-forward capacitor (CFF). However, a 10nF
external feed-forward capacitor optimizes the transient,
noise, and PSRR performances. A higher capacitance of
CFF can also be used, but the start-up time will be longer
and the power-good signal will incorrectly indicate that
the output voltage is settled.
Under-Voltage Lockout (UVLO)
The Under-Voltage Lockout (UVLO) threshold is the
minimum input operational voltage range that ensures the
device stays disabled. Figure 5 explains that the UVLO
circuits are triggered between three different input voltage
events(duration a, b and c), assuming VEN ≥ VEN_H all the
time. For duration “a”, the input voltage starts rising.
When VIN is over the UVLO rising threshold, VOUT starts
the power-on process. Then, when VOUT reaches the target
level, and it is under regulation. During “b”, although the
power line has a voltage drop, it does not drop below the
UVLO low threshold (falling threshold). As a result, the
device maintains normal operation, and VOUT is still
regulated. At duration “c”, VIN drops below the UVLO
falling threshold, so the control loop is disabled and there
is no regulation; meanwhile, VOUT drops. For general
application, instant power line transient with long power
trace at the VINpin may have VIN level unstable and force
a trap as shown in duration “c” which makes VOUT
collapse. In this case, adding more input capacitance or
improving input trace layout on PCB are effective to improve
input power stabilization.
Soft-Start and Noise Reduction (CNR/SS
)
The RTQ2532W is designed for a programmable,
monotonic soft-start time during the output rising, which
can be achieved via an external capacitor (CNR/SS) onNR/
SS pin. Using an external CNR/SS is recommended for
general application. It is not only for the in-rush current
minimization but also helps reduce the noise component
from the internal reference.
During the monotonic start-up procedure, the error amplifier
of the RTQ2532W tracks the voltage ramp of the external
soft-start capacitor (CNR/SS) until the voltage approaches
the internal reference 0.8V. The soft-start ramp time can
be calculated with Equation a1, which depends on the
soft-start charging current (INR/SS), the soft-start
capacitance (CNR/SS), and the internal reference 0.8V
(VREF).
V
C
REF
NR/SS
t
=
a1
SS
I
NR/SS
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RTQ2532W
c
a
b
UVLO Rising Threshold
UVLO Hystersis Falling
V
IN
V
OUT
Figure 5. Under-Voltage Lockout Trigging Conditions and Output Variation
Power-Good (PGOOD) Function
VIN, EN and protection status. During “a”, VEN is higher
than the VEN_H threshold, and the device is under operation.
In this period, VOUT starts rising (the rising time is related
to the soft-start capacitor CNR/SS). When VOUT is over the
PGOOD hysteresis threshold, the reflected feedback
voltage VFB exceeds VPGOOD_HYS threshold.
Cconsequently, the PGOOD pin becomes a high
impedance node. The duration “b” indicates some
unpredictable operation (ex : OTP, OCP or severe output
voltage drop caused by very fast load variation). When
VFB is lower than the VIT_PGOOD threshold, VPGOOD is pulled
to GND, which indicates that the output voltage is not
ready. In duration “c”, VOUT has a small drop which is
not lower than the PGOODfalling threshold; the PGOOD
pin remains in high impedance. After VEN becomes logic
“0”, VPGOOD is pulled to GND as shown in duration “d”.
The power-good function monitors the voltage level at the
feedback pin to indicate that the output voltage status is
normal or not. This function enables other devices receive
the RTQ2532W's power-good signal as a logic signal that
can be used for the sequence design of the system
application. The PGOOD pin is an open-drain structure
and an external pull-up resistor connected to an external
supply is necessary. The pull-up resistor value between
10kΩ to 100kΩ is recommended for proper operation.
The lower limit of 10kΩ results from the maximum pull-
down strength of the power-good transistor, and the upper
limit of 100kΩ results from the maximum leakage current
at the power-good node.
Figure 6 demonstrates some PGOOD scenarios versus
V
EN
a
c
d
b
PGOOD Hysteresis Rising
PGOOD Falling Threshold
V
OUT
V
PGOOD
Figure 6. PGOODTrigger Scenario withDifferent Operating Status
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RTQ2532W
Reverse Current Protection
calculated using the following formula :
The reverse current from VOUT to VIN that flows through
the body diode of the pass element instead of the
normal conducting channel can happen if the maximum
VOUT exceeds VIN + 0.3V; in this case, the pass element
may be damaged.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJAis the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a VQFN-
20L 5x5 package, the thermal resistance, θJA, is
35.8°C/W on a high effective thermal-conductivity four-
layer test board. The maximum power dissipation at TA =
25°C can be calculated as below :
For example, if the output is biased above the input supply
voltage level or the input supply has an instant drop at
light load operation that makes VIN < VOUT. As shown in
Figure 7, an external Schottky diode can be added to
prevent the pass element be damaged from the reverse
current.
PD(MAX) = (125°C − 25°C) / (35.8°C/W) = 2.79W for a
VQFN-20L 5x5 package.
VIN
RTQ2532W
GND
VOUT
C
OUT
C
IN
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curve in Figure 8 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.0
Figure 7. Application Circuit for Reverse Current
Protection
Four-Layer PCB
2.8
Thermal Considerations
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Thermal protection limits power dissipation in the
RTQ2532W. When power dissipation on the pass
element (PDIS = (VIN − VOUT) x IOUT ) is too high and raises
the junction operation temperature over 160°C, the OTP
circuit starts the thermal shutdown function and turns the
pass element off. The pass element turns on again after
the junction temperature cools down by 20°C.
The output is shorted to ground when there is short circuit
at the output. This procedure can reduce the chip
temperature and provide maximum safety to end users
when output short circuit occurs.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curve of Maximum PowerDissipation
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
Layout Considerations
For best performance of the RTQ2532W, the PCB layout
suggestions below are highly recommended. All circuit
components should be placed on the same side and as
close to the respective LDO pin as possible. Place the
ground return path connection to the input and output
capacitor. Connect the ground plane with a wide copper
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RTQ2532W
surface for good thermal dissipation. Using vias and long
power traces for the input and output capacitors
connections is not recommended and has negative effects
on performance. Figure 9 shows a layout example that
reduces conduction trace loops, helping to minimize
inductive parasitics and load transient effects while
improving the circuit stability.
Ground Power Plane for Thermal Dissipation/ Signal Ground
PGOOD reference supply
10
9
8
7
6
R3
1.6V
NC
50mV
PGOOD
FB
SNS
VOUT
11
12
5
4
21
GND
PG Output
C
NR/SS
NR/SS
EN
To Signal Ground
13
14
15
3
2
1
R2
VIN
16 17 18 19 20
R1
Output Power Plane
C
FF
Load
Input Power Plane
C
C
IN
OUT
Place capacitors as close as possible
to the connected pins for minimizing
power loop area and low Impedance
Ground Power Plane
Thermal vias can help to reduce power trace and
improve thermal dissipation.
connection to GND late.
Figure 9. PCB Layout Guide
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RTQ2532W
Outline Dimension
1
2
1
2
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min.
0.800
0.000
0.175
0.250
4.950
3.100
4.950
3.100
Max.
1.000
0.050
0.250
0.350
5.050
3.200
5.050
3.200
Min.
0.031
0.000
0.007
0.010
0.195
0.122
0.195
0.122
Max.
0.039
0.002
0.010
0.014
0.199
0.126
0.199
0.126
A
A1
A3
b
D
D2
E
E2
e
0.650
0.026
L
0.500
0.600
0.020
0.024
V-Type 20L QFN 5x5 Package
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Preliminary
RTQ2532W
Footprint Information
Footprint Dimension (mm)
Number of
Package
Pin
Tolerance
±0.05
P
Ax
Ay
Bx
By
C
D
Sx
Sy
V/W/U/XQFN5*5-20
20
0.65
5.80
5.80
3.80
3.80
1.00
0.40
3.25
3.25
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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