74AC74SJ [ROCHESTER]
D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14;
| 型号： | 74AC74SJ |
| 厂家： | 
Rochester Electronics |
| 描述： | D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：1043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC74, 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Features
General Description
■ I reduced by 50%
The AC/ACT74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the out-
puts on the positive edge of the clock pulse. Clock trig-
gering occurs at a voltage level of the clock pulse and is
not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
CC
■ Output source/sink 24mA
■ ACT74 has TTL-compatible inputs
Asynchronous Inputs:
■ LOW input to S (Set) sets Q to HIGH level
D
■ LOW input to C (Clear) sets Q to LOW level
D
■ Clear and Set are independent of clock
■ Simultaneous LOW on C and S makes both Q and
D
D
Q HIGH
Ordering Information
Package
Order Number Number
Package Description
74AC74SC
74AC74SJ
74AC74MTC
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC74PC
N14A
M14A
M14D
MTC14
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74SC
74ACT74SJ
74ACT74MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
Description
D , D
Data Inputs
1
2
CP , CP
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
1
2
C
, C
D2
D1
S
, S
D2
D1
Q , Q , Q , Q
2
1
1
2
Truth Table
(Each Half)
Inputs
Outputs
S
C
CP
X
D
X
X
X
H
L
Q
H
L
Q
L
D
D
L
H
H
L
L
L
X
H
H
L
X
H
H
L
H
H
H
H
H
H
H
L
X
Q
Q
0
0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q (Q ) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
0
0
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current
V = –0.5V
–20mA
+20mA
I
V = V + 0.5
I
CC
V
DC Input Voltage
–0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
–0.5V to V + 0.5V
O
CC
I
50mA
50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
–65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
AC
CC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
–40°C to +85°C
125mV/ns
A
∆V / ∆t
Minimum Input Edge Rate, AC Devices:
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
4
DC Electrical Characteristics for AC
T = +25°C
T = –40°C to +85°C
A
A
V
CC
Symbol
Parameter
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
Conditions
Typ.
Guaranteed Limits
Units
V
Minimum HIGH Level
Input Voltage
V
V
= 0.1V or
OUT
1.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
IH
– 0.1V
CC
2.25
2.75
1.5
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
V
V
IL
OUT
– 0.1V
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
V
= V or V ,
0.36
0.36
0.1
0.44
0.44
1.0
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(3)
I
Maximum Input
Leakage Current
5.5 V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
(2)
I
–75
20.0
OHD
(3)
OHD
I
Maximum Quiescent
Supply Current
= V or GND
2.0
CC
IN
CC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
5
DC Electrical Characteristics for ACT
T = +25°C
T = –40°C to +85°C
A
A
V
CC
Symbol
Parameter
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
Conditions
Typ.
Guaranteed Limits
Units
V
Minimum HIGH Level
Input Voltage
V
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
3.86
2.0
2.0
0.8
0.8
4.4
5.4
3.76
V
IH
– 0.1V
CC
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
1.5
V
V
IL
OUT
– 0.1V
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= –50µA
4.49
5.49
OH
OUT
V
= V or V ,
IN
IL
IH
I
= –24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 24mA
OL
5.5
V
= V or V ,
0.36
0.1
0.44
1.0
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
5.5 V = V , GND
µA
IN
I
CC
I
I
Maximum I /Input
5.5 V = V – 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
5.5
5.5
5.5
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
–75
20.0
I
Maximum Quiescent
Supply Current
= V or GND
2.0
CC
IN
CC
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
6
AC Electrical Characteristics for AC
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(6)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
f
Maximum Clock Frequency
3.3
100
140
3.5
2.5
4.0
3.0
4.5
3.5
3.5
2.5
125
160
8.0
6.0
10.5
8.0
8.0
6.0
8.0
6.0
95
125
2.5
2.0
3.5
2.5
4.0
3.0
3.5
2.5
MHz
MAX
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
t
Propagation Delay,
12.0
9.0
13.0
10.0
13.5
10.5
16.0
10.5
14.5
10.5
ns
ns
ns
ns
PLH
PHL
PLH
PHL
C
or S to Q or Q
Dn
Dn n
n
n
t
Propagation Delay,
or S to Q or Q
12.0
9.5
C
Dn
Dn
n
t
t
Propagation Delay,
CP to Q or Q
13.5
10.0
14.0
10.0
n
n
n
Propagation Delay,
CP to Q or Q
n
n
n
Note:
5. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for AC
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50 pF
L
L
(7)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Set-up Time, HIGH or LOW,
3.3
1.5
4.0
4.5
3.0
0.5
0.5
7.0
5.0
0
ns
S
D to CP
n
n
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1.0
–2.0
–1.5
3.0
3.0
0.5
0.5
5.5
4.5
0
t
Hold Time, HIGH or LOW,
D to CP
ns
ns
ns
H
n
n
t
CP or C or S Pulse Width
n Dn Dn
W
2.5
t
Recovery Time, C or S to CP
–2.5
–2.0
rec
Dn
Dn
0
0
Note:
6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
7
AC Electrical Characteristics for ACT
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(8)
Symbol
Parameter
Maximum Clock Frequency
Propagation Delay,
V
(V)
Min. Typ. Max.
Min.
Max.
Units
MHz
ns
CC
f
5.0
145
3.0
210
5.5
125
2.5
MAX
t
5.0
5.0
5.0
5.0
9.5
10.5
11.5
13.0.
11.5
PLH
PHL
PLH
PHL
C
or S to Q or Q
Dn
Dn n
n
t
Propagation Delay,
or S to Q or Q
3.0
4.0
3.5
6.0
7.5
6.0
10.0
11.0
10.0
3.0
4.0
3.0
ns
ns
ns
C
Dn
Dn
n
n
t
t
Propagation Delay,
CP to Q or Q
n
n
n
Propagation Delay,
CP to Q or Q
n
n
n
Note:
7. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for ACT
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(9)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Set-up Time, HIGH or LOW,
5.0
1.0
3.0
3.5
ns
S
D to CP
n
n
t
Hold Time, HIGH or LOW,
D to CP
5.0
–0.5
1.0
1.0
ns
H
n
n
t
CP or C or S Pulse Width
5.0
5.0
3.0
5.0
0
6.0
0
ns
ns
W
n
Dn
Dn
t
Recovery Time, C or S to CP
–2.5
rec
Dn
Dn
Note:
8. Voltage range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
Units
C
Input Capacitance
Power Dissipation Capacitance
V
= OPEN
= 5.0V
4.5
pF
pF
IN
CC
C
V
35.0
PD
CC
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
8
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
SEE DETAIL A
1.50
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.50
0.25
X 45°
R0.10
R0.10
GAGE PLANE
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
10
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
6.10
0.45
12.00°
TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
11
Physical Dimensions (Continued)
19.56
18.80
14
8
6.60
6.09
1
7
(1.74)
1.77
8.12
7.62
1.14
0.35
0.20
3.56
3.30
5.33 MAX
0.38 MIN
3.81
3.17
0.58
0.35
8.82
2.54
NOTES: UNLESS OTHERWISE SPECIFIED
THIS PACKAGE CONFORMS TO
A)
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
C)
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
12
TRADEMARKS
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subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
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PDP-SPM™
SyncFET™
®
FPS™
Power220®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
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FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
UniFET™
VCX™
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OPTOPLANAR®
FastvCore™
®
FlashWriter® *
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
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