AD7485BSTZ [ROCHESTER]
1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP48, 7 X 7 MM, ROHS COMPLIANT, MS-026BBC, LQFP-48;
| 型号： | AD7485BSTZ |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP48, 7 X 7 MM, ROHS COMPLIANT, MS-026BBC, LQFP-48 |
| 文件： | 总15页 (文件大小：2059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
1 MSPS, Serial 14-Bit SAR ADC
AD7485
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 1 MSPS
Wide Input Bandwidth: 40 MHz
Excellent DC Accuracy Performance
Flexible Serial Interface
AV
AGND
C
DV
V
DGND
DD
BIAS
DD
DRIVE
2.5V
REFERENCE
Low Power:
REFOUT
REFIN
BUF
80 mW (Full Power) and 3 mW (NAP Mode)
STANDBY Mode: 2 ꢀA Max
Single 5 V Supply Operation
Internal 2.5 V Reference
REFSEL
VIN
14-BIT
ALGORITHMIC
SAR
T/H
Full-Scale Overrange Indication
AD7485
GENERAL DESCRIPTION
MCLK
NAP
STBY
The AD7485 is a 14-bit, high speed, low power, successive-
approximation ADC. The part features a serial interface with
throughput rates up to 1 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input frequencies
in excess of 40 MHz.
TFS
CONTROL
LOGIC AND I/O
REGISTERS
SCO
RESET
CONVST
SDO
SMODE
The conversion process is a proprietary algorithmic successive-
approximation technique. The input signal is sampled and a
conversion is initiated on the falling edge of the CONVST signal.
The conversion process is controlled by an external master
clock. Interfacing is via standard serial signal lines, making the
part directly compatible with microcontrollers and DSPs.
The AD7485 features an on-board 2.5 V reference, but the part can
also accommodate an externally provided 2.5 V reference source.
The nominal analog input range is 0 V to 2.5 V.
The AD7485 also provides the user with overrange indication via a
fifteenth bit. If the analog input range strays outside the 0 V to
2.5 V input range, the fifteenth data bit is set to a logic high.
The AD7485 provides excellent ac and dc performance specifi-
cations. Factory trimming ensures high dc accuracy resulting in
very low INL, DNL, offset, and gain errors.
The AD7485 is powered from a 4.75 V to 5.25 V supply. The
part also provides a VDRIVE pin that allows the user to set the
voltage levels for the digital interface lines. The range for this
VDRIVE pin is from 2.7 V to 5.25 V. The part is housed in a
48-lead LQFP package and is specified over a –40°C to +85°C
temperature range.
The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 80 mW. There are two power-
saving modes: a NAP mode keeps reference circuitry alive for
quick power-up and consumes 3 mW, while a STANDBY mode
reduces power consumption to a mere 10 µW.
A
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax:
www.analog.com
© Analog Devices, Inc.,
781/461-3113
2010
(VDD = 5 V ꢁ 5%, AGND = DGND = 0 V, VREF = External, fSAMPLE = 1 MSPS; all specifica-
AD7485–SPECIFICATIONS1 tions TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Specification
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE2, 3
fIN = 500 kHz Sine Wave
Signal to Noise + Distortion (SINAD)4
76.5
78
77
–90
–95
–92
–88
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
Internal Reference
Total Harmonic Distortion (THD)4
Internal Reference
Peak Harmonic or Spurious Noise (SFDR)4
Intermodulation Distortion (IMD)4
Second-Order Terms
Third-Order Terms
Aperture Delay
–96
–94
10
dB typ
dB typ
ns typ
fIN1 = 95.053 kHz, fIN2 = 105.329 kHz
Full Power Bandwidth
40
3.5
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
14
1
0.5
0.75
0.25
6
0.036
6
0.036
Bits
Integral Nonlinearity4
LSB max
LSB typ
LSB max
LSB typ
LSB max
%FSR max
LSB max
%FSR max
Differential Nonlinearity4
Offset Error4
Guaranteed No Missed Codes to 14 Bits
Gain Error4
ANALOG INPUT
Input Voltage
0
2.5
1
V min
V max
µA max
pF typ
DC Leakage Current
Input Capacitance5
35
REFERENCE INPUT/OUTPUT
VREFIN Input Voltage
2.5
1
V
1% for Specified Performance
External Reference
V
V
V
V
V
V
REFIN Input DC Leakage Current
REFIN Input Capacitance5
REFIN Input Current6
REFOUT Output Voltage
REFOUT Error @ 25°C
REFOUT Error TMIN to TMAX
µA max
pF typ
ꢀA typ
V typ
mV typ
mV max
Ω typ
25
220
2.5
50
100
1
VREFOUT Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VDRIVE –1
0.4
1
V min
V max
µA max
pF typ
5
Input Capacitance, CIN
10
LOGIC OUTPUTS
7
Output High Voltage, VOH7
0.7 × VDRIVE
V min
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
0.3 × VDRIVE
V max
µA max
pF max
10
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
24
100
70
1
MCLKs
ns max
ns max
MSPS max
Sine Wave Input
Full-Scale Step Input
Throughput Rate
A
–2–
REV.
AD7485
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
5
V
5%
VDRIVE
2.7
5.25
V min
V max
IDD
Normal Mode (Static)
Normal Mode (Operational)
NAP Mode
13
17
0.6
2
mA max
mA max
mA max
µA max
µA typ
STANDBY Mode8
0.5
Power Dissipation
Normal Mode (Operational)
NAP Mode
85
3
10
mW max
mW max
µW max
STANDBY Mode8
NOTES
1Temperature ranges as follows: –40°C to +85°C.
2SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3See Typical Performance Characteristics section for analog input circuits used.
4See Terminology.
5Sample tested @ 25°C to ensure compliance.
6Current drawn from external reference during conversion.
7ILOAD = 200 µA.
8Digital input levels at GND or VDRIVE
.
Specifications subject to change without notice.
(VDD = 5 V ꢁ 5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and
TIMING CHARACTERISTICS1
valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
MCLK Period
fMCLK
t1
t2
t3
t4
t5
t6
t7
t8
0.01
40
25
100000
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conversion Time
t1 ꢁ 24
t1 ꢁ 22
10
0.4 ꢁ t1
0.4 ꢁ t1
7
CONVST Low Period (Mode 1)2
CONVST High Period (Mode 1)2
MCLK High Period
0.6 ꢁ t1
0.6 ꢁ t1
MCLK Low Period
CONVST Falling Edge to MCLK Rising Edge
MCLK Rising Edge to MSB Valid
Data Valid before SCO Falling Edge
Data Valid after SCO Falling Edge
CONVST Rising Edge to SDO Three-State
CONVST Low Period (Mode 2)2
CONVST High Period (Mode 2)3
CONVST Falling Edge to TFS Falling Edge
TFS Falling Edge to MSB Valid
TFS Rising Edge to SDO Three-State
TFS Low Period4
15
t9
10
20
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
6
10
10
10
t1 ꢁ 2
30
8
t1 ꢁ 22
10
5
5
TFS High Period4
MCLK Fall Time
MCLK Rise Time
MCLK – SCO Delay
25
25
25
6
NOTES
1All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
2CONVST idling high. See Serial Interface section for further details.
3CONVST idling low. See Serial Interface section for further details.
4TFS can also be tied low in this mode.
Specifications subject to change without notice.
REV.
A
–3–
AD7485
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
ꢂJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
ꢂJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 10°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND . . . . . –0.3 V to VDRIVE + 0.3 V
REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin except Supplies . . . . . . . . . 10 mA
Operating Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD7485
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
AV
36
35
34
33
32
31
30
29
28
27
26
25
SMODE
DD
PIN 1
IDENTIFIER
2
3
C
BIAS
TFS
DGND
DGND
AGND
4
AGND
5
AV
DD
AGND
VIN
V
DRIVE
AD7485
6
DGND
DGND
TOP VIEW
7
(Not to Scale)
8
REFOUT
REFIN
REFSEL
AGND
DV
DD
9
DGND
DGND
DGND
DGND
10
11
12
AGND
13 14 15 16 17 18 19 20 21 22 23 24
A
REV.
–4–
AD7485
PIN FUNCTION DESCRIPTIONS
Pin
No.
1, 5, 13, 46
2
Mnemonic
AVDD
CBIAS
Description
Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin
and AGND.
3, 4, 6, 11, 12,
14, 15, 47, 48
AGND
Power Supply Ground for Analog Circuitry
7
8
VIN
REFOUT
Analog Input. Single-ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF
capacitor must be placed between this pin and AGND.
9
REFIN
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using
an external voltage reference source, the reference voltage should be applied to this pin.
10
REFSEL
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected
from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.
16
17
18
STBY
NAP
Standby Logic Input. When this pin is logic high, the device will be placed in STANDBY mode.
See the Power Saving section for further details.
Nap Logic Input. When this pin is logic high, the device will be placed in a very low power mode.
See the Power Saving section for further details.
Master Clock Input. This is the input for the master clock, which controls the conversion cycle. The fre-
quency of this clock may be up to 25 MHz. Twenty-four clock cycles are required for each conversion.
Ground Reference for Digital Circuitry
MCLK
DGND
19, 20, 22–28
30, 31, 33, 34
37–39, 43, 44
21
SDO
Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It
should be latched into the receiving serial port of the DSP on the falling edge of SCO. The over-
range bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero.
29, 45
32
DVDD
VDRIVE
Positive Power Supply for Digital Circuitry
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
logic of the AD7485 will operate.
35
TFS
Transmit Frame Sync Input. In Serial Mode 2, this pin acts as a framing signal for the serial data
being clocked out on SDO. A falling edge on TFS brings SDO out of three-state and the data starts
to get clocked out on the next rising edge of SCO.
36
40
41
42
SMODE
SCO
Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial
Mode 2. See the Serial Interface section for further details.
Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from
the device. See the Serial Interface section for further details.
Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The
input track/hold amplifier goes from track mode to hold mode and the conversion process commences.
CONVST
RESET
Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a
conversion that may be in progress. Holding this pin low keeps the part in a reset state.
REV.
–5–
A
AD7485
TERMINOLOGY
Total Harmonic Distortion
Integral Nonlinearity
Total harmonic distortion (THD) is the ratio of the rms sum
of the harmonics to the fundamental. For the AD7485, it is
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
defined as:
2
V22 +V32 +V4 +V52 +V62
THD dB = 20 log
(
)
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the
offset error has been adjusted out.
Intermodulation Distortion
Track/Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2,
3, and so on. Intermodulation distortion terms are those for which
neither m nor n is equal to zero. For example, the second-order
terms include (fa + fb) and (fa – fb), while the third-order terms
include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within 1/2 LSB,
after the end of conversion (the point at which the track/hold
returns to track mode).
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
The AD7485 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion
is as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Signal to (Noise + Distortion) = 6.02 N + 1.76 dB
(
)
Thus, for a 14-bit converter this is 86.04 dB.
A
REV.
–6–
Typical Performance Characteristics–AD7485
1.0
0.8
–40
–50
0.6
100ꢂ
0.4
–60
51ꢂ
0.2
–70
0
–0.2
–0.4
–0.6
–0.8
–1.0
10ꢂ
–80
0ꢂ
–90
–100
100
1000
10000
0
4096
8192
12288
16384
INPUT FREQUENCY – kHz
ADC CODE
TPC 1. Typical DNL
TPC 4. THD vs. Input Tone for Different Input Resistances
1.0
0.8
0
100mV p-p SINE WAVE ON SUPPLY PINS
–10
–20
–30
–40
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
–60
–70
–80
0
4096
8192
12288
16384
10
100
1000
ADC CODE
FREQUENCY – kHz
TPC 5. PSRR without Decoupling
TPC 2. Typical INL
80
75
0.0004
0
–0.0004
–0.0008
–0.0012
70
65
–0.0016
–0.0020
10
100
1000
10000
–55
–25
5
35
65
95
125
INPUT FREQUENCY – kHz
TEMPERATURE – ꢃC
TPC 3. SINAD vs. Input Tone (AD8021 Input Circuit)
TPC 6. Reference Error
A
REV.
–7–
AD7485
0
0
fIN = 10.7kHz
SNR = 78.76dB
SNR + D = 78.70dB
THD = –97.10dB
fIN = 507.3kHz
SNR = 78.35dB
SNR + D = 78.33dB
THD = –100.33dB
–20
–20
–40
–60
–80
–40
–60
–80
–100
–120
–140
–100
–120
–140
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY – kHz
FREQUENCY – kHz
TPC 8. 64k FFT Plot with 500 kHz Input Tone
TPC 7. 64k FFT Plot with 10 kHz Input Tone
+V
S
Figure 1 shows the analog input circuit used to obtain the data
for the FFT plot shown in TPC 7. The circuit uses an Analog
Devices AD829 op amp as the input buffer. A bipolar analog
signal is applied as shown and biased up with a stable, low noise
dc voltage connected to the labeled terminal shown. A 220 pF
compensation capacitor is connected between Pin 5 of the AD829
and the analog ground plane. The AD829 is supplied with +12 V
and –12 V supplies. The supply pins are decoupled as close to
the device as possible, with both a 0.1 µF and 10 µF capacitor
connected to each pin. In each case, the 0.1 µF capacitor should be
the closer of the two capacitors to the device. More information
on the AD829 is available on the Analog Devices website.
8
1kꢂ
1kꢂ
100ꢂ
AC
7
+
–
3
2
SIGNAL
V
6
IN
AD829
BIAS
VOLTAGE
4
5
1
–V
S
220pF
150ꢂ
Figure 1. Analog Input Circuit Used for 10 kHz Input Tone
For higher input bandwidth applications, Analog Devices’ AD8021
op amp (also available as a dual AD8022) is the recommended
choice to drive the AD7485. Figure 2 shows the analog input
circuit used to obtain the data for the FFT plot shown in TPC 8.
A bipolar analog signal is applied to the terminal shown and
biased with a stable, low noise dc voltage connected as shown. A
10 pF compensation capacitor is connected between Pin 5 of the
AD8021 and the negative supply. As with the previous circuit,
the AD8021 is supplied with +12 V and –12 V supplies. The
supply pins are decoupled as close to the device as possible with
both a 0.1 µF and 10 µF capacitor connected to each pin. In each
case, the 0.1 µF capacitor should be the closer of the two capaci-
tors to the device. The AD8021 Logic Reference pin is tied to
analog ground and the DISABLE pin is tied to the positive sup-
ply as shown. Detailed information on the AD8021 is available
on the Analog Devices website.
+V
S
8
50ꢂ
AC
7
2
3
+
SIGNAL
V
6
IN
AD8021
220ꢂ
BIAS
VOLTAGE
4
–
5
1
10pF
–V
S
220ꢂ
10pF
Figure 2. Analog Input Circuit Used for 500 kHz Input Tone
A
REV.
–8–
AD7485
CIRCUIT DESCRIPTION
CONVERTER OPERATION
CAPACITIVE
DAC
The AD7485 is a 14-bit algorithmic successive-approximation
analog-to-digital converter based around a capacitive DAC. It pro-
vides the user with track-and-hold, reference, an A/D converter,
and versatile interface logic functions on a single chip. The analog
input signal range that the AD7485 can convert is 0 V to 2.5 V.
The part requires a 2.5 V reference that can be provided from
the part’s own internal reference or an external reference source.
Figure 3 shows a very simplified schematic of the ADC. The
Control Logic, SAR, and Capacitive DAC are used to add and
subtract fixed amounts of charge from the sampling capacitor to
bring the comparator back to a balanced condition.
A
V
IN
+
SW1
CONTROL LOGIC
B
–
SW2
COMPARATOR
AGND
Figure 5. ADC Acquisition Phase
ADC TRANSFER FUNCTION
The output coding of the AD7485 is straight binary. The designed
code transitions occur midway between successive integer LSB
values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size is
COMPARATOR
CAPACITIVE
DAC
V
REF/16384. The nominal transfer characteristic for the
AD7485 is shown in Figure 6.
V
IN
SWITCHES
SAR
V
REF
111...111
111...110
111...000
011...111
CONTROL
LOGIC
CONTROL
INPUTS
1LSB =V
/16384
REF
OUTPUT DATA
14-BIT SERIAL
000...010
000...001
000...000
Figure 3. Simplified Block Diagram
Conversion is initiated on the AD7485 by pulsing the CONVST
input. On the falling edge of CONVST, the track/hold goes from
track to hold mode and the conversion sequence is started.
Conversion time for the part is 24 MCLK periods. Figure 4 shows
the ADC during conversion. When conversion starts, SW2 will
open and SW1 will move to position B causing the comparator to
become unbalanced. The ADC then runs through its successive
approximation routine and brings the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion result is available in the SAR register.
0.5LSB
0V
+V
REF
–1.5LSB
ANALOG INPUT
Figure 6. Transfer Characteristic
POWER SAVING
The AD7485 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition to
this, the AD7485 features two power saving modes, NAP mode
and STANDBY mode. These modes are selected by bringing
either the NAP or STBY pin to a logic high.
When operating the AD7485 with a 25 MHz MCLK in normal,
fully powered mode, the current consumption is 16 mA during
conversion and the quiescent current is 12 mA. Operating at a
throughput rate of 500 kSPS, the conversion time of 960 ns
contributes 38.4 mW to the overall power dissipation.
CAPACITIVE
DAC
A
V
IN
+
SW1
CONTROL LOGIC
960 ns/2 ꢀs × 5V ×16 mA = 38.4 mW
(
)
(
)
B
–
SW2
COMPARATOR
For the remaining 1.04 µs of the cycle, the AD7485 dissipates
31.2 mW of power.
AGND
1.04 ꢀs/2 ꢀs × 5V ×12 mA = 31.2 mW
(
)
(
)
Figure 4. ADC Conversion Phase
Thus the power dissipated during each cycle is:
At the end of conversion, track-and-hold returns to tracking
mode and the acquisition time begins. The track/hold acquisition
time is 70 ns. Figure 5 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A. The comparator
is held in a balanced condition and the sampling capacitor acquires
the signal on VIN.
38.4 mW + 31.2 mW = 69.6 mW
A
REV.
–9–
AD7485
Figure 7 shows the AD7485 conversion sequence operating in
normal mode.
Figures 9 and 10 show a typical graphical representation of
power versus throughput for the AD7485 when in normal and
NAP modes, respectively.
2ꢀs
80
78
76
74
72
70
68
66
64
62
60
CONVST
READ DATA
960ns
CONVERSION
FINISHED
TFS
1.04ꢀs
Figure 7. Normal Mode Power Dissipation
In NAP mode, all the internal circuitry except for the internal
reference is powered down. In this mode, the power dissipation
of the AD7485 is reduced to 3 mW. When exiting NAP mode,
a minimum of 300 ns when using an external reference must be
waited before initiating a conversion. This is necessary to allow
the internal circuitry to settle after power-up and for the track/hold
to properly acquire the analog input signal.
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT – kSPS
If the AD7485 is put into NAP mode after each conversion, the
average power dissipation will be reduced but the throughput
rate will be limited by the power-up time. Using the AD7485 with
a throughput rate of 100 kSPS while placing the part in NAP
mode after each conversion would result in average power dissi-
pation as follows:
Figure 9. Normal Mode, Power vs. Throughput
50
45
40
35
30
25
20
15
10
5
The power-up phase contributes:
300 ns/10 ꢀs × 5V ×12 mA = 1.8 mW
(
)
(
)
The conversion phase contributes:
960 ns/10 ꢀs × 5V ×16 mA = 7.68 mW
(
)
(
)
While in NAP mode for the rest of the cycle, the AD7485 dissipates
only 2.185 mW of power.
8.74 ꢀs/10 ꢀs × 5V × 0.6 mA = 2.622 mW
0
(
)
(
)
0
50
100 150 200 250 300 350 400 450 500
THROUGHPUT – kSPS
Thus the power dissipated during each cycle is:
Figure 10. NAP Mode, Power vs. Throughput
1.8 mW + 7.68 mW + 2.622 mW + 12.1mW
In STANDBY mode, all the internal circuitry is powered down
and the power consumption of the AD7485 is reduced to 10 µW.
Because the internal reference has been powered down, the
power-up time necessary before a conversion can be initiated is
longer. If using the internal reference of the AD7485, the ADC
must be brought out of STANDBY mode 500 ms before a conver-
sion is initiated. Initiating a conversion before the required
power-up time has elapsed will result in incorrect conversion
data. If an external reference source is used and kept powered up
while the AD7485 is in STANDBY mode, the power-up time
required will be reduced to 80 µs.
Figure 8 shows the AD7485 conversion sequence if putting the
part into NAP mode after each conversion.
1.26ꢀs
8.74ꢀs
NAP
CONVST
TFS
300ns
10ꢀs
Figure 8. NAP Mode Power Dissipation
A
REV.
–10–
AD7485
DIGITAL
SUPPLY
4.75V–5.25V
ANALOG
SUPPLY
4.75V–5.25V
SERIAL INTERFACE
The AD7485 has two serial interface modes, selected by the state
of the SMODE pin. In both these modes, the MCLK pin must be
supplied with a clock signal of between 10 kHz and 25 MHz. This
MCLK signal controls the internal conversion process and is also
used to derive the SCO signal. As the AD7485 uses an algorithmic
successive-approximation technique, 24 MCLK cycles are
required to complete a conversion. Due to the error-correcting
operation of this ADC, all bit trials must be completed before the
conversion result is calculated. This results in a single sample
delay in the result that is clocked out.
+
+
10ꢀF
1nF
0.1ꢀF
0.1ꢀF
47ꢀF
0.1ꢀF
V
DV
AV
DRIVE
DD DD
C
ADM809
RESET
SMODE
NAP
BIAS
1nF
REFSEL
REFIN
STBY
AD780 2.5V
REFERENCE
0.47ꢀF
In Serial Mode 1 (Figure 13), the CONVST pin is used to
initiate the conversion and also frame the serial data. When
CONVST is brought low, the SDO line is taken out of three-
state, the overrange bit will be clocked out on the next rising
edge of SCO followed by the 14 data bits (MSB first) and a
trailing zero. CONVST must remain low for 22 SCO pulses to
allow all the data to be clocked out and the conversion in
progress to be completed. When CONVST returns to a logic
high, the SDO line returns to three-state. TFS should be tied to
ground in this mode.
AD7485
CONVST
REFOUT
ꢀC/ꢀP
TFS
SCO
SDO
0.47ꢀF
V
0V TO 2.5V
IN
25MHz
XO
MCLK
Figure 11. Typical Connection Diagram
Driving the CONVST Pin
In Serial Mode 2 (Figure 14), the CONVST pin is used to
initiate the conversion, but the TFS signal is used to frame the
serial data. The CONVST signal can idle high or low in this
mode. Idling high, the CONVST pulsewidth must be between
10 ns and two MCLK periods. Idling low, the CONVST
pulsewidth must be at least 10 ns. TFS must remain low for a
minimum of 22 SCO cycles in this mode but can also be tied
permanently low. If TFS is tied low, the SDO line will always
be driven.
To achieve the specified performance from the AD7485, the
CONVST pin must be driven from a low jitter source. Since the
falling edge on the CONVST pin determines the sampling instant,
any jitter that may exist on this edge will appear as noise when
the analog input signal contains high frequency components.
The relationship between the analog input frequency (fIN), timing
jitter (tj), and resulting SNR is given by the equation below.
1
SNRJITTER(dB) = 10 log
(2π × fIN × tj )2
The relationship between the MCLK and SCO signals is shown
in Figure 15.
As an example, if the desired SNR due to jitter was 100 dB with
a maximum full-scale analog input frequency of 500 kHz, ignor-
ing all other noise sources we get an allowable jitter of 3.18 ps
on the CONVST falling edge. For a 14-bit converter (ideal
SNR = 86.04 dB), the allowable jitter will be greater than the
figure given above; but due consideration needs to be given to the
design of the CONVST circuitry to achieve 14-bit performance
with large analog input frequencies.
Figure 11 shows a typical connection diagram for the AD7485.
In this case, the MCLK signal is provided by a 25 MHz crystal
oscillator module. It could also be provided by the second serial
port of a DSP (e.g., ADSP-2189M) if one were available.
In Figure 11 the VDRIVE pin is tied to DVDD, which results in logic
output levels being either 0 V or DVDD. The voltage applied to
VDRIVE controls the voltage value of the output logic signals. For
example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V
supply, the logic output levels would be either 0 V or 3 V. This
feature allows the AD7485 to interface to 3 V devices while still
enabling the A/D to process signals at 5 V supply.
The maximum slew rate at the input of the ADC should be
limited to 500 V/µs while the conversion is taking place. This
will prevent corruption of the current conversion. In any multi-
plexed application, the channel switching should occur as early
as possible after the first MCLK period.
A
REV.
–11–
AD7485
Board Layout and Grounding
To obtain optimum performance from the AD7485, it is recom-
mended that a printed circuit board with a minimum of three
layers is used. One of these layers, preferably the middle layer,
should be as complete a ground plane as possible to give the
best shielding. The board should be designed in such a way that
the analog and digital circuitry are separated and confined to
certain areas of the board. This practice, along with avoiding
running digital and analog lines close together, should help to
avoid coupling digital noise onto analog lines.
The power supply lines to the AD7485 should be approximately
3 mm wide to provide a low impedance path and reduce the
effects of glitches on the power supply lines. It is vital that good
decoupling is also present. A combination of ferrites and
decoupling capacitors should be used as shown in Figure 11.
Figure 12a
Figure 12b
The decoupling capacitors should be as close to the supply pins
as possible. This is made easier by the use of multilayer boards.
The signal traces from the AD7485 pins can be run on the top
layer while the decoupling capacitors and ferrites mounted on
the bottom layer where the power traces exist. The ground
plane between the top and bottom planes provides excellent
shielding.
Figures 12a–12e show a sample layout of the board area imme-
diately surrounding the AD7485. Pin 1 is the bottom left corner
of the device. Figure 12a shows the top layer where the AD7485
is mounted with vias to the bottom routing layer highlighted.
Figure 12b shows the bottom layer where the power routing is
with the same vias highlighted. Figure 12c shows the bottom
layer silkscreen where the decoupling components are soldered
directly beneath the device. Figure 12d shows the silkscreen
overlaid on the solder pads for the decoupling components, and
Figure 12e shows the top and bottom routing layers overlaid.
The black area in each figure indicates the ground plane present
on the middle layer.
Figure 12c
Figure 12d
Figure 12e
C1-6 : 100 nF, C7–8: 470 nF, C9: 1 nF
L1-4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2)
A
REV.
–12–
AD7485
t2
t4
t3
CONVST
t7
t1
t5
MCLK
SCO
t6
t8
t9
t10
t11
SDO
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 13. Serial Mode 1 (SMODE = 0) Read Cycle
t2
t12
t13
CONVST
t7
t1
t5
MCLK
SCO
t14
t6
t9
t10
SDO
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t15
t16
TFS
t17
t18
Figure 14. Serial Mode 2 (SMODE = 1) Read Cycle
t1
t6
MCLK
SCO
t19
t20
t5
t21
Figure 15. Serial Clock Timing
REV.
A
–13–
AD7485
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
12
0.15
0.05
13
24
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 1. 48-Lead Low Profile Quad Flatpack [LQFP]
7 mm × 7 mm, Very Thin Quad
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ST-48
AD7485BSTZ
−40°C to +85°C
48-Lead Low Profile Quad Flatpack [LQFP]
1 Z = RoHS Compliant Part.
REVISION HISTORY
4/10—Rev. 0 to Rev. A
Changes to Specifications Table .............................................................3
©2002-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02758-0-4/10(A)
Rev. A | Page 14
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