CY2CC910OXI-1 [ROCHESTER]
2CC SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, LEAD FREE, SSOP-20;
| 型号： | CY2CC910OXI-1 |
| 厂家： | 
Rochester Electronics |
| 描述： | 2CC SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, LEAD FREE, SSOP-20 驱动 光电二极管 输出元件 |
| 文件： | 总11页 (文件大小：1047K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2CC910
1:10 Clock Fanout Buffer
Features
Description
■
Low voltage operation
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic and buffers.
■
Full range support:
❐
❐
❐
3.3V
2.5V
1.8V
The Cypress CY2CC910 fanout buffer features one input and 10
outputs. It is ideal for conversion from and to 3.3V, 2.5V, and 1.8V
Designed for Data Communications clock management applica-
tions, the large fanout from a single input reduces loading on the
input clock.
■
Over voltage tolerant input hot swappable
■
■
1:10 Fanout
Drives either a 50-Ohm or 75-Ohm load
Cypress employs the unique AVCMOS type outputs VOI
(Variable Output Impedance) that dynamically adjust for variable
impedance matching, eliminate the need for series damping
resistors, and reduce overall noise.
■
■
■
■
■
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd less than 4 ns)
High speed operation:
❐
200 MHz at1.8V
❐
650 MHz at 2.5V and 3.3V
■
■
Industrial versions available
Available in SSOP package
Logic Block Diagram
3
Q 1
5
Q 2
7
Q 3
VD D
9
4,8
15,20
Q 4
11
Q 5
IN
1
12
INPUT
(AVCMOS)
2,6,10
13,17
Q 6
14
Q 7
16
Q 8
G N D
18
Q 9
19
Q 10
OUTPUT
(AVCMOS)
Cypress Semiconductor Corporation
Document #: 38-07348 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 18, 2010
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CY2CC910
Pin Configuration
Figure 1. 20-Pin SOIP-SSOP
20
19
18
17
16
15
14
13
12
11
VDD
IN
1
2
3
4
5
6
7
8
Q10
Q9
GND
Q1
VDD
Q2
GND
Q8
VDD
Q7
GND
Q3
GND
Q6
VDD
Q4
9
10
Q5
GND
20 pin SOIC/SSOP
Pin Description
Pin Number
1
Pin Name
Description
IN
Input
2,6,10,13,17
G
ND
Ground
4,8,15,20
VDD
Power Supply
Output
3,5,7,9,11,12,14,16,18,19
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10
Maximum Ratings[1]
Storage Temperature:................................. –65°C to +150°C
Ambient Temperature: .................................. –40°C to +85°C
Supply Voltage to Ground Potential
Supply Voltage to Ground Potential
(Outputs only)........................................... –0.5V to VDD + 1V
DC Output Voltage.................................... –0.5V to VDD + 1V
Power Dissipation........................................................ 0.75W
V
CC ...................................................................–0.5V to 4.6V
Input..................................................................–0.5V to 5.8V
Note
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Document #: 38-07348 Rev. *D
Page 2 of 10
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CY2CC910
Variable Output Impedance Control (VOI)
Figure 2. Output Voltage versus Output Current (TA = 25°C)
Pull Up
Pull Down
3.5
3
3.5
3
2.5
2.5
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Ioh (A)
Iol (A)
Vdd = 3.3 V
Vdd = 2.5 V
Vdd = 1.8 V
Vdd = 3.3 V
Vdd = 2.5 V
Vdd = 1.8 V
DC Electrical Characteristics
At 3.3V (See Figure 3)
Parameter
VOH
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Conditions
Min
Typ
Max
Unit
V
VDD = Min., VIN = VIH or VIL IOH = –12 mA 2.3
VDD = Min., VIN = VIH or VIL IOL = 12 mA
3.3
0.2
VOL
VIH
0.5
5.8
V
Guaranteed Logic High
Level
2
V
VIL
IIH
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power-down Disable
Input Hysteresis
Guaranteed Logic Low Level
VDD = Max.
0.8
1
V
VIN = 2.7V
VIN = 0.5V
μA
μA
μA
V
IIL
VDD = Max.
–1
II
VDD = Max., VIN = VDD(Max.)
VDD = Min., IIN = –18 mA
VDD = Max., VOUT = GND
VDD = GND, VOUT = < 4.5V
20
VIK
IOK
OOFF
VH
–0.7
80
–1.2
–50
100
mA
μA
mV
Document #: 38-07348 Rev. *D
Page 3 of 10
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CY2CC910
At 2.5V (See Figure 3)
Parameter
Description
Conditions
Min
1.8
1.6
Typ
Max
Unit
V
VOH
Output High Voltage
VDD = Min., VIN = VIH or VIL
IOH = –7 mA
OH = 12 mA
I
V
VOL
VIH
VIL
IIH
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
VDD = Min., VIN = VIH or VIL
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD = Max.
IOL = 12 mA
0.65
5.0
0.8
1
V
1.6
V
V
VIN = 2.4V
VIN = 0.5V
μA
μA
μA
V
IIL
VDD = Max.
–1
II
VDD = Max., VIN = VDD(Max.)
VDD = Min., IIN = –18 mA
20
VIK
IOK
OOFF
VH
–0.7
80
–1.2
–50
100
Continuous Clamp Current VDD = Max., VOUT = GND
mA
μA
mV
Power Down Disable
Input Hysteresis
VDD = GND, VOUT = < 4.5V
At 1.8V (See Figure 7)
Parameter
VDD
Description
Test Condition[2]
Min
1.71
Max
Unit
Supply Voltage
1.89
4.3
V
V
V
V
V
VIH
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
0.65VDD[1.1]
–0.3
VIL
0.35 VDD[0.6]
VOH
IOH = –2 mA
IOH = 2 mA
VDD – 0.45[1.2]
VOL
0.45
Capacitance
Parameter
Description
Test Conditions
VIN = 0V
Typ
2.5
6.5
Max
Unit
CIN
Input Capacitance
Output Capacitance
pF
pF
COUT
VOUT = 0V
Power Supply Characteristics (See Figure 3)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
ΔICC
Delta ICC Quiescent Power (IDD @ VDD = Max and VIN = VDD) – (IDD
50
μA
Supply Current
@ VDD = Max and VIN = VDD – 0.6V)
ICCD
Dynamic Power Supply
Current
VDD = Max
Input toggling 50% Duty Cycle, Outputs
Open
0.63
mA/
MHz
IC
Total Power Supply Current VDD = Max
Input toggling 50% Duty
Cycle, Outputs Open fL = 40 MHZ
25
mA
Note
2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.
Document #: 38-07348 Rev. *D
Page 4 of 10
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CY2CC910
High Frequency Parametrics
Parameter
Description
Test Conditions
Min Typ
Max
Unit
DJ
Jitter, Deterministic
50% duty cycle tW(50–50)
The “point to point load circuit”
| Output Jitter – Input Jitter |
See Figure 5
20
ps
Fmax
3.3V
Maximum frequency
VDD = 3.3V
50% duty cycle tW(50–50)
Standard Load Circuit.
See Figure 3
See Figure 5
See Figure 5
See Figure 7
See Figure 6
160
650
200
200
250
MHz
50% duty cycle tW(50–50)
The “point to point load circuit”
Fmax
2.5V
Maximum frequency
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V
MHz
MHz
MHz
Fmax
1.8V
Maximum frequency
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7/0.0V VOUT = 1.2V/0.4V
Fmax(20)
Maximum frequency
20% duty cycle tW(20-80)
V
DD = 3.3V
The “point to point load circuit”
VIN = 3.0V/0.0V VOUT = 2.3V/0.4V
tW
3.3V
Minimum pulse
VDD = 3.3V
The “point-to-point load circuit”
VIN = 3.0V/0.0V F = 100 MHz
See Figure 5
See Figure 5
See Figure 7
1
1
1
ns
ns
ns
V
OUT = 2.0V/0.8V
tW
2.5V
Minimum pulse
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V F = 100 MHz
V
OUT = 1.7V/0.7V
tW
1.8V
Minimum pulse
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7V/0.0V VOUT = 1.2V/0.4V
AC Switching Characteristics
At 3.3V (VDD = 3.3V ± 5%, Temperature = –40°C to +85°C)
Parameter
Description
Min
1.5
1.5
Typ
Max Unit
tPLH
tPHL
tR
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time
See Figure 4
2.7
2.7
0.8
0.8
3.5
3.5
ns
ns
V/ns
V/ns
ns
tF
Output Fall Time
tSK(0)
Output Skew: Skew between outputs of the same package (in See Figure 11
phase).
0.2
0.2
0.4
tSK(p)
tSK(t)
Pulse Skew: Skew between opposite transitions of the same
output (tPHL – tPLH).
See Figure 10
ns
ns
Package Skew: Skew between outputs of different packages at See Figure 12
the same power supply voltage, temperature and package type.
At 2.5V (VDD = 2.5V ± 5%, Temperature = –40°C to +85°C)
Parameter
tPLH
Description
Min Typ Max Unit
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time
See Figure 4
1.5
1.5
2.7 3.5
2.7 3.5
0.8
ns
ns
tPHL
tR
V/ns
V/ns
ns
tF
Output Fall Time
0.8
tSK(0)
tSK(p)
Output Skew: Skew between outputs of the same package (in phase). See Figure 11
0.2
Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 10
– tPLH).
0.2
ns
tSK(t)
Package Skew: Skew between outputs of different packages at the same See Figure 12
power supply voltage, temperature and package type.
0.4
ns
Document #: 38-07348 Rev. *D
Page 5 of 10
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CY2CC910
AC Switching Characteristics
At 1.8V(VDD = 1.8V ±5%, Temperature = –40°C to +85°C)
Parameter
Description
Min Typ Max Unit
tPLH
tPHL
tR
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time 20 – 80%
Output Fall Time 20 – 80%
See Figure 8
1.5
1.5
0.2
0.2
2.7 3.5
2.7 3.5
1.5
ns
ns
ns
ns
ns
tF
1.5
tSK(0)
Output Skew: Skew between outputs of the same package (in phase). See Figure 11
0.2
Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 10
– tPLH).
tSK(p)
tSK(t)
0.2
0.4
ns
ns
Package Skew: Skew between outputs of different packages at the same See Figure 12
power supply voltage, temperature and package type.
Parameter Measurement Information: VDD at 3.3V to 2.5V
Figure 3. Load Circuit [3,4,5]
Figure 5. Point to Point Load Circuit[3,4,5]
From Output
Under Test
From Output
Under Test
CL = 3 pF
500 ohm
CL = 50 pF
500 ohm
Figure 6. Voltage Waveforms – Pulse Duration[4]
Figure 4. Voltage Waveforms Propagation Delay Times[6]
0.8VDD
tw(50-50)
0.8VDD
VDD/2
VDD/2
VDD/2
VDD/2
Input
Input
VDD/2
Input
0 V
0 V
tPLH
tPHL
tw(20-80)
0.8VDD
VOH
VOL
VDD/2
VDD/2
Output
0 V
Document #: 38-07348 Rev. *D
Page 6 of 10
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CY2CC910
Parameter Measurement Information: VDD at 8V
Figure 7. Load Circuit [3,4,5]
Figure 9. Voltage Waveforms – Pulse Duration[4]
From Output
Under Test
tw(50-50)
0.9V
1.8V
Input
Input
0.9V
0.9V
CL = 6 pF
500 ohm
0 V
tw(20-80)
1.8V
0 V
Figure 10. Pulse Skew - tsk(p)
Figure 8. Voltage Waveforms Propagation
3V
1.8V
1.5V
0V
0.9V
0.9V
INPUT
Input
0 V
tPHL
tPLH
tPLH
tPHL
VOH
1.5V
VOL
VOH
VOL
0.9V
0.9V
OUTPUT
Output
tsk(P)
=
l
tPHL - tPLH
l
Figure 11. Output Skew - tsk(0)
3V
1.5V
0V
INPUT
tPHL1
tPLH1
VOH
1.5V
OUTPUT 1
OUTPUT 2
VOL
VOH
1.5V
tsk(O)
tsk(O)
VOL
tPLH 2
tPLH 2
tsk(P)
=
l
tPLH2 - tPLH1
l
or tPHL2 - tPHL1
l
Notes
3.
4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z = 50Ω, t < 2.5 ns, t < 2.5 ns.
C
includes probe and jig capacitance.
L
0
R
F
5. The outputs are measured one at a time with one transition per measurement.
6. and T are the same as t
T
.
pd
PLH
PHL
Document #: 38-07348 Rev. *D
Page 7 of 10
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CY2CC910
Figure 12. Package Skew - tsk(t)
3V
1.5V
0V
INPUT
tPHL1
tPLH1
VOH
1.5V
PACKAGE 1 OUTPUT
VOL
VOH
1.5V
tsk(t)
tsk(t)
VOL
PACKAGE 2 OUTPUT
tPLH 2
tPLH 2
tsk(t)
=
l
tPLH2 - tPLH1
l
or tPHL2 - tPHL1
l
Ordering Information
Part Number[7]
Package Type
Product Flow
Status
Pb-free
CY2CC910OXI
20-pin SSOP
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Active
Active
Active
Active
Active
Active
CY2CC910OXIT
CY2CC910OXC
CY2CC910OXCT
CY2CC910OXI-1
CY2CC910OXI-1T
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
Note
7. Devices with part numbers ending with -1 are identical to devices without the -1 suffix. There are no differences in specification.
Document #: 38-07348 Rev. *D
Page 8 of 10
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CY2CC910
Package Drawing
Figure 13. 20-Pin Shrunk Small Outline Package O20
1.14 DIA.
PIN 1 ID.
1.14
1
10
1.14
7.50
8.10
DIMENSIONS IN MILLIMETERS MIN.
MAX.
11
20
.235 MIN.
7.00
7.40
8°
GAUGE PLANE
0.25
SEATING PLANE
0.65 BSC.
4°
2.00
MAX
1.65
1.85
0.55
0.95
1.25 REF.
0.10
0.05
0.21
0.22
0.38
51-85077 *D
Document #: 38-07348 Rev. *D
Page 9 of 10
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CY2CC910
Document History Page
Document Title: CY2CC910 1:10 Clock Fanout Buffer
Document No: 38-07348
Orig. of
Change
Submission
Date
Rev.
ECN NO.
Description of Change
**
114318
119148
TSM
RGL
05/10/02
10/07/02
New Data Sheet
*A
Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics
@3.3V table.
Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Charac-
teristics @2.5V table.
Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical
Characteristics @1.8V table.
*B
*C
404287
RGL
See ECN
10/23/08
Added Lead-free devices for SSOP
2595534 CXQ/PYRS
Added “Status” column to Ordering Information table
Updated Package Diagram 51-85024
Updated template
*D
2896073
CXQ
03/19/10
Updated package diagram
Removed obsolete parts from ordering information table and added
CY2CC910OXI-1, CY2CC910OXI-1T
Removed reference to SOIC packages
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07348 Rev. *D
Revised March 18, 2010
Page 10 of 10
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