CY62256LL-70ZXI [ROCHESTER]
32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28;
| 型号： | CY62256LL-70ZXI |
| 厂家： | 
Rochester Electronics |
| 描述： | 32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62256
256K (32K x 8) Static RAM
Features
Functional Description[1]
• High speed
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and Tri-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
— 55 ns
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Voltage range
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
— 4.5V – 5.5V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
• Available in a Pb-free and non Pb-free standard 28-pin
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1
and 28-pin DIP packages
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
INPUTBUFFER
A
A
A
10
9
8
A
7
6
5
32K × 8
ARRAY
A
A
A
A
A
4
3
2
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY62256
Product Portfolio
Power Dissipation
Operating, ICC
(mA)
Standby, ISB2
VCC Range (V)
Typ.[2]
(µA)
Speed
(ns)
Product
Min.
Max.
Typ.[2]
25
Max.
50
Typ.[2]
Max.
50
5
CY62256L
CY62256LL
CY62256LL
CY62256LL
Com’l/Ind’l
4.5
5.0
5.5
55/70
70
2
Commercial
Industrial
25
50
0.1
0.1
0.1
55/70
55
25
50
10
Automotive
25
50
15
Pin Configurations
21
20
A
CE
I/O
I/O
I/O
I/O
I/O
OE
22
23
0
A
1
19
18
17
16
A
24
7
6
2
Narrow SOIC
DIP
A
3
25
26
A
5
4
3
4
Top View
Top View
TSOP I
Top View
(not to scale)
27
28
1
WE
15
14
13
V
CC
5
6
GND
I/O
A
A
28
1
V
CC
A
28
V
CC
1
2
3
4
5
5
A
2
2
3
27 WE
A
2
27 WE
26
A
12
11
I/O
1
6
A
7
6
I/O
A
8
4
A
26
0
3
A
A
7
A
7
4
4
10
9
A
13
5
A
14
9
10
11
A
A
4
A
25
3
24
A
25
3
24
A
8
8
A
A
6
7
8
A
A
A
A
12
5
A
9
10
5
6
2
9
10
2
A
23
22
A
A
23
22
A
6
1
1
A11
A10
A9
A8
8
9
A12
A13
A14
I/O0
I/O1
I/O2
7
6
A
11
OE
A
0
CE
A
11
OE
A
0
CE
7
7
8
9
10
11
12
13
14
21
20
19
18
17
10
11
12
13
14
15
16
A
21
20
19
18
17
5
4
3
A
8
9
12
12
A
A
TSOP I
Reverse Pinout
Top View
13
13
A
7
A
10
11
12
13
14
A
2
I/O
A6
A5
14
I/O
I/O
14
I/O
7
7
GND
I/O3
1
28
I/O
I/O
6
6
0
0
VCC
(not to scale)
I/O
I/O
I/O
I/O
5
5
1
1
27
26
25
24
23
I/O4
I/O5
I/O6
I/O7
CE
WE
A4
A3
A2
A1
OE
17
18
I/O
16 I/O
15
I/O
16 I/O
15
2
4
3
2
4
3
I/O
GND
I/O
GND
19
20
21
22
A0
Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19,
27
Type
Input
Input/Output I/O0–/O7. Data lines. Used as input or output lines depending on operation
Description
A0–A14. Address Inputs
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
22
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input
data pins
14
28
Ground
GND. Ground for the device
Power Supply VCC. Power supply for the device
Note:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.
A
CC
Document #: 38-05248 Rev. *F
Page 2 of 14
CY62256
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .............................................. –0.5V to +7V
Range
Commercial
Industrial
Ambient Temperature (TA)[4]
VCC
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
–40°C to +85°C
Automotive
–40°C to +125°C
Electrical Characteristics Over the Operating Range
CY62256−55
CY62256−70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = −1.0 mA
VCC = Min., IOL = 2.1 mA
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
2.4
2.2
2.4
V
V
V
VOL
0.4
0.4
VIH
VCC
2.2
VCC
+0.5V
+0.5V
VIL
IIX
Input LOW Voltage
–0.5
–0.5
–0.5
0.8
–0.5
0.8
+0.5
+0.5
50
V
Input Leakage Current GND < VI < VCC
+0.5 –0.5
+0.5 –0.5
50
µA
µA
mA
IOZ
ICC
Output Leakage Current GND < VO < VCC, Output Disabled
VCC Operating Supply VCC = 5.5V,
Current
L
25
25
25
25
IOUT = 0 mA,
f = fMax = 1/tRC
LL
50
50
ISB1
Automatic CE
Power-down Current— VIN > VIH or VIN < VIL,
TTL Inputs
VCC = 5.5V, CE > VIH,
L
0.4
0.3
0.6
0.5
0.4
0.3
0.6
0.5
mA
LL
f = fMax
ISB2
Automatic CE
Power-down Current—
CMOS Inputs
V
CC = 5.5V,
L
2
50
5
2
50
5
µA
CE > VCC − 0.3V
LL - Com’l
LL - Ind’l
LL - Auto
0.1
0.1
0.1
0.1
0.1
VIN > VCC − 0.3V, or
10
15
10
VIN < 0.3V, f = 0
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
6
8
COUT
pF
Thermal Resistance[5]
Parameter
ΘJA
Description
Test Conditions
DIP
SOIC TSOP RTSOP
Unit
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch, 75.61 76.56 93.89
2-layer printed circuit board
93.89
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
43.12 36.07 24.64
24.64
°C/W
Notes:
3. V (min.) = −2.0V for pulse durations of less than 20 ns.
IL
4. T is the “Instant-On” case temperature.
A
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05248 Rev. *F
Page 3 of 14
CY62256
AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
5V
OUTPUT
ALL INPUT PULSES
3.0V
GND
90%
10%
90%
OUTPUT
10%
R2
990Ω
R2
990Ω
100 pF
5 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THEVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
VDR
ICCDR
Description
Conditions[6]
Min.
Typ.[2]
Max.
Unit
V
VCC for Data Retention
Data Retention Current
2.0
L
VCC = 2.0V, CE > VCC − 0.3V,
IN > VCC − 0.3V, or VIN < 0.3V
2
50
5
µA
µA
µA
µA
ns
V
LL - Com’l
LL - Ind’l
LL - Auto
0.1
0.1
0.1
10
10
[5]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[5]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
VCC(min)
VCC(min)
V
V
CC
t
t
R
CDR
CE
Note:
6. No input may exceed V + 0.5V.
CC
Document #: 38-05248 Rev. *F
Page 4 of 14
CY62256
Switching Characteristics Over the Operating Range[7]
CY62256−55
CY62256−70
Parameter
Read Cycle
Description
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
55
5
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
55
70
tOHA
5
tACE
55
25
70
35
tDOE
tLZOE
5
5
0
5
5
0
tHZOE
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
20
20
55
25
25
70
tLZCE
tHZCE
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
tPU
tPD
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
40
25
0
50
30
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
tHD
tHZWE
tLZWE
20
25
5
5
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 100 pF load capacitance.
OL OH
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9. t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE L
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05248 Rev. *F
Page 5 of 14
CY62256
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
t
RC
CE
t
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
t
PU
ICC
ISB
VCC
SUPPLY
CURRENT
50%
50%
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA I/O
NOTE 17
DATA VALID
IN
t
HZOE
Notes:
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05248 Rev. *F
Page 6 of 14
CY62256
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
NOTE 17
DATA VALID
IN
t
t
LZWE
HZWE
Document #: 38-05248 Rev. *F
Page 7 of 14
CY62256
Typical DC and AC Characteristics
CURRENT
STANDBY
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
3.0
2.5
2.0
1.5
1.0
1.4
I
CC
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
I
CC
I
SB
V
IN
= 5.0V
T = 25°C
A
V
V
IN
= 5.0V
= 5.0V
0.5
0.4
CC
0.4
V
V
IN
= 5.0V
= 5.0V
CC
0.2
0.0
0.0
0.2
0.0
I
SB
–0.5
−55
25
105
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T = 25°C
A
V
CC
= 5.0V
T = 25°C
A
V
CC
= 5.0V
40
0.8
20
0
0.9
0.8
0.6
−55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
V
= 5.0V
CC
60
T = 25°C
A
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 38-05248 Rev. *F
Page 8 of 14
CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T = 2 5°C
A
V
IN
= 0.5V
V
= 4.5V
1.0
0.5
10.0
5.0
CC
T = 25°C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High-Z
Mode
Power
Deselect/Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High-Z
)
L
L
X
Write
)
L
H
H
Output Disabled
)
Document #: 38-05248 Rev. *F
Page 9 of 14
CY62256
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
55
CY62256LL−55SNI
CY62256LL−55SNXI
CY62256LL−55ZXI
CY62256LL−55SNE
CY62256LL−55SNXE
CY62256LL−55ZE
CY62256LL−55ZXE
CY62256LL−55ZRXE
CY62256LL−70PC
CY62256LL−70PXC
CY62256L−70SNC
CY62256L−70SNXC
CY62256LL−70SNC
CY62256LL−70SNXC
CY62256LL−70ZC
CY62256LL−70ZXC
CY62256L–70SNI
CY62256L–70SNXI
CY62256LL−70SNI
CY62256LL−70SNXI
CY62256LL−70ZXI
CY62256LL−70ZRI
CY62256LL−70ZRXI
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-free)
51-85071 28-pin TSOP I (Pb-free)
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-free)
51-85071 28-pin TSOP I
Industrial
Automotive
28-pin TSOP I (Pb-free)
51-85074 28-pin Reverse TSOP I (Pb-free)
51-85017 28-pin (600-Mil) Molded DIP
28-pin (600-Mil) Molded DIP (Pb-free)
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-free)
28-pin (300-mil Narrow Body) SNC
70
Commercial
28-pin (300-mil Narrow Body) SNC (Pb-free)
51-85071 28-pin TSOP I
28-pin TSOP I (Pb-free)
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-free)
28-pin (300-mil Narrow Body) SNC
Industrial
28-pin (300-mil Narrow Body) SNC (Pb-free)
51-85071 28-pin TSOP I (Pb-free)
51-85074 28-pin Reverse TSOP I
28-pin Reverse TSOP I (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05248 Rev. *F
Page 10 of 14
CY62256
Package Diagrams
MIN.
MAX.
DIMENSIONS IN INCHES
REFERENCE JEDEC Ms-020
28-pin (600-mil) Molded DIP (51-85017)
14
1
0.530
0.550
15
28
0.070
0.090
SEATING PLANE
0.600
0.625
1.380
1.480
0.140
0.195
0.155
0.200
0.009
0.012
3° MIN.
0.115
0.160
0.015
0.060
0.610
0.700
0.055
0.065
0.090
0.110
0.014
0.022
51-85017-*B
28-pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 38-05248 Rev. *F
Page 11 of 14
CY62256
Package Diagrams (continued)
28-pin Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 38-05248 Rev. *F
Page 12 of 14
CY62256
Package Diagrams (continued)
28-pin Reverse Thin Small Outline Package Type 1 (8x13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05248 Rev. *F
Page 13 of 14
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62256
Document History Page
Document Title: CY62256, 256K (32K x 8) Static RAM
Document Number: 38-05248
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
113454
03/06/02
MGN
Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
*A
*B
115227
116506
05/23/02
09/04/02
GBI
GBI
Changed SN Package Diagram
Added footnote 1
Corrected package description in Ordering Information table
*C
*D
*E
238448 See ECN
344595 See ECN
395936 See ECN
AJU
SYT
SYT
Added Automotive product information
Added Pb-free packages on page# 10
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added CY62256L–70SNXI package in the Ordering Information on Page # 10
*F
493277 See ECN
VKN
Updated Ordering Information table
Document #: 38-05248 Rev. *F
Page 14 of 14
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