CY7C1021CV33-8VCT [ROCHESTER]
Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, SOJ-44;
| 型号： | CY7C1021CV33-8VCT |
| 厂家： | 
Rochester Electronics |
| 描述： | Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, SOJ-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
• Pin- and function-compatible with CY7C1021BV33
• High speed
— tAA = 8 ns (Commercial & Industrial)
— tAA = 12 ns (Automotive)
• CMOS for optimum speed/power
• Low active power: 360 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
• Also available in Lead-Free 44-pin TSOP II, 400-mil SOJ
packages
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in standard 44-pin TSOP
Type II, 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
7
6
5
4
64K x 16
A
A
A
I/O –I/O
RAM Array
512 X 2048
1
8
3
2
1
0
I/O –I/O
9
16
A
A
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05132 Rev. *E
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised March 7, 2005
CY7C1021CV33
Selection Guide
CY7C1021CV33 CY7C1021CV33- CY7C1021CV33- CY7C1021CV33-
-8
10
10
90
-
12
12
85
90
5
15
15
80
-
Unit
ns
Maximum Access Time
8
Maximum Operating Current
95
-
mA
mA
mA
mA
Automotive
Automotive
Maximum CMOS Standby
Current
5
5
5
-
-
10
-
Pin Configurations
SOJ / TSOP II
Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
OE
A
1
BHE
BLE
I/O
A
0
CE
I/O
7
1
16
37
36
35
34
33
I/O2
8
I/O
I/O
15
14
13
I/O
9
3
10
11
12
13
I/O
I/O
4
V
V
SS
CC
V
V
SS
CC
32
31
30
29
28
I/O
I/O
I/O
5
12
11
I/O
14
15
16
6
I/O
I/O
7
10
9
I/O
I/O
8
WE 17
NC
18
27
26
25
A
A
8
15
19
A
A
14
9
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
48-ball FBGA
(Top View)
1
2
4
3
5
6
A
A
A
NC
I/O
OE
BLE
0
1
2
A
B
C
I/O
A
A
BHE
CE
8
4
3
0
I/O
10
A
A
6
I/O
I/O
I/O
1
5
9
2
I/O
A
I/O
V
CC
V
NC
NC
3
D
E
F
SS
7
11
NC
V
CC
V
SS
I/O
I/O
12
4
I/O
A
A
I/O
I/O
I/O
6
14
15
5
13
14
A
I/O
7
A
G
H
I/O
NC
WE
13
12
15
A
A
A
A
NC
NC
10
9
11
8
Document #: 38-05132 Rev. *E
Page 2 of 13
CY7C1021CV33
Pin Definitions
SOJ, TSOP
Pin Number
BGA Pin
Number
Pin Name
I/O Type
Description
Address Inputs used to select one of the address locations.
A0–A15
1–5, 18–21, A3, A4, A5,
24–27, 42–44 B3, B4, C3,
C4, D4, H2,
Input
H3, H4, H5,
G3, G4, F3,
F4
[2]
I/O0–I/O15
7–10, 13–16, B6, C6, C5, Input/Output Bidirectional Data I/O lines. Used as input or output lines
29–32, 35–38 D5, E5, F5,
F6, G6, B1,
C1, C2, D2,
E2, F2, F1,
G1
depending on operation.
NC
22, 23, 28 A6, D3, E3, No Connect No Connects. Not connected to the die.
E4, G2, H1,
H6
WE
CE
17
6
G5
Input/Control Write Enable Input, active LOW. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
B5
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
OE
39, 40
41
A1, B2
A2
Input/Control Byte Write Select Inputs, active LOW. BLE controls I/O8–I/O1,
BHE controls I/O16–I/O9.
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data
pins.
VSS
VCC
12,34
11,33
D1, E6
D6, E1
Ground
Ground for the device. Should be connected to ground of the
system.
Power Supply Power Supply inputs to the device.
Note:
2. I/O –I/O for SOJ/TSOP and I/O –I/O for BGA packages.
1
16
0
15
Document #: 38-05132 Rev. *E
Page 3 of 13
CY7C1021CV33
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature (TA)
VCC
0°C to +70°C
3.3V ± 10%
3.3V ± 10%
3.3V ± 10%
DC Voltage Applied to Outputs
in High-Z State[3] ......................................–0.5V to VCC+0.5V
–40°C to +85°C
–40°C to +125°C
DC Input Voltage[3]...................................–0.5V to VCC+0.5V
Automotive
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15
Parameter Description
Test Conditions
Output HIGH VCC = Min.,
Voltage OH = –4.0 mA
Output LOW VCC = Min.,
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
VOL
VIH
VIL
2.4
2.4
2.4
2.4
V
V
V
V
I
0.4
0.4
0.4
0.4
Voltage
IOL = 8.0 mA
Input HIGH
Voltage
2.0
–0.3
−1
VCC
+ 0.3
2.0
−0.3
−1
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
–0.3
–1
VCC
+ 0.3
Input LOW
Voltage[3]
0.8
0.8
+1
–0.3
0.8
0.8
+1
IIX
Input Load
Current
GND < VI <
VCC
Com’l / Ind’l
Automotive
Com’l / Ind’l
Automotive
+1
–1
–12
–1
+1
+12
+1
µA
µA
µA
µA
IOZ
Output
Leakage
GND < VI <
VCC,
Output
−1
+1
−1
+1
-
–1
-
+1
-
-
-
-
–12
+12
Current
Disabled
IOS
Output Short VCC = Max.,
-300
−300
–300
–300 mA
Circuit
VOUT = GND
Current[4]
ICC
VCC
VCC = Max., Com’l / Ind’l
95
-
90
-
85
90
80
-
mA
mA
Operating
Supply
Current
IOUT = 0 mA,
Automotive
f = fMAX
1/tRC
=
ISB1
Automatic CE Max. VCC
Power-Down CE > VIH
,
Com’l / Ind’l
Automotive
15
-
15
-
15
20
15
-
mA
mA
Current
VIN > VIH or
—TTL Inputs VIN < VIL,
f = fMAX
ISB2
Automatic CE Max. VCC
Power-Down CE > VCC
,
Com’l / Ind’l
Automotive
5
-
5
-
5
5
-
mA
mA
–
10
Current
—CMOS
Inputs
0.3V, VIN >
VCC – 0.3V,
or VIN < 0.3V,
f = 0
Notes:
3. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05132 Rev. *E
Page 4 of 13
CY7C1021CV33
Thermal Resistance[5]
48-ball
FBGA
44-lead
TSOP-II
Parameter
Description
Test Conditions
44-lead SOJ
Unit
ΘJA
Thermal Resistance Test conditions follow standard test
(Junction to Ambient) methods and procedures for
95.32
65.06
76.92
°C/W
measuring thermal impedance, per
EIA / JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
10.68
34.21
15.86
°C/W
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
CC = 3.3V
8
8
pF
pF
V
COUT
AC Test Loads and Waveforms[6]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
50Ω
30 pF*
R2
351Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
351Ω
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05132 Rev. *E
Page 5 of 13
CY7C1021CV33
Switching Characteristics Over the Operating Range[7]
1021CV33-8
1021CV33-10 1021CV33-12 1021CV33-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
10
3
Max.
Min.
12
3
Max.
Min.
15
3
Max. Unit
Read Cycle Time
8
3
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
tACE
8
5
10
5
12
6
15
7
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
4
4
5
5
6
6
7
7
tHZCE
[10]
tPU
[10]
tPD
8
5
10
5
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[11]
tWC
0
0
0
0
4
5
6
7
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
8
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[8]
5
6
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High-Z[8, 9]
4
5
6
7
tBW
Byte Enable to End of Write
6
7
8
9
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. At any given temperature and voltage condition, t is less than t , t is less than t , and t is less than t for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
9. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state
HZOE HZBE HZCE
HZWE
voltage.
10. This parameter is guaranteed by design and is not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a
Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the Write.
Document #: 38-05132 Rev. *E
Page 6 of 13
CY7C1021CV33
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BHE = V .
IL
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05132 Rev. *E
Page 7 of 13
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
15. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05132 Rev. *E
Page 8 of 13
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High-Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High-Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
Data In
Data In
High-Z
High-Z
High-Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
Selected, Outputs Disabled
Selected, Outputs Disabled
)
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1021CV33-8VC
Package Type
8
V34
Z44
44-lead (400-Mil) Molded SOJ
44-lead TSOP Type II
48-ball FBGA
Commercial
CY7C1021CV33-8ZC
CY7C1021CV33-8BAC
CY7C1021CV33-10VC
CY7C1021CV33-10VI
CY7C1021CV33-10ZC
CY7C1021CV33-10ZI
CY7C1021CV33-10BAC
CY7C1021CV33-10BAI
BA48A
V34
10
44-lead (400-Mil) Molded SOJ
44-lead (400-Mil) Molded SOJ
44-lead TSOP Type II
44-lead TSOP Type II
48-ball FBGA
Commercial
Industrial
V34
Commercial
Z44
Industrial
Commercial
BA48A
Industrial
Document #: 38-05132 Rev. *E
Page 9 of 13
CY7C1021CV33
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
12
CY7C1021CV33-12VC
CY7C1021CV33-12VI
CY7C1021CV33-12VE
CY7C1021CV33-12ZC
CY7C1021CV33-12ZI
CY7C1021CV33-12ZSE
CY7C1021CV33-12BAC
CY7C1021CV33-12BAI
CY7C1021CV33-12BAE
CY7C1021CV33-15VC
CY7C1021CV33-15VI
CY7C1021CV33-15ZC
CY7C1021CV33-15ZI
CY7C1021CV33-15BAC
CY7C1021CV33-15BAI
CY7C1021CV33-8VXC
CY7C1021CV33-8ZXC
CY7C1021CV33-8BAXC
CY7C1021CV33-10VXC
CY7C1021CV33-10VXI
CY7C1021CV33-10ZXC
CY7C1021CV33-10ZXI
CY7C1021CV33-10BAXC
CY7C1021CV33-10BAXI
CY7C1021CV33-12VXC
CY7C1021CV33-12VXI
CY7C1021CV33-12VXE
CY7C1021CV33-12ZXC
CY7C1021CV33-12ZXI
CY7C1021CV33-12ZSXE
CY7C1021CV33-12BAXC
CY7C1021CV33-12BAXI
CY7C1021CV33-12BAXE
CY7C1021CV33-15VXC
CY7C1021CV33-15VXI
CY7C1021CV33-15ZXC
CY7C1021CV33-15ZXI
CY7C1021CV33-15BAXC
CY7C1021CV33-15BAXI
V34
44-pin (400-Mil) Molded SOJ
Commercial
Industrial
Automotive
Commercial
Industrial
Z44
44-pin TSOP Type II
48-ball FBGA
Automotive
Commercial
Industrial
BA48A
Automotive
Commercial
Industrial
15
V34
Z44
44-pin (400-Mil) Molded SOJ
44-pin TSOP Type II
48-ball FBGA
Commercial
Industrial
BA48A
Commercial
Industrial
8
V34
Z44
44-lead (400-Mil) Molded SOJ (Pb-Free)
44-lead TSOP Type II (Pb-Free)
48-ball FBGA (Pb-Free)
Commercial
Commercial
Commercial
BA48A
V34
10
44-lead (400-Mil) Molded SOJ (Pb-Free)
44-lead (400-Mil) Molded SOJ (Pb-Free)
44-lead TSOP Type II (Pb-Free)
44-lead TSOP Type II (Pb-Free)
48-ball FBGA (Pb-Free)
Commercial
Industrial
V34
Commercial
Industrial
Z44
Z44
BA48A
Commercial
Industrial
12
V34
V34
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-lead TSOP Type II (Pb-Free)
44-lead TSOP Type II (Pb-Free)
44-pin TSOP Type II (Pb-Free)
48-ball FBGA (Pb-Free)
Commercial
Industrial
V34
Automotive
Commercial
Industrial
Z44
Z44
Z44
Automotive
Commercial
Industrial
BA48A
BA48A
BA48A
V34
48-ball FBGA (Pb-Free)
48-ball FBGA (Pb-Free)
Automotive
Commercial
Industrial
15
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-lead TSOP Type II (Pb-Free)
44-lead TSOP Type II (Pb-Free)
48-ball FBGA (Pb-Free)
V34
Z44
Commercial
Industrial
Z44
BA48A
Commercial
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05132 Rev. *E
Page 10 of 13
CY7C1021CV33
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05132 Rev. *E
Page 11 of 13
CY7C1021CV33
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05132 Rev. *E
Page 12 of 13
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33 1-Mbit (64K x 16) Static RAM
Document Number: 38-05132
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109472
115044
Description of Change
12/06/01
05/08/02
HGK
HGK
New Data Sheet
*A
Ram7 version C4K x 16 Async.
Remove “Preliminary”
*B
*C
*D
115808
120413
238454
06/25/02
10/31/02
See ECN
HGK
DFP
RKF
ISB1 and ICC values changed
Updated BGA pin E4 to NC.
1) Added Automotive Specs to Datasheet
2) Added Pb-Free devices in the Ordering information
*E
334398
See ECN
SYT
Added Pb-Free on page# 9 and 10
Document #: 38-05132 Rev. *E
Page 13 of 13
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