CY7C1021CV33-8VXCT [CYPRESS]
Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44;
| 型号： | CY7C1021CV33-8VXCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description
■ Temperature ranges
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from IO pins (IO1 through IO8), is written into the
location specified on the address pins (A0 through A15). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO9 through
IO16) is written into the location specified on the address pins (A0
through A15).
■ Pin and function compatible with CY7C1021BV33
■ High speed
❐ tAA = 8 ns (Commercial & Industrial)
❐ tAA = 12 ns (Automotive-E)
■ CMOS for optimum speed and power
■ Low active power: 325 mW (max)
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO1 to IO8. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO9 to IO16. For more information, see the
“Truth Table” on page 9 for a complete description of Read and
Write modes.
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ AvailableinPb-freeandnonPb-free44-pin400MilSOJ, 44-pin
TSOP II and 48-Ball FBGA packages
The input and output pins (IO1 through IO16) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
IO0–IO7
RAM Array
A3
A2
A1
A0
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 11, 2007
CY7C1021CV33
Selection Guide
-8
8
-10
10
-12
12
-15
15
80
80
Unit
ns
Maximum Access Time
Maximum Operating Current
Comm’l/Ind’l
Automotive-A
Automotive-E
Comm’l/Ind’l
Automotive-A
Automotive-E
95
90
85
mA
mA
mA
mA
mA
mA
90
5
Maximum CMOS Standby Current
5
5
5
5
10
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II [1]
Figure 2. 48-Ball FBGA Pinout [1]
A
A
A
1
2
3
4
6
5
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
A
6
A
7
OE
BHE
BLE
IO
16
IO
A
A
A
2
1
A0
A1
A2
NC
A
B
C
OE
BLE
0
A4
A6
A3
A5
IO8 BHE
CE
IO2
IO3
IO0
IO1
CE
IO
1
IO
IO10
IO11
IO9
VSS
VCC
2
15
IO
3
9
IO
14
IO
IO
4
10
11
12
13
14
15
16
13
VCC
A7
NC
D
E
F
NC
V
V
SS
CC
V
SS
V
CC
IO
IO
11
IO
10
IO4 VSS
IO12 NC
IO
5
6
7
8
12
IO
IO
IO
A14
A15
IO5
WE
IO6
IO7
NC
IO14 IO13
IO15 NC
IO
9
NC
WE 17
A12 A13
G
H
A
A
A
A
18
19
20
A
8
15
14
13
A
9
A
10
A9
A10 A11
A8
NC
12 21
A
11
NC
22
NC
Note
1. NC pins are not connected on the die.
Document Number: 38-05132 Rev. *H
Page 2 of 14
CY7C1021CV33
Pin Definitions
SOJ, TSOP
Pin Number
BGA Pin
Number
Pin Name
IO Type
Description
Address Inputs. Used to select one of the address locations.
A0–A15
1–5, 18–21, A3,A4,A5,B3,
24–27, 42–44 B4, C3, C4,
D4, H2, H3,
Input
H4, H5, G3,
G4, F3, F4
[2]
IO1–IO16
7–10, 13–16,
B6, C6, C5, Input or Output Bidirectional DataIOlines. Used as input or output lines depending
29–32, 35–38 D5, E5, F5, F6,
G6, B1, C1,
on operation.
C2, D2, E2,
F2, F1, G1
NC
WE
22, 23, 28
A6, D3, E3,
E4, G2, H1, H6
No Connect No Connects. Not connected to the die.
17
6
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
OE
40, 39
41
B2, A1
A2
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9,
BLE controls IO8 – IO1.
Input or
Control
Output Enable, Active LOW. Controls the direction of the IO pins.
When LOW, the IO pins are allowed to behave as outputs. When
deasserted HIGH, the IO pins are tri-stated and act as input data
pins.
VSS
VCC
12, 34
11, 33
D1, E6
D6, E1
Ground
Ground for the device. Connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Note
2. IO –IO for SOJ/TSOP and IO –IO for BGA packages.
1
16
0
15
Document Number: 38-05132 Rev. *H
Page 3 of 14
CY7C1021CV33
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch Up Current..................................................... >200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient
Temperature (TA)
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Range
VCC
Supply Voltage on VCC Relative to GND[3].....–0.5V to +4.6V
Commercial
0°C to +70°C
3.3V ± 10%
Industrial
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
DC Voltage Applied to Outputs
in High Z State[3]...................................... –0.5V to VCC+0.5V
Automotive-A
Automotive -E
DC Input Voltage[3] .................................. –0.5V to VCC+0.5V
Current into Outputs (LOW)......................................... 20 mA
Electrical Characteristics
Over the Operating Range
-8
-10
-12
-15
Parameter
Description
Test Conditions
Unit
Min Max Min Max Min Max Min Max
2.4 2.4 2.4 2.4
VOH
Output HIGH Voltage VCC = Min,
V
I
OH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min,
OL = 8.0 mA
0.4
0.4
0.4
0.4
V
V
I
Input HIGH
Voltage
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC
+ 0.3 + 0.3 + 0.3 + 0.3
VIL
IIX
Input LOW Voltage[3]
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
V
Input Leakage
Current
GND < VI < VCC
Com’l/Ind’l
Auto-A
–1
+1
+1
95
15
–1
+1
+1
90
15
–1
+1
–1
–1
+1
+1
µA
Auto-E
–12 +12
–1 +1
IOZ
Output Leakage
Current
GND < VI < VCC
,
Com’l/Ind’l
Auto-A
–1
–1
–1
–1
+1
+1
µA
mA
mA
Output disabled
Auto-E
–12 +12
85
ICC
VCC Operating
Supply Current
VCC = Max,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l/Ind’l
Auto-A
80
80
Auto-E
90
15
ISB1
Automatic CE Power Max VCC
Down Current —TTL CE > VIH
Inputs
,
Com’l/Ind’l
Auto-A
15
15
VIN > VIH or
IN < VIL, f = fMAX
Auto-E
20
5
V
ISB2
Automatic CE Power Max VCC
Down Current —
CMOS Inputs
,
Com’l/Ind’l
Auto-A
5
5
5
5
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Auto-E
10
Note
3.
V (min) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL IH CC
Document Number: 38-05132 Rev. *H
Page 4 of 14
CY7C1021CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max
8
Unit
pF
COUT
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
SOJ
TSOP II
FBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
65.06
76.92
95.32
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
34.21
15.86
10.68
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
50Ω
30 pF*
R2
351Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
351Ω
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Note
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown
in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document Number: 38-05132 Rev. *H
Page 5 of 14
CY7C1021CV33
Switching Characteristics
Over the Operating Range [5]
-8
-10
-12
-15
Parameter
Description
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle
[6]
tpower
VCC(Typical) to the First Access
Read Cycle Time
100
8
100
10
100
12
100
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
8
10
12
15
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
3
3
3
3
8
5
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
0
3
0
4
4
5
5
6
6
7
7
[9]
tPU
[9]
tPD
8
5
10
5
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[10]
tWC
0
0
0
0
4
5
6
7
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
8
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
5
6
tHD
0
0
0
tLZWE
tHZWE
tBW
3
3
3
WE LOW to High Z[7, 8]
4
5
6
7
Byte Enable to End of Write
6
7
8
9
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
6. gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
7. At any given temperature and voltage condition, t for any given device.
LZWE
t
POWER
CC
is less than t
, t
is less than t
, and t
is less than t
HZCE
LZCE HZOE
LZOE
HZWE
8.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms. Transition is measured ±500 mV from
HZOE HZBE HZCE
HZWE
steady state voltage.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The
transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
Document Number: 38-05132 Rev. *H
Page 6 of 14
CY7C1021CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
ICC
ISB
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes
11. Device is continuously selected. OE, CE, BHE, and/or BLE = V .
IL
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05132 Rev. *H
Page 7 of 14
CY7C1021CV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Notes
14. Data IO is high impedance if OE, BHE, and/or BLE= V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05132 Rev. *H
Page 8 of 14
CY7C1021CV33
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Truth Table
CE
H
OE
X
WE
X
BLE
X
BHE
X
IO1 – IO8 IO9 – IO16
High Z High Z
Data Out Data Out Read – All Bits
Data Out High Z Read – Lower Bits Only
Data Out Read – Upper Bits Only
Mode
Power
Power Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
L
L
)
L
H
L
)
H
L
High Z
Data In
Data In
High Z
High Z
High Z
)
L
X
L
L
Data In
High Z
Data In
High Z
High Z
Write – All Bits
)
L
H
L
Write – Lower Bits Only
Write – Upper Bits Only
)
H
X
)
L
L
H
X
H
X
X
Selected, Outputs Disabled
Selected, Outputs Disabled
)
H
H
)
Document Number: 38-05132 Rev. *H
Page 9 of 14
CY7C1021CV33
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY7C1021CV33-8VXC
CY7C1021CV33-8ZXC
CY7C1021CV33-8BAXC
CY7C1021CV33-10VC
CY7C1021CV33-10VXC
CY7C1021CV33-10ZXC
CY7C1021CV33-10ZI
CY7C1021CV33-10ZXI
CY7C1021CV33-10BAXI
CY7C1021CV33-12VC
CY7C1021CV33-12VXC
CY7C1021CV33-12ZXC
CY7C1021CV33-12VI
CY7C1021CV33-12VXI
CY7C1021CV33-12ZXI
CY7C1021CV33-12BAI
CY7C1021CV33-12BAXI
CY7C1021CV33-12VE
CY7C1021CV33-12VXE
CY7C1021CV33-12ZSE
CY7C1021CV33-12ZSXE
CY7C1021CV33-12BAE
CY7C1021CV33-15VXC
CY7C1021CV33-15ZXC
CY7C1021CV33-15ZI
CY7C1021CV33-15ZXI
CY7C1021CV33-15BAXI
CY7C1021CV33-15ZSXA
8
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
Commercial
51-85096 48-ball FBGA (Pb-free)
51-85082 44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II
10
12
Commercial
Industrial
44-pin TSOP Type II (Pb-free)
51-85096 48-ball FBGA (Pb-free)
51-85082 44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85082 44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85096 48-ball FBGA
Commercial
Industrial
48-ball FBGA (Pb-free)
51-85082 44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II
Automotive-E
44-pin TSOP Type II (Pb-free)
51-85096 48-ball FBGA
15
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II
Commercial
Industrial
44-pin TSOP Type II (Pb-free)
51-85096 48-ball FBGA (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
Automotive-A
Document Number: 38-05132 Rev. *H
Page 10 of 14
CY7C1021CV33
Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ
51-85082-*B
Document Number: 38-05132 Rev. *H
Page 11 of 14
CY7C1021CV33
Package Diagrams (continued)
Figure 10. 44-Pin Thin Small Outline Package Type II
51-85087-*A
Document Number: 38-05132 Rev. *H
Page 12 of 14
CY7C1021CV33
Package Diagrams (continued)
Figure 11. 48-Ball FBGA (7 x 7 x 1.2 mm)
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
Ø0.05 M C
PIN 1 CORNER
ꢀLASER MARKX
Ø0.25 M C A B
Ø0.30 0.05ꢀ4ꢁ8X
1
2
3
4
5
6
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
F
E
F
G
H
G
H
A
A
1.ꢁ75
0.75
3.75
B
7.00 0.10
7.00 0.10
B
0.15ꢀ48X
SEATING PLANE
C
1.20 MA8.
51-85096-*G
Document Number: 38-05132 Rev. *H
Page 13 of 14
CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05132
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
**
109472 12/06/01
115044 05/08/02
HGK
HGK
New datasheet
*A
Ram7 version C4K x 16 Async
Removed “Preliminary”
*B
*C
*D
115808 06/25/02
120413 10/31/02
238454 See ECN
HGK
DFP
RKF
I
SB1 and ICC values changed
Updated BGA pin E4 to NC
1) Added Automotive Specifications to datasheet
2) Added Pb-free devices in the Ordering Information
*E
*F
334398 See ECN
493565 See ECN
SYT
NXR
Added Pb-free on page 9 and 10
Added Automotive-A operating range
Corrected typo in the Pin Definition table
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
*G
*H
563963 See ECN
VKN
Added tPOWER specification in the AC Switching Characteristics table
Added footnote 8
1390863 See ECN VKN/AESA Corrected TSOP II package outline
© Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05132 Rev. *H
Revised October 11, 2007
Page 14 of 14
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