CY7C1021CV33_06 [CYPRESS]
1-Mbit (64K x 16) Static RAM; 1兆位（ 64K ×16 ）静态RAM
| 型号： | CY7C1021CV33_06 |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64K x 16) Static RAM |
| 文件： | 总13页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Pin- and function-compatible with CY7C1021BV33
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
— tAA = 8 ns (Commercial & Industrial)
— tAA = 12 ns (Automotive)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
• CMOS for optimum speed/power
• Low active power: 345 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin 400-Mil SOJ
44-pin TSOP II and 48-ball FBGA packages
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in 44-pin 400-Mil wide SOJ,
44-pin TSOP II and 48-ball FBGA packages.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
I/O1–I/O8
RAM Array
A3
A2
A1
A0
I/O9–I/O16
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05132 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 6, 2006
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CY7C1021CV33
Selection Guide
-8
8
-10
10
90
-12
12
-15
15
80
80
Unit
ns
Maximum Access Time
Maximum Operating Current Comm’l/Ind’l
Automotive-A
95
85
mA
mA
mA
mA
mA
mA
Automotive-E
90
5
Maximum CMOS Standby
Current
Comm’l/Ind’l
Automotive-A
Automotive-E
5
5
5
5
10
Pin Configurations[2]
SOJ/TSOP II
Top View
48-ball FBGA
Top View
A
A
A
A
A
7
OE
BHE
BLE
I/O
16
I/O
I/O
14
I/O
1
2
3
4
5
6
7
8
44
4
3
5
6
1
4
3
2
5
6
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
2
1
A
A
A
2
NC
I/O
OE
BLE
0
1
A
B
C
0
I/O
A
A
BHE
CE
CE
I/O
8
4
3
0
I/O
1
2
3
I/O
I/O
15
I/O
10
A
A
6
I/O
I/O
1
5
9
2
9
I/O
V
10
11
12
13
14
15
16
4
13
I/O
A
I/O
V
CC
V
NC
NC
3
D
E
F
SS
7
11
V
CC
SS
V
SS
I/O
V
CC
I/O
I/O
11
I/O
10
NC
5
V
V
SS
I/O
I/O
4
12
CC
12
I/O
6
I/O
I/O
7
8
I/O
A
A
I/O
5
I/O
I/O
6
14
15
13
14
I/O
9
WE 17
A
NC
A
A
A
I/O
7
18
G
H
15
I/O
NC
WE
8
13
12
15
A
A
A
A
19
20
21
22
14
13
12
9
A
10
A
A
A
A
NC
NC
10
9
11
8
A
11
NC
NC
Note:
2. NC pins are not connected on the die.
Document #: 38-05132 Rev. *G
Page 2 of 13
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CY7C1021CV33
Pin Definitions
SOJ, TSOP
Pin Number
BGA Pin
Number
Pin Name
I/O Type
Description
Address Inputs used to select one of the address locations.
A0–A15
1–5, 18–21, A3, A4, A5,
24–27, 42–44 B3, B4, C3,
C4, D4, H2,
Input
H3, H4, H5,
G3, G4, F3,
F4
[3]
I/O0–I/O15
7–10, 13–16, B6, C6, C5, Input/Output Bidirectional Data I/O lines. Used as input or output lines
29–32, 35–38 D5, E5, F5,
depending on operation.
F6, G6, B1,
C1, C2, D2,
E2, F2, F1,
G1
NC
22, 23, 28 A6, D3, E3, No Connect No Connects. Not connected to the die.
E4, G2, H1,
H6
WE
CE
17
6
G5
Input/Control Write Enable Input, active LOW. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
B5
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
OE
40, 39
41
B2, A1
A2
Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9,
BLE controls I/O8–I/O1.
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
VSS
VCC
12,34
11,33
D1, E6
D6, E1
Ground
Ground for the device. Should be connected to ground of the
system.
Power Supply Power Supply inputs to the device.
Note:
3. I/O –I/O for SOJ/TSOP and I/O –I/O for BGA packages.
1
16
0
15
Document #: 38-05132 Rev. *G
Page 3 of 13
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CY7C1021CV33
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[4] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature (TA)
VCC
0°C to +70°C
3.3V ± 10%
DC Voltage Applied to Outputs
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
in High-Z State[4] ......................................–0.5V to VCC+0.5V
Automotive-A
Automotive -E
DC Input Voltage[4]...................................–0.5V to VCC+0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
-8
-10
-12
-15
Parameter
Description
Test Conditions
VCC = Min.,
IOH = –4.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH
Voltage
2.4
2.4
2.4
2.4
V
VOL
VIH
VIL
IIX
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
V
Input HIGH
Voltage
2.0
VCC
+ 0.3
2.0
−0.3
−1
VCC
+ 0.3
2.0
–0.3
–1
VCC
+ 0.3
2.0
VCC
+ 0.3
V
Input LOW
Voltage[4]
–0.3 0.8
0.8
+1
0.8
+1
–0.3
0.8
V
Input Leakage
Current
GND < VI < VCC Com’l/Ind’l −1
+1
+1
95
15
–1
–1
+1
+1
µA
Auto-A
Auto-E
–12
–1
+12
+1
IOZ
Output Leakage GND < VI < VCC, Com’l/Ind’l −1
Current
−1
+1
90
15
–1
–1
+1
+1
µA
Output Disabled
Auto-A
Auto-E
–12
+12
85
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l/Ind’l
Auto-A
80
80
mA
mA
Auto-E
90
15
ISB1
Automatic CE
Power-Down
Current —TTL
Inputs
Max. VCC
CE > VIH
,
Com’l/Ind’l
Auto-A
15
15
mA
VIN > VIH or
IN < VIL,
Auto-E
20
5
V
f = fMAX
ISB2
Automatic CE
Power-Down
Current —CMOS VIN > VCC – 0.3V,
Max. VCC
,
Com’l/Ind’l
Auto-A
5
5
5
5
mA
CE> VCC –0.3V,
Auto-E
10
Inputs
or VIN < 0.3V,
f = 0
Note:
4. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
Document #: 38-05132 Rev. *G
Page 4 of 13
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CY7C1021CV33
Capacitance[5]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
8
8
COUT
pF
Thermal Resistance[5]
Parameter
Description
Test Conditions
SOJ
TSOP II
FBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
65.06
76.92
95.32
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
34.21
15.86
10.68
°C/W
AC Test Loads and Waveforms[6]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
50Ω
30 pF*
R2
351Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
351Ω
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05132 Rev. *G
Page 5 of 13
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CY7C1021CV33
Switching Characteristics Over the Operating Range[7]
-8
-10
-12
-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
[8]
tpower
VCC(typical) to the first access
Read Cycle Time
100
8
100
10
100
12
100
15
µs
tRC
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[9]
CE HIGH to High-Z[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
3
3
3
3
8
5
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
0
3
0
4
4
5
5
6
6
7
7
[11]
tPU
[11]
tPD
8
5
10
5
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[12]
tWC
0
0
0
0
4
5
6
7
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
8
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[9]
5
6
tHD
0
0
0
tLZWE
tHZWE
tBW
3
3
3
WE LOW to High-Z[9, 10]
4
5
6
7
Byte Enable to End of Write
6
7
8
9
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. t gives the minimum amount of time that the power supply should be at typical V values until the first memory access is performed.
POWER
CC
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state
HZOE HZBE HZCE
HZWE
voltage.
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a
Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the Write.
Document #: 38-05132 Rev. *G
Page 6 of 13
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CY7C1021CV33
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes:
13. Device is continuously selected. OE, CE, BHE and/or BLE = V
14. WE is HIGH for Read cycle.
.
IL
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05132 Rev. *G
Page 7 of 13
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CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[16, 17]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
16. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05132 Rev. *G
Page 8 of 13
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CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
[3]
[3]
CE OE WE BLE BHE
I/O1–I/O8
High-Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High-Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
Data In
Data In
High-Z
High-Z
High-Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
Selected, Outputs Disabled
Selected, Outputs Disabled
)
)
Document #: 38-05132 Rev. *G
Page 9 of 13
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CY7C1021CV33
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
Package Type
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
48-ball FBGA (Pb-free)
8
CY7C1021CV33-8VXC
CY7C1021CV33-8ZXC
CY7C1021CV33-8BAXC
CY7C1021CV33-10VC
CY7C1021CV33-10VXC
CY7C1021CV33-10ZXC
CY7C1021CV33-10ZI
CY7C1021CV33-10ZXI
CY7C1021CV33-10BAXI
CY7C1021CV33-12VC
CY7C1021CV33-12VXC
CY7C1021CV33-12VI
CY7C1021CV33-12VXI
CY7C1021CV33-12ZXC
CY7C1021CV33-12ZXI
CY7C1021CV33-12BAI
CY7C1021CV33-12BAXI
CY7C1021CV33-12ZSE
CY7C1021CV33-12ZSXE
CY7C1021CV33-12VE
CY7C1021CV33-12VXE
CY7C1021CV33-12BAE
CY7C1021CV33-15VXC
CY7C1021CV33-15ZXC
CY7C1021CV33-15ZI
CY7C1021CV33-15ZXI
CY7C1021CV33-15BAXI
CY7C1021CV33-15ZSXA
51-85082
Commercial
51-85096
51-85082
10
12
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II
Commercial
Industrial
51-85087
44-pin TSOP Type II (Pb-free)
48-ball FBGA (Pb-free)
51-85096
51-85082
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II (Pb-free)
48-ball FBGA
Commercial
Industrial
51-85087
51-85096
51-85087
51-85082
Commercial
Industrial
Industrial
48-ball FBGA (Pb-free)
44-pin TSOP Type II
Automotive-E
44-pin TSOP Type II (Pb-free)
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-free)
48-ball FBGA
51-85096
51-85082
51-85087
15
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II
Commercial
Commercial
Industrial
44-pin TSOP Type II (Pb-free)
48-ball FBGA (Pb-free)
51-85096
51-85087
44-pin TSOP Type II (Pb-free)
Automotive-A
Please contact local sales representative regarding availability of these parts
Document #: 38-05132 Rev. *G
Page 10 of 13
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CY7C1021CV33
Package Diagrams
44-pin (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-pin Thin Small Outline Package Type II (51-85087)
51-85087-*A
Document #: 38-05132 Rev. *G
Page 11 of 13
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CY7C1021CV33
Package Diagrams (continued)
48-ball FBGA (7 x 7 x 1.2 mm) (51-85096)
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
Ø0.05 M C
PIN 1 CORNER
ꢀLASER MARKX
Ø0.25 M C A B
Ø0.30 0.05ꢀ4ꢁ8X
1
2
3
4
5
6
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
F
E
F
G
H
G
H
A
A
1.ꢁ75
0.75
3.75
B
7.00 0.10
7.00 0.10
B
0.15ꢀ48X
51-85096-*F
SEATING PLANE
C
1.20 MA8.
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05132 Rev. *G
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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
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CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05132
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109472
115044
Description of Change
12/06/01
05/08/02
HGK
HGK
New Data Sheet
*A
Ram7 version C4K x 16 Async
Remove “Preliminary”
*B
*C
*D
115808
120413
238454
06/25/02
10/31/02
See ECN
HGK
DFP
RKF
ISB1 and ICC values changed
Updated BGA pin E4 to NC
1) Added Automotive Specs to Data sheet
2) Added Pb-free devices in the Ordering Information
*E
*F
334398
493565
See ECN
See ECN
SYT
NXR
Added Pb-free on page# 9 and 10
Added Automotive-A operating range
Corrected typo in the Pin Definition table
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
*G
563963
See ECN
VKN
Added tPOWER spec in the AC Switching Characteristics table
Added footnote #8
Document #: 38-05132 Rev. *G
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相关型号：
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Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
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