FAGD1657132BA [ROCHESTER]

ATM/SONET/SDH SUPPORT CIRCUIT, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32;


型号：	FAGD1657132BA
厂家：	Rochester Electronics
描述：	ATM/SONET/SDH SUPPORT CIRCUIT, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32 ATM 异步传输模式电信电信集成电路
文件：	总8页 (文件大小：796K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2.5 Gbit/s

Retiming

Laser Driver

GD16571

an Intel company

Preliminary

General Description

Features

The GD16571 is a high performance low

power 2.5 Gbit/s Laser Driver with

optional on chip retiming of data.

Retiming of the data signal connected to

the pins DIN, DINQ is made by means of

a DFF clocked by an external clock sig-

nal at the data rate fed to the pins CKIN

and CKINQ.

Complies with ITU-T STM-16 and

SONET OC-48 standards.

Intended for driving a 25 W load,

e.g. a laser diode with 25 W input

impedance.

The GD16571 is designed to meet and

exceed ITU-T STM-16 or SONET OC-48

fiberoptic communication systems re-

quirements.

A Mark-Space monitor is available on the

pins MARKP and MARKN. Together with

the symmetry adjustment pin (SYM) this

may be used to control the mark space

ratio of the output signal.

Clocked or non-clocked operation.

The GD16571 is designed to sink a

Modulation Current into the IOUT pin and

a Pre-Bias Current into the IPRE pin. The

Modulation Current is adjustable up to

70 mA by means of the pin VMOD. The

Pre-Bias Current may be adjusted up to

50 mA by means of the VPRE pin.

Large modulation current adjustment

range from 5 mA to 70 mA.

The GD16571 is implemented in a Sili-

con Bipolar process and requires a single

+5 V supply or a single -5.2 V supply.

Output voltage over / under shoot

less than ±2 % respectively ± 5 %.

Rise / fall times less than 100 ps.

The circuit is available in a thermally

enhanced 32-pin TQFP plastic package.

Laser diode pre-bias adjustable up to

50 mA.

Mark-Space monitor.

VADJEF VMOD VADJBUF

VPRE

Symmetry adjustment.

Internal 50 W termination of data and

clock inputs.

Modulation

Current

Control

Pre-Bias

Current

Control

IPRE

Operates up to 3.5 Gbit/s.

VDD

VDDR

VDDCONT

CKSEL

Power dissipation: 0.38 W.

Excluding Modulation Current and

Pre-bias Current.

Input

Buffer

Output

Driver

DIN

IOUT

DINQ

IOUTN

Silicon Bipolar process.

VEE

VEEP

VEEB

VEER

DINT

32 pin thermally enhanced TQFP

plastic package.

Mark/Space

Monitor

Input

Buffer

CKIN

MARKP

MARKN

SYM

CKINQ

Applications

CKINT

Tele Communication:

–

SDH STM-16

SONET OC-48

Datacom up to 3.125 Gbit/s.

Electro Absorption laser driver.

Direct Modulation laser driver.

Data Sheet Rev.: 10

Functional Details

GD16571 is a 2.5 Gbit/s laser driver with

an optional retiming of the data signal. It

is capable of driving high power laser di-

odes, typically having input impedance of

25 W, at a maximum modulation current

of 70 mA and a maximum pre-bias cur-

rent of 50 mA.

The output modulation current is con-

trolled by the pin VMOD and can be con-

trolled in the range from 0 mA to 70 mA,

however the specifications is only valid in

the range from 5 mA to 70 mA. The out-

put voltage swing across the external

load may be varied accordingly. The

modulation current control on pin VMOD

is implemented as a current mirror and

therefore sinks a current proportional to

the modulation current. The current sink

into the VMOD pin is approximately 3/80

of the modulation current. Two additional

pins (VADJBUF and VADJEF) are avail-

able in order to optimise the performance

of the output signal quality, specifically

with respect to overshoot and under-

shoot. Typically best performance is ob-

tained if these pins are connected to

VMOD.

GD16571 the voltage overshoot is less

than 2 % across the full modulation cur-

rent range, when driving a 25 W load.

Similarly the voltage undershoot is less

than 5 %.

A mark-space monitor is provided

through the pins MARKP and MARKN.

These may be connected as shown in

the application diagram below, with a ca-

pacitor across the two outputs and a

comparator (or Op-amp) to determine the

mark density. Symmetry input (SYM) is

available which may be used to control

the mark-space ratio.

Data (DIN, DINQ) is input to GD16571

and retimed within a DFF clocked by an

external clock (CKIN, CKINQ). Optionally

the retiming may be bypassed controlled

by a select pin (CKSEL).

Both the differential data (DIN, DINQ)

and clock inputs (CKIN, CKINQ) are in-

ternally terminated to 50 W. Termination

is made with a 50 W resistor from the two

differential inputs to a common pin called

DINT and CKINT respectively. The input

sensitivity when driven with a single

ended signal is better than 150 mV on

both clock and data inputs.

AC Coupled Output

When DC coupled the output swing will

be limited by IOUT output voltage speci-

fied to -2 V. For maximum output voltage

swing the output should be AC coupled.

The pre-bias current is controlled by the

pin VPRE and can be controlled from

0 mA to 50 mA. The pre-bias current

control on pin VPRE is implemented as a

current mirror and therefore sinks a cur-

rent proportional to the pre-bias current.

The current sink into the VPRE pin is ap-

proximately 3/500 of the pre-bias current.

VDD

The output pin (IOUT) is an open collec-

tor output designed for driving external

loads with 25 W characteristic imped-

ance. Because of the nature of an open

collector the output therefore may be re-

garded as a current switch, with infinite

output impedance. The characteristic im-

pedance through the package is approxi-

mately 25 W. Optimum performance of

GD16571 therefore is achieved if the out-

put is terminated into a 25 W impedance.

L1 and L3 = Siemens Chip

Inductors (B82432A1224K).

L2 and L4 = Siemens ferrite

cores B64290-A36-X33 with

8 turns of 0.22mm Cu-Wire.

220uH

100nF

IOUT

An important parameter for laser drivers

is voltage overshoot on the output pin

(IOUT), because it determines the extinc-

tion ratio. GD16571 has been designed

with special emphasis on achieving a

very small voltage overshoot. For

IOUTN

25W

VDD

Figure 2. AC Coupled Output

Control Voltage from

Modulation Current

Control System

Control Voltage from

Pre-Bias Current

Control System

Laser Diode Equivalent

25 W Input Impedance

VMOD / 20

VPRE / 16

VDD

Modulation

Current

Control

Pre-Bias

Current

Control

IPRE / 19

VDD

Input

Buffer

Output

Driver

DIN / 27

Differential or

Single-ended

Data Signal

IOUT / 13, 14

DINQ / 26

VDD

IOUTN / 11, 12

100n

DINT / 28

Mark/Space

Monitor

Input

Buffer

VDD

CKIN / 31

Differential or

Single-ended

Clock Signal

MARKP / 7

MARKN / 6

100n

CKINQ / 32

CKINT / 30

100n

VEEP / 18

Negative Ref.

Supply

Figure 1. Application Diagram

Data Sheet Rev.: 10

GD16571

Page 2 of 7

Pin List

Mnemonic:

Pin No.:

Pin Type:

Description:

DIN

DINQ

AC IN

Data inputs. Internally terminated in 50 W to DINT.

Internally biased to -1.3 V

DINT

ANL IN

AC IN

Termination voltage for DIN and DINQ.

CKIN

CKINQ

Clock inputs. Internally terminated in 50 W to CKINT.

Internally biased to -1.3 V.

CKINT

ANL IN

Termination voltage for CKIN and CKINQ.

IOUT

IOUTN

13, 14

11, 12

OPEN

COLLECTOR

Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modula-

tion current, which is controlled by the pin VMOD. The current into

IOUT is high when data is high on DIN.

IPRE

OPEN

COLLECTOR

Pre-bias current output. IPRE sinks a current, which is controlled

by the pin VPRE.

VMOD

ANL IN

Modulation current control input. The control system is made as a

current mirror. VMOD sinks a current proportional to the modula-

tion current. This current is approximately 3/80 times “The modu-

lation current”.

VPRE

ANL IN

Pre-bias current control input. The control system is made as a

current mirror. VPRE sinks a current proportional to the pre-bias

current. This current is approximately 3/500 times “The pre-bias

current”.

CKSEL

SYM

ECL IN

ANL IN

When CKSEL is low data is retimed. Otherwise data is bypassed

the retiming.

SYM controls the mark-space ratio of the output. Decreasing the

voltage of the SYM pin decreases the pulse width of a current

high into the IOUT pin.

MARKP

MARKN

ANL OUT

ANL IN

Mark-space monitor outputs. High impedance CML outputs. The

output voltage of the MARKP pin is the same as the voltage on

the DIN input.

VADJBUF

VADJEF

Pins used to optimise the performance of the output in terms of

overshoot and undershoot. Typically optimum performance will be

achieved when shorted to VMOD.

VDD

2, 4, 10, 15

PWR

Ground pins for laser driver part.

Ground pin for modulation current control system.

Ground pin for retiming part.

VDDCONT

VDDR

VEE

5, 8, 23

Negative supply pins for laser driver part.

Negative supply pin for output driver.

Negative supply pin for pre-bias circuitry.

Negative supply pin for retiming part.

Not Connected.

VEEP

VEEB

VEER

Heat sink

Package back

Connected to VEE.

Data Sheet Rev.: 10

GD16571

Page 3 of 7

Package Pinout

CKSEL

VDD

SYM

VEE

VDDCONT

VDD

VADJBUF

VADJEF

VMOD

IPRE

VEE

MARKN

MARKP

VEE

VEEP

VEEB

Figure 3. Package 32 TQFP, Top View

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages in table are referred to VDD.

All currents in table are defined positive out of the pin.

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

-6

TYP.:

MAX.:

UNIT:

Power Supply

V_O

Applied Voltage (All Outputs)

Applied Voltage (All Inputs)

Input Current (AC IN)

Input Current (VMOD)

V_EE-0.5

-1

V_I

0.5

I_IAC IN

I_IVMOD

I_IVPRE

T_O

°C

-4

Input Current (VPRE, VADJBUF and VADJEF) Note 1

-1

Operating Temperature

Storage Temperature

Base

-55

+125

+165

T_S

-65

°C

Note 1: Voltage and/or current should be externally limited to specified range.

Data Sheet Rev.: 10

GD16571

Page 4 of 7

DC Characteristics

T_CASE= -40 °C to 85 °C, appropriate heat sinking may be required.

All voltages in table are referred to VDD.

All currents in table are defined positive out of the pin.

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

TYP.:

- 5.2

MAX.:

UNIT:

Power Supply

- 5.5

-4.7

I_EE

Negative Supply Current

Power Dissipation

I_OUT= 0 A

P_DISS

V_EE= - 5.0 V,

I_OUT= 0 A,

I_PRE= 0 A

0.38

0.5

_ppAN IN

Peak- peak Voltage when Input is Driven Single V_VTH= - 1.3 V

ended.

150

800

V VMOD

I VMOD

Voltage Range for VMOD

Sink Current into Pin VMOD

V_EE

- 4

V_DD

_INNN

Input Voltage Range for VPRE, VADJBUF,

VADJEF and SYM

V_EE

V_DD

_SINKNN

Sink Current into pin VPRE, VADJBUF,

VADJEF and SYM

- 1

_INSYM

I_LEAKSYM

_INCKSEL

I_LEAKCKSEL

_LOMARK

_OMARK

_OIPRE

I IPRE

_OIOUT

_Mod,HIIOUT

_Mod,LOIOUT

Input Voltage Range for SYM

Leakage Current for CKSEL

Input Voltage Range for CKSEL

Leakage Current for SYM

V_EE

- 1

V_DD

V_EE

- 1

V_DD

Low Output Voltage for Mark-Space Monitor

Output Impedance for Mark-Space Monitor

IPRE Output Voltage

- 2.0

4.0

-2.0

-50

-2.0

-70

-3

IPRE Current

IOUT Output Voltage

Note 1

IOUT High Modulation Current

IOUT Low Modulation Current

Note 1,2

Note 1,3

Note 1: R_LOAD= 25 W to VDD connected to pin IOUT. Sink current is controlled by the VMOD pin, and may be adjusted in the

range as specified. Notice that high modulation current means that the output voltage level is low.

Note 2: The AC parameters are only specified in the range from -70 mA to -5 mA. However at T_CASE= 0 °C to 70 °C AC parame-

ters are specified from -80 mA to -5 mA.

Note 3: This is a leakage current. Max leakage current is present at max modulation current (i.e. at 70 mA modulation current).

The leakage current decreases for smaller leakage currents.

Data Sheet Rev.: 10

GD16571

Page 5 of 7

AC Characteristics

T_CASE= -40 °C to 85 °C, appropriate heat sinking may be required.

Symbol:

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

UNIT:

Mbit/s

f_MAXOUT

Data Output Frequency

Added Output Jitter

Output Rise Time

2500

_ppOUT

Note 1

_RISEOUT

_FALLOUT

100

Output Fall Time

t_PM

Phase Margin Clock to Data

Data Set-up Time

300

t_S

t_H

Data Hold Time

D_{CROSS_OVER}

Output Cross Over Control Range

Note 1

± 30

Note 1: R_LOAD= 25 W to VDD connected to pin IOUT. I_LD= 70 mA. Rise/Fall times at 20 – 80 % of HI/LO voltage levels.

Package Outline

Figure 4. Package 32 pin. All dimensions are in mm.

Data Sheet Rev.: 10

GD16571

Page 6 of 7

Device Marking

<1> = Wafer ID

GD16571

<2> = Design ID

<3> = Wafer Lot#

<4> = Assembly Lot#

<1> - <2> - <3>

<4> - YYWW

Pin 1 - Mark

Figure 5. Device Marking, Top View.

Ordering Information

To order, please specify as shown below:

Product Name:

Intel Order Number:

Package Type:

32L TQFP EDQUAD

Temperature Range:

GD16571-32BA

FAGD1657132BA

MM#: 836125

-40..85 °C

GD16571, Data Sheet Rev.: 10 - Date: 24 July 2001

an Intel company

Mileparken 22, DK-2740 Skovlunde

Denmark

Phone : +45 7010 1062

Distributor:

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

Fax : +45 7010 1063

E-mail : sales@giga.dk

Web site : http://www.intel.com/ixa

An Intel company

Please check our Internet web site

for latest version of this data sheet.

FAGD1657132BA [ROCHESTER]

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