MAC8SM [ROCHESTER]
600V, 8A, 4 QUADRANT LOGIC LEVEL TRIAC, TO-220AB, CASE 221A-09, 3 PIN;
| 型号： | MAC8SM |
| 厂家： | 
Rochester Electronics |
| 描述： | 600V, 8A, 4 QUADRANT LOGIC LEVEL TRIAC, TO-220AB, CASE 221A-09, 3 PIN 局域网 栅 三端双向交流开关 栅极 |
| 文件： | 总8页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAC8SD, MAC8SM, MAC8SN
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for industrial and consumer applications for full wave
control of ac loads such as appliance controls, heater controls, motor
controls, and other power switching applications.
http://onsemi.com
Features
TRIACS
8 AMPERES RMS
400 thru 800 VOLTS
• Sensitive Gate Allows Triggering by Microcontrollers and other
Logic Circuits
• Uniform Gate Trigger Currents in Three Quadrants; Q1, Q2, and Q3
• High Immunity to dv/dt − 25 V/ms Minimum at 110°C
• High Commutating di/dt − 8.0 A/ms Minimum at 110°C
MT2
MT1
G
• Maximum Values of I , V and I Specified for Ease of Design
GT GT
H
MARKING
DIAGRAM
• On-State Current Rating of 8 Amperes RMS at 70°C
• High Surge Current Capability − 70 Amperes
• Blocking Voltage to 800 Volts
• Rugged, Economical TO−220AB Package
• Pb−Free Packages are Available*
MAC8SxG
AYWW
TO−220AB
CASE 221A−09
STYLE 4
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
1
2
Rating
Symbol
Value
Unit
3
Peak Repetitive Off−State Voltage (Note 1)
V
V
V
DRM,
RRM
(T = −40 to 110°C,
J
x
= D, M, or N
Sine Wave, 50 to 60 Hz, Gate Open)
A
Y
= Assembly Location
= Year
MAC8SD
MAC8SM
MAC8SN
400
600
800
WW = Work Week
G
= Pb−Free Package
On-State RMS Current
I
8.0
A
A
T(RMS)
(Full Cycle Sine Wave, 60 Hz, T = 70°C)
C
PIN ASSIGNMENT
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
I
TSM
70
1
Main Terminal 1
T = 110°C)
J
2
3
4
Main Terminal 2
Gate
2
2
Circuit Fusing Consideration (t = 8.3 ms)
I t
20
16
A sec
Peak Gate Power
P
W
W
GM
Main Terminal 2
(Pulse Width ≤ 1.0 ms, T = 70°C)
C
Average Gate Power
P
0.35
G(AV)
ORDERING INFORMATION
(t = 8.3 ms, T = 70°C)
C
Device
Package
Shipping
Operating Junction Temperature Range
Storage Temperature Range
T
−40 to +110
−40 to +150
°C
°C
J
MAC8SD
TO−220AB
50 Units / Rail
50 Units / Rail
T
stg
MAC8SDG
TO−220AB
(Pb−Free)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
MAC8SM
TO−220AB
50 Units / Rail
50 Units / Rail
MAC8SMG
TO−220AB
(Pb−Free)
1. V
and V
for all types can be applied on a continuous basis. Blocking
DRM
RRM
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
MAC8SN
TO−220AB
50 Units / Rail
50 Units / Rail
MAC8SNG
TO−220AB
(Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 5
MAC8S/D
MAC8SD, MAC8SM, MAC8SN
THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
Unit
Thermal Resistance,
Junction−to−Case
Junction−to−Ambient
R
R
2.2
62.5
°C/W
q
JC
JA
q
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
T
260
°C
L
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
I
I
,
mA
DRM
−
−
−
−
0.01
2.0
(V = Rated V , V
DRM
; Gate Open)
RRM
T = 25°C
T = 110°C
J
RRM
D
J
ON CHARACTERISTICS
Peak On-State Voltage (Note ) (I = ꢀ11A)
V
−
−
1.85
V
TM
TM
Gate Trigger Current (Continuous dc) (V = 12 V, R = 100 W)
I
mA
D
L
GT
−
−
−
2.0
3.0
3.0
5.0
5.0
5.0
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
Holding Current (V = 12V, Gate Open, Initiating Current = ꢀ150mA)
I
−
3.0
10
mA
mA
D
H
Latching Current (V = 24V, I = 5mA)
I
D
G
L
−
−
−
5.0
10
5.0
15
20
15
MT2(+), G(+)
MT2(−), G(−)
MT2(+), G(−)
Gate Trigger Voltage (Continuous dc) (V = 12 V, R = 100W)
V
V
D
L
GT
0.45
0.45
0.45
0.62
0.60
0.65
1.5
1.5
1.5
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
= 400 V, I = 3.5 A, Commutating dv/dt = 10 V m/sec,
di/dt
8.0
25
10
75
−
−
A/ms
(c)
V
D
TM
Gate Open, T = 110°C, f = 500 Hz, Snubber: C = 0.01 mF,
J
S
R
S
=15 W, See Figure 16.)
Critical Rate of Rise of Off-State Voltage
(V = Rate V , Exponential Waveform, R = 510 W, T = 110°C)
dv/dt
V/ms
D
DRM
GK
J
2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.
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2
MAC8SD, MAC8SM, MAC8SN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Quadrant 1
MainTerminal 2 +
Symbol
Parameter
V
TM
V
Peak Repetitive Forward Off State Voltage
Peak Forward Blocking Current
DRM
DRM
on state
I
I
H
I
at V
RRM
V
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
RRM
RRM
I
RRM
V
Maximum On State Voltage
Holding Current
+ Voltage
off state
TM
I
I
at V
H
DRM
DRM
I
H
Quadrant 3
MainTerminal 2 −
V
TM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
(+) MT2
Quadrant II
Quadrant I
(−) I
(+) I
GT
GT
GATE
GATE
MT1
MT1
REF
REF
I
−
+ I
GT
GT
(−) MT2
(−) MT2
Quadrant III
Quadrant IV
(+) I
(−) I
GT
GT
GATE
GATE
MT1
REF
MT1
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
MAC8SD, MAC8SM, MAC8SN
110
100
90
25
DC
a
180°
120°
90°
a
20
a = 30 and 60°
a = CONDUCTION ANGLE
15
10
60°
a
a
80
90°
a = 30°
a = CONDUCTION ANGLE
180°
70
5
DC
60
0
0
2
I
4
6
8
10
12
0
2
4
6
8
10
12
I
, RMS ON−STATE CURRENT (AMPS)
, RMS ON−STATE CURRENT (AMPS)
T(RMS)
T(RMS)
Figure 1. RMS Current Derating
Figure 2. Maximum On−State Power Dissipation
1
100
10
1
Typical @ T = 25°C
J
Maximum @
T = 110°C
J
Z
= R
ꢁ r(t)
q
JC(t)
q
JC(t)
0.1
Maximum @
T = 25°C
J
0.1
0.01
0.1
1
10
t, TIME (ms)
100
1000
1@104
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
V , INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
T
Figure 3. On−State Characteristics
Figure 4. Transient Thermal Response
10
8
25
20
15
6
MT2 NEGATIVE
Q3
4
2
0
10
5
MT2 POSITIVE
Q1
−40 −25 −10
0
−40 −25 −10
5
20
35
50
65
80
95 110
5
20
35
50
65
80
95 110
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 6. Typical Latching Current Versus
Junction Temperature
Figure 5. Typical Holding Current Versus
Junction Temperature
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4
MAC8SD, MAC8SM, MAC8SN
1
14
12
10
8
Q1
0.9
Q3
0.8
0.7
0.6
0.5
Q3
Q3
6
Q2
4
Q2
0.4
0.3
2
0
Q1
Q1
−40 −25 −10
5
20
35
50
65
80
95 110
−40 −25 −10
5
20
35
50
65
80
95 110
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. Typical Gate Trigger Voltage Versus
Junction Temperature
Figure 7. Typical Gate Trigger Current Versus
Junction Temperature
130
120
110
100
200
180
160
140
120
100
80
R
= 510 W
G − MT1
T = 110°C
J
T = 100°C
J
V
= 400 V
PK
600 V
800 V
110°C
90
80
120°C
60
400
450
500
550
600
650
, Peak Voltage (Volts)
700
750
800
100 200
300
400
500
600
700
RGK, GATE−MT1 RESISTANCE (OHMS)
800
900 1000
V
PK
Figure 10. Typical Exponential Static dv/dt Versus
Peak Voltage, MT2(+)
Figure 9. Typical Exponential Static dv/dt Versus
Gate−MT1 Resistance, MT2(+)
130
120
110
100
90
350
300
250
200
150
100
V
= 400 V
PK
T = 100°C
J
600 V
800 V
110°C
R
= 510 W
G − MT1
R
= 510 W
G − MT1
80
70
100
105
T , Junction Temperature (°C)
110
400 450
500
550
600
650
, Peak Voltage (Volts)
700
750
800
V
J
PK
Figure 11. Typical Exponential Static dv/dt Versus
Junction Temperature, MT2(+)
Figure 12. Typical Exponential Static dv/dt Versus
Peak Voltage, MT2(−)
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5
MAC8SD, MAC8SM, MAC8SN
350
300
250
200
150
300
V
= 400 V
V
= 400 V
PK
PK
250
200
600 V
600 V
800 V
800 V
R
= 510 W
150
100
G − MT1
100
50
T = 110°C
J
100 200
300
400
500
600
700
800
900 1000
100
105
T , Junction Temperature (°C)
110
RGK, GATE−MT1 RESISTANCE (OHMS)
J
Figure 13. Typical Exponential Static dv/dt Versus
Junction Temperature, MT2(−)
Figure 14. Typical Exponential Static dv/dt Versus
Gate−MT1 Resistance, MT2(−)
100
V
= 400 V
PK
90°C
10
100°C
1
f =
2 t
w
t
w
6f I
TM
(di/dt)
=
c
1000
110°C
V
DRM
1
1
5
10
15
20
(di/dt) , CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
25
30
c
Figure 15. Critical Rate of Rise of
Commutating Voltage
L
1N4007
L
200 V
RMS
ADJUST FOR
, 60 Hz V
MEASURE
I
R
S
I
TM
AC
CHARGE
CONTROL
−
+
TRIGGER
200 V
CHARGE
C
S
ADJUST FOR
di/dt
MT2
G
(c)
1N914
51 W
MT1
NON-POLAR
C
L
Note: Component values are for verification of rated (di/dt) . See AN1048 for additional information.
c
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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6
MAC8SD, MAC8SM, MAC8SN
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
B
F
T
S
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
N
Q
R
S
T
V
J
G
D
U
V
Z
N
−−− 0.080
2.04
STYLE 4:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
4. MAIN TERMINAL 2
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MAC8S/D
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