MAX8564EUB+中文资料_数据手册_规格书

19-3290; Rev 2; 6/06

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

General Description

Features

The MAX8563/MAX8564/MAX8564A ultra-low-output dual

and triple LDO controllers allow flexible and inexpensive

point-of-load voltage conversion in motherboards,

desknotes, notebooks, and other applications.

♦ MAX8563: 3 Outputs

♦ MAX8564/MAX8564A: 2 Outputs

♦ ±±1 ꢀFFedbac ꢁFꢂuꢃbtꢄio

These parts feature a 0.5V reference voltage with ±±1

accuracy providing tight regulation of the output volt-

age. The MAX8563 has three n-channel MOSFET con-

troller outputs, and the MAX8564/MAX8564A has two

controller outputs.

♦ AejustbdꢃF Output ViꢃtbꢂF Diwo ti 0.5V

♦ Cbo UsF CFrbmꢄa Output Cbpbaꢄtirs

♦ WꢄeF Suppꢃy ViꢃtbꢂF ꢁboꢂF PFrmꢄts OpFrbtꢄio

frim 5V ir ±2V ꢁbꢄꢃs

Each controller output is adjustable from 0.5V to 3.3V

♦ Ioeꢄvꢄeubꢃ EobdꢃF Ciotriꢃ boe POK Sꢄꢂobꢃ Aꢃꢃiws

when V

= ±2V and between 0.5V and ±.8V when V

DD

SFquFoaꢄoꢂ

= 5V. Each output is independently enabled and asserts

a POK signal when the output reaches 941 of the set

value. Each output is protected against a soft short-circuit

condition by an undervoltage comparator that disables

the output when it drops to under 801 of the set voltage

for more than 50µs. For a catastrophic short condition, the

regulators are shut down immediately if the output drops

below 601 of the set voltage.

♦ OvFrꢃibe PritFatꢄio Aꢂbꢄost Sift Shirt-Cꢄrauꢄt

Cioeꢄtꢄio

♦ UoeFrviꢃtbꢂF Shirt-Cꢄrauꢄt PritFatꢄio

♦ DrꢄvF o-ChbooFꢃ MOSꢀETs

ꢃrdering Information

PIN-

PACKAGE

PKG

CODE

The MAX8563 is available in a ±6-pin QSOP

package, and the MAX8564/MAX8564A are available

PAꢁT

TEMP ꢁANGE

®

in a ±0-pin µMAX package.

MAX8563EEE

MAX8564EUB

-40°C to +85°C ±6 QSOP

-40°C to +85°C ±0 µMAX

E±6-±

U±0-2

Applications

MAX8564AEUB+ -40°C to +85°C ±0 µMAX

+Denotes lead-free package.

Motherboards

Ultra-Low-Dropout

Voltage Regulators

Low-Voltage DSP, µP, and

Microcontroller Power

Supplies

Dual/Triple Power Supplies

Desknotes and Notebooks

Graphic Cards

Pin Configurations appear at end of data sheet.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Typical ꢃperating Circuit

5V OR 12V

IN

1.8V 5% IN

C1

1.2V 5% IN

C2

C3

Q1

OUT1

1.5V/1.5A

C5

R2

Q2

DRV1

FB1

V

DD

C4

OUT2

1.05V/3A

R1

R3

C6

R5

R4

DRV2

C7

ON

MAX8563

OFF

EN1

FB2

EN2

ON

POK1

OFF

3.3V 5% IN

C8

GND

N.C.

POK2

N.C.

POK2

POK3

R6

Q3

C10

R7

OUT3

2.5V/2A*

DRV3

FB3

POK3

EN3

C9

ON

OFF

R8

R9

*2.5V OUTPUT ONLY WITH V = 12V

DD

________________________________________________________________ Maxim Integrated Products

±

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

ABSOLUTE MAXIMUM ꢁATINGS

DD

DRV±, DRV2, DRV3, EN±, EN2,

EN3 to GND............................................-0.3V to (V

V

to GND............................................................-0.3V to +±4V

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+±50°C

Storage Temperature Range.............................-65°C to +±50°C

Lead Temperature (soldering, ±0s) .................................+300°C

+ 0.3V)

DD

FB±, FB2, FB3, POK±, POK2, POK3 to GND ...........-0.3V to +6V

Continuous Power Dissipation (T = +70°C)

A

±0-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW

±6-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTꢁICAL CHAꢁACTEꢁISTICS

(V = V

= V

= 5V, V = 0V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note ±)

GND A A

DD

EN±

EN2

EN3

PAꢁAMETEꢁ

CONDITIONS

MIN

TYP

MAX

UNITS

GENEꢁAL

V

Voltage Range

4.5

±3.2

4.00

±600

±200

25

V

DD

Undervoltage-Lockout Threshold

Rising, 200mV hysteresis (typ)

3.56

3.76

930

660

V

= V

= ±2V (MAX8563)

EN_

DD

V

Quiescent Current

µA

DD

= ±2V (MAX8564/MAX8564A)

Shutdown Current

EN± = EN2 = EN3 = GND, V

= ±2V

DD

LDOs

T

= 0°C to +85°C

= -40°C to +85°C

= +25°C

0.494

0.489

-±00

0.5

0.504

0.509

+±00

A

FB_ Accuracy

V

FB_ Input Bias Current

nA

µA

mA

V

= +85°C

-8

±00

±0

MAX8563, MAX8564

MAX8564A

DRV_ Soft-Start Charging Current

DRV_ Max Sourcing Current

DRV_ Max Sinking Current

DRV_ Max Voltage

T

A

T

A

T

A

T

A

= 0°C to +85°C

= -40°C to +85°C

= 0°C to +85°C

= -40°C to +85°C

4

3

V

= 0.45V

= 0.6V

FB_

7

3

±.8

4.7

8.0

V

= 5V, V

= 0.46V

FB_

DD

= ±3.2V, V

= 0.46V

±0.9

FB_

FB_ Slow Short-Circuit Threshold

FB_ Fast Short-Circuit Threshold

Slow Short-Circuit Timer

FB_ to DRV_ Transconductance

LOGIC

Measured at FB_ (falling)

400

300

50

mV

µs

0.±±5

0.24

0.460

0.7

Mho

EN_ Input Low Level

V

EN_ Input High Level

±.3

T

= +25°C

= +85°C

-0.±

+0.±

A

V

= 0 and V

= ±3.2V

,

DD

EN_

DD

EN_ Input Leakage Current

µA

0.00±

A

2

_______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

ELECTꢁICAL CHAꢁACTEꢁISTICS (aiotꢄouFe)

(V = V

= V

= 5V, V = 0V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note ±)

GND A A

DD

EN±

EN2

EN3

PAꢁAMETEꢁ

CONDITIONS

Measured at FB_ (falling)

Measured at FB_ (rising)

Sinking ±mA, V = 4.5V, V

MIN

425

455

TYP

440

470

MAX

455

485

0.±

UNITS

mV

POK_ Threshold Falling

POK_ Threshold Rising at Startup

POK_ Output Low Level

mV

= 0.4V

FB_

V

DD

T

= +25°C

= +85°C

0.±

A

POK_ Output High Leakage

V

= 5.5V

µA

DD

0.00±

A

NitF ±: Specifications are production tested at T = +25°C. Maximum and minimum specifications over temperature are guaranteed by

A

design.

Typical ꢃperating Characteristics

(Circuit of Figure ±, T = +25°C.)

A

OUTPUT VOLTAGE vs. INPUT VOLTAGE

OUTPUT VOLTAGE vs. OUTPUT CURRENT

OUTPUT VOLTAGE vs. INPUT VOLTAGE

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

1.6

V

= 12V

V

= 12V

DD

V

= 5V

DD

V

OUT3

V

OUT3

OUT1

1.5

1.4

1.3

1.2

1.1

1.0

V

OUT1

V

OUT1

V

OUT2

V

OUT2

1.0

1.4

1.8

2.2

2.6

3.0

3.4

0

0.5

1.0

1.5

2.0

2.5

3.0

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

FEEDBACK VOLTAGE

vs. TEMPERATURE

PSRR vs. FREQUENCY

LOAD TRANSIENT

MAX8563 toc06

100

90

80

70

60

50

40

30

20

10

0

0.5000

0.4998

0.4996

0.4994

0.4992

0.4990

0.4988

0.4986

V

= 1.5V

OUT1

V

= 5V

I

DD

OUT2

= 2V

IN1

2A/div

0

LOAD = 1.25Ω

V

= 12V

DD

V

= 12V

V

DD

OUT2

20mV/div

AC-COUPLED

200mV/div

AC-COUPLED

V

IN2

V

DRV2

2V/div

0

V

= 12V

DD

FIGURE 1, C7 = 100μF 6TPE100MI

1k

10k

100

100k

10μs/div

-40

-15

10

35

60

85

FREQUENCY (Hz)

TEMPERATURE (°C)

_______________________________________________________________________________________

3

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Typical ꢃperating Characteristics (continued)

(Circuit of Figure ±, T = +25°C.)

A

POWER-ON SEQUENCING WITH V

DD

IN

MAX8563 toc07

MAX8563 toc08

V

20V/div

0

DD

20V/div

0

V

DD

ENABLE CONFIGURED AS

SHOWN IN FIGURE 4

RD = 100kΩ, RE = 4kΩ

2V/div

0

2V/div

0

V

OUT1

IN1

V

IN1

2V/div

0

2V/div

0

V

OUT1

2V/div

0

2V/div

0

POK1

V

POK1

20ms/div

10ms/div

ENABLE-ON SEQUENCING

SHORT-CIRCUIT PROTECTION

MAX8563 toc09

MAX8563 toc10

V

2V/div

0

IN1

2V/div

0

I

5A/div

0

OUT1

EN1

V

OUT1

1V/div

0

2V/div

0

V

OUT1

2V/div

0

V

DRV1

POK1

2V/div

0

20ms/div

20μs/div

4

_______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Functional Diagram

V

DD

VL

UVLO

0.5V

REF

MAX8563

MAX8564

MAX8564A

GND

V

DD

V

DD

0.5V

EN1

DRV1

FB1

GM

VL

POK1

POK

COMPARATOR

LDO

CONTROLLER 1

EN2

DRV2

FB2

LDO

CONTROLLER 2

POK2

EN3

DRV3

FB3

LDO

CONTROLLER 3

POK3

Pin Description

NAME

MAX8564/

ꢀUNCTION

MAX8563

MAX8564A

Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output ±.

DRV± is internally pulled to ground when EN± is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

±

DRV±

Feedback Input for Output ±. Connect to the center of a resistor-divider between output ± and GND to

set the output voltage of output ±. The feedback regulation voltage is 0.500V. See the Output Voltage

Setting section.

2

3

FB±

Enable Control for Output ±. Drive logic high to enable output ±, or logic low to disable the

EN±

output. Connect to V

for always-on operation.

DD

Output ± Power-Good Signal. Open-drain output pulls low when output ± is ±21 below the

nominal regulated voltage.

4

5

POK±

GND

—

POK±

GND

POK2

—

Ground

Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is ±21 below the

nominal regulated voltage.

6

N.C.

No Internal Connection

_______________________________________________________________________________________

5

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Pin Description (continued)

NAME

ꢀUNCTION

MAX8564/

MAX8564A

MAX8563

—

Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the

EN2

—

output. Connect to V

for always-on operation.

DD

7

Output 3 n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 3.

DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

DRV3

Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and

GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

—

FB2

—

8

Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and

GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

FB3

Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2.

DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

—

DRV2

—

9

Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the

EN3

—

output. Connect to V

for always-on operation.

DD

+5V or +±2V Supply Input. Connect to external +5V or +±2V supply rail. Bypass with a 0.±µF

ceramic or larger capacitor.

V

DD

±0

Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is ±21 below the

nominal regulated voltage.

POK3

N.C.

—

±±

±2

No Internal Connection

Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is ±21 below the

nominal regulated voltage.

POK2

Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the

±3

±4

EN2

FB2

—

output. Connect to a V

for always-on operation.

DD

Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and

GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2.

DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

±5

±6

DRV2

—

+5V or +±2V Supply Input. Connect to an external +5V or +±2V supply rail. Bypass with a 0.±µF

ceramic or larger capacitor.

V

DD

6

_______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Typical Application Circuits

MAX8563: Triple ꢃutput

5V OR 12V

1.8V 5% IN

IN

C1

1.2V 5% IN

C3

C2

Q1

OUT1

1.5V/1.5A

C5

R2

Q2

DRV1

FB1

V

DD

C4

R1

OUT2

1.05V/3A

C6

R4

C7

DRV2

FB2

R3

R5

ON

MAX8563

OFF

EN1

ON

OFF

POK1

EN2

3.3V 5% IN

C8

GND

N.C.

POK2

N.C.

POK2

POK3

Q3

R6

OUT3

2.5V/2A*

C10

R8

R7

DRV3

POK3

C9

ON

OFF

FB3

EN3

R9

*2.5V OUTPUT ONLY WITH V = 12V

DD

Figure 1. MAX8563 Typical Application Circuit

_______________________________________________________________________________________

7

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Typical Application Circuits (continued)

MAX8564/MAX8564A: Dual ꢃutput

1.8V 5% IN

C15

5V OR 12V

IN

1.2V 5% IN

C17

C11

Q4

OUT1

1.5V/1.5A

C20

OFF

R18

Q5

DRV1

FB1

V

DD

C14

R16

C18

R14

OUT2

1.05V/3A

R15

DRV2

FB2

C12

R17

MAX8564

MAX8564A

ON

EN1

ON

OFF

POK1

GND

EN2

POK2

R13

Figure 2. MAX8564/MAX8564A Typical Application Circuit

MAX8564/MAX8564A ExtFrobꢃ

CimpioFot Lꢄst

MAX8563 ExtFrobꢃ CimpioFot Lꢄst

COMPONENTS QTY

DESCꢁIPTION

COMPONENTS QTY

DESCꢁIPTION

C±±

±

0.±µF, ±6V X7R ceramic capacitor

2.2µF, ±0V X5R ceramic capacitors

(optional ±00µF, ±8mΩ, 6.3V

aluminum electrolytic, Sanyo

GTPE±00MI in parallel)

±00µF, ±8mΩ, 6.3V aluminum

electrolytic capacitors

Sanyo GTPE±00MI

C±, C3, C8

3

C±2, C±4

2

C2

±

3

0.±µF, ±6V X7R ceramic capacitor

2.2µF, ±0V X5R ceramic capacitors

(optional ±00µF, ±8mΩ, 6.3V

aluminum electrolytic, Sanyo

GTPE±00MI in parallel)

±00µF, ±8mΩ, 6.3V aluminum

electrolytic capacitors

Sanyo GTPE±00MI

C4, C7, C9

C±5, C±7

2

C5, C6, C±0

Q±/Q2 (dual)

3

±

±µF, ±6V X7R ceramic capacitors

C±8, C20

2

±

±µF, ±6V X7R ceramic capacitors

Dual n-channel MOSFETs, 30V, ±8mΩ

Vishay Si4922DY

Dual n-channel MOSFETs, 30V, ±8mΩ

Vishay Si4922DY

Q4/Q5 (dual)

n-channel MOSFET, 30V, 50mΩ

Fairchild Semiconductor FDD6630A

Q3

±

R±3

R±4

R±5

R±6

R±7

R±8

±

±65Ω ±±1 resistor

±82Ω ±±1 resistor

390Ω ±51 resistor

665Ω ±±1 resistor

332Ω ±±1 resistor

620Ω ±51 resistor

R±

R2

R3

R4

R5

R6

R7

R8

R9

±

665Ω ±±1 resistor

620Ω ±51 resistor

332Ω ±±1 resistor

390Ω ±51 resistor

±82Ω ±±1 resistor

±65Ω ±±1 resistor

9±0Ω ±51 resistor

±kΩ ±±1 resistor

249Ω ±±1 resistor

8

_______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Detailed Description

V

IN_

The MAX8563/MAX8564/MAX8564A triple and dual

LDO controllers allow flexible and inexpensive voltage

conversion by controlling the gate of an external

n-MOSFET in a source-follower configuration. The

MAX8563/MAX8564/MAX8564A consist of multiple

identical LDO controllers. Each LDO controller features

an enable input (EN_) and a power-OK output (POK_).

The MAX8563/MAX8564/MAX8564A also include a 0.5V

reference, an internal regulator, and an undervoltage

lockout (UVLO). The transconductance amplifier mea-

sures the feedback voltage on FB_ and compares it to

an internal 0.5V reference connected to the positive

input. If the voltage on FB_ is lower than 0.5V, the cur-

rent output on the gate-drive output DRV_ is increased.

If the voltage on FB_ is higher than 0.5V, the current out-

put on the gate-drive output is decreased.

Q1

MAX8563

MAX8564

MAX8564A

OUT1

C

R

C

DRV_

C

OUT

Figure 3. Soft-Start and Compensation Schematic

this value are covered in the Power MOSFET Selection

section.

The maximum input voltage to the drain of the n-MOSFET

is a function of the breakdown voltage and the thermal

conditions during operation. The breakdown voltage from

drain to source is normally provided in the MOSFET data

sheet. The theoretical maximum input voltage is the set

output voltage plus the breakdown voltage. The thermal

constraint is usually the largest concern when discussing

maximum input voltage. Details on calculating this value

are covered in the Power MOSFET Selection section. The

MOSFET package and thermal relief on the board are

the largest contributors to removing heat from the

n-MOSFET. Since output voltage is normally set and

maximum output current is fixed, the input voltage

becomes the only variable that determines the maxi-

mum power dissipated. Thus, the maximum input volt-

age is limited by the power capability of the n-MOSFET,

if it is less than the breakdown voltage, which is most

often the case. Ensure input capacitors handle the

maximum input voltage.

Bias ꢄoltage (ꢄ )% ꢀꢄ-ꢃ% and SoftꢁStart

DD

The MAX8563/MAX8564/MAX8564A bias current

for internal circuitry is supplied by V . The V

voltage

DD

range is from 4.5V to ±3.2V. If V

drops below 3.76V

DD

(typ), the MAX8563/MAX8564/MAX8564A assume that

the supply and reference voltages are too low and acti-

vate the UVLO circuitry. During UVLO, the internal regu-

lator (VL) and the internal bandgap reference are forced

off, DRV_ is pulled to GND, and POK_ is pulled low.

Before any internal startup circuitry is activated, V must

DD

be above the UVLO threshold. After UVLO indicates that

V

is high enough, the internal VL regulator, the internal

DD

bandgap reference, and the bias currents are activated.

If EN_ is logic-high after the internal reference and bias

currents are activated, then the corresponding DRV_ out-

put initiates operation in soft-start mode. Once the voltage

on FB_ reaches 941 of the regulation threshold, the full

output current of the LDO controller is permitted.

During a power-up sequence where V

and EN_ rise

DD

before the input to the drain of the n-MOSFET, the

MAX8563/MAX8564/MAX8564A drive DRV_ high but the

When an LDO is activated, the respective DRV_ is pulled

up from GND with a typical soft-start current of DRV soft-

start. The soft-start current limits the slew of the output

voltage and limits the initial spike of current that the drain

of the external n-MOSFET receives. The size of the com-

output does not rise. As DRV_ rails and V

is still below

FB_

801 of the regulation voltage, the MAX8563/MAX8564/

MAX8564A assume that an output short-circuit fault is

present and shut down that regulator. To avoid this error

condition, connect a resistor-divider from V

to IN_ with

DD

pensation capacitor (C ) limits the slew rate (see Figure

C

the middle node connected to the respective EN_ (see

Figure 4). Use the following equations to calculate the

resistor values.

3). This output voltage slew rate is equal to (DRV_soft-

start /C )mV/ms, where C is in µF. The maximum startup

C

drain current is the ratio of C

soft-start current.

to C multiplied by the

C

OUT

When V

is off or at a low-voltage state:

IN_

Input ꢄoltage (Drain ꢄoltage of the

External nꢁMꢃSFET)

The minimum input voltage to the drain of the n-MOSFET

is a function of the desired output voltage and the

dropout voltage of the n-MOSFET. Details on calculating

⎛

⎞

R

E

0.7 >

× V − V

+ V

IN_

(

)

DD

IN_

⎜

⎟

R +R

⎝

⎠

E

D

When V

is on or at a high-voltage state:

IN_

_______________________________________________________________________________________

9

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

The POK_ is an open-drain output that provides the sta-

tus of the output voltage and pulls low depending upon

V

DD

circuit conditions. During startup, once the FB_ reaches

the POK_ threshold, the POK_ signal goes high. The

POK_ threshold has 30mV of hysteresis. When the out-

put voltage drops ±21 below the nominal regulated

voltage, POK_ pulls low. All POK_ outputs pull low

when UVLO is activated or when the internal VL regula-

tor and reference are not ready.

MAX8563

MAX8564

MAX8564A

R

D

E

EN_

R

IN_

ꢃutput ꢀndervoltage and

ꢃverload Protection

When an overload event or short circuit occurs, the

device that is most vulnerable is the external n-MOSFET.

The MAX8563/MAX8564/MAX8564A monitor the output

voltage to protect the MOSFET. When DRV_ is at its maxi-

mum voltage and the output voltage drops below 801

but is still greater than 601 of its nominal voltage for

more than 50µs, the MAX8563/MAX8564/MAX8564A

shut down that particular regulator output by pulling

DRV_ to GND. Note that there is an additional inherent

delay in turning off the MOSFET. The delay is a function

of the compensation capacitor and the MOSFET. If the

output recovers to greater than 801 within 50µs, it is not

considered to be in overload and no action is taken.

When the output voltage drops below 601 of its nominal

voltage, the MAX8563/MAX8564/MAX8564A immediately

shut down that particular regulator output by pulling

Figure 4. Voltage-Divider on EN_

⎛

⎞

R

E

±.3 <

× V − V

+ V

IN_

(

)

DD

IN_

⎜

⎟

R +R

⎝

⎠

E

D

Set R = ±00kΩ. The above equations also assume that

D

> V

V

> ±V when V

is on or at a high-voltage

IN_

DD

IN_

state, and that V > 3V.

DD

Example: Connect ±00kΩ from EN to V

and 4kΩ from

DD

EN_ to IN_. Thus, when V

= ±2V and V _ = 0V, then

DD

IN

V

EN

V

EN

_ = 0.46V. When V

= ±2V and V _ = ±.2V, then

DD IN

_ = ±.6V.

Alternately, to avoid fault shutdown due to the delay of

V

relative to V , pull EN_ low with a separate control

DD

IN

logic and only drive high when V reaches a steady-

IN

DRV_ to GND. To restart that particular LDO, V

must

DD

state value.

be recycled below the UVLO or the corresponding EN_

must be recycled. The overload protection is shown in

the Typical Operating Characteristics.

ꢃutput ꢄoltage

The output voltage range at the source of the n-MOSFET

is from 0.5V to 3.3V when V

is ±2V and from 0.5V to

DD

Design Procedure

±.8V when V

is 5V. The maximum output voltage is a

DD

ꢃutput ꢄoltage Setting

The minimum output voltage for each controller of the

MAX8563/MAX8564/MAX8564A is typically 0.5V. The

maximum output voltage is adjustable up to 3.3V with

function of the minimum gate-to-source voltage (V ) of

GS

the MOSFET and V

.

DD

The external n-MOSFET contains a parasitic diode from

source to drain. If the output is ever anticipated to

exceed the input, current flows from source to drain. If

this is undesirable, external protection is needed. A

simple solution is the placement of a diode in series,

from IN_ to the drain of the n-MOSFET, so that reverse

current is not possible. Due to the forward-voltage drop

of the diode, the maximum output voltage is reduced

and additional power is consumed in the diode.

V

= ±2V, and up to ±.8V with V

= 5V. To set the out-

DD

put voltage, connect the FB_ pin to the center of a volt-

age-divider between OUT_ and GND (Figure 5). The

resistor-divider current should be at least ±mA per ±A of

maximum output current; i.e., for a 3A maximum output

current, set the resistor-divider bias current to ≥ 3mA:

I

OUT(MAX)

I

≥

OUT(MIN)

Enable and PꢃK

The MAX8563/MAX8564/MAX8564A have independent

enable control inputs (EN±, EN2, and EN3). Drive EN±

high to enable output ±. Drive EN2 high to enable out-

put 2. Drive EN3 high to enable output 3. When EN_ is

driven low, the corresponding DRV_ is internally pulled

to GND and POK_ is internally pulled low.

±000

V

500

I

OUT(MAX)

FB

OUT(MIN)

FB

R

≤

= ±000 ×

=

B

I

OUT(MAX)

±0 ______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

⎡

⎢

⎤

⎛

⎞

V

OUT

R

= R

×

− ± = R × 2 × V

− ±

⎥

(

)

A

B

OUT

⎜

⎟

OUT_

⎝

⎢

⎣

⎠

FB

⎥

⎦

MAX8563

MAX8564

MAX8564A

R

A

B

To set the output voltage to 0.5V, disconnect R from

B

FB_ and connect it to OUT_; this change maintains the

minimum load requirement on the output. In this case,

FB_

R can vary from ±kΩ to ±0kΩ.

A

R

Input and ꢃutput Capacitor Selection

The input filter capacitor aids in providing low input

impedance to the regulator and also reduces peak cur-

rents drawn from the power source during transient

conditions. Use a minimum 2.2µF ceramic capacitor

from IN_ (drain of the external pass n-MOSFET) to GND

(see Figures ± and 2). If large line transients or load

transients are expected, increase the input capaci-

tance to help minimize output voltage changes.

Figure 5. Adjustable Output Voltage

current (load current) is the maximum voltage dropout

across the MOSFET, V . Make sure that V

_

DS MIN

meets the condition below to avoid entering dropout,

where output voltage starts to decrease and any ripple

on the input also passes through to the output:

The output filter capacitor and its equivalent series

resistance (ESR) contribute to the stability of the regula-

tor (see the Stability Compensation section) and affect

the load-transient response. If large step loads (no load

to full load) are expected, and a very fast response

(less than a few microseconds) is required, use a

±00µF, ±8mΩ POSCAP for the output capacitor. If a

larger capacitance is desired, keep the capacitance

V

> V

_

+ V

IN_MIN

DS MIN OUT

where V

is the minimum input voltage at the drain

IN_MIN

of the MOSFET. V

_

has a positive temperature

DS MIN

coefficient; therefore, the value of V

operating junction temperature should be used.

_

at the highest

DS MIN

For thermal management, the maximum power dissipa-

tion in the MOSFET is calculated by:

ESR product (C

x R

) in the ±µs to 5µs range.

ESR

OUT

P = (V

- V

) x I

OUT OUT_MAX

D

IN_MAX

If the application expects smaller load steps (less than

501 of full load), then use a 6.8µF ceramic capacitor or

larger per ampere of maximum output current. This

option reduces the size and cost of the regulator circuit.

Note that some ceramic dielectrics exhibit large capaci-

tance variation with temperature. Use X7R or X5R

dielectrics to ensure sufficient capacitance at all operat-

ing temperatures. Tantalum and aluminum capacitors

are not recommended.

The MOSFET is typically in an SMT package. Refer to

the MOSFET data sheet for the PC board area needed

to meet the maximum operating junction temperature

required.

Stability Compensation

Connect a resistor, R , and a capacitor, C , in series

C

from the DRV_ pin to GND. The values of the compen-

sation network depend upon the external MOSFET

characteristics, the output current range, and the pro-

grammed output voltage. The following parameters are

needed from the MOSFET data sheet: the input capaci-

Poꢂer MꢃSFET Selection

The MAX8563/MAX8564/MAX8564A use an n-channel

MOSFET as the series pass transistor instead of a p-

channel MOSFET to reduce cost. The selected MOS-

FET must have a gate threshold voltage that meets the

following criteria:

tance (C

at V

= ±V), the typical forward transcon-

DS

ISS

ductance (g ), and the current at which g

was

FS

DFS

measured (I

). Calculate the transconductance of

the FET at the maximum load current (I

):

OUT_MAX

V

≤ V

- V

DD OUT_

GS_MAX

where V

is the controller bias voltage, and V

GS_MAX

DD

I

OUT_MAX

g

= g

×

is the maximum gate voltage required to yield the on-

C(MAX)

FS

I

DFS

resistance (R

data sheet. R

) specified by the manufacturer’s

multiplied by the maximum output

DS_ON

______________________________________________________________________________________ ±±

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

For the best transient response in applications with

±.5A

8.8A

large step loads (see the Input and Output Capacitor

Selection section for output capacitance requirements),

use the following equations to select the compensation

components:

g

= 30S x

=±2.4S

C(MAX)

±2.4S x

⎛

⎞

±.5V x ±00μF x ±2.4S x

⎜

⎝

⎟

⎠

±8mΩ +±

2

C

= 0.±6 x

−

C

±2.4S x ±.5V + ±.5A

(

)

0.±6 × V

× C

×

⎡

⎢

⎣

⎤

⎥

⎦

OUT

2500pF = 0.90μF, use ±μF.

g

× g

(

×R

ESR

+±

⎢

⎥

)

C(MAX)

C

=

− C

±.5V x ±00μF x ±2.4S x ±8mΩ +±

(

)

C

ISS

2

R

= 59 x

C

g

× V

+I

(

)

C(MAX)

OUT OUT_MAX

±μF ±2.4S x ±.5V + ±.5A

(

)

V

x C

g

x R

+±

= 599.4Ω, use 620Ω.

(

)

OUT

OUT C(MAX)

ESR

R

= 59 ×

C

x g

× V

+ I

(

)

C

C(MAX)

OUT

OUT_MAX

PC Board -ayout Guidelines

Due to the high-current paths and tight output accuracy

required by most applications, careful PC board layout is

required. An evaluation kit (MAX8563EVKIT) is available

to speed design.

where C

is the output capacitance and R

is the

OUT

ESR

ESR of C

.

OUT

To use a low-cost ceramic capacitor (see the Input and

Output Capacitor Selection section for load-transient

response characteristics), use the following equations

to select the compensation components:

It is important to keep all traces as short as possible to

maximize the high-current trace dimensions to reduce the

effect of undesirable parasitic inductance. The MOSFET

dissipates a fair amount of heat due to the high currents

involved, especially during large input-to-output voltage

differences. To dissipate the heat generated by the

MOSFET, make power traces very wide with a large

amount of copper area. An efficient way to achieve good

power dissipation on a surface-mount package is to lay

out copper areas directly under the MOSFET package on

multiple layers and connect the areas through vias. Use a

ground plane to minimize impedance and inductance. In

addition to the usual high-power considerations, here are

four tips to ensure high output accuracy:

C

x g

OUT

x V

C(MAX)

C

=

− C

ISS

C

g

(

+ I

)

C(MAX)

OUT_MAX

C

OUT

R

= ±5 x

C

x g

C(MAX)

C

Example

OUTPUT ± of Figure ± is used in this example. Table ±

shows the values required to calculate the compensa-

tion. The values were taken from the appropriate data

sheets and Figure ±.

•

Ensure that the feedback connection to C

short and direct.

is

OUT_

TbdꢃF ±. PbrbmFtFrs ꢁFquꢄrFe ti

CbꢃauꢃbtF CimpFosbtꢄio

•

Place the feedback resistors next to the FB pin.

Place R and C next to the DRV_ pin.

C

PAꢁAMETEꢁ CONDITIONS

MOSFET C = ±V

VALUE

2500

30

UNITS

pF

S

Ensure FB_ and DRV_ traces are away from noisy

sources to ensure tight accuracy.

V

ISS

DS

MOSFET GFS

IDFS = 8.8A

Figure ±

V

±.5

V

OUT±

I

±.5

A

OUT_MAX

C

±00

±8

µF

OUT±

ESR

R

mΩ

±2 ______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Pin Configurations

TOP VIEW

DRV1

1

2

3

4

5

6

7

8

16 V

DD

FB1

EN1

15 DRV2

14 FB2

POK1

GND

N.C.

MAX8563

13 EN2

12 POK2

11 N.C.

10 POK3

DRV1

FB1

1

2

3

4

5

10

9

V

DD

DRV2

FB2

MAX8564

MAX8564A

EN1

8

DRV3

FB3

POK1

GND

7

EN2

9

EN3

6

POK2

QSOP

μMAX

Chip Information

TRANSISTOR COUNT: ±80±

PROCESS: BiCMOS

______________________________________________________________________________________ ±3

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.mbxꢄm-ꢄa.aim/pbacbꢂFs.)

PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH

1

21-0055

F

1

±4 ______________________________________________________________________________________

±±1% ꢀltraꢁ-oꢂ ꢃutput ꢄoltage% Dual and Triple

-inear nꢁFET Controllers

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.mbxꢄm-ꢄa.aim/pbacbꢂFs.)

e

4X S

10

INCHES

MAX

MILLIMETERS

MAX

1.10

0.15

0.95

3.05

3.00

3.05

3.00

5.05

0.70

DIM MIN

MIN

-

A

-

0.043

0.006

0.037

0.120

0.118

0.120

0.118

0.199

A1

A2

D1

D2

E1

E2

H

0.002

0.030

0.116

0.114

0.116

0.114

0.187

0.05

0.75

2.95

2.89

2.95

2.89

4.75

0.40

H

Ø0.50 0.1

0.6 0.1

L

0.0157 0.0275

0.037 REF

L1

b

0.940 REF

0.007

0.0106

0.177

0.270

0.200

1

e

0.0197 BSC

0.500 BSC

0.6 0.1

c

0.0035 0.0078

0.0196 REF

0.090

BOTTOM VIEW

0.498 REF

S

α

TOP VIEW

0°

6°

0°

6°

D2

E2

GAGE PLANE

A2

c

A

E1

b

L

α

A1

D1

L1

FRONT VIEW

SIDE VIEW

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, 10L uMAX/uSOP

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0061

1

Revision History

Pages changes at Rev 2: ±, ±2, ±4, ±5

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products% ±20 San Gabriel Drive% Sunnyvale% CA 94086 408ꢁ737ꢁ7600 ____________________ ±5

is a registered trademark of Maxim Integrated Products, Inc.

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