MC14017BFR2_技术文档

MC14017B

Decade Counter

The MC14017B is a five−stage Johnson decade counter with

built−in code converter. High speed operation and spike−free outputs

are obtained by use of a Johnson decade counter design. The ten

decoded outputs are normally low, and go high only at their

appropriate decimal time period. The output changes occur on the

positive−going edge of the clock pulse. This part can be used in

frequency division applications as well as decade counter or decimal

decode display applications.

http://onsemi.com

MARKING

DIAGRAMS

• Fully Static Operation

16

• DC Clock Input Circuit Allows Slow Rise Times

• Carry Out Output for Cascading

• Divide−by−N Counting

PDIP−16

P SUFFIX

CASE 648

MC14017BCP

AWLYYWW

1

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• Pin−for−Pin Replacement for CD4017B

16

SOIC−16

D SUFFIX

CASE 751B

14017B

AWLYWW

• Triple Diode Protection on All Inputs

1

16

SOEIAJ−16

F SUFFIX

CASE 966

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

SS

MC14017B

ALYW

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage Range

−0.5 to +18.0

1

V , V

Input or Output Voltage Range

(DC or Transient)

−0.5 to V

DD

+ 0.5

V

in out

A

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

mA

WW, W = Work Week

P

D

Power Dissipation,

per Package (Note 3.)

500

mW

ORDERING INFORMATION

T

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

A

Device

Package

PDIP−16

SOIC−16

Shipping

T

stg

T

Lead Temperature

(8−Second Soldering)

MC14017BCP

MC14017BD

2000/Box

48/Rail

L

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

MC14017BDR2

SOIC−16 2500/Tape & Reel

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

MC14017BF

SOEIAJ−16

See Note 1.

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

MC14017BFEL

1. For ordering information on the EIAJ version of the

SOIC packages, please contact your local ON

Semiconductor representative.

high−impedance circuit. For proper operation, V and V

should be constrained

in out

to the range V

SS

v (V or V ) v V .

in out DD

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

SS DD

Semiconductor Components Industries, LLC, 2000

64

Publication Order Number:

August, 2000 − Rev. 4

MC14017B/D

MC14017B

PIN ASSIGNMENT

Q5

Q1

Q0

Q2

Q6

Q7

Q3

1

2

3

4

5

6

7

8

16

V

DD

15 RESET

14 CLOCK

13

12

CE

C

out

11 Q9

10 Q4

V

9

Q8

SS

FUNCTIONAL TRUTH TABLE

(Positive Logic)

BLOCK DIAGRAM

CLOCK 14

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

3

2

Clock

Decode

Clock Enable Reset Output=n

4

0

X

1

X

0

1

0

n

Q0

n+1

n

7

10

1

CLOCK

ENABLE

13

5

X

6

X

1

n

n+1

9

11

12

RESET 15

C

out

X = Don’t Care. If n < 5 Carry = “1”,

Otherwise = “0”.

V

= PIN 16

= PIN 8

DD

SS

LOGIC DIAGRAM

Q5

Q1

Q7

Q3

7

Q9

11

1

2

6

14

CLOCK

12

C

D

R

Q

C

D

R

Q

C

D

R

Q

C

D

R

Q

C

D

R R

Q

ENABLE

13

CARRY

Q

R

Q

R

Q

R

15

RESET

3

5

4

9

10

Q0

Q6

Q2

Q3

Q4

http://onsemi.com

65

MC14017B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

− 55_C

25_C

(4.)

125_C

V

Vdc

DD

Min

Max

Min

Typ

Max

Min

Max

Characteristic

Output Voltage

Symbol

Unit

“0” Level

“1” Level

“0” Level

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

V

in

= V

DD

or 0

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

V

in

= 0 or V

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

V

IH

Vdc

“1” Level

5.0

10

15

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

(V = 0.5 or 4.5 Vdc)

O

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V

= 2.5 Vdc)

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

Source

Sink

5.0

10

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

OH

15

(V

OL

(V

OL

(V

OL

= 0.4 Vdc)

= 0.5 Vdc)

= 1.5 Vdc)

I

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

OL

Input Current

I

15

—

± 0.1

—

±0.00001 ± 0.1

—

± 1.0

µAdc

in

Input Capacitance

C

—

5.0

7.5

—

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

5.0

10

20

—

0.005

0.010

0.015

5.0

10

20

—

150

300

600

µAdc

DD

(5.) (6.)

Total Supply Current

I

T

5.0

10

15

I

= (0.27 µA/kHz) f + I

= (0.55 µA/kHz) f + I

= (0.83 µA/kHz) f + I

T

DD

(Dynamic plus Quiescent,

Per Package)

(C = 50 pF on all outputs, all

L

buffers switching)

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C – 50) Vfk

T

L

T

L

where: I is in µA (per package), C in pF, V = (V

DD

– V ) in volts, f in kHz is input frequency, and k = 0.0011.

SS

T

L

http://onsemi.com

66

MC14017B

(7.)

SWITCHING CHARACTERISTICS

(C = 50 pF, T = 25_C)

L A

V

Vdc

DD

(8.)

Characteristic

Symbol

Min

Typ

Max

Unit

Output Rise and Fall Time

t

,

ns

TLH

t

, t

= (1.5 ns/pF) C + 25 ns

= (0.75 ns/pF) C + 12.5 ns

= (0.55 ns/pF) C + 9.5 ns

L

5.0

10

15

—

100

50

40

200

100

80

TLH THL

L

THL

, t

TLH THL

, t

TLH THL

Propagation Delay Time

Reset to Decode Output

t

,

ns

PLH

t

PHL

t

, t

= (1.7 ns/pF) C + 415 ns

= (0.66 ns/PF) C + 197 ns

L

= (0.5 ns/pF) C + 150 ns

5.0

10

15

—

500

230

175

1000

460

350

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

L

Propagation Delay Time

Clock to C

,

PLH

t

out

= (1.7 ns/pF) C + 315 ns

PHL

t

, t

5.0

10

15

—

400

175

125

800

350

250

PLH PHL

L

= (0.66 ns/pF) C + 142 ns

PLH PHL

, t

PLH PHL

= (0.5 ns/pF) C + 100 ns

L

Propagation Delay Time

Clock to Decode Output

,

PLH

t

PHL

t

, t

= (1.7 ns/pF) C + 415 ns

= (0.66 ns/pF) C + 197 ns

L

= (0.5 ns/pF) C + 150 ns

5.0

10

15

—

500

230

175

1000

460

350

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

L

Turn−Off Delay Time

t

PLH

Reset to C

out

= (1.7 ns/pF) C + 315 ns

t

5.0

10

15

—

400

175

125

800

350

250

PLH

L

= (0.66 ns/pF) C + 142 ns

L

= (0.5 ns/pF) C + 100 ns

L

Clock Pulse Width

t

5.0

10

15

250

100

75

125

50

35

—

ns

MHz

ns

w(H)

Clock Frequency

f

cl

5.0

10

15

—

5.0

12

16

2.0

5.0

6.7

Reset Pulse Width

t

5.0

10

15

500

250

190

250

125

95

—

w(H)

Reset Removal Time

Clock Input Rise and Fall Time

Clock Enable Setup Time

Clock Enable Removal Time

t

5.0

10

15

750

275

210

375

135

105

—

ns

rem

t

,

5.0

10

15

—

TLH

THL

No Limit

t

su

5.0

10

15

350

150

115

175

75

52

—

ns

t

5.0

10

15

420

200

140

260

100

70

—

ns

rem

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

http://onsemi.com

67

MC14017B

V

DD

V

Output

Sink Drive Source Drive

Output

out

CLOCK

ENABLE

V

SS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Clock to

desired

outputs

(S1 to B)

Decode

Outputs

(S1 to A)

A

B

V

S1

DD

I

D

RESET

Clock to 5

thru 9

(S1 to B)

V

Carry

S1 to A

SS

V

=

V

DD

− V

GS

DD

EXTERNAL

POWER

V

out

V − V

out DD

C

DS

CLOCK

out

SUPPLY

V

SS

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

V

DD

0.01 µF

CERAMIC

I

D

500 µF

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

CLOCK

ENABLE

RESET

CLOCK

f

c

PULSE

GENERATOR

C

out

V

SS

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

Figure 2. Typical Power Dissipation Test Circuit

http://onsemi.com

68

MC14017B

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are

sequential within each stage and from stage to stage, with no dead time (except propagation delay).

RESET

CLOCK

MC14017B

• • •

Q8 Q9

CE

• • •

Q0 Q1

Q8 Q9

Q0Q1

Q8 Q9

Q1

8 DECODED

OUTPUTS

9 DECODED

OUTPUTS

8 DECODED

OUTPUTS

CLOCK

FIRST STAGE

INTERMEDIATE STAGES

LAST STAGE

Figure 3. Counter Expansion

Pcp

Ncp

90%

V

DD

CLOCK

50%

V

SS

V

10%

20 ns

t

su

20 ns

rem

CLOCK

DD

ENABLE

V

SS

t

rem

RESET

20 ns

V

DD

V

SS

t

PLH

t

PHL

Q0

V

OH

V

OL

t

TLH

t

PHL

PLH

V

90%

10%

OH

50%

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

V

OL

t

THL

PLH

PHL

TLH

V

OH

V

OL

t

PHL

t

THL

PLH

TLH

V

OH

50%

V

OL

t

PLH

PHL

TLH

THL

V

OH

t

V

OL

THL

t

TLH

PLH

PHL

t

PHL

V

OH

V

OL

t

THL

TLH

t

PHL

PLH

V

90%

OH

10%

V

OL

t

THL

t

PHL

PLH

V

OH

V

OL

t

THL

V

t

OH

PLH

V

OL

t

THL

PLH

TLH

t

PHL

V

OH

Q9

C

V

OL

V

t

PHL

t

TLH

THL

PHL

t

PLH

out

OH

V

OL

t

THL

t

TLH

Figure 4. AC Measurement Definition and Functional Waveforms

http://onsemi.com

69


型号：	MC14017BFR2
厂家：	Rochester Electronics
描述：	Ring Counter, 4000/14000/40000 Series, Synchronous, Positive Edge Triggered, 10-Bit, Up Direction, CMOS, PDSO16, EIAJ, SOIC-16 光电二极管逻辑集成电路触发器
文件：	总7页 (文件大小：794K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14017BFR2 [ROCHESTER]

相关型号：

MC14017B_05

MC14018B

MC14018B

MC14018BALD

MC14018BALDS

MC14018BALS

MC14018BBEBS

MC14018BCL

MC14018BCLD

MC14018BCLDS

MC14018BCLS

MC14018BCP