MC74HCT245AH [ROCHESTER]
HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20;
| 型号： | MC74HCT245AH |
| 厂家： | 
Rochester Electronics |
| 描述： | HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20 光电二极管 输出元件 |
| 文件： | 总11页 (文件大小：901K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74HCT245A is identical in pinout to the LS245. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
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The MC74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses.
The device has an active–low Output Enable pin, which is used to
place the I/O ports into high–impedance states. The Direction control
determines whether data flows from A to B or from B to A.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
MARKING
DIAGRAMS
20
PDIP–20
N SUFFIX
CASE 738
MC74HCT245AN
AWLYYWW
20
1
1
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT245A
AWLYYWW
20
1
1
20
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
HCT
245A
ALYW
TSSOP–20
DT SUFFIX
CASE 948G
20
• Chip Complexity: 304 FETs or 76 Equivalent Gates
1
LOGIC DIAGRAM
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A
DATA
PORT
B
DATA
PORT
PIN ASSIGNMENT
DIRECTION
1
2
3
4
5
6
7
8
9
20
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
19 OUTPUT ENABLE
18 B1
1
DIRECTION
PIN 20 = V
CC
PIN 10 = GND
17 B2
19
OUTPUT ENABLE
16 B3
Design Criteria
Internal Gate Count*
Value Units
15 B4
76
1.0
ea
ns
14 B5
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
13 B6
12 B7
5.0
µW
pJ
GND 10
11 B8
0.005
*Equivalent to a two–input NAND gate.
FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Output
Device
Package
PDIP–20
Shipping
Enable
Direction
Operation
MC74HCT245AN
1440 / Box
38 / Rail
L
L
L
H
X
Data Transmitted from Bus B to Bus A
Data Transmitted from Bus A to Bus B
Buses Isolated (High–Impedance State)
MC74HCT245ADW
SOIC–WIDE
MC74HCT245ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT245ADT
TSSOP–20
75 / Rail
H
X = Don’t Care
MC74HCT245ADTR2
TSSOP–20 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HCT245A/D
MC74HCT245A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
6.0 mA
4.5
5.5
5.5
0.26
± 0.1
4.0
0.33
± 1.0
40
0.4
± 1.0
160
out
I
in
Maximum Input Leakage Current
V
in
= V
or GND, Pins 1 or 19
or GND
µA
µA
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
= 0 µA
CC
in
I
out
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
5.5
± 0.5
± 5.0
± 10
µA
OZ
V
in
= V or V
IL
= V
IH
or GND, I/O Pins
V
out
CC
∆I
CC
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
≥ –55 C
2.9
25 C to 125 C
in
in
out
= V
or GND, Other Inputs
CC
= 0 µA
5.5
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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2
MC74HCT245A
AC ELECTRICAL CHARACTERISTICS (V
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
CC
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, A to B or B to A
(Figures 1 and 3)
22
30
30
12
28
33
ns
PLH
PHL
t
t
,
Maximum Propagation Delay, Direction or Output Enable to A or B
(Figures 2 and 4)
36
36
15
42
42
18
ns
ns
ns
PLZ
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to A or 8
(Figures 2 and 4)
PZL
PZH
t
t
,
Maximum Output Transition Time. any Output
(Figures 1 and 3)
TLH
THL
C
Maximum Input Capacitance (Pin 1 or 19)
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State I/O Capacitance, (I/O in High–Impedance
State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
97
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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3
MC74HCT245A
SWITCHING WAVEFORMS
3.0 V
DIRECTION
1.3 V
1.3 V
GND
3.0 V
t
r
t
f
OUTPUT
ENABLE
1.3 V
3.0 V
GND
GND
INPUT
A OR B
2.7 V
1.3 V
0.3 V
t
t
PLZ
PZL
HIGH
IMPEDANCE
t
t
PHL
1.3 V
t
PLH
A OR B
A OR B
10%
90%
V
OL
90%
1.3 V
10%
OUTPUT
B OR A
t
PZH
PHZ
V
OH
1.3 V
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 1.
Figure 2.
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kΩ
OUTPUT
TESTING t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
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4
MC74HCT245A
EXPANDED LOGIC DIAGRAM
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
18
17
16
15
B1
B2
B3
B4
A
DATA
PORT
B
DATA
PORT
14
13
12
11
B5
B6
B7
B8
1
DIRECTION
19
OUTPUT ENABLE
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5
MC74HCT245A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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6
MC74HCT245A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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7
MC74HCT245A
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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PUBLICATION ORDERING INFORMATION
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MC74HCT245A/D
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Device MC74HCT245A
Octal 3-State Non-Inverting Transceiver
Reliability Data
PCN
High-Performance Silicon-Gate CMOS
Samples FAQ
Part Nomenclature
The MC74HCT245A is identical in pinout to the LS245. This device may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
Tech Support
The MC74HCT245A is a 3-state noninverting transceiver that is used for 2-way asynchronous communication between data
buses. The device has an active-low Output Enable pin, which is used to place the I/O ports into high-impedance states.
The Direction control determines whether data flows from A to B or from B to A.
Features:
l Output Drive Capability: 15 LSTTL Loads
l TTL/NMOS Compatible Input Levels
l Outputs Directly Interface to CMOS, NMOS and TTL
l Operating Voltage Range: 4.5 to 5.5 V
l Low Input Current: 1.0 mA
l In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
l Chip Complexity: 304 FETs or 76 Equivalent Gates
Orderable Parts
Package Pin
Desc. Count Outline
Case
Action Orderable Part
Short Desc.
Status
Price/Unit Pack Qty
N/A
N/A
MC74HCT245ADT
MC74HCT245ADW
Octal 3-State
Non-Inverting
Bus/Transceiver
TSSOP
SOIC
20
20
948E-02 Active
751D-05 Active
751D-05 Active
$0.320
$0.280
75
38
Octal 3-State
Non-Inverting
Bus/Transceiver
N/A
N/A
MC74HCT245ADWR2 Tape and Reel
SOIC
N/A
20
$0.280
$0.280
1000
40
MC74HCT245AF
Octal 3-State
Non-Inverting
Bus/Transceiver
N/A
N/A
Active
N/A
N/A
N/A
MC74HCT245AFEL
MC74HCT245AFL1
MC74HCT245AN
Tape and Reel
Tape and Reel
N/A
N/A
N/A
20
N/A
Active
$0.280
$0.280
2000
360
N/A
N/A
LifeTime
Active
Octal 3-State
Non-Inverting
Bus/Transceiver
PDIP
738-03
N/A
N/A
MC74HCT245ADTR2
MC74HCT245AH
Tape and Reel
TSSOP
PDIP
14
948G-01 Active,
Not Rec
$0.320
$0.280
2500
360
Octal 3-State
Non-Inverting
Transceiver
804-01
Active,
Not Rec
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