MC74VHC244MEL [ROCHESTER]
AHC/VHC SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20;
| 型号： | MC74VHC244MEL |
| 厂家： | 
Rochester Electronics |
| 描述： | AHC/VHC SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20 驱动 光电二极管 输出元件 |
| 文件： | 总9页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC244
Octal Bus Buffer
The MC74VHC244 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology.
The MC74VHC244 is a noninverting 3--state buffer, and has two
active--low output enables. This device is designed to be used with
3--state memory address drivers, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
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MARKING DIAGRAM
20
VHC244
AWLYYWWG
• High Speed: tPD = 3.9 ns (Typ) at VCC = 5 V
20
1
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
1
SOIC--20 WB
DW SUFFIX
CASE 751D
20
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: VOLP = 0.9 V (Max)
VHC
244
ALYW
20
1
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V
Machine Model > 200 V
• Chip Complexity: 136 FETs
• Pb--Free Packages are Available*
1
TSSOP--20
DT SUFFIX
CASE 948E
20
1
74VHC244
AWLYWW
20
1
SOIC EIAJ--20
M SUFFIX
CASE 967
2
4
6
8
18
16
14
12
A1
A2
A3
A4
YA1
YA2
YA3
YA4
A
= Assembly Location
= Year
WL, L = Wafer Lot
YY, Y
WW, W = Work Week
PIN ASSIGNMENT
DATA
INPUTS
NONINVERTING
OUTPUTS
11
13
15
17
9
7
5
3
OEA
1
20
V
CC
B1
B2
B3
B4
YB1
YB2
YB3
YB4
A1
YB4
A2
2
3
4
5
6
7
8
9
19 OEB
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
YB3
A3
YB2
A4
1
19
OEA
OEB
OUTPUT
ENABLES
YB1
GND 10
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the
Ordering Information Table on page 2 of this data sheet.
*For additional information on our Pb--Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 -- Rev. 7
MC74VHC244/D
MC74VHC244
FUNCTION TABLE
INPUTS
OUTPUTS
OEA, OEB
A, B
L
YA, YB
L
L
L
H
Z
H
H
X
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC244DW -- OBSOLETE*
MC74VHC244DWR2
MC74VHC244DT
SOIC--20 WB
SOIC--20 WB
38 Units/Rail
1000/Tape & Reel
75 Units/Rail
TSSOP--20
(Pb--Free)
MC74VHC244DTR2
TSSOP--20
(Pb--Free)
2500/Tape & Reel
1600 Units/Box
MC74VHC244M -- OBSOLETE*
MC74VHC244MEL
SOIC EIAJ--20
(Pb--Free)
SOIC EIAJ--20
(Pb--Free)
2000/Tape & Reel
*This device is obsolete, information available for reference.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
--0.5 to +7.0
--0.5 to +7.0
CC
IN
V
DC Output Voltage
--0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
-- 2 0
±20
±25
±75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC
TSSOP
500
450
D
T
Storage Temperature Range
ESD Withstand Voltage
--65 to +150
°C
STG
V
Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ESD
Charged Device Model (Note 4)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
±300
mA
LATCHUP
CC
θ
JA
Thermal Resistance, Junction--to--Ambient
SOIC
96
°C/W
TSSOP
128
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. V and V should be constrained to the range GND ≤ (V orV ) ≤ V . Unused inputs must always be tiedto anappropriate logic voltage
in
out
in
out
CC
level (e.g., either GND or V ). Unused outputs must be left open.
CC
2. Tested to EIA/JESD22--A114--A
3. Tested to EIA/JESD22--A115--A
4. Tested to JESD22--C101--A
5. Tested to EIA/JESD78
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2
MC74VHC244
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
0
V
V
OUT
CC
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
-- 5 5
0
125
°C
ns/V
A
t , t
r
V
V
= 3.3 V + 0.3 V
= 5.0 V + 0.5 V
100
20
f
CC
CC
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 2. Failure Rate vs. Time Junction Temperature
DC CHARACTERISTICS (Voltages Referenced to GND)
V
T
A
= 25°C
T
A
≤ 85°C
-- 5 5 °C ≤ T ≤ 125°C
A
CC
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
1.5
Min
Max
Unit
V
V
V
Minimum High--Level
Input Voltage
2.0
1.5
1.5
1.5
V
IH
3.0 to
5.5
V
CCX
V
CCX
V
CCX
V
CCX
0.7
0.7
0.7
0.7
Maximum Low--Level
Input Voltage
2.0
0.5
0.5
0.5
V
V
IL
3.0 to
5.5
V
CCX
V
CCX
V
CCX
0.3
0.3
0.3
V
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
Maximum High--Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
I
= --50 mA
OH
V
IN
= V or V
IH
I
= --4 mA
3.0
4.5
2.58
3.94
2.48
3.8
2.34
3.66
OH
I
= --8 mA
OH
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Maximum Low--Level
Output Voltage
V
IH
OL
I
OL
= 50 mA
V
IN
= V or V
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OH
I
OH
I
I
Input Leakage Current
V
= 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
mA
IN
IN
Maximum 3--State
Leakage Current
V
V
= V or V
IL
5.5
±0.25
±2.5
±2.5
OZ
CC
IN
IH
= V or GND
OUT
CC
I
Maximum Quiescent
Supply Current
(per package)
V
IN
= V or GND
5.5
4.0
40.0
40.0
mA
CC
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3
MC74VHC244
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
-- 5 5 °C ≤ T
A
≤ 125°C
T
A
= 25°C
T ≤ 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Maximum Propagation
Delay, A to YA or
B to YB
V
V
V
= 3.3 ± 0.3 V
C
C
= 15 pF
= 50 pF
5.8
8.3
8.4
11.9
1.0
1.0
10.0
13.5
1.0
1.0
11.0
14.5
ns
PLH
CC
CC
CC
L
L
PHL
= 5.0 ± 0.5 V
C
L
C
L
= 15 pF
= 50 pF
3.9
5.4
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.5
9.5
t
t
,
Output Enable Time
OEA to YA or
OEB to YB
= 3.3 ± 0.3 V
= 1 kΩ
C
L
C
L
= 15 pF
= 50 pF
6.6
9.1
10.6
14.1
1.0
1.0
12.5
16.0
1.0
1.0
13.5
17.0
ns
ns
ns
PZL
R
PZH
L
V
R
= 5.0 ± 0.5 V
= 1 kΩ
C
L
C
L
= 15 pF
= 50 pF
4.7
6.2
7.3
9.3
1.0
1.0
8.5
10.5
1.0
1.0
9.5
11.5
CC
L
t
t
,
Output Disable Time
OEA to YA or
OEB to YB
V
R
= 3.3 ± 0.3 V
= 1 kΩ
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
10.3
14.0
9.2
1.5
1.0
10
1.0
16.0
10.5
1.5
1.0
17.0
11.5
1.5
PLZ
CC
L
L
L
L
PHZ
L
V
R
= 5.0 ± 0.5 V
= 1 kΩ
6.7
1.0
1.0
CC
L
t
,
Output to Output Skew
V
= 3.3 ± 0.3 V
CC
OSLH
t
(Note 6)
OSHL
V
= 5.0 ± 0.5 V
1.0
1.5
CC
(Note 6)
C
in
Maximum Input
Capacitance
4
6
10
10
pF
pF
C
Maximum Three--State
Output Capacitance
(Output in High--Impedance
State)
out
Typical @ 25°C, V = 5.0V
CC
19
C
Power Dissipation Capacitance (Note 7)
= |t
pF
PD
6. Parameter guaranteed by design. t
-- t
|, t
= |t
-- t
|.
PHLn
OSLH
PLHm
PLHn OSHL
PHLm
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ¯ V ¯ f + I /8 (per bit). C is used to determine the no--load
CC(OPR
CC
PD CC in CC PD
2
dynamic power consumption; P = C ¯ V
¯ f + I ¯ V
.
D
PD
CC
in
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
Quiet Output Maximum Dynamic V
0.6
0.9
-- 0 . 9
3.5
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
-- 0 . 6
V
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
1.5
V
ILD
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4
MC74VHC244
SWITCHING WAVEFORMS
V
CC
V
CC
A or B
OEA or OEB
50%
50%
GND
GND
t
t
PLZ
PZL
HIGH
t
t
PHL
PLH
IMPEDANCE
YA or YB
50% V
CC
YA or YB
YA or YB
50% V
CC
V
V
+0.3V
OL
t
t
PHZ
PZH
--0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kΩ
OUTPUT
TESTING t AND t
.
PLZ
PZL
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
INPUT
Figure 7. Input Equivalent Circuit
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5
MC74VHC244
OUTLINE DIMENSIONS
SOIC--20 WB
DW SUFFIX
CASE 751D--05
ISSUE G
D
A
θ
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
20
11
10
E
B
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
T
0.25
A
B
A
e
H
h
L
θ
1.27 BSC
10.05
0.25
0.50
10.55
0.75
0.90
SEATING
PLANE
18X
e
0
7
_
_
A1
C
T
TSSOP--20
DT SUFFIX
CASE 948E--02
ISSUE B
20X K REF
NOTES:
M
S
S
0.10 (0.004)
T U
V
S
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
0.15 (0.006) T U
K
K1
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
20
11
2X L/2
J
J1
B
L
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
-- U --
PIN 1
IDENT
SECTION N--N
1
10
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE --W--.
0.25 (0.010)
N
S
0.15 (0.006) T U
M
A
-- V --
N
F
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
DETAIL E
A
B
C
6.40
4.30
-- -- --
6.60 0.252
4.50 0.169
1.20
-- -- --
-- W --
D
F
0.05
0.50
0.15 0.002
0.75 0.020
C
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
G
D
H
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
DETAIL E
0.100 (0.004)
-- T -- SEATING
PLANE
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
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6
MC74VHC244
OUTLINE DIMENSIONS
SOIC EIAJ--20
M SUFFIX
CASE 967--01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
20
11
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
e
A
DIM MIN
MAX
2.05
0.20 0.002
0.50 0.014
0.27 0.007
12.80 0.486
5.45 0.201
MIN
-- -- --
MAX
0 . 0 8 1
0.008
0.020
0.011
0.504
0.215
c
A
1
b
c
-- -- --
0.05
0.35
0.18
12.35
5.10
A
D
E
e
A
1
b
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
E
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
L
L
E
M
Q
Z
0
0.70
-- -- --
10
10
0.035
0 . 0 3 2
0
_
_
_
_
0.90 0.028
0 . 8 1 -- -- --
1
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7
MC74VHC244
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC244/D
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