S3012A_技术文档

®

DEVICE SPECIFICATION

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

BiCMOS PECL CL

K GENERATOR

GENERAL DESCRIPTION

FEATURES

• Complies with ANSI, Bellcore, and ITU-T

specifications

The S3011/S3012 SONET/SDH transmitter and re-

ceiver chips are fully integrated serialization/

deserialization SONET OC-3 (155.52 Mbit/s) interface

devices. With architecture developed by the Pacific

Microelectronics Centre (PMC), the chipset performs

allnecessaryserial-to-parallelandparallel-to-serialfunc-

tions in conformance with SONET/SDH transmission

standards. The devices are also suitable for ATM appli-

cations. Figure 1 shows a typical network application.

• On-chip high-frequency PLL for clock

generation and clock recovery

• Supports 155.52 Mbit/s (OC-3)

• Reference frequency of 19.44 MHz

• Interface to both PECL and TTL/CMOS logic

• 8-bit TTL/CMOS datapath

• Compact 80 PQFP package

• Diagnostic loopback mode

• Lock detect

On-chip clock synthesis is performed by the high-

frequency phase-locked loop on the S3011 transmitter

chip allowing the use of a slower external transmit clock

reference. Clock recovery is performed on the S3012

receiver chip by synchronizing its on-chip VCO directly

to the incoming data stream. The S3012 also performs

SONET/SDH frame detection. The chipset can be used

with 19.44 MHz reference clocks, in support of existing

system clocking schemes.

• Low jitter PECL interface

• < 2.5 Watt per set

APPLICATIONS

• SONET/SDH-based transmission systems

• SONET/SDH modules

• SONET/SDH test equipment

• ATM over SONET

• Section repeaters

• Add drop multiplexors

• Broad-band cross-connects

• Fiber optic terminators

• Fiber optic test equipment

The low jitter PECL interface guarantees compliance

with the bit-error rate requirements of the Bellcore,

ANSI, and ITU-T standards. The S3011/S3012 chipset

is packaged in a 80 PQFP, offering designers a small

package outline.

Figure 1. System Block Diagram

S3011

SONET/SDH

Transmitter

Network

Interface

Processor

8

Network

Interface

Processor

S3012

SONET/SDH

Receiver

OTX

ORX

1

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Figure 2. SONET Structure

SONET OVERVIEW

Layer Overhead

(Embedded Ops

Channel)

Synchronous Optical Network (SONET) is a standard

for connecting one fiber system to another at the optical

level. SONET, together with the Synchronous Digital

Hierarchy (SDH) administered by the ITU-T, forms a

single international standard for fiber interconnect be-

tweentelephonenetworksofdifferentcountries.SONET

is capable of accommodating a variety of transmission

rates and applications.

Functions

Payload to

SPE mapping

Path layer

Line layer

Maintenance,

protection,

switching

576 Kbps

192 Kbps

Line layer

Scrambling,

framing

Section layer

The SONET standard is a layered protocol with four

separate layers defined. These are:

Optical

transmission

Photonic layer

0 bps

• Photonic

• Section

• Line

Fiber Cable

End Equipment

• Path

Figure 2 shows the layers and their functions. Each of

thelayershasoverheadbandwidthdedicatedtoadmin-

istration and maintenance. The photonic layer simply

handles the conversion from electrical to optical and

back with no overhead. It is responsible for transmitting

the electrical signals in optical form over the physical

media. The section layer handles the transport of the

framed electrical signals across the optical cable from

one end to the next. Key functions of this layer are

framing, scrambling, and error monitoring. The line

layer is responsible for the reliable transmission of the

path layer information stream carrying voice, data, and

video signals. Its main functions are synchronization,

multiplexing, and reliable transport. The path layer is

responsible for the actual transport of services at the

appropriate signaling rates.

Table 1. SONET Signal Hierarchy

Elec.

STS-1

ITU-T

STM-1

STM-4

Optical Data Rate (Mbit/s)

OC-1

51.84

STS-3

OC-3

155.52

466.56

622.08

933.12

1244.16

1866.24

2488.32

STS-9

OC-9

STS-12

STS-18

STS-24

STS-36

STS-48

OC-12

OC-18

OC-24

OC-36

OC-48

STM-16

Figure 3. STS–3/OC–3 Frame Format

A1 A1 A1 A2 A2 A2 C1 C1 C1

Data Rates and Signal Hierarchy

B1

D1 *

*

E1

D2

*

F1

D3 *

*

Table 1 contains the data rates and signal designations

of the SONET hierarchy. The lowest level is the basic

SONET signal referred to as the synchronous transport

signal level-1 (STS-1). An STS-N signal is made up of

N byte-interleaved STS-1 signals. The optical counter-

part of each STS-N signal is an optical carrier level-N

signal(OC-N). TheS3011/S3012chipsetsupportsOC-

3 rates (155.52 Mbit/s).

9 x 261 =

2349 bytes

H1 H1 H1 H2 H2 H2 H3 H3 H3

9

B2 B2 B2 K1

*

K2

*

Rows

D4 *

D7 *

*

D5 *

D8

D11

D6

D9

D12

*

D10

*

Z1 Z1 Z1 Z2 Z2 Z2 E2

Transport Overhead

Synchronous Payload

Envelope

9 Columns

261 Columns

Frame and Byte Boundary Detection

125 µsec

The SONET/SDH fundamental frame format for STS-3

consists of nine transport overhead bytes followed by

Synchronous Payload Envelope (SPE) bytes. This pat-

tern of 9 overhead and 261 SPE bytes is repeated nine

times in each frame. Frame and byte boundaries are

detected using the A1 and A2 bytes found in the

transport overhead. (See Figure 3.)

For more details on SONET operations, refer to the

ANSI SONET standard document.

2

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3011/S3012 OVERVIEW

Internal clocking and control functions are transparent

totheuser. DetailsofdatatimingcanbeseeninFigures

9 through 14.

The S3011 transmitter and S3012 receiver implement

SONET/SDHserialization/deserialization,transmission,

and frame detection/recovery functions. The block dia-

grams in Figures 4 and 5 show basic operation of both

chips. These chips can be used to implement the front

end of SONET equipment, which consists primarily of

the serial transmit interface (S3011) and the serial

receive interface (S3012). The chipset handles all the

functions of these two elements, including parallel-to-

serialandserial-to-parallelconversion,clockgeneration

and recovery, and system timing, which includes man-

agement of the datastream, framing, and clock

distribution throughout the front end.

A lock detect feature is provided on the S3012, which

indicates that the PLL is locked (synchronized) to the

data stream, and facilitates continuous down-stream

clocking in the absence of data.

Suggested Interface Devices

PMC PM5345

IGT WAC–013–A

Fujitsu MB86683

PMC PM5301

Siemens

SUNI

Saturn User Network Interface

SONET LAN ATM Processor

Network Termination Controller

Section Overhead Transceiver

Fiber Optic Transceiver

NTC

SSTX

Operation of the S3011/S3012 chips is straightforward.

The sequence of operations is as follows:

V23806-A8-C1

HFBR-520X

ODL-1408

HP

Fiber Optic Transceiver

CTS

Fiber Optic Transceiver

Transmitter

Sumitomo

AMP

SDM4123-XC

269039-1

Fiber Optic Transceiver

1. 8-bit parallel input

2. Parallel-to-serial conversion

3. Serial output

Mitsubishi

MF-156DS-TR124

Fiber Optic Transceiver

Receiver

1. Clock and data recovery from serial input

2. Frame detection

3. Serial-to-parallel conversion

4. 8-bit parallel output

Figure 4. S3011 Functional Block Diagram

TSCLKSEL

DLEB

2

DLDP/N

TSDP/N

2

8

D

PIN[7:0]

8:1 PARALLEL

TO SERIAL

PICLK

PCLK

PAE

TIMING

GEN

SYNC

TESTEN

REFCLK

CLOCK

SYNTHESIZER

RSTB

CAP1

CAP2

TESTRST

3

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Figure 5. S3012 Functional Block Diagram

LOS

8

1:8 SERIAL

TO PARALLEL

POUT[7:0]

TIMING

GEN

OOF

POCLK

FP

FRAME

BYTE

DETECT

DLEB

2

M

U

X

RSDP/N

DLDP/N

BACKUP

REFERENCE

GEN

2

CLOCK

RECOVERY

LOCKDET

REFCLK

CAP1

CAP2

TESTEN

RSTB

TESTRST

4

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

In the parallel-to-serial conversion process, the incom-

ing data is passed from the PICLK byte clock timing

domain to the internally generated byte clock timing

domain, which is phase aligned to transmit serial clock.

Although the frequency of PICLK and the internally

generated byte clock is the same, their phase relation-

ship is arbitrary. To prevent errors caused by short

setup or hold times between the two timing domains,

the timing generator circuitry monitors the phase rela-

tionship between PICLK and the internally generated

byte clock. Should the magnitude of the phase differ-

ence be less than one bit period, and if the SYNC input

is high, the timing block inverts the internal byte clock.

S3011 TRANSMITTER

FUNCTIONAL DESCRIPTION

TheS3011transmitterchipperformstheserializing stage

in the processing of a transmit SONET STS-3 bit serial

datastream. Itconvertsthebyteserial19.44Mbyte/sec

data stream to bit serial format at 155.52 Mbit/sec.

A high-frequency bit clock can be generated from a

19.44 MHz frequency reference by using an integral

frequency synthesizer consisting of a phase-locked

loop circuit with a divider in the loop.

Diagnostic loopback is provided (transmitter to re-

ceiver) when used with the compatible S3012. (See

Other Operating Modes.)

Sincetheinversionoftheinternalbyteclockwillcorrupt one

byte of data, SYNC should be held low except when a

phasecorrectionisdesired. Whenatimingdomain phase

difference of less than one bit period is detected, the

PhaseAlignmentEventoutput(PAE)pulseshighforone

PCLK clock period. If the condition persists, PAE will

remainhigh.WhenPAEconditionsoccur,SYNCshould

be activated until the condition is no longer present.

Clock Synthesizer

The Clock Synthesizer, shown in the block diagram in

Figure 4, is a monolithic PLL that generates the serial

output clock phase synchronized with the input refer-

ence clock (REFCLK).

The REFCLK input must be generated from a TTL

crystal oscillator which has a frequency accuracy of

better than 20 ppm in order for the TSCLK frequency to

have the same accuracy required for operation in a

SONET system. Lower accuracy crystal oscillators may

beusedinapplicationslessdemandingthanSONET/SDH.

After the S3011 device is reset, two cycles of PICLK are

required to initialize the internal byte clock. The starting

pointoftheinternalbyteclockisfourserialbittimesafterthe

detected rising edge of PICLK. The relative phase

betweenPICLKandthePCLKoutputisarbitrary,butitmust

remainconstantwithvariationswithintherangeof-2to +3

bittimes(-90° to+135°)inordertoavoidgeneratingPAE

pulses. This operating constraint must be observed if

the SYNC and PAE functions are not used or desired.

The on-chip PLL consists of a phase detector, which

compares the phase relationship between the VCO

outputandtheREFCLKinput,aloopfilterwhichconverts

the phase detector output into a smooth DC voltage,

and a VCO, whose frequency is varied by this voltage.

Parallel-to-Serial Converter

The Parallel-to-Serial converter shown in Figure 4 is

comprised of two byte-wide registers. The first register

latchesthedatafromthePIN[7:0]busontherisingedge

ofPICLK.Thesecondregisterisaparallelloadableshift

registerwhichtakesitsparallelinputfromthefirstregister.

The loop filter generates a VCO control voltage based

on the average DC level of the phase discriminator

output pulses. A single external clean-up capacitor is

utilized as part of the loop filter. The loop filter’s corner

frequency is optimized to minimize output phase jitter.

An internally generated byte clock, which is phase

aligned to the transmit serial clock as described in the

Timing Generator description, activates the parallel

data transfer between registers. The serial data shifts

out of the second register and into the output selection

logic at the transmit serial clock rate.

Timing Generator

The Timing Generator, seen in Figure 4, provides two

separate functions. It provides a byte rate version of the

transmit serial clock, and a mechanism for aligning the

phase between the incoming byte clock and the clock

which loads the parallel-to-serial shift register.

ThePCLKoutputisabyterateversionoftransmitserial

clock at 19.44 MHz. PCLK is intended for use as a byte

speed clock for upstream multiplexing and overhead

processing circuits. Using PCLK for upstream circuits will

ensure a stable frequency and phase relationship be-

tweenthedatacomingintoandleavingtheS3011device.

5

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

This transfer function yields a typical capture time of 32

µs for random incoming NRZ data. A single external

clean-up capacitor is utilized as part of the loop filter.

S3012 RECEIVER

FUNCTIONAL DESCRIPTION

The S3012 receiver chip provides the first stage of

digital processing of a receive SONET STS-3 bit-serial

stream. It converts the bit-serial 155.52 Mbit/sec data

stream into a 19.44 Mbyte/sec byte-serial data format.

The total loop dynamics of the clock recovery PLL yield

a jitter tolerance which meets, with ample margin, the

minimum tolerance proposed for SONET equipment by

the T1X1.6/91-022 document, shown in Figure 6.

Clockrecoveryisperformedontheincomingscrambled

NRZ data stream. A 19.44 MHz reference clock is

required for phase locked loop start-up and proper

operation under loss of signal conditions. An integral

prescaler and phase locked loop circuit is used to

multiply this reference to the nominal bit rate.

Figure 6. Clock Recovery Jitter Tolerance

15

Jitter

Amplitude

(Ulpp)

1.5

A loopback mode is provided for diagnostic loopback

(transmittertoreceiver), whenusedwiththecompatible

S3011 device.

Minimum proposed

tolerance

OC-3

6.5k

(T1X1.6/91-022)

0.15

Clock Recovery

30

300

25k 65k 250k

Jitter Frequency (Hz)

Clock Recovery, as shown in the block diagram in

Figure 5, generates a clock that is at the same fre-

quency as the incoming data bit rate at the RSD or DLD

inputs. The clock is phase aligned by a PLL so that it

samples the data in the center of the data eye pattern.

Backup Reference Generator

The Backup Reference Generator seen in Figure 5

provides backup reference clock signals to the clock

recovery block when the clock recovery block detects a

lossofsignalcondition.Itcontainsacounterthatdivides

the clock output from the clock recovery block down to

the same frequency as the reference clock REFCLK.

The phase relationship between the edge transitions of the

data and those of the generated clock are compared by a

phase/frequency discriminator. Output pulses from the

discriminator indicate the required direction of phase

corrections.Thesepulsesaresmoothedbyanintegralloop

filter. The output of the loop filter controls the frequency of

the Voltage Controlled Oscillator (VCO), which generates

the recovered clock. Frequency stability without incom-

ing data is guaranteed by an alternate reference input

(REFCLK) that the PLL locks onto when data is lost.

Frame and Byte Boundary Detection

The Frame and Byte Boundary Detection circuitry

searches the incoming data for three consecutive A1

bytes followed immediately by three consecutive A2

bytes. Framing pattern detection is enabled and dis-

abled by the out-of-frame (OOF) input. Detection is

enabled by a rising edge on OOF, and remains enabled

for the duration that OOF is set high. It is disabled when

a framing pattern is detected and OOF is no longer set

high. When framing pattern detection is enabled, the

framing pattern is used to locate byte and frame bound-

aries in the incoming data stream (RSD or DLD). The

timing generator block takes the located byte boundary

and uses it to block the incoming data stream into bytes

for output on the parallel output data bus (POUT[7:0]).

Theframeboundaryisreportedontheframepulse(FP)

output when any 48-bit pattern matching the framing

pattern is detected on the incoming data stream. When

framingpatterndetectionisdisabled, thebyteboundary is

frozen to the location found when detection was previously

enabled. Only framing patterns aligned to the fixed byte

boundary are indicated on the FP output.

The clock recovery circuit monitors the incoming data

streamforlossofsignal.Iftheincomingdatastreamhas

had no transitions for between 96 and 208 bit times

(depending upon the state of an internal counter at the

timeoflasttransistion),lossofsignalisdeclaredandthe

PLL will switch from locking onto the incoming data to

locking onto the reference clock. Alternatively, the loss-

of-signal(LOS)inputcanbeusedtoforcealoss-of-signal

condition. When set low, LOS squelches the incoming

data stream, and thus causes the PLL to switch its

source of reference 64 to 128 bit times afterwards.

Loss-of-signal condition is removed when LOS is high,

and good data, with acceptable pulse density and run

length, returns on the incoming data stream.

The loop filter transfer function is optimized to enable the

PLL to track the jitter, yet tolerate the minimum transi-

tion density expected in a received SONET data signal.

6

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

edge of POCLK, which is independent of the byte

boundaries. The advantage of this serial to parallel

converter is that POCLK is neither truncated nor ex-

tended during reframe sequences.

The probability that random data in an STS-3 stream

will generate the 48-bit framing pattern is extremely

small. It is highly improbable that a mimic pattern would

occur within one frame of data. Therefore, the time to

match the first frame pattern and to verify it with down-

stream circuitry, at the next occurrence of the pattern,

isexpectedtobelessthantherequired250µs, evenfor

extremely high bit error rates.

OTHER OPERATING MODES

Diagnostic Loopback

Once down-stream overhead circuitry has verified that

frame and byte synchronization are correct, the OOF

inputcanbesetlowtodisabletheframesearchprocess

from trying to synchronize to a mimic frame pattern.

The Diagnostic Loopback consists of alternate serial

dataoutputs(inthecaseoftheS3011)andinputs(inthe

case of the S3012).

On the S3011, the differential PECL output DLD pro-

vides Diagnostic Loopback serial data. When the

Diagnostic Loopback Enable (DLEB) input and

TSCLKSEL are low, this data output is a replica of TSD.

When DLD is connected to the S3012, a loopback from

the transmitter to the receiver at the serial data rate can

be set up for diagnostic purposes. When DLEB is high

and TSCLKSEL is low, DLD is held in the inactive state,

with the positive output high and the negative output

low. In the inactive state, there will be no interference

from the transmitter to the receiver.

Serial-to-Parallel Converter

The Serial-to-Parallel Converter consists of three 8-bit

registers. The first is a serial-in, parallel-out shift regis-

ter,whichperformsserialtoparallelconversionclocked

by the clock recovery block. The second is an 8-bit

internal holding register, which transfers data from the

serial to parallel register on byte boundaries as deter-

mined by the frame and byte boundary detection block.

On the falling edge of the free running POCLK, the data

intheholdingregisteristransferredtoanoutputholding

register which drives POUT[7:0].

On the receiver side, the differential PECL input DLD is

the Diagnostic Loopback serial data input. When the

Diagnostic Loopback Enable (DLEB) input is set low,

the DLD input is routed in place of the normal data

stream (RSD).

The delay through the Serial-to-Parallel converter can

vary from 1.5 to 2.5 byte periods (12 to 20 serial bit

periods) measured from the first bit of an incoming byte

to the beginning of the parallel output of that byte. The

variation in the delay is dependent on the alignment of

the internal parallel load timing, which is synchronized

to the data byte boundaries, with respect to the falling

Figure 7. Loopback Diagram

Data In

Control

S3011

Data Out

CLK

S3012

S3011

Data Out

CLK

Data In

Control

7

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3011 Transmitter Pin Assignment and Descriptions

Pin Name

Level I/O

Pin # Description

PIN7

PIN6

PIN5

PIN4

PIN3

PIN2

PIN1

PIN0

TTL

I

36

35

31

30

28

26

25

17

Parallel data input, a 19.44 Mbyte/sec word, aligned to the

PICLK parallel input clock. PIN7 is the most significant bit

(corresponding to bit 1 of each PCM word, the first bit

transmitted). PIN0 is the least significant bit (corresponding to bit

8 of each PCM word, the last bit transmitted). PIN(7-0) is

sampled on the rising edge of PICLK.

PICLK

TTL

I

16

Parallel input clock, a 19.44 MHz nominally 50% duty cycle input

clock, to which PIN(7-0) is aligned. PICLK is used to transfer the

data on the PIN inputs into a holding register in the parallel-to-

serial converter. The rising edge of PICLK samples PIN(7-0).

After a Master Reset two rising edges of PICLK are required to

fully initialize the internal datapath.

TESTEN

SYNC

TTL

I

6

Test clock enable signal, set high to provide access to the PLL

during production tests.

45

Active high synchronization enable input that enables the timing

generator to invert the internal byte transfer clock if transfers

from the PIN(7-0) input holding register are occurring less than

one bit period before or after clocking new data into the holding

register. The SYNC pin is an asynchronous input.

REFCLK

DLEB

TTL

I

75

50

Input used as the reference for the internal bit clock frequency

synthesizer.

Diagnostic loopback enable signal. Enables the DLD output

when low and TSCLKSEL is low. When DLEB is high, the DLD

output is held in the inactive state to prevent interference

between the transmit and receive devices.

RSTB

TTL

–

I

15

46

51

Reset input for the device, active low.

TSCLKSEL

TESTRST

Active high transmit clock select input which, when enabled,

directs the transmit serial clock through the DLDP/N output.

I

Used to reset portions of the clock recovery PLL during

production testing. Held low for normal operation.

CAP1

CAP2

I

3

78

The loop filter capacitor is connected to these pins. The

capacitor value should be 0.01µf ±10% tolerance, X7R dielectric.

50 V is recommended (16 V is acceptable).

TSDP

TSDN

Diff.

PECL

O

73

71

Serial data stream signals. Normally connected to an optical

transmitter module.

8

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3011 Transmitter Pin Assignment and Descriptions (Continued)

Pin Name Level I/O

Pin #

Description

DLDP

DLDN

Diff.

PECL

O

69

67

Serial data stream signals, normally connected to a companion

S3012 device for diagnostic loopback purposes. They are held

inactive when DLEB is high and TSCLKSEL is low. The serial

data stream is output when DLEB is low and TSCLKSEL is low.

When enabled by the TSCLKSEL input, the transmit serial clock

will be output through this pin. The transmit serial clock is a

buffered version of the internal frequency synthesizer clock,

which is phase-aligned with the TSD output signal. The TSD is

updated on the falling edge of the transmit serial clock.

PCLK

PAE

O

10

44

A reference clock generated by dividing the internal bit clock by

eight. It is normally used to coordinate byte-wide transfers

between upstream logic and the S3011 device.

CMOS

TTL/

CMOS

Phase alignment event signal, that pulses high during each

PCLK cycle for which there is less than one bit period between

the internal byte clock and PICLK timing domains. PAE is

updated on the falling edge of the PCLK outputs.

+5V

–

7, 14, 27, Digital +5V

34, 47,

54

TGND

TTLVCC

A+5V

GND

+5V

–

76

TTL Ground (Digital 0V)

TTL Power Supply (+5V if TTL)

23, 38

5, 56, 66, Analog +5V

74

AGND

GND

+5V

–

4, 57, 64, Analog 0V

72

ECLIOVCC

24, 37

Digital +5V

IOGND

GND

–

18, 43

Digital 0V

1, 2, 8, Digital 0V

13, 19,

20, 21,

22, 29,

32, 39,

40, 41,

42, 48,

53, 59,

60, 61,

62, 79,

80

9

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3011 Transmitter Pin Assignment and Descriptions (Continued)

Pin Name Level I/O

Pin #

Description

NC

–

9, 11, 12, Not connected

33, 49,

52, 55,

58, 63,

65, 68,

70, 77

10

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3012 Receiver Pin Assignment and Descriptions

Pin Name

Level I/O

Pin # Description

RSDP

RSDN

Diff.

PECL

I

63

65

Serial data stream signals normally connected to an optical

receiver module. A clock is recovered from transitions on the

RSD inputs.

DLDP

DLDN

Diff.

PECL

I

67

69

Serial data stream signal, normally connected to a companion

S3011 device for diagnostic loopback purposes. Clock is

recovered from transitions on the DLD inputs while in diagnostic

loopback.

DLEB

TTL

I

51

Selects diagnostic loopback. When DLEB is high, the S3012

device uses the primary data (RSD) input. When low, the S3012

device uses the diagnostic loopback data (DLD) input, and the

LOS signal is disabled.

TESTEN

OOF

TTL

I

6

Test clock enable signal, set high to provide access to the PLL

during production tests.

10

Out of frame indicator used to enable framing pattern detection

logic in the S3012. This logic is enabled by a rising edge on

OOF, and remains enabled until frame boundary is detected or

when OOF is set low, whichever is longer. OOF is an

asynchronous signal with a minimum pulse width of one POCLK

period. (See Figures 13 and 14.)

LOS

PECL

I

9

An active-low, single-ended 10K ECL input to be driven by the

external optical receiver module to indicate a loss of received

optical power (Loss of Signal). When LOS is low, the data on

the Serial Data In (RSDP/N) pins will be internally forced to a

constant zero, LOCKDET will be forced low, and the PLL will

lock to the REFCKINP/N inputs. When DLEB is low, LOCKDET

remains high if there are transitions on DLDP/N for either state

of LOS. This signal must be used to assure correct automatic

reacquisition to serial data following an interruption and

subsequent reconnection of the optical path. (This ensures that

the PLL does not "wander" out of reacquisition range by tracking

the random phase/frequency content of the optical detector's

noise floor while monitoring "dark" fiber.) When LOS is high,

data on the RSDP/N pins will be processed normally.

REFCLK

TESTRST

RSTB

TTL

I

75

49

50

Input normally used as the reference for the integral clock

recovery PLL.

Used to reset portions of the clock recovery PLL during

production testing. Held low for normal operation.

Reset input for the device, active low. Initializes the device to a

known state and forces the PLL to acquire to the reference

clock. A reset of at least 16 ms should be applied at power-up

and whenever the user wishes to force the PLL to re-acquire to

the reference clock. The S3012 will also re-acquire to the

reference clock if the serial data input is held quiescent for at

least 16 ms.

11

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3012 Receiver Pin Assignment and Descriptions (Continued)

Pin Name Level I/O

Pin #

Description

CAP1

CAP2

–

I

3

78

The loop filter capacitor is connected to these pins. The

capacitor value should be 0.1µf ±10% tolerance, X7'R dielectric.

50 V is recommended (16 V is acceptable).

POUT7

POUT6

POUT5

POUT4

POUT3

POUT2

POUT1

POUT0

TTL/

CMOS

O

16

17

25

26

28

35

36

44

Parallel data output, a 19.44 Mbyte/sec word, aligned to the

POCLK parallel output clock. POUT7 is the most significant bit

(corresponding to bit 1 of each PCM word, the first bit received).

POUT0 is the least significant bit (corresponding to bit 8 of each

PCM word, the last bit received). POUT(7-0) is updated on the

falling edge of POCLK.

FP

TTL/

O

12

Frame pulse. Indicates frame boundaries in the incoming data

stream (RSD). If framing pattern detection is enabled, as

controlled by the OOF input, FP pulses high for one POCLK

cycle when a 48-bit sequence matching the framing pattern is

detected on the RSD inputs. When framing pattern detection is

disabled, FP pulses high when the incoming data stream, after

byte alignment, matches the framing pattern. FP is updated on

the falling edge of POCLK.

CMOS

POCLK

TTL/

CMOS

45

52

Parallel output clock, a 19.44 MHz nominally 50% duty cycle,

byte rate output clock, that is aligned to POUT(7-0) byte serial

output data. POUT(7-0) and FP are updated on the falling edge

of POCLK.

LOCKDET

+5V

TTL

+5V

O

–

Clock recovery indicator. Set high when the internal clock

recovery has locked onto the incoming data stream. LOCKDET

is an asynchronous output.

7, 14, 27, Digital +5V

34, 47,

54

TGND

TTLVCC

A+5V

GND

+5V

–

76

TTL Ground (Digital 0V)

TTL Power Supply (+5V if TTL)

23, 38

5, 56, 66, Analog +5V

70

AGND

GND

+5V

–

4, 57, 64, Analog 0V

68

ECLIOVCC

24, 37

Digital +5V

IOGND

GND

–

18, 43

Digital 0V

12

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

S3012 Receiver Pin Assignment and Descriptions (Continued)

Pin Name Level I/O

Pin #

Description

ITPWR

ITGND

+5V

–

31, 46

Digital +5V

GND

11, 15, Digital 0V

30, 33

GND

–

1, 2, 8, Digital 0V

13, 19,

20, 21,

22, 29,

32, 39,

40, 41,

42, 48,

53, 59,

60, 61,

62, 79,

80

NC

–

55, 58, Not connected

71, 72,

73, 74,

77

13

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Figure 8. 80 PQFP Package

80

78

76

74

72

70

68

66

64

62 61

1

2

60

59

4

6

57

55

53

51

49

47

8

10˚

TOP

VIEW

10

12

14

16

18

20

1.28 ± .10

2.70 ± .10

1.28 ± .10

45

43

41

0.30

0.65

0.88 + .15 - .10

14.0 ± .10

17.2 ± .25

All dimensions nominal in mm.

14

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Performance Specifications

Parameter

Min

Typ

Max

Units

Condition

Nominal VCO

Center Frequency

622.08

MHz

In CSU mode, given 56 ps rms

jitter on REFCLK in 12KHz to

1 MHz band

PECL Data Output Jitter

64

ps (rms)

Reference Clock Frequency

Tolerance

Required to meet SONET/ATM

output frequency specification

lock Synthesis (S3011)

lock Recovery (S3012)

-20

-100

+20

+100

ppm

OC-3/STS-3

Capture Range

Lock Range

Clock Output

Duty Cycle

±200ppm

+8%, -12%

With respect to fixed reference

frequency

48

30

52

% of UI

Minimum transition density of

20%

With device already powered up

and valid REFCLK

Acquisition Lock Time

64.0

70

µsec

Reference Clock

Input Duty Cycle

% of period

Reference Clock Rise & Fall

Times

5.0

ns

ps

10% to 90% of amplitude

PECL Output Rise & Fall

Times

20% to 80%, 50 to VCC -2

equivalent load, 5 pf cap

600

15

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Absolute Maximum Ratings

PARAMETER

Case Temperature under Bias

Typ Max

125 °C

Min

–55

Unit

Junction Temperature under Bias

Storage Temperature

–55

–65

150 °C

Voltage on VCC with Respect to GND –0.5

+7.0

+5.5

VCC

V

Voltage on Any TTL Input Pin

Voltage on Any PECL Input Pin

TTL Output Sink Current

–0.5

VCC–3

20 mA

10 mA

TTL Output Source Current

High Speed PECL Output Source

Current

50 mA

V

Static Discharge Voltage

500

Recommended Operating

Conditions

Typ Max Unit

70 °C

125 °C

Min

PARAMETER

Ambient Temperature under Bias

Junction Temperature under Bias

Voltage on VCC with Respect to GND

Voltage on Any TTL Input Pin

Voltage on Any PECL Input Pin

S3011 ICC

0

20

4.75 5.0 5.25

V

0

VCC

VCC–2

210 mA

270 mA

S3012 ICC

16

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

(T_A= 0°C to +70°C, V_CC= 5 V ±5%)

TTL/CMOS Input/Output DC Characteristics

Symbol

Parameter

Input LOW Voltage

Input HIGH Voltage

Input LOW Current

Input HIGH Current

Min

Typ

Max

0.8

Unit

Volts

µA

Conditions

Guaranteed Input LOW Voltage

1

V

I

IL

1

2.0

Guaranteed Input HIGH Voltage

IH

-400.0

V

= MAX, V = 0.5V

IN

CC

IL

50.0

1.0

µA

= MAX, V = 2.7V

IN

I

IH

Input HIGH Current at

Max VCC

mA

V

= MAX, V = 5.5V

IN

I

CC

-100.0

-1.2

-25.0

0.5

mA

V

CC

V

CC

V

CC

V

CC

= MAX, V

= 0.5V

I

Output Short Circuit Current

Input Clamp Diode Voltage

Output LOW Voltage

OUT

= MIN, I = -18 ma

OS

V

Volts

IK

IN

= MIN, I

= 8 ma

OL

= -1 ma

Output HIGH Voltage

Volts

V

2.7

OH

1. These input levels provide zero noise immunity and should only be tested in a static, noise-free

environment.

PECL Input/Output DC Characteristics ^1,2

(T_A= 0°C to +70°C, V_CC= 5 V ±5%)

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

Guaranteed Input LOW Voltage

for single-ended inputs

Input LOW Voltage

V

-2.000

V

-1.450

Volts

IL

CC

Guaranteed Input HIGH Voltage

for single-ended inputs

Volts

Input HIGH Voltage

-1.180

-0.600

IH

IL

CC

Guaranteed Input LOW Voltage

for differential inputs

Input LOW Voltage

Input HIGH Voltage

V

-2.000

-1.750

V

-0.700

-0.450

Volts

CC

Guaranteed Input HIGH Voltage

for differential inputs

IH

ID

0.250

0.500

1.400

Volts

µA

V

I

Input Diff. Voltage

Input High Current

Input Low Current

Differential Input Voltage

20.000

-0.500

V

= 500mV

IH

ID

µA

I

IL

V

50 ohm termination to V

-2V

V

-2.000

V

-1.565

Volts

Output LOW Voltage

OL

CC

V

Output HIGH Voltage

Output Diff. Voltage

50 ohm termination to V

-1.070

-0.695

Volts

OH

OD

CC

0.495

1.305

Differential Output Voltage

1. These conditions will be met with no airflow.

2. When not used, tie the positive differential PECL pin to V and the negative

CC

differential ECL pin to ground via a 3.9K resistor.

17

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

(T_A= 0°C to +70°C, V_CC= 5 V ±5%)

Table 2. S3011 AC Timing Characteristics

Symbol

Description

Min

Max

Units

TSCLK Frequency

156

MHz

TSCLK Duty Cycle

40

5

60

%

ns

%

tS_PIN

PIN [7:0] Set-up Time w.r.t. PICLK

PIN [7:0] Hold Time w.r.t. PICLK

PCLK Low to PAE Valid Propagation Delay

PICLK Duty Cycle

tH_PIN

tP_PAE1

5

10

65

35

Figure 9. PIN AC Input Timing

PICLK

tS

tH

PIN[7:0]

1. When a set-up time is specified on TTL signals between an input and a clock,

the set-up time is the time in nanoseconds from the 50% point of the input to

the 50% point of the clock.

2. When a hold time is specified on TTL signals between an input and a clock,

the hold time is the time in nanoseconds from the 50% point of the clock to

the 50% point of the input.

Figure 10. PAE Output Timing

PCLK

tP

PAE

Notes on TTL Output Timing

1. Outputpropagationdelaytimeisthetimeinnanosecondsfromthe50%point

of the reference signal to the 30% or 70% point of the output.

2. Maximum output propagation delays are measured with a 15 pF load on the

outputs.

18

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Table 3. S3012 AC Timing Characteristics

Symbol

Description

Min

Max

60

Units

%

POCLK Duty Cycle

40

tP_POUT

tP_FP

POCLK Low to POUT[7:0] Valid Prop. Delay

POCLK Low to FP Valid Propagation Delay

RSD Minimum Pulse Width

15

ns

15

ns

1.6

ns

Figure 11. Output Timing Diagram

POCLK

tP

POUT

POUT[7:0]

tP

FP

Notes on Output Timing:

1. Output propagation delay time of TTL outputs is the time in nanoseconds

from the 50% point of the reference signal to the 30% or 70% point of the

output.

2. Maximum output propagation delays of TTL outputs are measured with a

15 pF load and 500 ohms to ground on the outputs.

19

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

The frame and byte boundary detection block is activated

by the rising edge of OOF, and stays active until the first

RECEIVER FRAMING

Figure 12 shows a typical reframe sequence in which a

byte realignment is made. The frame and byte bound-

ary detection is enabled by the rising edge of OOF and

remains enabled while OOF is high. Both boundaries

are recognized upon receipt of the third A2 byte which

is the first data byte to be reported with the correct byte

alignmentontheoutgoingdatabus(POUT[7:0]).Concur-

rently, the frame pulse is set high for one POCLK cycle.

FP pulse or until OOF goes low, whichever occurs last.

Figure 13 shows a typical OOF timing pattern which

occurs when the S3012 is connected to a down stream

section terminating device. OOF remains high for one

full frame after the first FP pulse. The frame and byte

boundary detection block is active until OOF goes low.

Figure14showstheframeandbyteboundarydetection

activation by a rising edge of OOF, and deactivated by

the first FP pulse.

When interfacing with a section terminating device, the

OOF input remains high for one full frame after the first

framepulsewhilethesectionterminatingdeviceverifies

internally that the frame and byte alignment are correct, as

shown in Figure 13. Since at least one framing pattern

has been detected since the rising edge of OOF,

boundary detection is disabled when OOF is set low.

Figure 12. Frame and Byte Detection

NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles

Figure 13. OOF Operation Timing with SSTX

Figure 14. Alternate OOF Timing

BOUNDARY DETECTION ENABLED

OOF

FP

20

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

Ordering Information

GRADE

TRANSMITTER

PACKAGE

A – 80 PQFP

S – commercial

3011

PACKAGE

GRADE

RECEIVER

S – commercial

3012

A – 80 PQFP

X XXXX

X

Grade Part number

Package

Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121

Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885

http://www.amcc.com

AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and

advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied

on is current.

AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it

convey any license under its patent rights nor the rights of others.

AMCC reserves the right to ship devices of higher grade in place of those of lower grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR

USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

AMCC is a registered trademark of Applied Micro Circuits Corporation.

June 2, 1997

21


型号：	S3012A
厂家：	Rochester Electronics
描述：	Receiver, 1-Func, PQFP80, PLASTIC, QFP-80
文件：	总21页 (文件大小：136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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