SN74LVC1G66DCKR [ROCHESTER]
1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5, GREEN, PLASTIC, SC-70, 5 PIN;
| 型号： | SN74LVC1G66DCKR |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5, GREEN, PLASTIC, SC-70, 5 PIN PC 光电二极管 |
| 文件： | 总21页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
FEATURES
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
•
•
•
Low On-State Resistance, Typically ≈5.5 Ω
(VCC = 4.5 V)
•
•
•
•
•
•
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
High On-Off Output Voltage Ratio
High Degree of Linearity
– 1000-V Charged-Device Model (C101)
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
YEA, YEP, YZA,
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
OR YZP PACKAGE
(BOTTOM VIEW)
3
4
5
C
GND
B
1
2
3
5
A
V
CC
A
B
V
CC
1
2
3
5
1
2
3
5
4
A
B
V
CC
2
1
B
V
A
CC
4
GND
C
4
GND
C
C
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
SN74LVC1G66YEAR
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA
(Pb-free)
SN74LVC1G66YZAR
SN74LVC1G66YEPR
SN74LVC1G66YZPR
Reel of 3000
_ _ _C6_
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
–40°C to 85°C
Reel of 3000 SN74LVC1G66DBVR
Reel of 250 SN74LVC1G66DBVT
Reel of 3000 SN74LVC1G66DCKR
Reel of 250 SN74LVC1G66DCKT
Reel of 4000 SN74LVC1G66DRLR
SOT (SOT-23) – DBV
C66_
C6_
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of up
to 5.5 V (peak) to be transmitted in either direction.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
ON
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
4
2
B
A
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range(2)
Input voltage range(2)(3)
6.5
V
VI/O
IIK
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port diode current
–0.5 VCC + 0.5
V
VI < 0
–50
±50
±50
±100
206
252
142
154
132
mA
mA
mA
mA
IIOK
IT
VI/O < 0 or VI/O > VCC
VI/O < 0 to VCC
On-state switch current
Continuous current through VCC or GND
DBV package
DCK package
θJA
Package thermal impedance(5)
DRL package
°C/W
°C
YEA/YZA package
YEP/YZP package
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) The package thermal impedance is calculated in accordance with JESD 51-7.
2
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
VCC
VI/O
Supply voltage
I/O port voltage
5.5
V
V
0
VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
V
CC × 0.65
V
CC × 0.7
CC × 0.7
CC × 0.7
VIH
High-level input voltage, control input
V
V
V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
V
CC × 0.35
V
CC × 0.3
CC × 0.3
CC × 0.3
5.5
VIL
VI
Low-level input voltage, control input
Control input voltage
V
V
V
V
VCC = 4.5 V to 5.5 V
0
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
20
20
∆t/∆v
TA
Input transition rise/fall time
Operating free-air temperature
ns/V
°C
10
VCC = 4.5 V to 5.5 V
10
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IS = 4 mA
VCC
1.65 V
2.3 V
3 V
MIN TYP(1)
MAX UNIT
12
9
30
VI = VCC or GND,
VC = VIH
IS = 8 mA
IS = 24 mA
IS = 32 mA
IS = 4 mA
IS = 8 mA
IS = 24 mA
IS = 32 mA
20
Ω
ron
On-state switch resistance
(see Figure 1 and
Figure 2)
7.5
5.5
74.5
20
15
4.5 V
1.65 V
2.3 V
3 V
10
120
VI = VCC or GND,
VC = VIH
(see Figure 1 and
Figure 2)
30
Ω
ron(p)
Peak on resistance
11.5
7.5
20
4.5 V
15
VI = VCC and VO = GND or
±1
Off-state switch leakage
current
IS(off)
VI = GND and VO = VCC
,
5.5 V
µA
±0.1(1)
VC = VIL (see Figure 3)
±1
µA
On-state switch leakage
current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
IS(on)
5.5 V
5.5 V
5.5 V
±0.1(1)
±1
µA
II
Control input current
Supply current
VC = VCC or GND
±0.1(1)
10
µA
ICC
VC = VCC or GND
VC = VCC – 0.6 V
1(1)
∆ICC
Supply current change
5.5 V
5 V
500
µA
Cic
Control input capacitance
2
6
pF
Switch input/output
capacitance
Cio(off)
Cio(on)
5 V
5 V
pF
pF
Switch input/output
capacitance
13
(1) TA = 25°C
3
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.5 V
MIN MAX
0.6
PARAMETER
UNIT
MIN
MAX MIN
MAX MIN
1.2
MAX
0.8
5
(1)
tpd
A or B
B or A
A or B
A or B
2
12
10
ns
ns
ns
(2)
ten
C
C
2.5
2.2
1.9
1.4
6.5
6.9
1.8
2
1.5
1.4
4.2
5
(3)
tdis
6.5
(1) tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
(2) tPZL and tPZH are the same as ten
.
(3) tPLZ and tPHZ are the same as tdis
.
Analog Switch Characteristics
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
VCC
TYP UNIT
1.65 V
2.3 V
3 V
35
120
175
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response(1)
(switch ON)
4.5 V
1.65 V
2.3 V
3 V
195
MHz
>300
A or B
B or A
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
>300
>300
>300
35
4.5 V
1.65 V
2.3 V
3 V
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 7)
50
Crosstalk
(control input to signal output)
C
mV
70
4.5 V
1.65 V
2.3 V
3 V
100
–58
–58
–58
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
Feedthrough attenuation(2)
(switch OFF)
4.5 V
1.65 V
2.3 V
3 V
–58
dB
A or B
–42
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
–42
–42
4.5 V
1.65 V
2.3 V
3 V
–42
0.1
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 9)
0.025
0.015
4.5 V
1.65 V
2.3 V
3 V
0.01
%
Sine-wave distortion
A or B
B or A
0.15
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 9)
0.025
0.015
0.01
4.5 V
(1) Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
(2) Adjust fin voltage to obtain 0 dBm at input.
4
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
8
9
9
11
pF
5
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
B or A
A or B
V = V or GND
V
I
CC
O
C
V
IH
V
C
(ON)
GND
I
S
VI * VO
ron
+
W
IS
V
V − V
I
O
Figure 1. On-State Resistance Test Circuit
100
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 3.0 V
10
V
CC
= 4.5 V
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
IN
− V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
B or A
A or B
V
I
A
V
V
O
C
IL
V
C
(OFF)
GND
Condition 1: V = GND, V = V
CC
I
O
Condition 2: V = V , V = GND
I
CC
O
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
CC
V
B or A
A or B
A
V = V or GND
V
O
I
CC
V
O
= Open
C
V
IH
V
C
(ON)
GND
Figure 4. On-State Switch Leakage-Current Test Circuit
7
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
CC
V
CC
V
CC
V
CC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
CC
/2
CC
/2
CC
/2
CC
2 × V
2 × V
2 × V
2 × V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
V
V
V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
0.1 µF
B or A
A or B
C
V
O
R
L
C
L
V
IH
50 Ω
f
in
V
C
(ON)
GND
V /2
CC
R /C : 600 Ω/50 pF
L
L
R /C : 50 Ω/5 pF
L
L
Figure 6. Frequency Response (Switch ON)
V
CC
CC
V
R
in
600 Ω
B or A
A or B
C
V /2
CC
V
O
R
L
C
L
600 Ω
50 pF
V
C
GND
V /2
CC
50 Ω
Figure 7. Crosstalk (Control Input – Switch Output)
9
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323K–JUNE 2001–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
0.1 µF
50 Ω
B or A
A or B
C
V
O
C
L
R
L
R
L
V
IL
V
C
f
in
(OFF)
GND
V /2
CC
V /2
CC
R /C : 600 Ω/50 pF
L
L
R /C : 50 Ω/5 pF
L
L
Figure 8. Feedthrough (Switch OFF)
V
CC
CC
V
10 µF
10 µF
B or A
A or B
C
V
O
C
L
R
10 kΩ
L
V
IH
50 pF
600 Ω
V
C
f
in
(ON)
GND
V /2
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V, V = 1.4 V
I P-P
= 2.3 V, V = 2 V
I
P-P
P-P
P-P
= 3 V, V = 2.5 V
I
= 4.5 V, V = 4 V
I
Figure 9. Sine-Wave Distortion
10
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
SN74LVC1G66DBVR
SN74LVC1G66DBVRE4
SN74LVC1G66DBVRG4
SN74LVC1G66DBVT
SN74LVC1G66DBVTE4
SN74LVC1G66DCKR
SN74LVC1G66DCKRE4
SN74LVC1G66DCKRG4
SN74LVC1G66DCKT
SN74LVC1G66DCKTE4
SN74LVC1G66DRLR
SN74LVC1G66DRLRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DRL
DRL
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G66YEAR
SN74LVC1G66YEPR
SN74LVC1G66YZAR
NRND
NRND
NRND
WCSP
WCSP
WCSP
YEA
YEP
YZA
5
5
5
3000
3000
TBD
TBD
SNPB
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
3000 Green (RoHS &
no Sb/Br)
SNAGCU
SN74LVC1G66YZPR
ACTIVE
WCSP
YZP
5
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
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Addendum-Page 2
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