BD18333EUV-M (新产品) [ROHM]
BD18333EUV-M is 24CH constant current driver with 8-bit PWM dimming and 8-bit local DC dimming individual channels. Communication with μ-Controller is available via UART.;
| 型号： | BD18333EUV-M (新产品) |
| 厂家： | 
ROHM |
| 描述： | BD18333EUV-M is 24CH constant current driver with 8-bit PWM dimming and 8-bit local DC dimming individual channels. Communication with μ-Controller is available via UART. |
| 文件： | 总95页 (文件大小：5007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nano CapTM
Datasheet
Automotive LED Driver Series
24CH Linear LED Driver Embedded
Automotive Lamps LED Driver
BD18333EUV-M
General Description
Key Specification
BD18333EUV-M is 24CH constant current driver with 8-
bit PWM dimming and 8-bit local DC dimming individual
channels. Communication with μ-Controller is available
via UART.
◼Operating Input Voltage Range：
◼LED Pin Maximum Output Current：
◼Operating Temperature Range： -40 °C to +125 °C
4.5 V to 40.0 V
125 mA
Features
Package
HTSSOP-C48
W (Typ) x D (Typ) x H (Max)
12.5 mm x 8.1 mm x 1.0 mm
◼ Nano CapTM Integrated
◼ AEC-Q100 Qualified(Note 1)
◼ ISO 26262 Process Compliant to Support ASIL-B
◼ Integrated 24CH LED Constant Current Driver
◼ UART Interface
◼ Independent 8-bit PWM Dimming Function
◼ Independent 8-bit Local DC Dimming Function
◼ Independent 4-bit Delay Function
◼ LSI Protection Function (UVLO, TSD)
◼ LED Abnormality Detection Function (Open/Short)
◼ LED Cathode Short Detection Function
◼ Integrated Abnormality Output the FAILB Pin
(Note 1) Grade 1
Application
◼ Rear Lamps (+ Animation)
◼ Position/DRL (+ Animation)
◼ Turn (+ Animation)
Typical Application Circuit
VIN
1
2
3
4
5
6
7
8
9
VREG3
GND
48
N.C. 47
CS0 46
CS1 45
CS2 44
EXP_PAD
VREG5
EN
RX
CAN TRANCSIVER
CS3
TX
43
PWMIN
LGND.
FAILB
PWMOUT 42
LGND 41
TEST 40
5V
LDO
10 LED1
11 LED2
12 LED3
13 LED4
14 LED5
15 LED6
16 N.C.
LED24 39
LED23 38
LED22 37
LED21 36
LED20 35
LED19 34
N.C. 33
17 LED7
18 LED8
19 LED9
20 LED10
21 LED11
22 LED12
23 EXTISET
24 LGND
LED18 32
LED17 31
LED16 30
LED15 29
LED14 28
LED13 27
EXTISET2 26
LGND 25
EXP_PAD
Figure 1. Application Circuit
Nano Cap™ is a trademark or a registered trademark of ROHM Co., Ltd.
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD18333EUV-M
Pin Configuration
HTSSOP-C48
(TOP VIEW)
1
2
3
4
5
6
7
8
9
VREG3
GND
VIN 48
N.C. 47
VREG5
EN
CS0 46
CS1 45
RX
CS2 44
TX
CS3 43
PWMIN
LGND
FAILB
PWMOUT 42
LGND
41
TEST 40
LED24 39
LED23 38
LED22 37
LED21 36
LED20 35
LED19 34
N.C. 33
10 LED1
11 LED2
12 LED3
13 LED4
14 LED5
15 LED6
16 N.C.
17 LED7
18 LED8
19 LED9
20 LED10
21 LED11
22 LED12
23 EXTISET1
24 LGND
LED18 32
LED17 31
LED16 30
LED15 29
LED14 28
LED13 27
EXTISET2 26
LGND 25
EXP_PAD
Figure 2. Pin Configuration
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BD18333EUV-M
Pin Description
Pin
No.
Pin Name
Function
1
VREG3
GND
3.3 V voltage output
Ground
2
3
VREG5
EN
5.0 V voltage output
Chip enable
4
5
RX
UART signal receiver
UART signal transmitter
6
TX
7
PWMIN
LGND
FAILB
LED1
LED2
LED3
LED4
LED5
LED6
N.C.
PWM input frequency for PWM frequency synchronization
LED driver ground
8
9
Error flag
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LED current output
LED current output
LED current output
LED current output
LED current output
LED current output
Non wire connection
LED current output
LED current output
LED current output
LED current output
LED current output
LED current output
LED current setting Pin
LED driver ground
LED7
LED8
LED9
LED10
LED11
LED12
EXTISET1
LGND
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BD18333EUV-M
Pin Description - continued
Pin
Pin Name
No.
Function
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
-
LGND
EXTISET2
LED13
LED14
LED15
LED16
LED17
LED18
N.C.
LED driver ground
LED current setting Pin for LIMPHOME mode
LED current output
LED current output
LED current output
LED current output
LED current output
LED current output
Non wire connection
LED current output
LED current output
LED current output
LED current output
LED current output
LED current output
TEST mode setting Pin
LED driver ground
LED19
LED20
LED21
LED22
LED23
LED24
TEST
LGND
PWMOUT
CS3
PWM output signal for PWM frequency synchronization
Chip select
CS2
Chip select
CS1
Chip select
CS0
Chip select
N.C.
Non wire connection
Power supply input
VIN
Exposed pad. Connect EXP-PAD to the internal PCB ground plane using multiple via, it will
provide excellent heat dissipation characteristics.
EXP-PAD
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BD18333EUV-M
Block Diagram
LED1
LED2
VREF33
Current
Driver
TEST
LGND
AKSHORT
ULVO /
TSD
VLEDSH
VIN
LED OPEN
VDRV5
LED23
LED24
Bandgap
VREG5
VBG
0.3 V
VREG5
VREF33
LGND1
LGND2
LGND3
LGND4
VREG3
FAILB
EXTISET1
Short
VREG3
Control
Logic
FAIL
I/O
EXTISET2
Short
EN
RX
to Current
Driver
EXTISET1
EXTISET2
External
Current
Reference
TX
to Current
Driver
CS0
CS1
CS2
External
Current
Reference
Limp Home
CS3
RingOSC
PWMOUT
I/O
PWMIN
GND
Figure 3. Block Diagram
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BD18333EUV-M
Description of Block
1. Reference Voltage (VREG5, VREG3)
This IC generates 5.0 V (Typ) and 3.3 V (Typ) from the voltage input to VIN. These voltages are output on the VREG5 and
the VREG3 pins. The output voltage of the VREG5 pin (VVREG5) is used as the power supply for the internal circuit, and the
output voltage of the VREG3 pin (VVREG3) is used as the power supply for the internal digital circuit. To secure the phase
compensation capacitance, it is necessary to connect 1.0 μF to 10 μF to the VREG5 pin and 0.0 μF (the VREG3 pin is able
to set for capacitor less application with Nano CapTM technology) to 0.1 μF to the VREG3 pin. If a capacitor is not connected
to the VREG5 pin, circuit operation such as oscillation of the reference voltage will be very unstable. Do not use these pins
voltages as a power source other than this LSI.
UVLO function is built in to the VIN pin, the VREG5 pin and the VREG3 pin. When the conditions of VIN > 4.2 V (Typ),
VREG5 > 4.2 V (Typ), VREG3 > 2.8 V (Typ) are satisfied, the IC starts operating. If any condition of VIN < 4.0 V (Typ),
VREG5 < 4.0 V (Typ), VREG3 < 2.7 V (Typ) is satisfied, the IC will stop operating.
Nano Cap™ is a combination of technologies which allow stable operation even if output capacitance is connected with the
range of nF unit. And, this IC achieve capacitor less technology with the Nano CapTM
.
2. Current Driver
This IC has a built-in 24CH constant current driver. The maximum output current of the constant current driver is 125 mA/CH
when the EXTISET1 function is used. Built-in PWM dimming and DC dimming function for each CH. The resolution for each
dimming mode depends on the register settings. Please refer to the detailed description of Address 0x00h, 0x24h to 0x2Fh,
0x30h to 0x32h, 0x33h to 0x4Ah for the setting of dimming mode and output current.
Control Logic
LEDx
ILEDx
DC
Dimming
Circuit
Short Circuit
Protection
for EXTISET
External
Current
Refernce
LGND
EXTISET1
REXTISET1
Figure 4. LED Current Setting
Local PWM Dimming Control and LED Current Setting
This IC has a built-in 8-bit PWM dimming function. LED current PWM on duty of each channel can be controlled by
UART input. To use 8-bit PWM dimming, set the DIMMODE register value to "0". When using PWM dimming, the
LED current can be set by the built-in 4-bit DC dimming function.
LED current PWM on duty and LED current ILEDx (X = 1 to 24) can be calculated by the following formula.
[
]
푃푊푀 푂푁 푑푢푡푦 = 퐷퐼ꢀ푆퐸푇푥 7:0 +1 × ꢁꢂꢂ [%]
256
where:
ꢃꢄ푀ꢅꢆꢇꢈ[ꢉ: ꢂ] is the decimal number of DIMSETx[7:0]. (x = 01 to 24)
In case of using the EXTISET1 pin
(
[
]
)
퐷퐶퐷퐼ꢀ푥 3:0 +1
× ꢊ푉푅
ꢋ푋ꢌꢍꢎꢋꢌꢏ
× ꢁꢐꢂꢂꢂꢑ [A]
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢄ퐿퐸퐷푥
=
16
where:
ꢃꢒꢃꢄ푀ꢈ[ꢓ: ꢂ] is the decimal number of DCDIMx[3:0]. (x = 01 to 24)
ꢔ퐸ꢕ푇퐼푆퐸푇1 is the EXTISET1 pin voltage, 600 mV (Typ).
ꢖ퐸ꢕ푇퐼푆퐸푇1 is the Resistor for connecting the EXTISET1 pin.
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BD18333EUV-M
2. Current Driver -continued
(2) Local PWM Delay Control
This IC can reduce the load fluctuation by controlling the rising timing of LED current for each CH. This setting is
not required when using Local DC dimming described later.
Delay width (tDLY_LED) can be calculated by the following formula.
[
]
푡퐷퐿푌_퐿퐸퐷 = 4푏푖푡_ꢃꢒ_푃푊푀ꢃꢗꢘꢈ ꢓ: ꢂ × 8 ꢙ ꢐ4 [μs]
where:
4푏푖푡_ꢃꢒ_푃푊푀ꢃꢗꢘꢈ[ꢓ: ꢂ] is the decimal number of PWMDLYx[3:0]. (x = 01 to 24)
tLED_ONn is LED current PWM on time. (n = 1 to 24)
fPWM is PWM dimming frequency.
tDLY_LED
Internal
Reference
PWM Signal
ILEDn
tLED_ONn
1 / fPWM
PWM ON Duty = tLED_ONn × fPWM
Figure 5. Local PWM Delay Control
Local DC Dimming Control
This IC can switch the 8-bit PWM dimming register for Local DC dimming. To use 8-bit DC dimming, set the
DIMMODE register value to "1". When using 8-bit DC dimming, PWM ON Duty is fixed at 100 %.
LED current ILEDn (n = 1 to 24) can be calculated by the following formula.
In case of using the EXTISET1 pin
(
[
]
)
퐷퐼ꢀ푆퐸푇푥 7:0 +1
× ꢊ푉푅
ꢋ푋ꢌꢍꢎꢋꢌꢏ
× ꢁꢐꢂꢂꢂꢑ [A]
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢄ퐿퐸퐷푛
=
256
where:
ꢃꢄ푀ꢅꢆꢇꢈ[ꢉ: ꢂ] is the decimal number of DIMSETx[7:0].
ꢔ퐸ꢕ푇퐼푆퐸푇1 is the EXTISET1 pin voltage, 600 mV (Typ).
ꢖ퐸ꢕ푇퐼푆퐸푇1 is the Resitor for connecting the EXTISET1 pin.
LED Current Output Enable (PWMOUT, LEDEN)
This IC can individually turn off the CH regardless of the PWM/DC dimming setting. It can be set by updating the
register of Address 0x30h (PWMOUTL), 0x31h (PWMOUTM) and 0x32h (PWMOUTH). When this register is set,
the output is kept on until the next PWM cycle and the output is turn off at the PWM rising timing. The LED current
ON/OFF control can also be controlled using the Address 0x04h (LEDENL), 0x05h (LEDENM) and 0x06h
(LEDENH) registers. For these registers, ON/OFF control is reflected immediately when written to the register.
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Description of Blocks - continued
3. Diagnosis Enable (DEN)
When VIN < VIN_DEN , the IC cannot detect LED Open Detection (LEDOP).
VIN_DEN can be defined by setting register. (Address 0x17h)
4. LED Short Detection and Open Detection
This IC has LED short detection and open detection. LED short detection can be disabled, and LED short detect voltage
can be controlled by UART input. (Disable setting : Address 0x09h, 0x0Ah, LED detect voltage setting : Address 0x0Bh to
0x16h) LED error detection status of each channel can be read by UART input. (LED short : Address 0x4Bh to 0x4Dh, LED
open : Address 0x4Dh to 0x50h)
The IC can detect LED short condition when IC meets the following condition:
ꢔ
퐿퐸퐷푥
> ꢔ
푎ꢚ푑 ꢔ > ꢔ
퐿퐸퐷푆퐻 퐼ꢛ 퐼ꢛ_퐷퐸ꢛ
Where:
ꢔ
is the LEDx pin voltage. (x = 1 to 24)
is the LED short detect voltage
퐿퐸퐷푥
ꢔ
퐿퐸퐷푆퐻
ꢔ
is the Diagnosis Enable VIN voltage
퐼ꢛ_퐷퐸ꢛ
The IC can also detect LED open condition when the IC meets the following condition:
ꢔ
퐿퐸퐷푥
< ꢔ
푎ꢚ푑 ꢔ > ꢔ
퐿퐸퐷ꢜꢝ 퐼ꢛ 퐼ꢛ_퐷퐸ꢛ
Where:
ꢔ
is the LEDx pin voltage. (x = 1 to 24)
is the LED open detecting voltage, 0.3 V (Typ).
is the Diagnosis Enable VIN voltage.
퐿퐸퐷푥
ꢔ
퐿퐸퐷ꢜꢝ
ꢔ
퐼ꢛ_퐷퐸ꢛ
If the IC detects LED error (short or open) mode and set AUTOOFF register to “1” (Address 0x07h: SYSSET4), Current
Driver of detected CH is turn off and the FAILB pin voltage is switched to “Low”. Other current driver CH are continuing to
output.
LEDx
Current
Driver
125 mA (Max)
LGND
FAILB
LED short
Control
Logic
FAIL
VLEDSH
LED OPEN
0.3 V
Figure 6. LED Open Detection
LED Error Output Mask Time Setting
The mask time for LED error detection can be controlled by UART input. (Address 0x03h: SYSSET3)
LED error detection is disabled until the mask time has elapsed.
LED Error
Occurs
LED Error Detect
(Short / Open)
tERRMASK
ON
Current Driver
Latch OFF
FAILB
Figure 7. LED Error Output Mask Time Setting
Where:
tERRMASK is the mask time for LED error detection.
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BD18333EUV-M
Description of Blocks – continued
5. Protection Feature
Table 1. Protection Table 1
Detect
condition
Release
condition
Current
Driver
No.
1
Protection
FAILB
Low
Low
Low
Low
Low
Low
Low
Low
Status register
UVLOTSDERR
UVLOTSDERR
UVLOTSDERR
UVLOTSDERR
TSDW
LIMPHOME(Note 2)
VIN
UVLO
VIN <
4.0 V (Typ)
VIN >
4.2 V (Typ)
OFF
OFF
O
O
O
O
O
O
-
VREG5
UVLO
VREG5 <
4.0 V (Typ)
VREG5 >
4.2 V (Typ)
2
VREG3
UVLO
VREG3 <
2.7 V (Typ)
VREG3 >
2.8 V (Typ)
3
OFF
Ta >
175 °C (Typ)
Ta <
150 °C (Typ)
4
TSD
OFF
TSD
warning
Ta >
125 °C (Typ)
Ta <
110 °C (Typ)
5
operating
operating
VLEDx
<
VLEDx
>
6
LED open
LED Short
LOPERR
0.3 V (Typ)
0.4 V (Typ)
VLEDx
>
VLEDx <
7
register setting register setting operating
& PWM “High” & PWM “High”
LSHERR
LED cathode
short(Note 1)
VLEDx < 0.3 V
8
-
operating
CATHERR
-
(Typ)
Error in data
setent in
UART
Write/Read
No error in
data sent in
UART Write
9
CRC error
operating
Low
CRCERR
O
no access
during 100 ms
10
11
12
UART WDT
ISETSH1
ISETSH2
-
operating
operating
operating
Low
Low
Low
WDTERR
ISETSHERR
ISETSHERR
-
REXTISET1
<
REXTISET1
30 kΩ (Typ)
>
O
O
30 kΩ (Typ)
REXTISET2
<
REXTISET2
30 kΩ (Typ)
>
30 kΩ (Typ)
When it detects “VINUVLO” or “VREG3UVLO” or “VREG5UVLO” or “TSD” or “EN = L”, it invokes system reset. it can’t detect
other protection. (x = 1 to 24)
(Note 1) “LED open protection” is not available when set CATHEN register to “1”.
(Note 2) “O” this protection can be detected during LIMPHOME mode. “-” this protection cannot be detected during LIMPHOME mode. If any of “-” protection is
detect before entering LIMPHOME mode, keep status register until mode returns to normal.
The FAILB pin is recommended to pull up to VREG5. Recommended value for pull up resistance is 20 kΩ to 100 kΩ. When
above failure is detected, the FAILB pin voltage becomes “Low”. If the FAILB pin is not used pin shall be kept open.
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BD18333EUV-M
5. Protection Feature - continued
Table 2. Protection Table 2
Status and FAILB
output latch
enable
No.
Protection
SSMASK
ERRMASK
Protection enable
AUTOOFF
VIN
UVLO
1
2
-
-
-
-
-
-
O
-
-
VREG5
UVLO
O
VREG3
UVLO
3
-
-
-
O
O
-
4
TSD
-
-
-
-
TSD
warning
5
-
-
TSDWEN
LOPEN
LSHEN
CATHEN
-
-
-
6
LED open
LED short
O
O
-
O
O
-
LOPLAT
LSHLAT
O
O
O
-
7
LED cathode short
CRC error
7
8
-
-
CRCERLAT
O
-
9
UART WDT
ISETSH1
-
-
WDTEN
ISETSEL
ISETSEL
-
10
11
-
-
ISETLAT
ISETLAT
-
ISETSH2
-
-
-
O: It has this function by default.
-: It doesn’t have this function.
6. PWM Synchronization for Each Device
This feature allows BD18333EUV-M to synchronize internal clock with other BD18333EUV-M and vice versa. SYNCSET
register can set this IC as Leader or Follower. As Leader Device, it generates 488 Hz (Typ) reference signal (duty = 50 %)
in PWMOUT that other Follower devices use to adjust internal clock. As Follower Device, it enables PWMIN input to receive
the reference signal to adjust internal clock and LED output timing.
DUT#1
DUT#2
DUT#3
PWMOUT PWMIN
PWMOUT PWMIN
pwm
gen
pwm
gen
pwm
gen
pwm
pwm
pwm
sample
sample
sample
ring
ring
ring
oscillator
oscillator
oscillator
Figure 8. PWM Synchronization Setting
In this figure above, DUT#1 is a Leader device, it generates the reference signal via PWMOUT. On the other hand, DUT#2
receives the reference signal via PWMIN, it processes this signal to adjust the internal ring oscillator. Same process in
DUT#2 occur in DUT#3 and so on. There is only a single Leader device.
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BD18333EUV-M
Description of Blocks – continued
7. LIMPHOME Function
This IC has LIMPHOME function. This function is controlled by LIMPHEN register (Address 0x5Eh, initially enabled). If
LIMPHEN is “1” and there is no UART access (no CRC OK) for over 1.0 s (Typ), device detects the error and operates LED
dimming. In each state, LED dimming is according to the latest register value (DIMSET, DCDIM and LHDTY). The registers
are updated at the timing described in the register description.
Note: Devices can be connected in parallel, refer to UART Protocol for more details. When a device is connected in parallel
and is not being accessed while other devices are being accessed, it will not enter LIMPHOME mode.
System Reset
(UVLO, TSD)
Other
IDLE
No UART Access > 1.0 s
UART Access
Other
Other
UART Access
STANDBY
LIMPHOME1
LIMPHEN = 1 & No UART
Access > 1.0 s
DIMSTART = 1
Other
DIMSTART = 0
UART Access
Other
LIMPHEN = 1 & No UART Access > 1.0 s
UART Access
Normal Dimming
LIMPHOME2
Figure 9. LIMPHOME Function
Table 3. LIMPHOME Dimming Settings ( x = 1 to 24 )
Dimming setting
State
Description
Reset condition,
Current reference setting
-
DC current setting
-
PWM duty setting
-
IDLE
No lighting
During initial setting,
No lighting
-
-
-
STANDBY
lighting by EXTISET2
resistor (UART error
condition)
EXTISET2
100 % (DCDIMx)
100 % (LHDTYx)
LIMPHOME1
Normal dimming condition
ISETSEL = 0 (Internal ISET)
ISETSEL = 1 (EXTISET1)
DIMMODE = 0
DCDIMx
DIMMODE = 0
DIMSETx
Normal
Dimming
DIMMODE = 1
DIMSETx
DIMMODE = 0
DCDIMx
DIMMODE = 1
DIMSETx
DIMMODE = 1
100 %
LHDTYx
lighting by UART
LIMPHOME setting (UART
error condition)
LEXTISET2SEL = 1(Note 1)
EXTISET1 + EXTISET2
LIMPHOME2
LEXTISET2SEL = 0
ISETSEL = 0 (Internal ISET)
ISETSEL = 1 (EXTISET1)
(Note 1) Not Recommended Setting
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BD18333EUV-M
7. LIMPHOME Function – continued
At LIMPHOME1,
In case of the EXTIET2 pin set “OPEN”
ILEDn = 0 [A]
In case of the EXTISET2 pin set REXTISET2
푉
푅
ꢋ푋ꢌꢍꢎꢋꢌꢞ
× ꢁꢐꢂꢂꢂ [A]
ꢋ푋ꢌꢍꢎꢋꢌꢞ
ꢄ퐿퐸퐷푛
=
At LIMPHOME2,
[
]
퐿퐻퐷푇푌푥 3:0 + 1
푃푊푀 푂푁 푑푢푡푦 =
× ꢁꢂꢂ [%]
16
In case of using the EXTISET2 pin and the EXTISET2 pin set “OPEN”
ILEDn = 0 [A]
In case of using the EXTISET2 pin and DIMMODE = 0
(
[
]
)
퐷퐶퐷퐼ꢀ푥 3:0 + 1
× ꢊ푅푉ꢋ푋ꢌꢍꢎꢋꢌꢏ ꢙ 푉푅ꢋ푋ꢌꢍꢎꢋꢌꢞꢑ × ꢁꢐꢂꢂꢂ [A]
16
ꢋ푋ꢌꢍꢎꢋꢌꢏ ꢋ푋ꢌꢍꢎꢋꢌꢞ
ꢄ퐿퐸퐷푛
=
In case of using the EXTISET2 pin and DIMMODE = 1
(
[
]
)
퐷퐼ꢀ푆퐸푇푥 7:0 + 1
푉
× ꢊ푉푅
ꢙ 푅ꢋ푋ꢌꢍꢎꢋꢌꢞꢑ × ꢁꢐꢂꢂꢂ [A]
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢄ퐿퐸퐷푛
=
256
ꢋ푋ꢌꢍꢎꢋꢌꢞ
In case of using the Internal Current Set and DIMMODE = 0
(
[
]
)
퐷퐶퐷퐼ꢀ푥 3:0 + 1
× ꢂ.ꢂꢟꢂ [A]
16
ꢄ퐿퐸퐷푛
=
In case of using the Internal Current Set and DIMMODE = 1
(
[
]
)
퐷퐼ꢀ푆퐸푇푥 7:0 + 1
× ꢂ.ꢂꢟꢂ [A]
256
ꢄ퐿퐸퐷푛
=
In case of using the EXTISET1 pin and DIMMODE = 0
(
[
]
)
퐷퐶퐷퐼ꢀ푥 3:0 + 1
× ꢊ푅푉
× ꢁꢐꢂꢂꢂꢑ [A]
× ꢁꢐꢂꢂꢂꢑ [A]
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢄ퐿퐸퐷푛
=
16
In case of using the EXTISET1 pin and DIMMODE = 1
(
[
]
)
퐷퐼ꢀ푆퐸푇푥 7:0 + 1
× ꢊ푉푅
ꢋ푋ꢌꢍꢎꢋꢌꢏ
256
ꢋ푋ꢌꢍꢎꢋꢌꢏ
ꢄ퐿퐸퐷푛
=
where: (n = 1 to 24, x = 01 to 24)
ꢄ퐿퐸퐷푛 is the each channel current.
ꢔ퐸ꢕ푇퐼푆퐸푇2 is the EXTISET2 pin voltage. It is 300 mV (Typ).
ꢖ퐸ꢕ푇퐼푆퐸푇2 is the Resistor for connecting the EXTISET2 pin.
ꢗꢠꢃꢇꢘꢈ[ꢓ: ꢂ] is the decimal number of LHDTYx[3:0].
ꢃꢒꢃꢄ푀ꢈ[ꢓ: ꢂ] is the decimal number of DCDIMx[3:0].
ꢃꢄ푀ꢅꢆꢇꢈ[ꢉ: ꢂ] is the decimal number of DIMSETx[7:0].
ꢔ퐸ꢕ푇퐼푆퐸푇1 is the EXTISET1 pin voltage, 600 mV (Typ).
ꢖ퐸ꢕ푇퐼푆퐸푇1 is the Resistor for connecting the EXTISET1 pin
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BD18333EUV-M
Absolute Maximum Ratings (Tj = 25 °C)
Parameter
Symbol
VIN
Rating
Unit
V
Power Supply Voltage
EN Pin Voltage
-0.2 to +42.0
VEN
-0.2 to VIN
-0.2 to +42.0
-0.2 to +4.5
V
V
V
LED1 to LED24 Pin Voltage
VREG3 Pin Voltage
VLED1 to VLED24
VVREG3
VREG5, FAILB, RX, TX, PWMIN,
PWMOUT, CS0, CS1, CS2, CS3,
EXTISET1, EXTISET2 Pin Voltage
VVREG5, VFAILB, VRX, VTX, VPWMIN, VPWMOUT, VCS0
VCS1, VCS2, VCS3, VEXTISET1, VEXTISET2
,
-0.2 to +7.0
< VVREG5
V
Storage Temperature Range
Tstg
-55 to +150
°C
°C
Maximum Junction Temperature
Tjmax
150
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
HTSSOP-C48
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
71.20
9.00
28.30
7.00
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A (Still-Air), using a BD18333EUV-M Chip.
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface
of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70 μm
Footprints and Traces
Layer Number of
Measurement Board
Thermal Via(Note 5)
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Bottom
Copper Pattern
Footprints and Traces
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 5) This thermal via connect with the copper pattern of layers 1,2, and 4. The placement and dimensions obey a land pattern.
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BD18333EUV-M
Recommended Operating Condition
Parameter
Symbol
VIN
Min
4.5
Typ
Max
40.0
Unit
V
Comment
Power Supply Voltage(Note 1)
Operating Temperature
12.0
-40
1.0
0.0
56
25
4.7
-
+125
10.0
0.1
°C
μF
μF
kΩ
kΩ
kΩ
Hz
Topr
CVREG5
CVREG3
REXTISET1
REXTISET2
RFAILB
The Capacitor
for Connecting the VREG5 Pin
The Capacitor
for Connecting the VREG3 Pin(Note 2)
The Resistor
-
1200
720
220
600
for Connecting the EXTISET1 Pin
The Resistor
56
-
for Connecting the EXTISET2 Pin
The Resistor
56
100
488
for Connecting the FAILB Pin
PWMIN Frequency
fEXTCLK
400
Please connect to the
PWMOUT pin of Leader
device
-
50
-
%
PWMIN Duty
DEXTCLK
Note: Above operation range is referring to IC independently. Thorough verification of the coefficient setting in actual application shall be practiced.
(Note 1) When IC is started, the volrage must be UVLO release voltage or more. Therefore, consider the power supply drop caused by the parasitic resistor.
VIN (Min) = 4.5V is the minimum value that can operate the IC independently after started. The minimum value of power supply voltage that can be set
depends on the voltage drop due to the parasitic resistor of power line.
(Note 2) The VREG3 pin is designed to work with “Capacitor less” application for use Nano CapTM technology. When adding capacitor, it may affect noise.
So please kindly consider noise reduction such as using a 2s2p PCB board and etc.
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TSZ22111 • 15 • 001
09.Sep.2022 Rev.001
BD18333EUV-M
Electrical Characteristic
(Unless otherwise specified : VIN = 13 V , Tj= -40 °C to +150 °C)
Parameter
[Device Overview]
Symbol
Min
Typ
Max
Unit
Condition
VEN = High,
24CH Current driver OFF
Circuit Current
ICC
-
-
12.5
7.0
20.0
15.0
mA
Standby Current
ISTB
μA
VEN = Low
[VREG5 Block]
VREG5 Pin Output Voltage
VVREG5
ΔVVREG5
IVREG5OCP
4.5
-
5.0
5.5
50
-
V
IVREG5 = 0 mA
IVREG5 = 5 mA
VREG5 Pin
Load Regulation Voltage
-
-
mV
mA
VREG5 Pin Over Current Protection
[VREG3 Block]
60
VREG3 Pin Output Voltage
VVREG3
ΔVVREG3
IVREG3OCP
3.1
-
3.3
3.5
30
-
V
IVREG3 = 0 mA
IVREG3 = 5 mA
VREG3 Pin
Load Regulation Voltage
-
-
mV
mA
VREG3 Pin Over Current Protection
30
[Constant Current Driver Block]
RLED1
RLED2
-
-
-
-
6.5
9.5
Ω
Ω
Tj = 25 °C,
LED Pin ON Resistance
Tj = -40 °C to +150 °C,
Tj = 25 °C,
REXTISET1 = 120 kΩ,
ISETSEL = 1,
DCDIMx[3:0] = 0xFh,
DIMSETx[7:0] = 0xFFh
(x = 01 to 24)
-3.5
-
+3.5
%
LED Pin Output Current
Absolute Error 1
(IOUT_AVE/IOUT_IDEAL - 1)
ΔIOUTA1
Tj = -40 °C to +150 °C,
REXTISET1 = 120 kΩ,
ISETSEL = 1,
DCDIMx[3:0] = 0xFh,
DIMSETx[7:0] = 0xFFh
(x = 01 to 24)
Tj = 25 °C,
REXTISET1 = 120 kΩ,
ISETSEL = 1,
-5.5
-4
-
-
+5.5
+4
%
%
LED Pin Output Current
Relative Error 1
ΔIOUTR1
(IOUTx/IOUT_AVE - 1)
DIMSETx[7:0] = 0xFFh
(x = 01 to 24)
Tj = 25 °C
REXTISET1 = 120 kΩ,
ISETSEL = 0,
DIMMODE = 0,
DCDIMx[3:0] = 0x0h to 0xFh
DIMSETx[7:0] = 0xFFh,
(x = 01 to 24)
IINL
-1.5
-1.5
-
-
+1.5
+1.5
LSB
LSB
LED Pin Output Current
DC Dimming Function
Differential Nonlinearity
(Note 1)
IDNL
PWM Frequency
fPWM
440
488
30
535
50
Hz
kΩ
kΩ
EXTISET1 Pin
Short Circuit Protection Resistor
REXTISET1_SCP
REXTISET2_SCP
-
-
EXTISET2 Pin
Short Circuit Protection Resistor
(Note 1) Guaranteed by design only
30
50
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BD18333EUV-M
Electrical Characteristic - continued
(Unless otherwise specified: VIN = 13 V , Tj= -40 °C to +150 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
[PROTECT LOGIC Block]
VVREG5 falling detect
threshold
VREG5UVLO Detection Voltage
VREG5UVLO Hysteresis Voltage
VREG3UVLO Detection Voltage
VREG3UVLO Hysteresis Voltage
VINUVLO Detection Voltage
VVREG5UVLO
VVREG5UVHYS
VVREG3UVLO
VVREG3UVHYS
VVINUVLO
3.8
-
4.0
200
2.7
4.2
-
V
mV
V
VVREG3 falling detect
threshold
2.5
-
2.9
-
100
4.0
mV
V
3.8
-
4.2
-
VVIN falling detect threshold
VINUVLO Hysteresis Voltage
[LED Abnormal Detection Block]
LEDOPEN Detection Voltage
VVINUVHYS
200
mV
VLEDn falling detect threshold
(n = 1 to 24)
VLEDn rising detect threshold
(n = 1 to 24)
LEDSHx[7:0] = 0x21h
(x = 01 to 24)
VLEDOP
VLEDSH
VIN_DEN
0.2
1.8
6.3
0.3
2.0
7.0
0.4
2.2
7.7
V
V
V
SHORT Detection Voltage
Diagnosis Enable VIN Voltage
DENVOLT[3:0] = 0x7h
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BD18333EUV-M
Electrical Characteristic - continued
(Unless otherwise specified: VIN = 13 V, Tj = -40 °C to +150 °C)
Parameter
[EN Input Pin]
Symbol
Min
Typ
Max
Unit
Condition
EN Pin Input Current
IEN
2.5
5
-
10
VIN
μA
V
VEN = 5.0 V
0.75 x
VVREG5
EN Input Pin High Voltage
VENH
VENL
0.2 x
VVREG5
EN Input Pin Low Voltage
-0.2
-
V
[LOGIC Input (CS0, CS1, CS2, CS3)]
CSx Pin Output Current
(x = 0,1,2,3)
VCSx = 0.0 V
ICSx
-10
-
-5
-
-
μA
2.5
CSx Pin Setting Voltage
[LOGIC Input (PWMIN)]
PWMIN Pin Input Current
VCSxSET
V
IPWMIN
VPWMINH
VPWMINL
20
50
-
100
μA
V
VPWMIN = 5.0 V
0.75 x
VVREG5
VVREG5
+ 0.2
PWMIN Input Pin High Voltage
0.2 x
VVREG5
PWMIN Input Pin Low Voltage
[LOGIC Input (RX)]
-0.2
-
V
0.75 x
VVREG5
VVREG5
+ 0.2
RX Input Pin High Voltage
VRXH
VRXL
-
-
V
V
0.2 x
VVREG5
RX Input Pin Low Voltage
[LOGIC Output Block (PWMOUT)]
Output High Voltage
-0.2
0.75 x
VVREG5
VVREG5
+ 0.2
VOUTH
VOUTL
-
-
V
V
IPWMOUT = -1 mA
IPWMOUT = +1 mA
Output Low Voltage
-
0.2
[LOGIC Output Block (TX) Block]
Output High Voltage
0.75 x
VVREG5
VVREG5
+ 0.2
VTXH
VTXL
-
-
V
V
ITX = -1 mA
ITX = +1 mA
0.2 x
VVREG5
Output Low Voltage
-
[FAILB Output Block]
FAILB Pin ON Resistance
RFAILB
0.30
0.65
1.00
kΩ
μA
IFAILB = 1 mA
VFAILB = 5.0 V
FAILB Pin Leak Current
ILEAKFAILB
-
-
10
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BD18333EUV-M
Typical Performance Curve
(Unless otherwise specified VIN = 13 V, Tj = -40 °C to +150 °C, CVREG5 = 4.7 µF)
20.0
14.0
18.0
16.0
14.0
12.0
10.0
8.0
12.0
10.0
8.0
6.0
6.0
4.0
4.0
2.0
2.0
0.0
0.0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Temperature [°C]
Temperature [°C]
Figure 10. Circuit Current vs Temperature
Figure 11. Standby Current vs Temperature
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
3.5
3.4
3.3
3.2
3.1
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Temepature [°C]
Temperature [°C]
.
Figure 12. VREG5 Pin Output Voltage vs Temperature
Figure 13. VREG3 Pin Output Voltage vs Temperature
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BD18333EUV-M
Typical Performance Curve - continued
(Unless otherwise specified VIN = 13 V, Tj = -40 °C to +150 °C , CVREG5 = 4.7 µF)
63.50
9.00
62.50
61.50
60.50
59.50
58.50
57.50
56.50
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
ILED = 50 mA
ILED = 100 mA
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Temperature [°C]
Temperature [°C]
Figure 14. LED Pin Ron vs Temperature
Figure 15. LED Pin Output Current vs Temperature
65
60
55
50
45
40
35
30
25
20
15
10
5
600
580
560
540
520
500
480
460
440
420
400
Tj = +150 °C
Tj = +25 °C
Tj = -40 °C
0
-50 -25
0
25 50 75 100 125 150
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DCDIM DAC [bit]
Temperature [°C]
Figure 16. LED Pin Output Current DC Dimming
vs DCDIM DAC
Figure 17. PWM Frequency vs Temperature
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BD18333EUV-M
Functions of Logic Block
1. UART Protocol and AC Electrical Characteristics
This device has a UART Interface (Universal Asynchronous Receiver-Transmitter). This interface uses the RX (Receiver)
and TX (Transmitter) pins for communication. The initial value of UART communication RX and TX is “High”. The format of
a frame consists of 10-bit: start bit, 8-bit data and stop bit. Data is sent from LSB first to MSB last.
For read command, MCU must synchronize each frame of UART start bit and strobe data at 50 % to provide enough margin
to ensure successful communication.
start bit
"0"
stop bit
"1"
data0
data1 data2
data3
data4
data5
data6
data7
Figure 18. Data Format of a Frame
start bit
"0"
stop bit
"1"
1
0
1
0
1
0
1
0
initialized format
Figure 19. Clock Synchronization (SYNC)
SYNC
Dev,B,RW
NumOfData
Address
Data1
Datan
CRCL
CRCH
RX
TX
Hi-z
Figure 20. UART Protocol (WRITE)
ND ND ND ND ND ND ND ND
[0] [1] [2] [3] [4] [5] [6] [7]
DA DA DA DA
[0] [1] [2] [3]
RW
B
1
0
1
0
1
0
1
0
0
0
RX
TX
S
P
S
P
S
P
S:
P:
RW:
B:
start condition
stop condition
0: Write / 1: Read
Broadcast
Device Address[5:0]
RW,DevAdd[2:0]
clock synchronization
(0x55)
NumofData[7:0]
DA[3:0]: Device Address
ND[7:0]: Number Of Data
AD[7:0]: Register Address
DT[7:0]: Data
Hi-z
CR[15:0]: CRC16
AD AD AD AD AD AD AD AD
[0] [1] [2] [3] [4] [5] [6] [7]
DT DT DT DT DT DT DT DT
[0] [1] [2] [3] [4] [5] [6] [7]
CR CR CR CR CR CR CR CR
[0] [1] [2] [3] [4] [5] [6] [7]
CR CR CR CR CR CR CR CR
P
[8] [9] [10] [11] [12] [13] [14] [15]
RX S
TX
P
S
P
S
P
S
Hi-z
Figure 21. Detail of UART Protocol (WRITE)
0.5 bit to 1.5 bit
stop
SYNC
Dev,B,RW
NumOfData
Address
CRCL
CRCH
RX
TX
start
Hi-z
Data1
Datan
CRCL
CRCH
Figure 22. UART Protocol (READ)
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BD18333EUV-M
Functions of Logic Block – continued
2. UART AC Timing
RX
TX
high Vth
low Vth
trx
trxslew1
trxslew2
ttxwait
ttxslew1
ttxslew2
ttx
Figure 23. UART AC Timing
tresetwait
trxwait1
trxwait2
SWRST
RX
TX
Write command (SWRST)
to next write command
Write command to
next write command
Read command to
next write command
Figure 24. UART Inter-command Timing
Table 4. UART AC Characteristics
Recommended Operation Condition (Unless otherwise specified, VIN =13 V ,Tj = -40 °C to +150 °C)
Rating
Parameter
Symbol
Unit
Comments
Min
1.0
1.0
0.5
-
Typ
Max
10.0
RX transfer time
trx
-
μs
μs
bit
μs
μs
μs
μs
TX transfer time
ttx
-
10.0
TX output delay time
ttxwait
trxslew1
trxslew2
ttxslew1
ttxslew2
1.0
1.5
RX slew rate High to Low
RX slew rate Low to High
TX slew rate High to Low
TX slew rate Low to High
-
-
-
-
trx x 10 %
trx x 10 %
ttx x 10 %
ttx x 10 %
-
-
-
The time interval between
continuous write commands.
The time interval between read
and write commands.
The time required after the
software reset write.
RX to RX wait time
trxwait1
trxwait2
2.0
2.0
100
-
-
-
-
-
-
μs
μs
μs
TX to RX wait time
RX to RX wait after SWRST
tresetwait
(Output load capacitance：15 pF)
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BD18333EUV-M
Functions of Logic Block – continued
3
UART Protocol
3.1 Initialize Format
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
1
0
1
0
1
0
1
This interface receives SYNC frame 0x55h (0b01010101) to calculate the baudrate of the incoming UART command.
It generates internal sampling time based on the computed baudrate (1-bit period / 2). After receiving the SYNC frame,
this interface expects succeeding frames have the same baudrate as that of the SYNC frame. If incorrect input timing
occurred, it may trigger communication error.
3.2
Device Address, Broadcast, Read/Write
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RW
B
DA[5:0]
bit
Parameter
Function
We can set from “0b000000” to “0b001111”.
DA[0] = CS0 setting
DA[1] = CS1 setting
DA[2] = CS2 setting
DA[3] = CS3 setting
DA[4] = 0
DA[5:0]
Device Address
DA[5] = 0
Note:
1. When the CSx (x = 0 to 3) pin are OPEN, DA[5:0] = 0b000000.
2. When the CSx pin short to GND, DA[n] is “High”, inverted operation. (n = 0 to 5)
3. When the CSx pin set to over 4.5 V (Typ), DA[n] is “Low”, inverted operation.
bit
B
Parameter
Broadcast
Function
0: Access the device that matched the device address
1: Access all devices connected to the UART line.
Note:
1. Broadcast is not possible for Read access
2. If B = 1, device address setting is ignored.
bit
Parameter
Read/Write
Function
0: Write access
1: Read access
RW
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BD18333EUV-M
3
UART Protocol – continued
3.3
Number of Data
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
NumOfData[7:0]
bit
Parameter
Function
NumOfData [7:0]
Number of Data transferred
Available to use from 1 to 27.
Note:
1. Available data buffer for multiple write access is 27 data.
2. NumOfData = 0 is not valid.
3. NumOfData > 27 is not valid.
3.4
Register Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RegAddr [7:0]
bit
Parameter
Function
RegAddr [7:0]
Register Address
It is available to access from 0x00h to 0x5Eh.
3.5
Data
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Data [7:0]
bit
Parameter
value
Data [7:0]
Data
0x00h to 0xFFh.
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BD18333EUV-M
3
UART Protocol – continued
3.6
CRC
16bit LSB First:
Cyclic Redundancy Check (CRC)
The CRC-16 is used to detect errors in the UART I/F Communication data.
The data included for CRC computation are the following: Device address, Number of Data, Address Data, Write or
Read Data.
During write communication (both write and read command has write communication),
The last 2 frames received in a write communication is a 16-bit CRC data that will be compared to the computed CRC.
If CRC data is the same with the computed CRC, Register Map will be updated with all the written data.
Else, All written data will be disregarded, CRC Status Register becomes High and FAILB output becomes “Low”.
"
CRC Error is released after sending UART Write command with correct data (Matched CRC Calculation). UART Read
command will not release CRC Error.
CRC Polynomial:
CRC Polynomial is expressed as
CRC16-IBM
x16+x15+x2+1
Bit Order LSB First:
The CRC calculation starts with LSB and proceeds from bit[0] to bit[7] of each byte.
Figure 25. CRC Polynomial
CRC Initial Setting:
The initial value is “0x0000h”.
The CRC calculate registers are reset to the initial value of “0x0000h” prior to each CRC bytes calculation.
Example for
RW,B,DA[5:0] NumofData[7:0]
Address[7:0]
Data[7:0]
CRC Data[7:0] CRC Data[15:8]
Figure 26. CRC Data Format
RW,B,DA[5:0]:
NumOfData[7:0]:
Address[7:0]:
Data[7:0]:
CRC Data[7:0]:
CRC Data[15:8]:
DA[7:0] = 0x1Ah to
ND[7:0] = 0x02h to
AD[7:0] = 0xA5h to
DT[7:0] = 0x5Ah to
CR[7:0] = 0xBAh to
CR[15:8] = 0xCDh to
DA[0:7] = 0x58h
ND[0:7] = 0x40h
AD[0:7] = 0xA5h
DT[0:7] = 0x5Ah
CR[0:7] = 0xB3h
CR[8:15] = 0x5Dh
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BD18333EUV-M
3.6
CRC - continued
ꢡ16 ꢙ ꢡ15 ꢙ ꢡ2 ꢙ ꢁ
Initial Value: 0x0000
LSB First
Data
0
0
0
1
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
2
0
0
1
1
1
0
1
0
0
3
0
0
0
1
1
1
0
1
0
4
0
0
0
0
1
1
1
0
1
5
0
0
0
0
0
1
1
1
0
6
0
0
0
0
0
0
1
1
1
7
0
0
0
0
0
0
0
1
1
8
0
0
0
0
0
0
0
0
1
9
0
0
0
0
0
0
0
0
0
10 11 12 13 14 15
MSB first LSB first
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1A
02
A5
5A
58
40
A5
5A
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
1
0
1
1
0
0
0
3
D
8
3
C
1
1
7
A
8
5
0
B
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
5
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
0
B
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
CRC:
BACD
D
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BD18333EUV-M
3. UART Protocol - continued
3.7
Example of UART Protocol
Single device, 1 byte Write (Write to Device #1)
(CS3,CS2,CS1,CS0) =
B =
DevAddr[5:0] =
NumOfData[7:0] =
RW =
“0101”
0:
0x05h:
1:
Target Device receives the data
Target Device Address
1 byte Write mode
Write
0:
RegAddr[7:0] =
Data[7:0] =
0x02h:
0xAAh: Data
Address
RX
S
initialize (0x55)
P
S
Device address
(0x5)
B
RW P
S
NumOfData (0x1)
P
S
Address (0x2)
P
S
Data(0xAA)
P
Figure 27. UART Protocol of the 1 byte Write to Device #1
4. Communication Reset
UART IF has a communication reset function. This function can be used to interrupt UART communication and return to idle
condition. This function is triggered by setting RX to “High” for atleast 2.75 ms (Typ). This feature can be used to recover
from communication. If Communication Reset is executed, it will not affect LED Dimming. When UART is in IDLE condition
it does not detect Communication Reset.
Communication Comm Reset
Error
UART recovered
Can Write/Read
RX
TX
UART State
machine
CRC Error
Status
FAILB
output
Succeeding UART commands malfunction
due to Communication error
Figure 28. Communication Reset
5. Watchdog Timer (WDT)
UART IF has a watchdog timer function. This function monitors the RX line for no UART access for 100 ms (Typ) and notifies
via status register and FAILB output. This no UART access means no successful UART command (no CRC OK). This
function is enabled by WDTEN (initial is “Low”) and the status can be checked in WDTERR Status register and can be
observed in the FAILB pin output. When detected, it returns the UART state to idle condition and does not affect LED Dimming.
Details of the operation is further discussed in Error Control and Error Sequence.
When a device is connected in parallel and is not being accessed, it will not detect WDT
UART commands
stopped
Watchdog timer
100 ms
UART
(RX/TX)
CRC OK
WDTERR
Error Status
FAILB
output
Figure 29. Watchdog Timer
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BD18333EUV-M
Functions of Logic Block – continued
6. Register Map
Each registers is updated at the 2 timings.
Reset Condition: “UVLO” condition = VREG3UVLO, VREG5UVLO, VINUVLO, TSD or EN is detected.
Register Update timing for control data:
A. Updated to the newest data immediately when the data is written.
B. Updated to the newest data when the next PWM (PWM is internal signal) timing after the data is written.
MCU
Analog Circuit
Type A/Type B
(DIMMODE = 1)
UART
Write
Immediate
(UARTwrite
after CRC OK)
Buffer 1
Control Data
UART
Read
Type B
(DIMMODE = 0)
(Base PWM
timing)
(PWM Gen
Timing)
UART
PWMIN
update
Register Map
(Update Timing A)
update
Buffer 1
update
Control Signal
(Update Timing B)
ILEDx (x = 1 to 24)
(PWM output)
Figure 30. UART Data Flow
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BD18333EUV-M
6. Register Map – continued
*Attention:
Please don’t access (Write/Read) register except for following registers (0x00h to 0x5Eh) and write “0” in “-“.
“RESERVED” Registers can be written/read. Do not update.
Address 0x00h to 0x23h (1/3)
Register
Access
Reset
Condition
update
timing
Register Name
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
initial
comments
UVLO or
SWRST
UVLO or
SWRST
2)
1)
2)
1)
PWMTIM(Note
FAILBEN
PWMPSYNC(Note
PWMFSYNC(Note
SWRST(Note
SYNC
0x00
0x01
PWMFSYNCSET
FAILBCNT
ISETSEL
SLOPEEN
DIMMODE
DIMSTART
R/W
R/W
0x00
0x00
Type A PWM phase syncronization and output
PWM frequency synchronous setting and SSCG
enable, FAILB control setting
RESERVED
SYNCSET[1:0]
SYSSET1
SYSSET2
Type A
UVLO or
SWRST
RESERVED
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x20
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Type A Reserved
UVLO or
SWRST
Error mask for LED open/short, Error mask setting
during softstart
ERRMASK[3:0]
RESERVED
SYSSET3
Type A
UVLO or
SWRST
LEDEN[7:0]
LEDENL
Type A Channel enable for LED1 to LED8
Type A Channel enable for LED9 to LED16
Type A Channel enable for LED17 to LED24
Type A Error status and flag latch setting
UVLO or
SWRST
LEDEN[15:8]
LEDENM
UVLO or
SWRST
LEDEN[23:16]
LEDENH
UVLO or
SWRST
1)
ERRCLR(Note
SYSSET4
-
-
ISETLAT
AUTOOFF
RESERVED
CRCERLAT
TSDWEN
LSHLAT
WDTEN
LOPLAT
LOPEN
UVLO or
SWRST
error enable
Type A
CATHEN(Note
1)
SYSSET5
-
RESERVED
RESERVED
LSHEN[7:0]
CATHEN returns ‘0’ automatically
UVLO or
SWRST
LEDSHENL
Type A LED short enable
UVLO or
SWRST
ISETSHCNT[1:0]
LSHEN[11:8]
LEDSHENH
LEDSHTH0102
LEDSHTH0304
LEDSHTH0506
LEDSHTH0708
LEDSHTH0910
LEDSHTH1112
LEDSHTH1314
LEDSHTH1516
LEDSHTH1718
LEDSHTH1920
LEDSHTH2122
-
-
Type A LED short enable, OCP current setting
UVLO or
SWRST
LEDSHTH0102[7:0]
LEDSHTH0304[7:0]
LEDSHTH0506[7:0]
LEDSHTH0708[7:0]
LEDSHTH0910[7:0]
LEDSHTH1112[7:0]
LEDSHTH1314[7:0]
LEDSHTH1516[7:0]
LEDSHTH1718[7:0]
LEDSHTH1920[7:0]
LEDSHTH2122[7:0]
LEDSHTH2324[7:0]
Type A LED short detection voltage for LED1 and LED2
Type A LED short detection voltage for LED3 and LED4
Type A LED short detection voltage for LED5 and LED6
Type A LED short detection voltage for LED7 and LED8
Type A LED short detection voltage for LED9 and LED10
Type A LED short detection voltage for LED11 and LED12
Type A LED short detection voltage for LED13 and LED14
Type A LED short detection voltage for LED15 and LED16
Type A LED short detection voltage for LED17 and LED18
Type A LED short detection voltage for LED19 and LED20
Type A LED short detection voltage for LED21 and LED22
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
LEDSHTH2324
DENVOLT
0x16
0x17
0x18
R/W
R/W
R/W
0x00
0x00
0x00
Type A LED short detection voltage for LED23 and LED24
Type A DEN threshold voltage
UVLO or
SWRST
RESERVED
PWMFREQ[1:0]
DENVOLT[3:0]
UVLO or
SWRST
PWMDLY0102
PWMDLY02[3:0]
PWMDLY04[3:0]
PWMDLY06[3:0]
PWMDLY08[3:0]
PWMDLY10[3:0]
PWMDLY12[3:0]
PWMDLY14[3:0]
PWMDLY16[3:0]
PWMDLY18[3:0]
PWMDLY20[3:0]
PWMDLY22[3:0]
PWMDLY24[3:0]
PWMDLY01[3:0]
Type A PWM delay setting for LED1 and LED2
UVLO or
SWRST
PWMDLY0304
PWMDLY0506
PWMDLY0708
PWMDLY0910
PWMDLY1112
PWMDLY1314
PWMDLY1516
PWMDLY1718
PWMDLY1920
PWMDLY2122
PWMDLY2324
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
PWMDLY03[3:0]
PWMDLY05[3:0]
PWMDLY07[3:0]
PWMDLY09[3:0]
PWMDLY11[3:0]
PWMDLY13[3:0]
PWMDLY15[3:0]
PWMDLY17[3:0]
PWMDLY19[3:0]
PWMDLY21[3:0]
PWMDLY23[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Type A PWM delay setting for LED3 and LED4
Type A PWM delay setting for LED5 and LED6
Type A PWM delay setting for LED7 and LED8
Type A PWM delay setting for LED9 and LED10
Type A PWM delay setting for LED11 and LED12
Type A PWM delay setting for LED13 and LED14
Type A PWM delay setting for LED15 and LED16
Type A PWM delay setting for LED17 and LED18
Type A PWM delay setting for LED19 and LED20
Type A PWM delay setting for LED21 and LED22
Type A PWM delay setting for LED23 and LED24
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
UVLO or
SWRST
WO: Write Only, RO: Read Only, R/W: Read and Write
(Note 1) PWMPSYNC,CATHEN, SWRST and ERRCLR are “write only”, and reset condition of SWRST is only “UVLO/TSD”
(Note 2) PWMTIM and PWMFSYNC are read-only Registers
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BD18333EUV-M
6. Register Map – continued
Address 0x24h to 0x51h (2/3)
Register
Access
Reset
Condition
update
timing
Register Name
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
initial
comments
UVLO or
SWRST
DC Dimming setting for LED1 and LED2 in PWM
mode
DCDIM0102
DCDIM0304
DCDIM0506
DCDIM0708
DCDIM0910
DCDIM1112
DCDIM1314
DCDIM1516
DCDIM1718
DCDIM1920
DCDIM2122
DCDIM2324
PWMOUTL
PWMOUTM
PWMOUTH
DIMSET01
DIMSET02
DIMSET03
DIMSET04
DIMSET05
DIMSET06
DIMSET07
DIMSET08
DIMSET09
DIMSET10
DIMSET11
DIMSET12
DIMSET13
DIMSET14
DIMSET15
DIMSET16
DIMSET17
DIMSET18
DIMSET19
DIMSET20
DIMSET21
DIMSET22
DIMSET23
DIMSET24
LSHERRL
LSHERRM
LSHERRH
LOPERRL
LOPERRM
LOPERRH
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
DCDIM02[3:0]
DCDIM04[3:0]
DCDIM06[3:0]
DCDIM08[3:0]
DCDIM10[3:0]
DCDIM12[3:0]
DCDIM14[3:0]
DCDIM16[3:0]
DCDIM18[3:0]
DCDIM20[3:0]
DCDIM22[3:0]
DCDIM24[3:0]
DCDIM01[3:0]
DCDIM03[3:0]
DCDIM05[3:0]
DCDIM07[3:0]
DCDIM09[3:0]
DCDIM11[3:0]
DCDIM13[3:0]
DCDIM15[3:0]
DCDIM17[3:0]
DCDIM19[3:0]
DCDIM21[3:0]
DCDIM23[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
Type B
UVLO or
SWRST
DC Dimming setting for LED3 and LED4 in PWM
mode
UVLO or
SWRST
DC Dimming setting for LED5 and LED6 in PWM
mode
UVLO or
SWRST
DC Dimming setting for LED7 and LED8 in PWM
mode
UVLO or
SWRST
DC Dimming setting for LED9 and LED10 in PWM
mode
UVLO or
SWRST
DC Dimming setting for LED11 and LED12 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED13 and LED14 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED15 and LED16 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED17 and LED18 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED19 and LED20 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED21 and LED22 in
PWM mode
UVLO or
SWRST
DC Dimming setting for LED23 and LED24 in
PWM mode
UVLO or
SWRST
PWM output enable for LED1 to LED8 in PWM
mode
PWMOUTEN[7:0]
UVLO or
SWRST
PWM output enable for LED9 to LED16 in PWM
mode
PWMOUTEN[15:8]
PWMOUTEN[23:16]
DIMSET01[7:0]
DIMSET02[7:0]
DIMSET03[7:0]
DIMSET04[7:0]
DIMSET05[7:0]
DIMSET06[7:0]
DIMSET07[7:0]
DIMSET08[7:0]
DIMSET09[7:0]
DIMSET10[7:0]
DIMSET11[7:0]
DIMSET12[7:0]
DIMSET13[7:0]
DIMSET14[7:0]
DIMSET15[7:0]
DIMSET16[7:0]
DIMSET17[7:0]
DIMSET18[7:0]
DIMSET19[7:0]
DIMSET20[7:0]
DIMSET21[7:0]
DIMSET22[7:0]
DIMSET23[7:0]
DIMSET24[7:0]
LSHERR[7:0]
LSHERR[15:8]
LSHERR[23:16]
LOPERR[7:0]
UVLO or
SWRST
PWM output enable for LED17 to LED24 in PWM
mode
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED1
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED2
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED3
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED4
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED5
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED6
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED7
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED8
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED9
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED10
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED11
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED12
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED13
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED14
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED15
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED16
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED17
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED18
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED19
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED20
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED21
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED22
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED23
UVLO or
SWRST
PWM On Duty in PWM mode or DC Dimming
setting in DC mode for LED24
UVLO or
SWRST
Type A status of "LED short error" for LED1 to LED8
Type A status of "LED short error" for LED9 to LED16
Type A status of "LED short error" for LED17 to LED24
Type A status of "LED open error" for LED1 to LED8
Type A status of "LED open error" for LED9 to LED16
Type A status of "LED open error" for LED17 to LED24
UVLO or
SWRST
RO
UVLO or
SWRST
RO
UVLO or
SWRST
RO
UVLO or
SWRST
LOPERR[15:8]
LOPERR[23:16]
RO
UVLO or
SWRST
RO
UVLO or
SWRST
UVLO or TSD Error, CRC Error, WDT Error.
Type A
UVLOERR
0x51
ISETSHERR
RESERVED
RESERVED
CATHERR
TSDWERR
WDTERR
CRCERR
UVLOTSDERR
RO
0x01
Cathode short error, OCP Error status
WO: Write Only, RO: Read Only, R/W: Read and Write
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BD18333EUV-M
6. Register Map – continued
Address 0x52h to 0x5Eh (3/3)
Register
Access
Reset
Condition
update
timing
Register Name
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
initial
comments
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED01 and LED02
LHDTY0102
LHDTY0304
LHDTY0506
LHDTY0708
LHDTY0910
LHDTY1112
LHDTY1314
LHDTY1516
LHDTY1718
LHDTY1920
LHDTY2122
LHDTY2324
LIMPHOME
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
LHDTY02
LHDTY04
LHDTY06
LHDTY08
LHDTY10
LHDTY12
LHDTY14
LHDTY16
LHDTY18
LHDTY20
LHDTY22
LHDTY24
LHDTY01
LHDTY03
LHDTY05
LHDTY07
LHDTY09
LHDTY11
LHDTY13
LHDTY15
LHDTY17
LHDTY19
LHDTY21
LHDTY23
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x03
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
Type A
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED03 and LED04
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED05 and LED06
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED07 and LED08
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED09 and LED10
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED11 and LED12
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED13 and LED14
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED15 and LED16
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED17 and LED18
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED19 and LED20
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED21 and LED22
UVLO or
SWRST
Duty Setting of PWM for Stand Alone Mode for
LED23 and LED24
UVLO or
SWRST
LEXTISET2SEL
LIMPHEN
Type A LIMPHOME setting
-
-
-
-
-
-
WO: Write Only, RO: Read Only, R/W: Read and Write
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BD18333EUV-M
Description of Registers
Address 0x00h : SYNC
Setting of PWM phase synchronized for all device[Write]
initial value 0x00h
bit No
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
Name PWMFSYNCSET
PWMTIM ISETSEL SLOPEEN
DIMMODE
PWMPSYNC
DIMSTART
SWRST
Initial
value
0
0
0
0
0
0
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
These registers return to “0” automatically (PWMPSYNC and SWRST).
bit[7]
PWMFSYNCSET
This register is controls the PWM Synchronization rate.
Please set this register in initial setting.
Table 5. PWMFSYNCSET Setting
PWMFSYNCSET
PWM Synchronization
0
1
Fast Synchronization of internal clock
Slow Synchronization of internal clock
Legend:
10 ms (Max)
20 ms (Max)
Target Frequency
Slave frequency(PWMFSYNCSET = H "Slow")
Slave frequency(PWMFSYNCSET = L "Fast")
Time
Figure 31. PWM Synchronization Time Image
PWMFSYNCSET register setting is operated only when the IC is Follower mode (SYNCSET = 10b or 11b). In worst condition for
Leader (min frequency) to Follower (max frequency) or vice versa, the IC can synchronize after 10 ms (Max) for PWMFSYNCSET
= L and 20 ms (Max) for PWMFSYNCSET = H. This wait time is valid when there is no UART communication while synchronizing,
because UART commands pause clock synchronization for successful writing.
bit[6]
PWMTIM
This register is controlled as following figure. This register is read-only.
488 Hz (2.049 ms)
PWM signal
25 % duty
(around 500 μs)
PWMTIM
Figure 32. PWMTIM Image
This function can be used for synchronizing MCU (sending UART) and Device (LED Dimming).
MCU executes register polling to PWMTIM register continuously until PWMTIM is High is detected and then it will send succeeding
UART commands for LED Dimming for maximum of 16 devices. The number of devices that can be updated per successful
register poll is dependent on PWMFREQ register setting.
Consider the example in Figure 33 and Figure 34.
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Description of Registers - continued
CASE1: PWMFREQ = 0h (488 Hz), Around 2000 μs period, UART Baudrate = 1 Mbps, Max data per UART transaction is 27.
MCU wants to send data during 1 PWM cycle.
Total duration is 300 μs per UART transaction
(2000 μs to 500 μs (polling time)) / 300 μs = 4 to 5 devices (considering tolerance)
For High Sampling,
Internal PWM
PWMFREQ "00" (488 Hz)
Register
DIMSTART "High"
Register
PWMTIM
UART
R
R
R
R
R
WtoD1 WtoD2 WtoD3 WtoD4
R
R
WtoD1 WtoD2 WtoD3 WtoD4
Figure 33. High Sampling UART Access Using PWMTIM Register
For Low Sampling,
Internal PWM
PWMTIM
UART
R
R
R
WtoD1 WtoD2 WtoD3 WtoD4
Figure 34. Low Sampling UART Access Using PWMTIM Register
Where:
R – Read Command for PWMTIM
WtoDn – Write to Device (n = device number)
For the number of devices that can be written based on the PWMFREQ setting, please refer to the table below.
This is considered at typical operating frequency 18 MHz (Typ) and 1 Mbps baudrate for UART.
Table 6. PWM Frequency Setting
Number of devices can
PWMFREQ
PWM frequency (Hz)
be accessed
0
1
2
3
488
976
1952
3904
4 to 5
2 to 3
1
Cannot be used
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BD18333EUV-M
Description of Registers - continued
bit[5]
ISETSEL
Please set this register in initial setting.
Table 7. LED Current Setting
ISETSEL
0
LED Current setting
LED current is controlled by internal circuit.
ISET Short (ISETSHERR) protection detection is
disabled.
LED current is controlled by a resistor in the EXTISET1
pin. EXTISET1 Short (ISETSHERR) protection
detection is enabled. This register setting does not
release the protection status when it is already
detected.
1
bit[4]
SLOPEEN
Slope enable setting for DC Dimming Mode.
Please set this register in initial setting.
Table 8. SLOPE Setting for DC Dimming
SLOPEEN
Slope setting
Disabled
Enabled
0
1
SLOPEEN function is available only in DC Dimming mode (DIMMODE = 1).
For SLOPEEN = 0,
UART
DIMSET01
ILED01
n
m
ILED_Max * (n + 1) / 256
ILED_Max * (m + 1) / 256
Figure 35. DC Dimming When SLOPEEN “Disabled”
For SLOPEEN = 1,
UART
DIMSET01
n
m
ILED_Max * (n + 1) / 256
ILED_Max * (m + 1) / 256
PWM Freq = 488 Hz
ILED_Max = 60 mA
Slope (Typ) :
± 5 mA / 8 μs
ILED01
4.92 mA (Typ)
= (60 mA / 256) * 21
8 μs (Typ)
UART
DIMSET01
n
m
ILED_Max * (n + 1) / 256
ILED_Max * (m + 1) / 256
PWM Freq = 1952 Hz
ILED_Max = 60 mA
Slope (Typ) :
± 20 mA / 8 μs
ILED01
4.92 mA (Typ)
= (60 mA / 256) * 21
2 μs (Typ)
Figure 36. DC Dimming When SLOPEEN “Enabled”
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BD18333EUV-M
Description of Registers - continued
bit[3]
DIMMODE
Dimming mode select setting
Table 9. DIMMODE Select Setting
Normal Dimming
LIMPHOME Mode
DIMMODE
Dimming mode
PWM duty for
each channel
DC current for
each channel
PWM duty for
each channel
DC current for
each channel
0
1
PWM dimming mode DIMSETx register
DC dimming mode 100 % fixed
DCDIMx register
DIMSETx register
LHDTYx register
DCDIMx register
LHDTYx register
Please refer to DCDIMx, DIMSETx and LHDTYx for description of register. (x = 01 to 24)
bit[2]
PWMPSYNC
PWM phase synchronous setting
Table 10. PWMPSYNC Setting
PWMPSYNC
Counter for PWM Generator
Not synchronize
0
Synchronize phase of PWM
counter by this register setting
1
This function synchronizes the phase of the PWM output between multiple devices. When this function is used in a single device,
it will initialize the phase of the PWM output based on the UART access time. Please send PWMPSYNC when clock is already
synchronized (PWMFSYNC = 0).
PWMPSYNC = 1
UART
Device 1
LED1
Device 2
LED1
Enlarged
SYNC
Device 1
counter
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
LED1
Device 2
counter
0xBC
0xBC
0xBD
0xBE
0xBF
0xC0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
LED1
Figure 37. SYNC Register Setting Function
Dimming start setting
bit[1]
DIMSTART
Table 11. DIMSTART Setting
DIMSTART
0
PWM Generator for LED dimming
OFF
Start the operation of DC/DC and
Current Driver.
1
bit[0]
SWRST
Software reset setting
Please set this register when you want to reset digital circuit.
Table 12. SWRST Description
SWRST
0
Reset
Normal
Synchronous reset for digital circuit
(Automatically returns to “0” )
1
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BD18333EUV-M
Description of Registers - continued
Address 0x01h: SYSSET1
system setting1
[Read/Write]
initial value 0x00h
bit[1] bit[0]
SYNCSET[1:0]
bit No
Name
bit[7]
FAILBCNT
0
bit[6]
FAILBEN
0
bit[5]
bit[4]
RESERVED
0
bit[3]
0
bit[2]
PWMFSYNC
0
Initial value
0
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
bit[7]
bit[6]
FAILBCNT
FAILBEN
Please set this register in initial setting.
Table 13. FAILBEN and FAILBCNT Description
FAILBEN
Operation
0
1
FAILB output is controlled by error status.
FAILB output is controlled by FAILBCNT.
FAILB
All error signal
FAILBCNT register
FAILBEN register
0
1
Figure 38. FAILB Controlled Circuit Image
bit[5:3]
RESERVED
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BD18333EUV-M
Description of Registers - continued
bit[2]
PWMFSYNC
This is a read-only register. When device is set as Follower (SYNCSET = 10b or 11b) it monitors if the internal
clock of the Follower device is synchronized to the Leader device. It synchronizes internal clock using the
PWMIN input from Leader device. When PWMIN input clock is stable and no UART communication during
synchronization, Follower device can synchronize around 10 ms (Max) for PWMFSYNC = “Low” and 20 ms
(Max) for PWMFSYNC = “High”. In the event that PWMIN frequency changes, PWMFSYNC becomes High
until stable condition is achieved.
When device is set as Leader, this register is fixed to “0”. When device is set as Follower and there is no
PWMIN input, this register is “High” until PWMIN input is present and clock is synchronized.
Table 14. PWMFSYNC Description
PWMFSYNC
Operation
Internal clock is stable
Internal clock is not stable
0
1
#DUT1
BD18333
24ch
Linear
Driver
PWMIN PWMOUT
RingOSC
SYNCSET="00"
Figure 39. SYNCSET setting for Stand Alone
#DUT1
#DUT2
#DUT3
#DUT4
BD18333
BD18333
BD18333
BD18333
24ch
Linear
Driver
24ch
Linear
Driver
24ch
Linear
Driver
24ch
Linear
Driver
PWMIN PWMOUT
PWMIN
PWMIN PWMOUT
PWMIN PWMOUT
PWMOUT
RingOSC
RingOSC
RingOSC
RingOSC
SYNCSET="01"
SYNCSET="11"
SYNCSET="11"
SYNCSET="10"
Figure 40. SYNCSET setting for multiple connection
bit[1:0]
SYNCSET
Use this register to select if device is Stand Alone, Leader or Follower.
Please set this register in initial setting.
Table 15. PWMIN/PWMOUT Setting
PWM
SYNCSET[1:0] PWMIN Port
PWMOUT Port
Comment
adjusting
00
01
10
11
Disable
Disable
Enable
Enable
Disable
Disable
Stand Alone
Leader device
(Output PWM frequency from the
PWMOUT pin)
Enable
(PWM output)
Disable
Enable
Enable
Disable
Follower device
Follower device
(Output PWM frequency from the
PWMOUT pin)
Enable
(PWM output)
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BD18333EUV-M
Description of Registers - continued
Address 0x03h: SYSSET3
system setting3
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
ERRMASK[3:0]
0
bit[5]
bit[4]
0
bit[3]
0
bit[2]
bit[1]
bit[0]
RESERVED
0
0
0
0
0
Update: Immediately
bit [7:4] ERRMASK
Configurable mask time for “LED open protection”. If the protection detection time is more than this value,
the corresponding protection is detected. Protection is detected in status register and FAILB output after 1
or 2 clock (1.125 MHz) cycles. Please set this register in initial setting.
Table 16. ERRMASK Setting
ERRMASK[3:0]
0x0h to 0x1h
0x2h
Mask time [μs]
1.8
3.6
0x3h
5.3
0x4h
7.1
0x5h
8.9
0x6h
0x7h
0x8h
0x9h
0xAh
0xBh
0xCh
0xDh
10.7
12.4
14.2
16.0
17.8
19.6
21.3
23.1
24.9
26.7
0xEh
0xFh
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Description of Registers – continued
Address 0x04h: LEDENL
LED channel enable1
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
0
bit[2]
bit[1]
bit[0]
LEDEN[7:0]
0
0
0
0
0
0
0
Update: immediately
Address 0x05h: LEDENM
LED channel enable2
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
bit[4]
0
bit[3]
LEDEN[15:8]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
0
Update: immediately
Address 0x06h: LEDENH
LED channel enable3
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
bit[4]
LEDEN[23:16]
0
bit[3]
0
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
Update: immediately
These data in register is updated to the newest data immediately when the new data is written.
This registers control enable/disable each LED channel. For enable control, the LED Channel outputs according to the setting of
PWM Duty Setting. For disable control, LED Channel output is OFF regardless of the PWM Duty Setting, protection and DC/DC
feedback is disabled for the controlled channel.
Table 17. LED Channel Enable Setting (x = 0 to 23)
LEDEN[x]
Operation
0
1
“LEDx+1” is disabled.
“LEDx+1” is enabled.
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Description of Registers – continued
Address 0x07h: SYSSET4
system setting4
[Read/Write]
bit[2]
CRCERLAT
0
initial value 0x00h
bit No
Name
bit[7]
-
bit[6]
ISETLAT
0
bit[5]
bit[4]
bit[3]
RESERVED
0
bit[1]
bit[0]
LOPLAT
0
AUTOOFF ERRCLR
LSHLAT
0
Initial value
0
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
bit[6]
ISETLAT
Please set this register in initial setting.
Table 18. ISETLAT Setting
Operation
Normal (Auto-release)
ISETLAT
0
Enable latch condition for the EXTISET1 pin
and the EXTISET2 pin short detection.
Outputs based on ISETSHCNT[1:0] setting are
latched until writing ERRCLR = 1. Please refer
detailed information on ISETCNT register
description.
1
bit[5]
AUTOOFF
Please set this register in initial setting.
Table 19. AUTOOFF Setting
operation
Normal
AUTOOFF
0
Target channel is disabled automatically when
“LED open error” is detected.
1
bit[4]
ERRCLR
Table 20. ERRCLR Setting
operation
ERRCLR
0
Normal
This register clears error status registers the
EXTISET1 pin and the EXTISET2 pin short detection
(ISETSHERR when ISETLAT = H), LED open
protection (LOPERR when LOPLAT = H), UART CRC
error (CRCERR when CRCERLAT = H), UVLO
protection (UVLOTSDERR), Cathode short protection
(CATHERR) and UART WDT protection (WDTERR).
This register returns to “0” automatically.
1
bit[3]
bit[2]
RESERVED
CRCERLAT
Please set this register in initial setting.
Table 21. CRCERLAT Setting
operation
Normal (Auto-release)
CRCERLAT
0
Enable latch condition for UART CRC
detection. This setting latches detection in the
FAILB pin output “Low” and “CRC error”
status register (CRCERR) until writing “1” in
ERRCLR register.
1
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Description of Registers – continued
bit[1]
LSHLAT
Please set this register in initial setting.
Table 22. LSHLAT Setting
AUTOOFF
0
LSHLAT
0
LED Channel Control
Operation
FAILB output (Low) and “LED short
error” status register (LSHERR[x])
returns to normal condition after
error isreleased.
Must set register LEDEN[x] = 0 via
UART to disable target channel
0
1
1
*
FAILB output (Low) and “LED short
error” status register (LSHERR[x])
are latched until writing ‘1’ in
ERRCLR register.
LEDEN[x] = 0 automatically after
detection
x: error channel number -1
bit[0]
LOPLAT
Please set this register in initial setting.
Table 23. LOPLAT Setting
AUTOOFF
0
LOPLAT
0
LED Channel Control
Operation
Normal (auto-release)
Enable latch condition for LED
Open detection. This setting latches
the detection in the FAILB pin
output “Low” and “LED open error”
status register (LOPERR[x]) are
latched until writing “1” in ERRCLR
register.
The FAILB pin output and LOPERR
status register is released
automatically with LED Channel
disable.
Must set register LEDEN[x] = 0 via
UART to disable target channel
0
1
1
*
LEDEN[x] = 0 automatically after
detection
x: error channel number -1
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Description of Registers – continued
Address 0x08h: SYSSET5
ERROR output mask setting register
[Read/Write]
bit[2]
initial value 0x00h
bit No
Name
Initial
value
bit[7]
-
bit[6]
-
bit[5]
bit[4]
bit[3]
CATHEN
bit[1]
bit[0]
RESERVED RESERVED
TSDWEN
WDTEN
LOPEN
0
0
0
0
0
0
0
0
Update: immediately
These data in register is updated to the newest data immediately when the new data is written.
CATHEN returns “0” automatically.
Bit[5:4]
Bit[3]
RESERVED
CATHEN
Please set this register in initial setting.
Table 24. CATHEN Register
CATHEN
0
Operation
Cathode short protection is disabled.
Cathode short protection is enabled. Enable
this function at initialization and the device
monitors “Cathode short error” after 10 ms. If it
detects the error, it sets CATHERR status
register and the FAILB pin output “Low”. This
register automatically returns “0” after
monitoring. CATHERR status register is
latched automatically. When CATHEN = 1,
“LED open protection” is disabled.
1
Bit[2]
TSDWEN
Please set this register in initial setting.
Table 25. TSDWEN Register
TSDWEN
0
Operation
TSD Warning protection is disabled.
TSD Warning protection is enabled. If it
detects error, It sets TSDW status register and
the FAILB pin output “Low”. This register
setting does not release the protection status
when it is already detected.
1
bit[1]
WDTEN
Please set this register in initial setting.
Table 26. WDTEN Register
WDTEN
0
operation
Watch Dog Timer for UART is disabled.
Watch Dog Timer for UART is enabled. If it
detects disconnection over 100 ms (Typ), It
sets WDTERR status register and the FAILB
pin output “Low”. This register setting does not
release the protection status when it is already
detected.
1
bit[0]
LOPEN
Please set this register in initial setting.
Table 27. LOPEN Register
LOPEN
0
operation
LED open protection is disabled.
LED open protection is enabled. If it detects
error, It sets LOPERR status register and the
FAILB pin output “Low”. This register setting
does not release the protection status when it
is already detected.
1
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Description of Registers – continued
Address 0x09h: LEDSHENL ERROR output mask time setting register
[Read/Write]
initial value 0x00h
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
LSHEN[7:0]
Initial value
0
0
0
0
0
0
0
0
Update: immediately
Address 0x0Ah: LEDSHENH ERROR output mask time setting register
[Read/Write]
initial value 0x00h
bit No
Name
bit[7]
-
bit[6]
-
bit[5]
ISETSHCNT[1:0]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
LSHEN[11:8]
Initial value
0
0
0
0
0
0
0
0
Update: immediately
These registers are updated to the newest data immediately when the new data is written.
Addr 0x09h bit[7:0], Addr 0x0Ah bit[3:0] LSHEN[11:0]
This register control “LED short error” protection. This register is assigned each 2 channel.
This only affect protection detection and will not release the protection when already detected. This is for
latch conditions.
Table 28. LSHEN Enable Setting
LSHEN[n]
n=0
Operation
LED1 and LED2 channel short protection enable
LED3 and LED4 channel short protection enable
LED5 and LED6 channel short protection enable
LED7 and LED8 channel short protection enable
LED9 and LED10 channel short protection enable
LED11 and LED12 channel short protection enable
LED13 and LED14 channel short protection enable
LED15 and LED16 channel short protection enable
LED17 and LED18 channel short protection enable
LED19 and LED20 channel short protection enable
LED21 and LED22 channel short protection enable
LED23 and LED24 channel short protection enable
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10
n=11
Table 29. LSHEN Register (n = 0 to 11)
Operation
LSHEN[n]
0
1
LED Short protection is disabled for LEDn
LED Short protection is enabled for LEDn
Addr 0x0Ah bit[5:4] ISETSHCNT[1:0]
This register is the output control setting for ISETSH1 and ISETSH2 detection. Please set this register in
initial setting.
Table 30. ISETSHCNT Register Setting
ISETSEL
Register
ISETSHCNT
Register
Status
register
EXTISET1 Selector
(ISETSEL)
Internal ISET
EXTISET2 Selector
(LEXTISET2SEL)
FAILB
LEDEN
0
1
1
1
1
-
-
-
0
1
2
3
H
H
H
L
L
L
-
L
-
-
-
L(Note 2)
L(Note 1)
Not used
This table shows the state of the outputs when EXTISET1 and EXTISET 2 short is detected. "-" not affected
(Note 1) When detected, output state is latched until ERRCLR is sent. This function is not dependent on ISETLAT setting.
For Latch function via ISETLAT setting, output conditions corresponding to ISETSHCNT setting are latched when protection is detected. Latched condition
is cleared by system reset or sending ERRCLR.
(Note 2) When IC is at LIMPHOME mode and ISET Short is detected, change ISET selector from external (EXTISET1/EXTISET2) to internal. This function is not
dependent on ISETLAT setting. Latched condition is cleared by system reset or sending ERRCLR.
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Description of Registers – continued
Address 0x0B: LEDSHTH0102
LED Short Detection Voltage for LED1 and LED2 [Read / Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
0
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
LEDSHTH0102[7:0]
0
0
0
0
0
0
0
Update:immediately
These register data in updated to the newest data immediately when the new data is written.
Please set this register in initial setting.
Table 31. LED Short Detection Voltage
LEDSHTH0102
Detection voltage (VLEDSH) [V]
0 to 15
16
0.93
1.00
17
1.05
-
-
n
(15 / 256) x (n + 1)
-
-
251
252
253
254
255
14.77
14.82
14.88
14.94
15.00
LEDx
Current
Driver
125 mA (Max)
LGND
FAILB
LED Short
Control
Logic
FAIL
VLEDSH
LED OPEN
0.3 V
Figure 41. LED Pin Protection Circuit Image
Address 0x0C to 0x16: LEDSHTHx (x = 0304 to 2324)
This register is used to make LED Short detection voltage setting for LED3 to LED24. The setting procedure is the same as
that for LED1 with Address set to 0x0B.
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Description of Registers – continued
Address 0x17h: DENVOLT
DEN Threshold voltage setting register
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
PWMFREQ[1:0]
0
bit[4]
bit[3]
0
bit[2]
DENVOLT[3:0]
0
bit[1]
bit[0]
RESERVED
0
0
0
0
0
Update: immediately
These data in register is updated to the newest data immediately when the new data is written.
bit[7:0]
bit[5:4]
RESERVED
PWMFREQ[1:0]
This register setting determines the LED output frequency.
This setting is also applicable to PWMTIM.
Table 32. PWM Frequency Setting
PWMFREQ[1:0]
0x0h
LED PWM Dimming Frequency(Note 1)
488 Hz (Typ)
976 Hz (Typ)
1952 Hz (Typ)
3904 Hz (Typ)
0x1h
0x2h
0x3h
(Note 1) The frequency indicated above is based on 18 MHz (Typ) system clock. It may vary depending on internal clock frequency.
bit[3:0]
DENVOLT[3:0]
When VIN < VIN_DEN , IC cannot detect LED open detection (LEDOP).
VIN_DEN can be defined by setting register and set by the following table.
Table 33. DENVOLT Register
VIN_DEN detection
DENVOLT[3:0]
voltage [V]
0x0h
0x1h
0x2h
0x3h
0x4h
0x5h
0x6h
0x7h
0x8h
0x9h
0xAh
0xBh
0xCh
0xDh
0xEh
0xFh
4.5
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
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Description of Registers – continued
Address 0x18h: PWMDLY0102
PWM delay setting
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
0
bit[4]
bit[3]
0
bit[2]
bit[1]
bit[0]
PWMDLY02
PWMDLY01
0
0
0
0
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
Please set this register in initial setting.
This register is used to set phase shift/delay width for PWM light modulation in a total of 4-bit.
Table 34. PWMDLY Register
PWMDLY01[3:0]
LED Delay Width [µs]
PWMDLY02[3:0]
0x0h
0x1h
0x2h
0x3h
0x4h
0x5h
0x6h
0x7h
0x8h
0x9h
0xAh
0xBh
0xCh
0xDh
0xEh
0xFh
24
32
40
48
56
64
72
80
88
96
104
112
120
128
136
144
Address 0x19h to 0x23h: PWMDLYx (x = 0304 to 2324)
This register is used make setting for PWM delay width setting for LED3 to LED24. The setting procedure is the same as that for
LED1 with Address set to 0x18h.
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Description of Registers – continued
Address 0x24h: DCDIM0102
DC Current Setting for CH1,2
[Read/Write]
initial value 0xFFh
bit No
Name
Initial value
bit[7]
bit[6]
DCDIM02[3:0]
1
bit[5]
bit[4]
bit[3]
1
bit[2]
DCDIM01[3:0]
1
bit[1]
bit[0]
1
1
1
1
1
Update: immediately
The data in register is updated to the newest data immediately when the new data is written.
Please set this register in initial setting.
Table 35. DCDIM Register
DCDIM01[3:0]
DCDIM02[3:0]
LED current setting [mA]
0x0h
0x1h
0x2h
0x3h
0x4h
0x5h
0x6h
0x7h
0x8h
0x9h
0xAh
0xBh
0xCh
0xDh
0xEh
0xFh
3.75
7.50
11.25
15.00
18.75
22.50
26.25
30.00
33.75
37.50
41.25
45.00
48.75
52.50
56.25
60.00
Address 0x25h to 0x2Fh: DCDIMx (x = 0304 to 2324)
This register is used to make DC current setting for LED3 to LED24. The setting procedure is the same as that for LED1 with
Address set to 0x24h.
The data in register is updated to the newest data immediately when the new data is written.
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Description of Registers – continued
Address 0x30h: PWMOUTL
PWM output enable setting 1
[Read/Write]
initial value 0x00h
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
PWMOUTEN[7:0]
bit[3]
bit[2]
bit[1]
bit[0]
Initial value
0
0
0
0
0
0
0
0
Update: PWM
Address 0x31h: PWMOUTM
PWM output enable setting 2
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
0
bit[5]
bit[4]
PWMOUTEN[15:8]
0
bit[3]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
Update: PWM
Address 0x32h: PWMOUTH
PWM output enable setting 3
[Read/Write]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
0
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
PWMOUTEN[23:16]
0
0
0
0
0
0
0
Update: PWM
Address 0x33h: DIMSET01
PWM duty or DC dimming setting for LED1
[Read/Write]
initial value 0x00h
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
DIMSET01[7:0]
bit[3]
bit[2]
bit[1]
bit[0]
Initial value
0
0
0
0
0
0
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
This register is used to make setting of pulse duty for PWM light modulation in a total of 8-bits in PWM dimming mode.
Table 36. DIMSET Register
DIMMODE
PWMOUTEN[0]
0
DIMSET01[7:0]
0x00h to 0xFFh
0x00h
PWM Duty
0.0 %
0.4 %
DC current
0x01h
0.8 %
0x02h
0x03h
-
xx
-
1.2 %
1.6 %
-
DCDIM01[3:0] register
setting
0
1
(xx + 1) / 256
-
0xFEh
99.6 %
Normally set to
High (Duty 100 %)
0 %
0xFFh
0
1
0x00h to 0xFFh
0.23 mA
0.23 mA
0.47 mA
0.70 mA
0.94 mA
-
0x00h
0x01h
0x02h
0x03h
-
1
100 %
xx
-
(xx + 1) / 256 x 60 mA
-
0xFEh
0xFFh
59.77 mA
60.00 mA
Address 0x34h to 0x4Ah: DIMSETx (x = 02 to 24)
This register is used to make setting of PWM pulse width for LED2 to LED24. The setting procedure is the same as that for LED1
with Address set to 0x33h.
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Description of Registers – continued
Address 0x4B: LSHERRL
LED1 to LED8 pin short error status
[Read]
bit[2]
initial value 0x00h
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
0
bit[1]
bit[0]
0
LSHERR[7:0]
Initial value
0
0
0
0
0
0
Update:
-
Address 0x4C: LSHERRM
LED9 to LED16 pin short errors status
[Read]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
bit[4]
LSHERR[15:8]
0
bit[3]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
0
Update:
-
Address 0x4D: LSHERRH
LED17 to LED24 pin short error status
[Read]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
bit[5]
bit[4]
LSHERR[23:16]
0
bit[3]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
0
Update:
-
The register data is updated to the newest data immediately when the data (“LED short error”) is detected.
Table 37. LED Short Error Status (n = 1 to 24)
LSHERR[n-1]
status
0
1
Normal
Detect error(Note 1)
(Note 1) How to return “0” for status register.
AUTOOFF = 0, LSHLAT = 0 : (n = 1 to 24)
Please set LEDEN[n-1] = 0 or PWMOUTEN[n-1] = 0 to release error channel and status register.
AUTOOFF = 0, LSHLAT = 1 : (n = 1 to 24)
Please set LEDEN[n-1] = 0 or PWMOUTEN[n-1] = 0 to release error channel.
Please set ERRCLR = 1 to clear status register
AUTOOFF = 1, LSHLAT = 0/1 : (n = 1 to 24)
Please set ERRCLR = 1 to clear status register
(Operates LEDEN[n-1] = 0 automatically)
Please refer timing chart of error control.
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Description of Registers – continued
Address 0x4Eh: LOPERRL
LED1 to LED8 open error status
[Read]
bit[2]
initial value 0x00h
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[1]
bit[0]
LOPERR[7:0]
Initial value
0
0
0
0
0
0
0
0
Update:
-
-
-
Address 0x4Fh: LOPERRM
LED9 to LED16 open error status
[Read]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
0
bit[5]
bit[4]
LOPERR[15:8]
0
bit[3]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
Update:
Address 0x50h: LOPERRH
LED17 to LED24 open error status
[Read]
initial value 0x00h
bit No
Name
Initial value
bit[7]
bit[6]
0
bit[5]
bit[4]
LOPERR[23:16]
0
bit[3]
bit[2]
bit[1]
bit[0]
0
0
0
0
0
0
Update:
The register data is updated to the newest data immediately when the data (“LED open error”) is detected.
Table 38. LOPERR Register (n = 1 to 24)
LOPERR[n-1]
status
0
1
Normal
Detect error(Note 1)
(Note 1) How to return “0” for status register.
AUTOOFF = 0, LOPLAT = 0: (n = 1 to 24)
Set LEDEN[n-1] = 0 or PWMOUTEN[n-1] = 0 to release error channel and status register.
AUTOOFF = 0, LOPLAT = 1: (n = 1 to 24)
Set LEDEN[n-1] = 0 or PWMOUTEN[n-1] = 0 to release error channel.
Set ERRCLR = 1 to clear status register.
AUTOOFF = 1, LOPLAT = 0/1: (n = 1 to 24)
Set ERRCLR = 1 to clear status register.
(Operates LEDEN[n-1] = 0 automatically.)
Please refer timing chart of error control.
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Description of Registers – continued
Address 0x51h: UVLOERR
CRC and UVLO,TSD error status
[Read]
bit[2]
WDTERR
initial value 0x01h
bit[0]
bit No
Name
Initial
value
bit[7]
ISETSHERR
bit[6]
RESERVED
bit[5]
bit[4]
bit[3]
bit[1]
CATHERR TSDWERR
CRCERR
UVLOTSDERR
0
0
0
0
0
0
0
1
Update:
-
bit[7]
ISETSHERR
The register data is updated to the newest data immediately when the data (“ISET short Error”) is detected.
Table 39. ISETSHERR Register Setting
ISETSHERR
0
Status
Normal (or ISETSEL = 0)
Detect ISET Short Error (under 4.7 kΩ)
when ISETSEL = 1
1
Table 40. EXTISET Pin Short Detection Setting
ISETSEL
0
ISETLAT
Release condition
*
Internal ISET setting. This protection is not available.
ISETSHERR error condition is released when protection is released.
When “ISETSHCNT = 2”, status register is latched and can be
released when “ERRCLR = 1” is set.
1
1
0
1
Status condition is released when “ERRCLR = 1” is set
bit[6:5]
bit[4]
RESERVED
CATHERR
The register data is updated to the newest data immediately when the data (“Cathode Short Error ”) is detected.
Table 41. CATHERR Register
CATHERR
Status
0
1
Normal
Detect Cathode Short Error(Note 1)
(Note 1) Release “CATHERR” protection by ERRCLR = 1.
CATHEN automatically return “0” after monitoring “cathode short error”.
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Description of Registers – continued
Address 0x51h: UVLOERR – continued
bit[3]
TSDW
The register data is updated to the newest data immediately when the data (“TSD warning”) is detected.
Table 42. TSDW Register
TSDW
Status
0
1
Normal
Detect TSD warning
Table 43. TSD Warning Release Condition
Status
TSDWEN
It is not available to control status and FAILB
output.
TSD warning protection is enabled.
0
1
bit[2]
WDTERR
The register data is updated to the newest data immediately when the data (“UART WDT Error”) is detected.
Table 44. WDTERR Register
WDTERR
Status
0
1
Normal
Detect UART WDT(Note 1)
(Note 1) Release “WDTERR” protection by ERRCLR = 1.
bit[1]
CRCERR
The register data is updated to the newest data immediately when the data (“CRC error”) is detected.
Table 45. CRCERR Register
CRCERR
Status
0
1
Normal
Detect CRC Error until CRC OK.
Table 46. CRC Error Release Condition
Release condition
CRCERLAT
0
CRC OK condition (for Write command)
releases the status register and FAIL output.
Status Register is released when “ERRCLR = 1”
is set.
1
bit[0]
UVLOTSDERR
The register data is updated to the newest data immediately when the data (“UVLO or TSD error”) is detected.
Table 47. UVLOTSDERR Register
UVLOTSDERR
Status
0
1
Normal
Detect UVLO or TSD(Note 2)
(Note 2) When EN = L, this register is initialized to H. SWRST does not initialize this status register.
UVLOTSDERR is released if “ERRCLR = 1” is set.
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Description of Registers – continued
Address 0x52h: LHDTY0102 LIMPHOME2 PWM duty setting for LED1 and LED2
[Read/Write]
bit[2]
LHDTY01
1 1
initial value 0xFFh
bit No
Name
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[1]
bit[0]
LHDTY02
Initial value
1
1
1
1
1
1
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
This register is used to make setting of pulse duty for PWM light modulation in a total of 4-bits in PWM dimming mode.
Table 48. PWM Duty Setting at LIMPHOME2 (x = 01 to 02)
LHDTYx
PWM Duty Setting for each CH
DC Dimming Setting for each CH
0x0h
0x1h
0x2h
0x3h
0x4h
0x5h
0x6h
0x7h
0x8h
0x9h
0xAh
0xBh
0xCh
0xDh
0xEh
0xFh
OFF
5 %
10 %
15 %
20 %
25 %
30 %
40 %
45 %
50 %
55 %
60 %
70 %
80 %
90 %
100 %
DC Dimming is based on DCDIMx[3:0]
register (DIMMODE = 0) or DIMSETx[7:0]
register (DIMMODE = 1)
Address 0x53h to 0x5Dh: LHDTYx (x = 0304 to 2324)
This register is used for PWM duty setting for LED3 to LED24 during LIMPHOME mode. The setting procedure is the same as
LED1 and LED2 with address set to 0x52h.
Address 0x5Eh: LIMPHOME
[Read/Write]
bit[3] bit[2]
initial value 0x03h
bit No
Name
bit[7]
-
bit[6]
-
0
bit[5]
-
0
bit[4]
-
0
bit[1]
bit[0]
-
-
LEXTISET2SEL
1
LIMPHEN
1
Initial value
0
0
0
Update: Immediate
bit[1]
LEXTISET2SEL
This register is used to select the source for LED current setting operation during LIMPHOME.
Table 49. LED Current Setting Operation at LIMPHOME2
LEXTISET2SEL
0
Operation
LED current setting operation is based on ISETSEL
register. It selects either internal current setting or
using the EXTISET1 pin.
LED current setting operated using the EXTISET2 pin.
This is operational only during LIMPHOME mode.
1
bit[0]
LIMPHEN
This register is used to enable LIMPHOME Mode detection.
Table 50. LIMPHOME2 Enable Setting
LIMPHEN
0
Operation
LIMP HOME Detection is disabled
Enter LIMPHOME mode after 1.0 s of no UART
access. Refer to LIMPHOME sequence.
1
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Timing Chart
Dimming
1.1 PWM Delay Setting
Example of PWM behavior for LED1 is shown as follows.
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting (n = 01 to 24)
DIMSTART = 1
DIMMODE = 0
(
⁄
)
PWMDLYn[3:0]: refer to 푃푀푊 ꢃ푒푙푎푦 ꢇ푖푚푒= ꢐ4 휇푠 ꢙ 푃푊푀ꢃꢗꢘꢈ[ꢓ: ꢂ] × ꢁ8 푀ꢠ푧 ꢁ44 (x = 01 to 24)
Figure 43.
DIMSETn[7:0] = 0x7Fh (50 % Duty)
Other: normal dimming setting
・ Internal signal
CLKDIV144: internal clock (18 MHz / 144)
PWM base timing: base timing of PWM dimming
1.1.1
PWM Delay Setting
Enlarged view
ILED1
(PWMDLY01[3:0] = 0x0h)
Pin
ILED2
(PWMDLY02[3:0] = 0x1h)
ILED3
(PWMDLY03[3:0] = 0x2h)
ILED23
(PWMDLY23[3:0] = 0xEh)
ILED24
(PWMDLY24[3:0] = 0xFh)
Internal
Signal
PWM base timing
Figure 422. PWM Delay Setting
1.1.2
PWM Delay Setting (Enlarged View)
24 μs (Typ)
ILED1
(PWMDLY01[3:0] = 0x0h)
32 μs (Typ)
ILED2
(PWMDLY02[3:0] = 0x1h)
Pin
ILED3
40 μs (Typ)
(PWMDLY03[3:0] = 0x2h)
ILED23
136 μs (Typ)
144 μs (Typ)
(PWMDLY23[3:0] = 0xEh)
ILED24
(PWMDLY24[3:0] = 0xFh)
CLKDIV144
Internal
Signal
PWM base timing
(
⁄
)
푃푀푊 ꢃ푒푙푎푦 ꢇ푖푚푒 = ꢐ4 휇푠 ꢙ 푃푊푀ꢃꢗꢘꢈ[ꢓ: ꢂ] × ꢁ8 푀ꢠ푧 ꢁ44
(x = 01 to 24)
Figure 433. PWM Delay Setting (Enlarged View)
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1. Dimming – continued
1.2 PWM Diming
Example：
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting (n = 01 to 24)
DIMSTART = 1
DIMMODE = 0
SYNCSET = 1
PWMDLYn[3:0] = 0x0Fh
PWMOUTEN[23:0] = 0x000000h
DIMSETn[7:0] = 0x7Fh (50 % Duty)
Other: normal dimming setting
・ Internal signal
pwmouten_buf:
dimset01_buf:
pwmouten_cnt[0]:
PWM output enable setting. This signal is updated at PWM base timing.
PWM duty setting. This signal is updated at PWM base timing.
PWM output enable setting. This signal is updated with a delay of the PWMDLY01
setting from PWM base timing.
dimset01_cont:
PWM duty setting. This signal is updated with a delay of the PWMDLY01 setting from
PWM base timing.
4
write PWMOUTEN[0] = 1,
DIMSET01[7:0] = 0x7Fh
write PWMOUTEN[1] = 1,
DIMSET02[7:0] = 0x7Fh
write PWMOUTEN[2] = 1,
DIMSET03[7:0] = 0x7Fh
PWMIN
Pin
1
ILED1
ILED2
ILED3
PWM base timing
PWMOUTEN[0]
1
DIMSET01[7:0]
0x7Fh
2
Internal
Signal
pwmounten_buf[0]
dimset01_buf
1
0x7Fh
3
1
pwmouten_cont[0]
0x7Fh
Figure 44. Dimming Setting in DIMMODE = 0
This example shows PWM Dimming control, DIMMODE = 0 (PWM Dimming).
①
②
③
④
Send PWM settings (PWMOUTEN[0], DIMSET01[7:0], via UART) and other Settings like DIMMODE, PWMDLY01[3:0]
and DCDIM01[3:0] are updated during initialization.
At internal base PWM rising edge timing (for Leader) or PWMIN rising edge timing (for Follower), transfer data
(PWMOUTEN, DIMSET) to buffer to prevent data from changing every base PWM cycles.
After PWMDLY01[3:0] setting, transfer data (PWMOUTEN[0], DIMSET01[7:0]) to start PWM output control. Control
PWM duty based on DIMSET01[7:0] register value and DC dimming based on DCDIM01[3:0] register value.
Set LED2 = ON (PWMOUTEN[1], DIMSET02[7:0], via UART) and LED3 = ON (PWMOUTEN[2], DIMSET03[7:0], via
UART) output at next PWMIN, after writing the corresponding settings.
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1. Dimming – continued
1.3 PWM Dimming (Duty = 100 %)
Examples below show PWM Dimming control, DIMMODE = 0 (PWM Dimming) and duty setting is 100 % (DIMSET = 0xFFh)
while having different Leader vs Follower frequency. The timing of the LED output generation is dependent on the timing of
the rising edge of PWMIN input. The internal frequency of an Follower device is dependent on PWMIN input as reference
signal. PWMIN input in this example is from a Leader device. Faster frequency of Leader device produces faster PWMIN input
to Follower device and vice versa.
During PWM synchronization, the Follower device adjust internal clock to be the same as Leader device. In the example below,
Leader device has equal frequency vs Follower Device.
Example：
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting: (n = 01 to 24)
SYNCSET = 1 (Leader), SYNCSET = 2 (Follower)
DIMSTART = 1
DIMMODE = 0
DIMSETn[7:0] = 0xFFh (100 % Duty)
・ Internal signal
PWM counter: this counter generates the PWM control for ILED current.
1
2
WR to LED1
WR to LED1
UART(RX)
Pin
Leader Device
PWMOUT
Follower Device
PWMIN
ILED1
Typical on time of LED out with 100 % duty
Internal
Signals
pwm counter
Figure 45. Dimming at 100 % Duty Setting and Leader device and Follower device has typical frequency
In the example below, Leader device has faster frequency vs Follower Device that resulted to faster PWMIN input. In the
Follower device, the timing of LED output is dependent on a faster PWMIN input, the internal counter is restarted in each rising
edge of PWMIN signal resulting to the total length of LED output that is shorter than typical.
Example：
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting: (n = 01 to 24)
SYNCSET = 1 (Leader), SYNCSET = 2 (Follower)
DIMSTART = 1
DIMMODE = 0
DIMSETn[7:0] = 0xFFh (100 % Duty)
・ Internal signals:
PWM counter: this counter generates the PWM control for ILED current.
1
2
WR to LED1
WR to LED1
UART(RX)
Leader Device
PWMOUT
Pin
Follower Device
PWMIN
ILED1
Short on time of LED out with 100 % duty
Internal
Signals
pwm counter
Figure 46. Dimming at 100 % Duty Setting and Leader Device has Higher Frequency vs Follower Device
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1.3 PWM Dimming (Duty = 100 %) – continued
In the example below, Leader device has slower frequency vs Follower Device that resulted to slower PWMIN input. In the
Follower device, the timing of LED output is dependent on a slower PWMIN input, internal counter for the 100 % duty finishes
earlier then wait for PWMIN rising edge before restarting resulting to LED output turning off then the LED output continues
after receiving PWMIN input.
Example：
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting: (n = 01 to 24)
SYNCSET = 1 (Leader), SYNCSET = 2 (Follower)
DIMSTART = 1
DIMMODE = 0
DIMSETn[7:0] = 0xFFh (100 % Duty)
・ Internal signals:
PWM counter: this counter generates the PWM control for ILED current.
1
2
WR to LED1
WR to LED1
UART (RX)
Pin
Leader Device
PWMOUT
Follower Device
PWMIN
ILED1
On time of LED out with 100 % duty with faster internal clock
Intenal
pwm counter
Signals
Figure 47. Dimming at 100 % Duty Setting and Leader Device has Lower Frequency vs Follower Device
All UART commands in the figures above are sent with the same timing to observe the length of the LED output. The sequence
is as follows,
①
Send DIMSETn[7:0] = 0xFFh (100 % Duty ) via UART. At PWMIN rising edge timing for Follower device, Start LED output
control based on DIMSETn[7:0] setting.
②
Send DIMSETn[7:0] = 0x00h (0 % Duty ) via UART. At PWMIN rising edge timing for Follower device, Start LED output
control based on DIMSETn[7:0] setting.
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1. Diming – continued
1.4
PWMFREQ Setting
Example : (n = 01 to 24)
Register setting
DIMMODE = 0
PWMOUTEN[23:0] = 0xFFFFFFh
DIMSETn[7:0] = 0x7Fh (50 % Duty)
Other: normal diming setting
ILEDx: LEDx pin current (x = 1 to 24)
DIMSTART = H
UART (RX)
Pin
ILED1
DIMSTART register
Internal
Signals
Internal PWM
PWMTIM register
PWM Dimming
PWM Dimming
PWM Dimming
PWM Dimming
Figure 48. PWMFREQ = 0
Figure 49. PWMFREQ = 1
Figure 50. PWMFREQ = 2
Figure 51. PWMFREQ = 3
DIMSTART = H
DIMSTART = H
DIMSTART = H
UART (RX)
Pin
ILED1
DIMSTART register
Internal
Signals
Internal PWM
PWMTIM register
UART (RX)
Pin
ILED1
DIMSTART register
Internal
Signals
Internal PWM
PWMTIM register
UART (RX)
Pin
ILED1
DIMSTART register
Internal
Signals
Internal PWM
PWMTIM register
This example shows PWM Dimming control using different PWMFREQ setting.
In the timing diagram above, PWMFREQ setting must be configured before DIMSTART = H.
After DIMSTART “L to H” will be soft start and dimming starts at succeeding internal PWM cycles.
(1)
(2)
(3)
(4)
PWMFREQ = 0, PWM Dimming frequency is 488 Hz (Typ).
PWMFREQ = 1, PWM Dimming frequency is 976 Hz (488 Hz x 2).
PWMFREQ = 2, PWM Dimming frequency is 1952 Hz (488 Hz x 4).
PWMFREQ = 3, PWM Dimming frequency is 3904 Hz (488 Hz x 8).
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Timing Chart – continued
2. ERROR Control
There are the following internal signals on timing charts: (n = 1 to 24)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
“PWM_OH[n-1]”
“CLKDIV16”
“CLKDIV144”
“TSD_IL”
PWM signal for LEDn (High: LED ON, Low: LED OFF).
internal clock (divided by 16).
internal clock (divided by 144).
TSD signal (Low: error)
Soft start mask signal (Low: mask).
TSD warning signal (Low: error).
LED open error signal (Low: error).
retiming signal.
“SSEND”
“WARTSD_IL”
“LOPDET_IL[n-1]”
r_lopdet, r_lshdet, r_wartsd
err_mskcnt
error mask counter.
ERRCLR register.
ERRCLR
Timing chart of each ERROR detection is as follows.
2.1
VINUVLO/VREG5UVLO/VREG3UVLO/TSD
If the device detects TSD, internal digital circuit is reset as shown in the figure. Other error (UVLO) is almost same
as this. ERRMASK and SSMASK don’t have effect in this protection. During detection, other protection are masked.
UVLOTSDERR register is reset to initial value “1”. ERRCLR is necessary to release UVLOTSDERR and the FAILB
pin.
Enlarged view A
Enlarged view B
UART(RX)
FAILB
Pin
TSD_IL signal
Internal
Signals
ERRCLR register
UVLOTSDERR register
Figure 52. TSD Detection Function
Pin
UART(RX)
FAILB
no access
CLKDIV16
Internal
Signals
asynchronous reset
TSD_IL signal
ERRCLR register
High
'0'
UVLOTSDERR register
Figure 53. TSD Detected Function (Enlarged View A)
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2. ERROR Control – continued
2.1. VINUVLO/VREG5UVLO/VREG3UVLO/TSD – continued
Pin
UART(RX)
FAILB
CLKDIV16
Internal
Signals
TSD_IL
signal
reset released
ERRCLR
UVLOTSDERR
Figure 54. TSD Released Function (Enlarged View B)
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2. ERROR Control – continued
2.2
TSD Warning
If temperature is over 125 °C, It can detect “WARTSD” (WARTSD_IL = Low). During detection, It update FAILB =
Low. At release, it update FAILB = High after released. ERRMASK and SSMASK does not have effect in this
protection.
Enlarged view A
Enlarged view B
Pin
FAILB
Internal WARTSD_IL
Signals signal
TSDW register
Figure 55. TSD Warning Function
Pin
FAILB
CLKDIV16
Internal
Signals
synchronized
WARTSD_IL
signal
High
TSDW register
Figure 56. TSD Warning Detected Function (Enlarged View A)
Pin
FAILB
Internal
Signals
CLKDIV16
WARTSD_IL
signal
synchronized
TSDW register
Figure 57. TSD Warning Released Function (Enlarged View B)
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2. ERROR Control – continued
2.3. LED Short Protection
When VLEDx > VLEDSH, LED Short Protection is detected and when VLEDx < VLEDSH, LED Short Protection is released.
The detection and release of this protection is shown in
Example :
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting (n = 01 to 24)
DIMSTART = 1
DIMMODE = 0
ERRMASK = 0x2h
LSHLAT = 0
DIMSETn[7:0] = 0x7Fh
Other: normal diming setting internal signal
CLKDIV16: internal clock (18 MHz / 16)
PWM_OH[1]: Current Driver control signal (High: lighting) for LED2
LSPDET_IL[1]: LED open error signal (low: error) for LED2
err_mskcnt: error mask filter of detection and released for LED short protection
Enlarged view A
Enlarged view B
PWMIN
CLKDIV16
PWM_OH[1]
LSPDET_IL[1]
r_lspdet[1]
SSEND
err_mskcnt[4:0]
LSHLAT register
LSHERR register
FAILB
0x0
0x0
0x2
All '0'
LED2: 1, other: 0
Figure 58. LED Short Protection Function
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2.3. LED Short Protection – continued
PWMIN
CLKDIV16
PWM_OH[1]
LSPDET_IL[1]
2 clock delay
(synchronized by 18 MHz)
r_lspdet[1]
mask time
SSEND
"High"
0x0
err_mskcnt[4:0]
ERRMASK register
LSHERR register
FAILB
0x1
0x2
0x3
0x4
0x0
0x02
All '0'
LED2: '1', other: '0'
Figure 59. LED Short Protection Function (Enlarged View A)
PWMIN
CLKDIV16
PWM_OH[1]
LSPDET_IL[1]
r_lspdet[1]
"High"
"High"
mask time
SSEND
"High"
err_mskcnt[4:0]
ERRMASK register
LSHERR register
FAILB
0x0
0x1
0x2
0x3 0x4
0x0
0x02
LED2: '1', other: '0'
All '0'
Figure 60. LED Short Protection (Enlarged View B)
Operation:
When SSEND= ‘High’ (Soft Start end), PWM_OH[1] = ‘High’ and LSPDET_IL[1] = ‘Low’ (LED short protection) is
detected, ERRMASK starts counting with CLKDIV16 (err_mskcnt_r) from the rise-edge of PWM_OH[1]. When the set
value (0x03h) is reached, FAIL is set to ‘Low’, i.e. ERROR is detected.
When ERROR is detected and PWM_OH[1] = ‘High’ and LSPDET_ID[1] = ’High’, ERRMASK starts counting with
CLKDIV16 (err_mskcnt_r) from the rise-edge of PWM_OH[1]. When the set value (0x03h) is reached, FAILB is set to
‘High’, i.e. It release the ERROR condition.
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2. ERROR Control – continued
2.4
LED Open Protection
When VLEDx < 0.3 V (Typ), LED Open protection is detected and when VLEDx > 0.3 V (Typ), LED Open protection is
released. The detection and release of this protection is shown in Figure 61.
Example :
・ ILEDx: LEDx pin current (x = 1 to 24)
・ Register setting (n = 01 to 24)
DIMSTART = 1
DIMMODE = 0
ERRMASK = 0x2h
LOPLAT = 0
DIMSETn[7:0] = 0x7Fh
Other: normal diming setting internal signal
CLKDIV16: internal clock (18 MHz / 16)
PWM_OH[1]: Current Driver control signal (High: lighting) for LED2
LOPDET_IL[1]: LED open error signal (low: error) for LED2
err_mskcnt: error mask filter of detection and released for LED open detection
Enlarged view A
Enlarged view B
PWMIN
Pin
FAILB
CLKDIV16
Internal
Signals
PWM_OH[1]
LOPDET_IL[1]
r_lopdet[1]
err_mskcnt[4:0]
LOPERR register
0x0
0x0
All "0"
LED2: "1", other: "0"
Figure 61. LED Open Protection Function
Enlarged View A
Enlarged View B
PWMIN
FAILB
Pin
1st
2nd 3rd
4th
5th
1st
2nd 3rd
4th
5th
CLKDIV16
Internal
Signals
PWM_OH[1]
LOPDET_IL[1]
r_lopdet[1]
2clock delay
(synchronized by 18MHz)
mask time
0x1 0x2
mask time
0x2 0x3
err_mskcnt[4:0]
LOPERR register
0x0
0x3
0x4
0x0
0x1
0x4
0x0
All "0"
LED2: "1", other: "0" LED2: "1", other: "0"
All "0"
Figure 62. LED Open Protection Function (Enlarged View A)
Operation :
When SSEND = “High” (Soft Start end), PWM_OH[1] = “High” and LOPDET_IL[1] = “Low” (LED open protection) is
detected, ERRMASK starts counting with CLKDIV16 (err_mskcnt) from the rise-edge of PWM_OH[1]. When the set
value (0x03h) is reached, FAIL is set to “Low”, i.e. ERROR is detected.
When ERROR is detected and PWM_OH[1] = “High” and LOPDET_ID[1] = “High”, ERRMASK starts counting with
CLKDIV16 (err_mskcnt) from the rise-edge of PWM_OH[1]. When the set value (0x03h) is reached, FAILB is set to
“High”, i.e. It release the ERROR condition.
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2.4. LED Open Protection – continued
Example : Low width error case, Register setting: ERRMASK[3:0] = 0x02h, LOPLAT = 0
Enlarged view A
Enlarged view B
PWMIN
Pin
FAILB
CLKDIV16
Internal
Signals
PWM_OH[1]
LOPDET_IL[1]
r_lopdet[1]
0x0h
0x0h
err_mskcnt[4:0]
LOPERR register
Figure 63. LED Open Protection Mask Function
PWMIN
FAILB
"high"
"high"
Pin
1st
2nd 3rd
CLKDIV16
Internal
Signals
PWM_OH[1]
"high"
LOPDET_IL[1]
r_lopdet[1]
2clock delay
(synchronize)
mask(3 to 4 clock)
err_mskcnt[4:0]
LOPERR register
0x0h
0x0h
0x1h 0x2h 0x3h 0x0h
All "0"
Figure 64. LED Open Protection Masked (Enlarged View A)
PWMIN
FAILB
Pin
1st
2nd 3rd
4th
1st
2nd 3rd
4th
CLKDIV16
Internal
Signals
PWM_OH[1]
"high"
"high"
"high"
0x0h
LOPDET_IL[1]
r_lopdet[1]
mask time
mask time
0x1h 0x2h 0x3h 0x4h
0x0h
0x1h 0x2h 0x3h 0x4h
err_mskcnt[3:0]
LOPERR register
0x0h
All "0"
LED2:"1", other: "0"
All "0"
Figure 65. LED Open Protection (Enlarged View B)
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2. ERROR Control – continued
2.5
LED Cathode Short Protection
Write CATHEN = 1 via UART to use cathode short protection.
It will monitor the LED pin voltage after 10 ms. If this voltage less than 0.3 V (Typ), it detects “cathode short error”. This
condition is the same as LED Open detection, during the 10 ms counting, LED Open protection cannot be detected.
UART(RX)
Pin
FAILB
CATHEN
Internal
10 ms
Signals
release
error
LOPDET_IL[1]
ERRCLR
CATHERR
Figure 66. LED Cathode Short Protection (Error)
UART(RX)
Pin
FAILB
"High"
CATHEN
10 ms
Internal
Signals
LOPDET_IL[1]
CATHERR
"Low"
no error
Figure 67. LED Cathode Short Protection (No Error)
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2. ERROR Control – continued
2.6
UART WDT
This device has watch-dog timer (WDT) for UART communication when WDTEN register is set to "High".
It detects WDT Error when there is no activity for 100 ms in UART interface (RX line). When detected, this protection
will set WDTERR Status register to "High" and FAILB output is latched to "Low". This condition is latched until
"ERRCLR" is sent via UART to release this condition.
Example1 : WDT protection detection
1
2
3
4
5
UART (RX)
Pins
FAILB
WDTEN Register
WDT Counter
ERRCLR register
WDTERR register
Internal
Signals
100 ms
Figure 68. WDT Protection
①
②
③
Set WDTEN = H, this setting enables WDT error detection.
Any UART command with CRC OK resets the watch dog counter.
No CRC OK is received within 100 ms, WDT Error is detected. It sets WDTERR status register to “High” and the
FAILB pin output to “Low”.
④
⑤
Send UART Read to Status registers.
WDTERR status register and FAILB are cleared when ERRCLR is received.
Register Settings:
WDTEN register = 1
1
2
4
5
UART(RX)
Pins
3
FAILB
100 ms
WDT Counter
ERRCLR
CRCERR
WDTERR
Internal
Signals
Figure 69. WDT Protection with CRC Error
①
②
③
UART command received with CRC OK resets the watch dog counter.
UART command with CRC error is detected, CRCERR status register is set to “High” and FAILB to “Low”.
No CRC OK is received within 100 ms, WDT Error is detected. It sets WDTERR status register to “High” and
FAILB is already “low” since CRC Error is detected.
④
⑤
Send UART Read to Status registers.
WDTERR status register, CRC Error Register and the FAILB pin output are cleared when ERRCLR is received.
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2. ERROR Control – continued
2.7
ISET Short Protection
When ISETSEL is High, user can use external resistor to set the ISET current. ISET Short protection is detected when
REXTISET1 < 20 kΩ (Typ). When protection is detected continuously for 56 μs (Typ), it sets ISETSHERR status register
to High and FAILB output to Low. After released continuously for 56 μs (Typ), it clears status register (ISETSHERR =
Low) and FAILB = High.
Depending on ISETSHCNT register setting, output LED or ISETSEL (internal/external selector) can be controlled when
ISETSH Error is detected. When ISETSEL is “Low”, this function is not active.
This protection is not affected by ERRMASK and SSMASK.
Register Settings: (x = 01 to 24)
DIMSTART = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
ISETSEL register = 1
ISETSHCNT register = 0x0h or 0x3h
ISETLAT register = 0
Pin
FAILB
ISETSH Error
2FFh Sync
Internal
Signals
ISET Filter = 56 μs (Typ)
ISETSHERR register
LED Channel
(LEDEN[0])
"ON"
"External Source EXTISET"
ISETSEL Setting
Figure 70. Operation when ISETLAT = 0 and ISETSHCNT = 0
The operation in the diagram above shows the default operation of ISETSH error detection with ISETSHCNT register
= 0 and ISETLAT register = 0. Status register and the FAILB pin output can be monitored in this operation. When the
protection is released, status register and the FAILB pin output are released.
Register Settings: (x = 01 to 24)
DIMSTART = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
ISETSEL register = 1
ISETSHCNT register = 0x1h
ISETLAT register = 1
Pin
FAILB
2FFh Sync
ISETSH Error
Internal
Signals
ISET Filter = 56 μs (Typ)
ISETSHERR register
LED Channel
(LEDEN[0])
"ON"
ISETSEL Setting
"External Source EXTISET"
Figure 71. Operation when ISETLAT = 0 and ISETSHCNT = 1
The operation in the diagram above shows the default operation of ISETSH error detection with ISETSHCNT register
= 1 and ISETLAT register = 0. Status register and the FAILB pin output can be monitored in this operation. When
ISETSH error is detected, LED output turns off. When the protection is released, LED output turns on, status register
and FAILB output is released.
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2.7
ISET Short Protection – continued
Register Settings: (x = 01 to 24)
DIMSTART = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
ISETSEL register = 1
ISETSHCNT register = 0x2h
ISETLAT register = 0 or 1
UART(RX)
Pin
FAILB
2FFh Sync
ISETSH
Internal
ISET Filter = 56 μs
ERRCLR
ISETSHERR register
LED Channel
(LEDEN[0])
"ON"
ISETSEL Setting
"External Source EXTISET"
"Internal ISET"
Figure 72. Operation when ISETLAT = 0 or 1 and ISETSHCNT = 2
The operation in the diagram above shows the default operation of ISETSH error detection with ISETSHCNT register
= 2 and ISETLAT register = 0. Status register and the FAILB pin output can be monitored in this operation. When
ISETSH error is detected, it changes the input selector for LED current setting (ISETSEL) from external to internal
source. ERRCLR is necessary to clear this condition. Release condition for 56 μs (Typ) will not release the protection.
Upon executing clear condition, input selector for ISET (ISETSEL) returns from internal to external.
Register Settings: (x = 01 to 24)
DIMSTART = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
ISETSEL register = 1
ISETSHCNT register = 0x0h o 0x3h
ISETLAT register = 1
UART(RX)
Pin
FAILB
2FFh Sync
ISETSH Error
Internal
ISET Filter = 56μs (Typ)
ERRCLR Register
ISETSHERR
Status Register
LED Channel
(LEDEN[0])
"ON"
ISETSEL Setting
"External Source EXTISET"
Figure 73. Operation when ISETLAT = 1 and ISETSHCNT = 0
The operation in the diagram above shows the operation of ISETSH error detection with ISETSHCNT register = 0 and
ISETLAT register = 1. Status register and the FAILB pin output can be monitored in this operation. Sending ERRCLR
is necessary to clear the status register and the FAILB pin output.
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BD18333EUV-M
2.7
ISET Short Protection – continued
Register Settings: (x = 01 to 24)
DIMSTART = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
ISETSEL register = 1
ISETSHCNT register = 0x1h
ISETLAT register = 1
UART(RX)
Pin
FAILB
2FFh Sync
ISETSH
Internal
ERRCLR register
ISET Filter = 56 μs (Typ)
ISETSHERR
register
LED Channel
(LEDEN[0])
"ON"
External Source EXTISET
ISETSELSetting
Figure 74. Operation when ISETLAT = 1 and ISETSHCNT = 1
The operation in the diagram above shows the default operation of ISETSH error detection with ISETSHCNT register
= 1 and ISETLAT register = 1. Status register and the FAILB pin output can be monitored in this operation. When
ISETSH error is detected, LED turns off. Sending ERRCLR is necessary to clear the LED output, status register and
the FAILB pin output.
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BD18333EUV-M
Sequence
1. Start-up Sequence
①
⑩
VIN
⑨
Pin
EN
②
VREG5 UVLO
VREG3 UVLO
③
VREG5
VREG3
④
⑤
⑥
⑦
⑧
UART(RX)
PWM generating
time
wait 1 ms (Min)
PWM clock
synchronous time
for DUT1
for DUT2
for DUT1,2
Cathode short protection time
LED1 to LED24 (DUT1)
LED1 to LED24 (DUT2)
FAILB (DUT1)
FAILB (DUT2)
Figure 75. Starting Sequence for Normal Operation
When you light the LED by general UART control, please follow the below sequence.
①
②
③
Input power supply in the VIN pin.
Launch the EN pin from “Low” to “High”, the VREG5 and VREG3 pins are generated.
Write initial setting from address 0x01h to 0x17h.
Write ERRCLR, to release FAILB. If you write CATHEN, it start to operate cathode short error.
Write initial setting from address 0x18h to 0x2Fh.
Write initial setting from address 0x30h to 0x4Ah.
Write SYNCSET register to 10b.
All device starts dimming at same timing.
Operate dimming control for each channel.
Dimming is stopped.
④
⑤
⑥
⑦
⑧
⑨
⑩
Stop input power supply in the VIN pin.
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BD18333EUV-M
Sequence – continued
2. PWM Synchronization Sequence
Sequence (x = 01 to 24)
DUT1 (Leader):
SYNCSET register = 0x1h (Leader)
DIMSETx[7:0] = 0x7Fh (50 % Duty)
DUT2 (Follower):
SYNCSET register = 0x2h (Follower)
DIMSETx[7:0] = 0x7Fh (50 % Duty)
for DUT1
for DUT2
for DUT1,2
①
②
④
DUT1 Master
UART (RX)
PWMOUT
pin
LED1
SYNCSET register
PWMFSYNC register
PWMPSYNC register
DIMSTART register
1d
internal
signals
DUT2 Slave
UART (RX)
PWMIN
pin
LED02
③
Internal PWM
SYNCSET Register
PWMFSYNC Register
PWMPSYNC Register
DIMSTART Register
2d
internal
signals
Figure 76. PWM Synchronization Operation
When it synchronize PWM phase with other device, please follow the sequence below.
①
②
③
Write SYNCSET register for Leader device. Leader starts to output reference signal from PWMOUT.
Write SYNCSET register for Follower device. Follower devices start to monitor PWMIN to adjust internal oscillator.
When it detects unstable clock condition in Follower devices, PWMFSYNC register = 1. Meaning, internal clock of the
Follower device is not yet synchronized to Leader clock. During this time, it is possible to send UART command to read
the status of PWMFSYNC, however, internal frequency adjusting stops during UART communication.
④
Write PWMPSYNC and DIMSTART register after clock is already stable. PWMPSYNC command triggers all device to
lock the phase of the PWM generation. DIMSTART command triggers all device to start LED output.
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BD18333EUV-M
Sequence – continued
3. Error Sequence
3.1
Protection Sequence for “LED Open Error” without LOPLAT
Example : Register Settings (x = 01 to 24)
AUTOOFF register = 0
LOPLAT register = 0
LOPEN register = 1
DIMMODE= 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
Detected “LED open error” in LED1: (n = 1 to 24)
PWMIN
Pin
1
Error
condition
LED open condition
ERRMASK time
3
LED1
4
UART (RX)
FAILB
2
ERRCLR register
LOPERR
"Low"
Internal
Signals
5
0x000000h
0x000001h
0x000000h
register
LSHERR
register
0x000000h
LEDEN[0] register
PWMn
*internal signal for PWM OFF
6
Enlarged view:
Enlarged view:
UART
UART
register Read:
register Write:
LEDEN
0x4Bh to 0x51h
(error status register)
Figure 77. Error Sequence for “LED Open Error” without LOPLAT
“LED Open Error” is detected after ERRASK time.
①
If Error condition is released before ERRMASK time setting is reached, Error condition is not detected in
FAILB and status register.
②
③
④
In error detection, corresponding status register (LOPERR) is updated and FAILB = Low.
MCU received FAILB = Low condition and issues a read command to status registers (0x4Bh to 0x51h).
After confirming status, MCU issues write command to set ”LEDEN[0] = 0” to affected “Error Channel” for
protection.
⑤
⑥
“Error register” and FAILB return to normal condition.
Corresponding channel output PWMn = Low.
Note: MCU cannot detect Error condition if “error condition” is cleared before reading “error register”.
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3
Error Sequence - continued
3.2
Protection Sequence for “LED Open Error” with LOPLAT
Example : Register Settings (x = 01 to 24)
AUTOOFF register = 0
LOPLAT register = 1
LOPEN register = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
Detected “LED open error” in LED1: (n = 1 to 24)
PWMIN
Pin
1
LED open condition
ERRMASK time
4
Error
condition
LED1
3
6
UART(RX)
FAILB
ERRCLR register
LOPERR register
"Low"
7
Internal
Signals
2
0x000000h
0x000001h
0x000000h
LSHERR register
LEDEN[0] (LED1)
0x000000h
5
*internal signal for PWM OFF
PWMn
Enlarged view:
UART
Enlarged view:
UART
register Read:
0x4Bh to 0x51h
(error status
register)
register Write:
LEDEN
ERRCLR
Figure 78. Error Sequence for “LED Open Protection” with LOPLAT
①
“LED Open Error” is detected after ERRASK time.
If Error condition is released before ERRMASK time setting is reached, Error condition is not detected in
FAILB and status register.
②
③
④
In error detection, corresponding status register (LOPERR) is updated and FAILB = Low.
MCU received FAILB = Low condition and issues a read command to status registers (0x4Bh to 0x51h).
After confirming status, MCU issues write command to set ”LEDEN[0] = 0” to affected “Error Channel” for
protection.
⑤
⑥
⑦
Corresponding channel outputs PWMn = Low.
MCU issues a write command to set ”ERRCLR = 1” to release “latch condition”.
“Error register” and the FAILB pin output return to normal condition after setting “ERRCLR = 1”.
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3
Error Sequence - continued
3.3
Protection Sequence for “LED Open Error” with AUTOOFF
Example : Register Settings (x = 01 to 24)
AUTOOFF register = 1
LOPLAT register = 0
LOPEN register = 1
DIMMODE = 0
DIMSETx[7:0] = 0x7Fh (50 % Duty)
Detected “LED open error” in LED1: (n = 1 to 24)
PWMIN
Pin
1
LED open condition
Error
condition
ERRMASK time
LED1
5
6
UART (RX)
FAILB
2
ERRCLR register
LOPERR register
"Low"
Internal
signals
7
0x000000h
0x000001h
0x000000h
LSHERR register
LEDEN[0] (LED1)
0x000000h
3
8
4
PWMn
*internal signal for PWM OFF
Enlarged view:
Enlarged view:
UART
UART
register Read:
register Write:
0x49h to 0x4Fh
ERRCLR
(error status
register)
Figure 79. Error Sequence for “LED Open Protection” with AUTOOFF
①
“LED Open Error” is detected after ERRMASK time. If Error condition is released before ERRMASK time
setting is reached, Error condition is not detected in FAILB and status register.
In error detection, corresponding status register (LOPERR) is updated and FAILB = Low.
Corresponding “LEDEN[0] = 0” of “Error channel” is released automatically due to AUTOOFF Setting.
Corresponding channel outputs PWMn = Low.
MCU reads “Error register” after MCU receives FAILB = Low condition.
MCU issues a write command to set “ERRCLR = 1” to release “Latch condition” and another write command
to set “LEDEN[0] = 1”.
②
③
④
⑤
⑥
⑦
⑧
“Error register” and the FAILB pin output return to normal condition after “ERRCLR = 1”.
“LEDEN[0] = 1” and PWM output recovered after “ERRCLR = 1”.
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3
Error Sequence - continued
3.4
Protection Sequence for “LED Short Error” without LSHLAT
Example : It detects “LED short error” in LED1.
PWMIN
①
Error
LED1: LED short error
condition
ERRMASK time
LED1
③
④
UART
AUTOOFF
(register)
"Low"
"Low"
"Low"
"High"
LSHLAT
(register)
ERRCLR
(register)
LSHEN
(register)
LOPERR
(register)
0x000000
②
⑤
LSHERR
(register)
0x000000
0x000001
0x000000
LEDEN[0] (LED1)
PWMn
*internal signal for PWM OFF
FAILB
Enlarged view
Enlarged view
UART
UART
register
register Write:
LEDEN
Read:
0x49h to 0x4Fh
(error status register)
Figure 80. Error Sequence for “LED Short Protection” without LSHLAT
①
It detecs “LED short error” after ERRMASK time.
If Error condition is released in this timing, it outputs High from FAILB after ERRMASK.
it outputs Low from FAILB and update “error register”.
MCU reads “Error register” after MCU receives FAILB = Low condition.
MCU writes “LEDEN[0] = 0” to “Error Channel” for protection.
It doesn’t output PWM.
②
③
④
⑤
It releases “Error register” and FAILB.
MCU can’t detect Error condition if “error condition” is cleared before reading “error register”.
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3
Error Sequence - continued
3.5
Protection Sequence for “LED Short Error” without AUTOOFF
Example : It detects “LED short Error” in LED1.
PWMIN
①
LED short condition
ERRMASK time
Error
condition
LED1
UART
⑤
⑥
AUTOOFF
(register)
"High"
"Low"
"Low"
"High"
LSHLAT
(register)
ERRCLR
(register)
LSHEN
(register)
LOPERR
(register)
0x000000
0x000000
p
LSHERR
(register)
0x000001
0x000000
③
q
LEDEN[0] (LED1)
④
PWMm
FAILB
*internal signal for PWM OFF
②
Enlarged view
Enlarged view
UART
UART
register Read:
0x49h to 0x4Fh
register Write:
ERRCLR
(error status
register)
Figure 81. Error Sequence for “LED Short Protection” without ERRLAT
①
It detects “LED short error” after ERRMASK time.
If Error condition is released in this timing, it keeps Low in FAILB and “Error register”.
It outputs Low from FAILB and update “error register”.
“LEDEN[0] = 0” of “Error Channel” for protection condition released automatically.
It ouputs PWM = Low.
MCU reads “Error register” after MCU receives FAILB = Low condition.
MCU writes “ERRCLR = 1” for releasing “Latch condition”.
“Error register” and FAILB return normal condition after “ERRCLR = 1”.
“LEDEN[0] = 1” and PWM output recovered after “ERRCLR = 1”.
②
③
④
⑤
⑥
⑦
⑧
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3
Error Sequence - continued
3.6
Protection Sequence for “CRC Error” without CRCERLAT
Example :
Register Setting
CRCERLAT register = 0
Detected “CRC Error”.
3
4
1
CRC NG
CRC OK
UART(RX)
Pins
UART(TX)
FAILB
ERRCLR register
CRCERR register
"Low"
Internal
Signals
2
Enlarged view:
Enlarged view:
UART
UART
register Read:
register Write:
other
0x49h to 0x4Fh
(error status
register)
Figure 82. CRC Error Sequence for UART without CRCERLAT
①
②
③
“CRC Error” is detected due to a communication error in the UART command.
In error detection, status register (CRCERR) is updated and FAILB = Low.
MUC issues read “Error register” after MCU receiving FAILB = Low condition.
Read Command does not clear CRC Error status.
④
If MCU write data of “CRC OK”, it outputs FAILB = High and update error register.
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3
Error Sequence - continued
3.7
Protection Sequence for “CRC Error” with CRCERLAT
Example :
Register Setting
CRCERLAT register = 1
“CRC Error” is detected.
1
3
4
5
CRC NG
CRC OK
UART(RX)
Pin
UART(TX)
FAILB
ERRCLR register
CRCERR register
"Low"
Internal
Signals
2
Enlarged view:
UART
Enlarged view:
UART
register Read:
0x49h to 0x4Fh
register ERRCLR
(error status
register)
Figure 83. CRC Error Sequence with CRCERLAT
①
②
③
④
⑤
“CRC Error” is detected due to a communication error in the UART command.
In error detection, status register (CRCERR) is update and FAILB = Low.
MCU reads “Error register” after MCU receives FAILB = Low condition.
Read Command does not clear CRC Error status.
MCU writes “ERRCLR = 1” to release “Latch condition”.
“Error register” and the FAILB pin return normal condition after “ERRCLR = 1”.
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3
Error Sequence - continued
3.8
Protection Sequence for “UART WDT Error”
Example :
Register Setting
WDTEN register = 1
It detects “UART WDT Error”.
1
3
4
UART(RX)
100 ms
Pin
UART(TX)
FAILB
ERRCLR register
WDTERR register
"Low"
Internal
Signals
2
5
Enlarged view:
Enlarged view:
UART
UART
register Read:
register ERRCLR
0x49h to 0x4Fh
(error status
register)
Figure 84. Error Sequence for WDT
①
②
③
④
⑤
“UART WDT Error” is detected over 100 ms after last UART access.
In error detection, Error register (WDTERR) and FAILB = Low.
MCU read “Error register” after MCU receiving FAILB = Low condition and is automatically latched.
MCU writes “ERRCLR = 1” to release “Latch condition”.
“Error register” and the FAILB pin return normal condition after “ERRCLR = 1”.
Note: MCU cannot detect Error condition if “error condition” is cleared before reading “error register”.
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3
Error Sequence - continued
3.9
Protection Sequence for “Cathode Short Error”
Example : “Cathode short error” is detected during turn on.
4
EN
Pin
Error
condition
LED1
1
3
UART(RX)
FAILB
2
10 ms
CATHEN register
CATHERR register
Internal
Signals
Enlarged view:
Enlarged view:
UART
UART
register Read:
0x49h to 0x4Fh
register ERRCLR
(error status
register)
Figure 85. Error Sequence for “Cathode Short Error” without ERRLAT
①
②
MCU writes to CATHEN register to start checking for “Cathode Short Error”.
“Cathode Short Error” is detected after 10 ms.
Status register (CATHERR) is updated and FAILB = Low.
③
④
MCU read “Error register” after MCU receiving FAILB = Low condition.
Status register (CATHERR) and the FAILB pin return to normal after EN = Low.
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Sequence – continued
4. FAILB Control Sequence
This IC can control FAILB output by register setting.
1
2
3
Pin
UART
FAILB
Internal
Signals
FAILBEN register
FAILBCNT register
Enlarged view:
UART
Enlarged view:
Enlarged view:
UART
UART
register
register
write
FAILBEN
register
Write:
FAILBCNT
Write:
FAILBCNT
Figure 86. FAILB Control Sequence
①
②
③
It is available to control FAILB output by FAILBEN = 1.
FAILBCNT = High, so it outputs High from the FAILB pin.
FAILBCNT = Low, so it outputs Low from the FAILB pin.
5. Unused Pin Setting
Please kindly set unused pin following the table below.
Table 51. Unused Pin Setting
Pin Name
FAILB
EXTISET1
EXTISET2
PWMIN
PWMOUT
LEDx (x = 1 to 24)
TEST
Setting
Unused Condition
Open
Open
Open
Open
Open
Open
Open
Unused the FAIL Flag.
Unused the ISETSEL Function.
Unused the LIMPHOME1 Function.
Unused the External PWM Frequency Synchronization Function.
Unused the Output PWM Frequency to next Follower device.
Unused the LED pin in application.
-
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LIMPHOME Sequence
This IC can operate lighting in LIMPHOME.
1. CASE1: No Lighting in LIMPHOME
LIMPHOME1:
Normal dimming:
LIMPHOME2:
OFF (EXTISET2 = OPEN)
120 mA (REXTISET1 = 60 kΩ)
OFF (EXTISET2 = OPEN)
Example : Register Settings (x = 01 to 24)
LIMPEN register = 1
LEXTISET2SEL register = 1
ISETSEL register = 1
DIMMODE register = 0 or 1
LHDTYx[3:0] = 0xFh (100 % Duty)
2
3
4
5
Pin
UART
LED current
6
FAILB
Internal
Signals
reset
1
7
state
IDLE
1.0 s
LIMPHOME1
STANDBY
Normal Dimming
LIMPHOME2
1.0 s
ISETSEL
LEXISET2SEL
LED current
reference setting
internal
EXTISET2
internal
EXTISET1
EXTISET2
Enlarged view:
UART
Enlarged view:
Enlarged view:
Enlarged view:
UART
UART
UART
register
register write register
register ERRCLR
register Write:
Write:
All initial setting
ISETSEL
DIMSETx
All register
are targeted
Figure 87. LIMPHOME Function Sequence (Case1)
①
If UART are not accessed over 1.0 s from reset released, this IC operates “LIMPHOME1” with
EXTISET2 resistor setting (REXTISET2). But, IC starts “No Lighting” in case of the EXTISET2 pin set to
“OPEN”.
②
③
④
If register is written and CRC OK, it operates change from “LIMPHOME1” to “STANDBY” state.
If ERRCLR is written, the FAILB pin returns to "High”.
All register are updated for dimming, It starts lighting in DIMSETx[7:0] or DCDIMx[3:0] register setting
after DIMSTART = 1. (x = 01 to 24)
⑤
⑥
⑦
Dimming data are updated.
If UART are not accessed over 100 ms (WDTEN = 1), it outputs FAILB = Low.
If UART are not accessed over 1.0 s from last signal, this IC operates “LIMPHOME2” with EXTISET2
resistor setting (REXTISET2). But, IC starts “No Lighting” in case of the EXTISET2 pin set to “OPEN” when
Address 0x5Eh (LIMPHOME) set to initial.
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LIMPHOME Sequence – continued
2. CASE2: 30 mA in LIMPHOME1 and LIMPHOME2
LIMPHOME1:
30 mA (REXTISET2 = 120 kΩ )
Normal Dimming: 120 mA (REXTISET1 = 60 kΩ)
LIMPHOME2:
150 mA (REXTISET1 = 60 kΩ + REXTISET2 = 120 kΩ)
Example : Register Settings (x = 01 to 24)
LIMPEN register = 1
LEXTISET2SEL register = 1
ISETSEL register = 1
DIMMODE register = 0 or 1
LHDTYx[3:0] = 0xFh (100 % Duty)
2
3
4
5
UART
Pin
LED current
6
FAILB
reset
Internal
Signals
1
7
state
IDLE
LIMPHOME1
STANDBY
Normal Dimming
LIMPHOME2
1.0 s
1.0 s
ISETSEL
LEXISET2SEL
LED current
reference setting
internal
EXTISET2
internal
EXTISET1
EXTISET1+EXTISET2
Enlarged view:
UART
Enlarged view:
Enlarged view:
Enlarged view:
UART
UART
UART
register
register write register
register ERRCLR
register Write:
Write:
All initial setting
ISETSEL
DIMSETx
All register
are targeted
Figure 88. LIMPHOME Function Sequence (Case2)
①
If UART are not accessed over 1.0 s from reset released, this IC operates “LIMPHOME1” with
EXTISET2 resistor setting (REXTISET2).
②
③
④
If register is written and CRC OK, it operates change from “LIMPHOME1” to “STANDBY” state.
If ERRCLR is written, the FAILB pin turns to “High”.
All register are updated for dimming, It starts lighting in DIMSETx[7:0] or DCDIMx[3:0] register setting
after DIMSTART = 1. (x = 01 to 24)
⑤
⑥
⑦
Dimming data are updated.
If UART are not accessed over 100 ms (WDTEN = 1), it outputs FAILB = Low.
If UART are not accessed over 1.0 s from last signal, this IC operates “LIMPHOME2” with EXTISET2
resistor setting (REXTISET2) when Address 0x5Eh (LIMPHOME) set to initial.
DC Dimming is changed from DIMSETx[7:0] (DIMMODE = 1) or DCDIMx[3:0] (DIMMODE = 0) at
“LIMPHOME2” status. And, PWM Dimming is changed from LHDTYx[3:0] regiser setting.
(x = 01 to 24)
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LIMPHOME Sequence – continued
3. CASE3: Mix Setting in LIMPHOME1 and LIMPHOME2
LIMPHOME1:
Normal Dimming: 120 mA (REXTISET1 = 60 kΩ)
LIMPHOME2: 120 mA (REXTISET1 = 60 kΩ)
0 mA (EXTISET2 = OPEN)
Example : Register Settings (x = 01 to 24)
LIMPEN register = 1
LEXTISET2SEL register = 0
ISETSEL register = 1
DIMMODE register = 0 or 1
LHDTYx[3:0] = 0xFh (100 % Duty)
2
3
4
5
UART
Pin
LED current
6
FAILB
reset
Internal
Signals
7
1
state
IDLE
LIMPHOME1
STANDBY
Normal Dimming
LIMPHOME2
1.0 s
1.0 s
ISETSEL
LEXISET2SEL
LED current
reference setting
EXTISET2
internal
EXTISET1
EXTISET1
Enlarged view:
Enlarged view:
Enlarged view:
Enlarged view:
UART
UART
UART
UART
register write register
register ERRCLR
register Write:
register
Write:
DIMSETx
All initial setting
All register
are targeted
(include LIMPHOME
setting 0x52h to 0x5Eh
Figure 89. LIMPHOME Function Sequence (Case3)
①
If UART are not accessed over 1.0 s from reset released, this IC operates “LIMPHOME1” with
EXTISET2 resistor setting (REXTISET2). But, IC starts “No Lighting” in case of the EXTISET2 pin set to
1.0 V or “OPEN”.
②
③
④
If register is written and CRC OK, it operates change from “LIMPHOME1” to “STANDBY” state.
If ERRCLR is written, the FAILB pin turns to "High”.
All register are updated for dimming. we should use continuous writing when we write LIMPHOME
register. LIMPHOME register don’t split “updated” and “not updated”. It starts lighting in DIMSETx[7:0]
or DCDIMx[3:0] register setting after DIMSTART = 1. (x = 01 to 24)
Dimming data are updated.
If UART are not accessed over 100 ms (WDTEN = 1), it outputs FAILB = Low.
If UART are not accessed over 1.0 s from last signal, this IC operates “LIMPHOME2” with internal
ISET setting (60 mA) when Address 0x5Eh (LIMPHOME) set to 0x01h (LEXTISETSEL = 0) and
ISETSEL = 0.
⑤
⑥
⑦
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Application Examples
External
BUCK Driver
+B
EN
BD18333EUV-M (DUT1 : Leader)
VREG3
BD18333EUV-M (DUT2 : Follower)
VIN
VIN
1
2
3
4
5
6
7
8
9
48
1
2
3
4
5
6
7
8
9
VREG3
GND
48
N.C. 47
CS0 46
CS1 45
CS2 44
10 μF
10 μF
GND
N.C. 47
CS0 46
CS1 45
CS2 44
4.7 μF
4.7 μF
VREG5
EN
VREG5
EN
5V
RX
TX
RX
TX
RX
RX
CAN
TRANCSIVER
Device : 0000
Device : 0001
CS3
CS3
TX
43
TX
43
PWMIN
LGND
FAILB
PWMOUT 42
LGND 41
TEST 40
PWMIN
LGND
FAILB
PWMOUT 42
LGND 41
TEST 40
100 kΩ
100 kΩ
10 LED1
11 LED2
12 LED3
13 LED4
14 LED5
15 LED6
16 N.C.
LED24 39
LED23 38
LED22 37
LED21 36
LED20 35
LED19 34
N.C. 33
10 LED1
11 LED2
12 LED3
13 LED4
14 LED5
15 LED6
16 N.C.
LED24 39
LED23 38
LED22 37
LED21 36
LED20 35
LED19 34
N.C. 33
17 LED7
18 LED8
19 LED9
20 LED10
21 LED11
22 LED12
23 EXTISET
24 LGND
LED18 32
LED17 31
LED16 30
LED15 29
LED14 28
LED13 27
EXTISET2 26
LGND 25
17 LED7
18 LED8
19 LED9
20 LED10
21 LED11
22 LED12
23 EXTISET
24 LGND
LED18 32
LED17 31
LED16 30
LED15 29
LED14 28
LED13 27
EXTISET2 26
LGND 25
EXP_PAD
EXP_PAD
240 kΩ
240 kΩ
120 kΩ
120 kΩ
Figure 90. Leader and Follower Connection Application Example
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I/O Equivalence Circuit
1. VREG3
3. VREG5
4. EN
VIN
VIN
500 k
VREG3
VREG5
EN
2.34 M
1.95 M
4.67 M
1 M
2.0 M
5. RX
6. TX
7. PWMIN
VREG5
VREG5
VREG5
PWMIN
20 k
1 k
20 k
RX
TX
100 k
10 to 15,17 to 22. LEDx (x = 1 to 12)
9. FAILB
23,26. EXTISET1, EXTISET2
VREG5
EXTISET1
EXTISET2
50 k
1 k
0.5 k
20 k
FAILB
LEDx
27 to 32,34 to 39. LEDx (x = 13 to 24)
40. TEST
42. PWMOUT
VREG5
VREG5
VREG5
50 k
TEST
10 k
PWMOUT
10 k
LEDx
100 k
43 to 46. CSx (x = 0 to 3)
VREG5
1 M
CSx
10 k
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Ordering Information
B D 1
8
3
3
3
E U V
-
M E2
Part Number
Package
EUV: HTSSOP-C48
Packing and Forming Specification
M: For Automotive
E2: Embossed Tape and Reel
Marking Diagram
HTSSOP-C48 (TOP VIEW)
Part Number Marking
LOT Number
BD18333EUV
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
HTSSOP-C48
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
6.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
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Operational Notes – continued
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10.
Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 91. Example of Monolithic IC Structure
11.
Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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BD18333EUV-M
Operational Notes – continued
12.
Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
13.
14.
Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
Functional Safety
“ISO 26262 Process Compliant to Support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in
the datasheet.
“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional Safety Supportive Automotive Products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
www.rohm.com
© 2021 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0T1T0B300440-1-2
09.Sep.2022 Rev.001
91/92
BD18333EUV-M
Revision History
Date
09.Sep.2022
Revision
001
Changes
1st released
www.rohm.com
© 2021 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0T1T0B300440-1-2
09.Sep.2022 Rev.001
92/92
Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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