BD18342FV-M_技术文档

Datasheet

Constant Current LED Drivers

Constant Current Controller

for Automotive LED Lamps

BD18342FV-M

General Description

Key Specifications

BD18342FV-M is 70V-withstanding constant current

controller for automotive LED lamps. It is able to drive at

maximum 10 rows of PNP transistors. It can also

contribute to reduction in the consumption power of the

set as it has the built-in standby function. The IC provides

high reliability because it has LED open detection, short

circuit protection, over voltage mute function and LED

failure input/output function.



Input Voltage Range:

FB Pin Voltage Accuracy:

4.5 V to 19 V

650 mV ±3 %

@Ta=25 °C to 125 °C

0 µA (Typ)



Stand-by Current:

Operating Temperature Range: -40 °C to +125 °C

Package

W (Typ) x D (Typ) x H (Max)

5.00 mm x 6.40 mm x 1.35 mm

SSOP-B16

Features



AEC-Q100 Qualified^{(Note 1)}

PWM Dimming Function

LED Open Detection

Short Circuit Protection (SCP)

Over Voltage Mute Function (OVM)

Disable LED Open Detection Function

at Reduced-Voltage



LED Failure Input/Output Functions (PBUS)

(Note 1) Grade1

SSOP-B16

Applications



Automotive LED Exterior Lamp

(Rear Lamp, Turn Lamp, DRL/Position Lamp, Fog

Lamp etc.)



Automotive LED Interior Lamp

(Air Conditioner Lamp, Interior Lamp, Cluster Light

etc.)

Typical Application Circuit

RFB1

RFB2

VIN

EN

FB

PWM_in

D1

RLIM

ZD1

CVIN1

CCRT

CVIN2

BASE

D2

D3

CRT

OP

DC_in

RCRT

SCP

CLED

DISC

D

BD18342FV-M

RDCIN

VREG

OPM

CVREG

ROPM

CD

PBUS

GND

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration

(TOP VIEW)

FB

BASE

N.C.

VIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

EN

DISC

CRT

D

OP

SCP

GND

PBUS

N.C.

VREG

OPM

Pin Description

Pin No.

Pin Name

Function

1

2

FB

BASE

N.C.

OP

Feedback voltage input

Connecting PNP Tr. BASE

No internal connection^{(Note 1)}

LED open detection input

Short circuit protection input

GND

3

4

5

SCP

GND

PBUS

N.C.

OPM

VREG

N.C.

D

6

7

Output for fault flag / Input to disable Output current

No internal connection^{(Note 1)}

8

9

Connecting resistor for disable LED open detection voltage setting at reduced voltage

Internal reference voltage output

10

11

12

13

14

15

16

No internal connection^{(Note 1)}

Connecting capacitor for disable LED open detection time setting

Connect capacitor and resistor to set output current ON Duty

Connecting resistor to set output current on time

Enable input

CRT

DISC

EN

VIN

Power supply input

(Note 1) Leave this pin unconnected

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Block Diagram

VREG

VIN

EN

FB

VREG

PBUS

BASE

Over

Voltage

Mute

VREF

PBUS

OPM

LED OPEN

OP

VREG

VIN

1.2 V

Control

Logic

OPEN

MASK

VREG

SCP

20 µs

Filter

D

D COMP

1.20 V ⇔1.25 V

Rise 1 µs

Filter

1.0 V

VREG

CRT

CR

TIMER

DISC

GND

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Absolute Maximum Ratings (Ta=25°C)

Parameter

Symbol

V_IN

Rating

-0.3 to +70.0

-0.3 to V_IN+0.3

-0.3 to +5.0

-0.3 to +7.0

-0.3 to V_REG+0.3

-55 to +150

150

Unit

V

Power Supply Voltage(VIN)

EN, CRT, DISC Pin Voltage

FB, BASE, OP, SCP Pin Voltage

V_EN, V_CRT, V_DISC

V_FB, V_BASE, V_OP,V_SCP

V_{IN_FB}, V_{IN_BASE}

V_PBUS, V_REG

V_OPM, V_D

V

VIN-FB, VIN-BASE

Inter-Pin Voltage

V

PBUS, VREG Pin Voltage

OPM, D Pin Voltage

V

Storage Temperature Range

Tstg

°C

Maximum Junction Temperature

Tjmax

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 3)}

2s2p^{(Note 4)}

SSOP-B16

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

140.9

6

77.2

5

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A(Still-Air).

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

Footprints and Traces

70 μm

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

4 Layers

Top

Copper Pattern

Bottom

Copper Pattern

74.2 mm x 74.2 mm

Thickness

Copper Pattern

Thickness

Footprints and Traces

70 μm

74.2 mm x 74.2 mm

35 μm

70 μm

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Recommended Operating Conditions

Parameter

Symbol

V_IN

Min

4.5

100

10

Typ

Max

19.0

5000

-

Unit

V

Supply Voltage^{(Note 1) (Note 2)}

13.0

CR TIMER Frequency Range

PWM Minimum Pulse Width^{(Note 3)}

f_PWM

t_MIN

-

Hz

µs

°C

Operating Temperature

Topr

-40

+125

(Note 1) ASO should not be exceeded

(Note 2) At start-up time, please apply a voltage 5 V or more once. The value is the voltage range after the temporary rise to 5 V or more.

(Note 3) At connecting the external PNP Tr. (2SAR573DFHG (ROHM), 1 pcs). That is the same when the pulse input to the CRT pin.

Operating Conditions

Parameter

Symbol

C_VIN1

Min

1.0

Max

-

Unit

μF

kΩ

Ω

Capacitor

Connecting VIN Pin 1

Capacitor

(Note 4)

C_VIN2

0.047

1.0

-

Connecting VIN Pin 2

Capacitor

(Note 5)

C_VREG

4.7

0.68

0.22

50.0

6.5

Connecting VREG Pin

Capacitor

C_LED

0.10

0.01

0.1

Connecting LED Anode

Capacitor

C_CRT

R_CRT

for Setting CRT Timer

Resistor

for Setting CRT Timer

Resistor

(Note 6)

R_FB1, R_FB2

0.8

for Setting LED Current

Resistor for Disable LED Open

Detection Voltage Setting

at Reduced Voltage

R_OPM

R_DCIN

25

55

kΩ

Resistor for DCIN Pull-down

-

10

kΩ

μF

Ω

Capacitor for Setting Disable LED

Open Detection Time

(Note 5)

C_D

R_LIM

Q₁

0.001

0.100

Resistor for Limiting

Base Pin Current

See Features Description 5

External PNP Transistor

-

(Note 7)

(Note 4) Recommended ceramic capacitor. ROHM Recommended Value (0.1 μF GCM155R71H104KE37 murata)

(Note 5) Recommended ceramic capacitor. Please setting the Disable LED Open Detection Time less than PWM minimum pulse width.

(Note 6) At connecting the external PNP Tr. 2SAR573DFHG (ROHM), 1 pcs.

(Note 7) For external PNP transistor, please use the recommended device 2SAR573DFHG for this IC.

While using non-recommended part device, validate the design on actual board.

Please check hfe of the part to design base current limit resistor. (See Features Description, section 5).

As for parasitic capacitance, please evaluate over shoot of I_LEDon actual board. (See Features Description, Section 8 -Evaluation example,

I_LEDpulse width at PWM Dimming operation).

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Electrical Characteristics

(Unless otherwise specified Ta=-40 °C to +125 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

Limit

Parameter

[Circuit Current I_VIN

Symbol

Unit

Conditions

Min

Typ

Max

]

V_EN=0 V

V_FB=V_IN

Circuit Current at Stand-by Mode

Circuit Current at Normal Mode

I_VIN1

I_VIN2

I_VIN3

I_VIN4

-

0

10

5.0

μA

V_EN=V_IN, V_FB=V_IN-1.0 V

Base Current Subtracted

2.0

mA

Circuit Current

at LED Open Detection

mA V_EN=V_IN, V_FB=V_IN-1.0 V

V_EN=V_IN, V_FB=V_IN-1.0 V

V_PBUS=0 V

Circuit Current at PBUS=Low

mA

[VREG Voltage]

I_VREG=-100 μA

V

4.85

5.00

5.15

Ta=25 °C to 125 °C

VREG Pin Voltage

V_REG

I_VREG

I_VREG=-100μA

Ta=-40 °C to +125 °C

4.75

-1.0

5.00

-

5.25

-

V

VREG Pin Current Capability

mA

[DRV]

V_FBREG=V_IN-V_FB

mV R_FB1=R_FB2=1.8 Ω,

Ta=25 °C to 125 °C

V_FBREG=V_IN-V_FB

mV R_FB1=R_FB2=1.8 Ω,

Ta=-40 °C to +125 °C

630

617

650

670

683

FB Pin Voltage

V_FBREG

FB Pin Input Current

I_FB

7.5

10

15

-

30

-

μA

mA

kΩ

V_FB=V_IN

BASE Pin Sink

Current Capability

V_FB=V_IN, V_BASE=V_IN-1.5 V

Ta=25 °C

I_BASE

R_BASE

V_CRT=0 V

V_FB=V_IN, V_BASE=V_IN-1.0 V

BASE Pin Pull-up Resistor

0.5

1.0

1.5

[Over Voltage Mute Function (OVM)]

ΔV_FB=10.0 mV

Over Voltage Mute Start Voltage

Over Voltage Mute Gain

V_OVMS

20.0

-

22.0

-25

24.0

-

V

ΔV_FB=V_FB(@V_IN=13 V)-

V_FB(@V_IN=V_OVMS

)

V_OVMG

mV/V ΔV_FB/ΔV_IN

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Electrical Characteristics – continued

(Unless otherwise specified Ta=-40 °C to +125 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

Limit

Parameter

[CR TIMER]

Symbol

Unit

Conditions

Min

Typ

Max

CRT Pin Charge Current

CRT Pin Charge Voltage

CRT Pin Discharge Voltage 1

CRT Pin Discharge Voltage 2

CRT Pin Charge Resistor

CR Timer Discharge Constant

DISC Pin ON Resistor 1

I_CRT

36

0.72

1.80

2.10

28.5

0.38

20

40

0.80

2.00

2.40

30.0

0.40

50

44

μA

V

V_{CRT_CHA}

V_{CRT_DIS1}

V_{CRT_DIS2}

R_CHA

0.88

2.20

3.00

31.5

0.42

100

10

V

When V_CRT> V_{CRT_DIS2}

R_D1→ R_D2

,

V

R_CHA

=

kΩ

V/V

Ω

(V_{CRT_DIS1}-V_{CRT_CHA})/I_CRT

V_{CRT_CHA}

V_{CRT_DIS1}

/

R_DISC1

R_DISC2

I_DISC=10 mA

I_DISC=100 μA

VCRT=V_IN

DISC Pin ON Resistor 2

2.5

5.0

kΩ

μA

CRT Pin Leakage Current

[LED Open Detection]

I_{CRT_LEAK}

-

10

LED Open Detection Voltage

V_OPD

I_OP

1.1

19

1.2

21

1.3

23

V

V_OPD=V_IN-V_OP

V_OP=V_IN-0.5 V

OP Pin Input Current

μA

[Disable LED Open Detection Function at Reduced-Voltage]

OPM Pin Source Current

I_OPM

38

40

42

μA

V

VIN Pin Disable LED Open

Detection Voltage

at Reduced-Voltage

V_OPM

x 5.9

V_OPM

x 6.0

V_OPM

x 6.1

V_{IN_OPM}

V_{OPM_R}

OPM Pin Input Voltage Range

1.0

-

2.2

V

[Disable LED Open Detection Time Setting D Function]

Input Threshold Voltage

D Pin Source Current

D Pin ON Resistor

V_DH

I_DSOURCE

R_D

0.9

100

-

1.0

230

-

1.1

400

950

V

μA

Ω

I_{D_EXT}=100 μA

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Electrical Characteristics – continued

(Unless otherwise specified Ta=-40 °C to +125 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[Short Circuit Protection (SCP)]

Short Circuit Protection Voltage

V_SCPD

V_SCPR

V_SCPHYS

I_SCP

1.10

1.15

-

1.20

1.25

50

1.30

1.35

-

V

Short Circuit Protection

Release Voltage

Short Circuit Protection

Hysteresis Voltage

mV

mA

V

SCP Pin Source Current

0.2

1.15

10

1.0

2.0

1.45

45

SCP Pin Source Current

ON Voltage

V_SCP2

t_SCP

1.30

20

SCP Delay Time

[PBUS]

µs

Input High Voltage

V_PBUSH

V_PBUSL

V_PBUSHYS

I_PBUS

2.4

-

V

Input Low Voltage

-

0.6

-

Hysteresis Voltage

200

150

-

mV

μA

V

PBUS Pin Source Current

PBUS Pin Output Low Voltage

PBUS Pin Output High Voltage

75

-

300

0.6

5.5

10

V_EN=5 V

V_{PBUS_OL}

V_{PBUS_OH}

I_{PBUS_LEAK}

I_{PBUS_EXT}=3 mA

I_{PBUS_EXT}=-10 μA

V_PBUS=7 V

3.5

-

4.5

-

V

PBUS Pin Leakage Current

[EN]

μA

Input High Voltage

V_ENH

V_ENL

V_ENHYS

I_EN

2.4

-

0.6

-

V

Input Low Voltage

Hysteresis Voltage

-

60

7

mV

μA

Pin Input Current

[UVLO VIN]

15

V_EN=5 V

UVLO Detection Voltage

V_UVLOD

V_UVLOR

V_HYS

3.88

4.25

-

4.10

4.50

0.4

4.32

4.75

-

V

V_IN: Sweep down

V_IN: Sweep up,

V_REG> 3.75 V

UVLO Release Voltage

UVLO Hysteresis Voltage

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Typical Performance Curves (Reference Data)

(Unless otherwise specified Ta=25 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ta=+125 °C

Ta=+25 °C

Ta=-40 °C

Ta=+125 °C

Ta=+25 °C

Ta=-40 °C

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

Supply Voltage : V_IN[V]

Figure 1. Circuit Current at Normal Mode vs Supply

Voltage

Figure 2. VREG Pin Voltage vs Supply Voltage

500

400

300

200

100

0

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

-50 -25

0

25 50 75 100 125 150

0

2

4

6

8

10

12

14

Resistor for Setting LED Current :

Temperature[°C]

R_FB1+R_FB2[Ω]

Figure 3. VREG Pin Voltage vs Temperature

Figure 4. LED Current vs Resistor for Setting LED Current

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Typical Performance Curves (Reference Data) – continued

(Unless otherwise specified Ta=25 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

690

680

670

660

650

640

630

620

610

5

4

3

2

1

0

-1

-2

-3

-4

-5

ΔI_LED=(I_LED/{0.65 V/(R_FB1+R_FB2)}-1)

x100[%]

0

2

4

6

8

10

12

14

-50 -25

0

25 50 75 100 125 150

Resistor for Setting LED Current :

Temperature[°C]

R_FB1+R_FB2[Ω]

Figure 5. LED Current Accuracy vs Resistor for Setting

LED Current

Figure 6. FB Pin Voltage vs Temperature

50

45

40

35

30

800

700

600

500

400

300

200

100

0

Ta=+25 °C

Ta=-40 °C

25

Ta=+125 °C

Ta=+25 °C

Ta=-40 °C

20

Ta=+125 °C

15

10

6

11 16 21 26 31 36 41 46 51 56

Supply Voltage : V_IN[V]

4

6

8

10 12 14 16 18 20

Supply Voltage : V_IN[V]

Figure 7. BASE Pin Sink Current Capability vs Supply

Voltage

Figure 8. FB Pin Voltage vs Supply Voltage

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Typical Performance Curves (Reference Data) – continued

(Unless otherwise specified Ta=25 °C, V_IN=13 V, C_VREG=1.0 µF, Transistor PNP=2SAR573DFHG)

42.0

41.5

41.0

40.5

40.0

39.5

39.0

38.5

38.0

42.0

41.5

41.0

40.5

40.0

39.5

39.0

38.5

38.0

-50 -25

0

25 50 75 100 125 150

-50 -25

0

25 50 75 100 125 150

Temp[℃]

Temperature[°C]

Figure 9. CRT Pin Charge Current vs Temperature

Figure 10. OPM Pin Source Current vs Temperature

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Description of Function

(Unless otherwise specified, Ta=25 °C, V_IN=13 V, Transistor PNP=2SAR573DFHG, and numbers are “Typical” values.)

1. LED Current Setting

LED current I_LEDcan be defined by setting resistances R_FB1and R_FB2

.

푉

퐹퐵푅ꢀ퐺

퐼_퐿퐸퐷

=

[A]

ꢁ

+ꢁ

퐹퐵2

퐹퐵1

where:

ꢂ

ꢃꢄꢁ퐸ꢅ

is the FB pin voltage 650 mV (Typ).

●How to connect LED current setting resistors

LED current setting resistors must always be connected at least two or more in series as below.

If only one current setting resistor is used, then in case of a possible resistor short (pattern short on the board

etc.), the external PNP Tr. and LED may be broken due to large current flow.

PNP Tr. rating current, LED rating current, R_FB1and R_FB2must have the following relations:

푉

퐹퐵푅ꢀ퐺

퐼_{퐿퐸퐷_푀퐴푋}> 퐼_{푃푁푃_푀퐴푋}

>

[A]

푀푖푛(ꢁ

,ꢁ

)

퐹퐵1 퐹퐵2

where:

퐼_{퐿퐸퐷_푀퐴푋}

is the LED rating current.

퐼_{푃푁푃_푀퐴푋}

ꢂ

ꢃꢄꢁ퐸ꢅ

is the PNP Tr. rating current.

is the FB pin voltage 650 mV (Typ).

ꢆꢇꢈ(ꢉ_ꢃꢄꢊ, ꢉ_ꢃꢄꢋ

)

is the lowest value of R_FB1and R_FB2.

R

FB1

FB2

VIN

FB

+B

EN

VREG

BASE

VCE_PNP

VREG

VREF

GND

C

VREG

ILED

Figure 11. LED Current Setting

●Constant current control dynamic range

Constant current control dynamic range of LED current I_LEDcan be calculated as follows.

ꢂ ≥ ꢂ

× ꢍ ꢎ ꢂ

ꢎ ꢂ

ꢃꢄꢁ퐸ꢅ

[V]

ꢌ푁

푓_퐿퐸퐷

퐶퐸_푃푁푃

where:

ꢂ

푓_퐿퐸퐷

is the VIN pin voltage.

is the LED Vf.

ꢌ푁

ꢍ

is the number of rows of LED.

ꢂ

is the external PNP Tr. collector-emitter saturation voltage.

is the FB pin voltage 650 mV (Typ).

퐶퐸_푃푁푃

ꢂ

ꢃꢄꢁ퐸ꢅ

2. Reference voltage (VREG)

Reference voltage VREG 5.0 V (Typ) is generated from VIN input voltage. This voltage is used as power source for the

internal circuit, and also used to fix the voltage of pins outside LSI to HIGH side. The VREG pin must be connected with

C_VREG=1.0 μF to 4.7 μF to ensure capacity for the phase compensation. If C_VREGis not connected, the circuit behavior

would become extraordinarily unstable, for example with the oscillation of the reference voltage.

The VREG pin voltage must not be used as power source for other devices than this LSI.

VREG circuit has a built-in UVLO function. The IC is activated when the VREG pin voltage rises to 4.00 V (Typ) or higher,

and shut down when the VREG pin voltage drops to 3.75 V (Typ) or lower.

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Description of Function – continued

3. Table of Operations

The PWM dimming mode switches to DC control depending on the CRT pin voltage.

The switching conditions are as shown in the table below. When V_IN> 22.0 V (Typ), LED current is limited to reduce the

heat dissipation of external PNP Tr..

Depending on the OP pin and the SCP pin voltage status, detect LED open or short circuit then LED current is turned

OFF. LED current is also turned OFF when Low signal is input to the PBUS pin.

In addition, UVLO and TSD further increases system reliability.

For each functions, please refer to Description of Function.

Detecting Condition

Operation

Mode

CRT

LED Current

(I_LED

PBUS Pin

Hi-Z

)

[Detect]

[Release]

Stand-by

Mode^{(Note 1)}

-

V_EN≤ 0.6 V

V_EN≥ 2.4 V

OFF^{(Note 3)}

V_CRT

2.0 V (Typ)

≥

High

4.5 V (Typ)

DC

-

50 mA to 400 mA

See Features

Description 4

See Features

Description 4

High

4.5 V (Typ)

PWM Dimming

Over Voltage

Mute

V_IN

>

V_IN

≤

See Features

Description 10

High

4.5 V (Typ)

-

22.0 V (Typ)

LED Open

Detection^{(Note 2)}

V_OP

≥

V_OP

<

OFF^{(Note 3)}

Low

V_IN–1.2 V (Typ)

V_IN– 1.2 V (Typ)

Short Circuit

Protection (SCP)

V_SCP

1.20 V (Typ)

≤

V_SCP≥

1.25 V (Typ)

PBUS Control

OFF

Input

V_PBUS≤ 0.6 V

V_PBUS≥ 2.4 V

V_IN≤ 4.10 V (Typ)

V_IN≥ 4.50 V (Typ)

OFF^{(Note 3)}

UVLO

TSD

-

High

Hi-Z

or

V_REG≤ 3.75 V (Typ) V_REG≥ 4.00 V (Typ)

Tj ≥

Tj ≤

OFF^{(Note 3)}

175 C (Typ)

150 C(Typ)

(Note 1) Circuit current 0 μA (Typ)

(Note 2) In regard to the sequence of LED current OFF, see Features Description 5.

(Note 3) The BASE pin sink current: OFF, and LED current(I_LED): OFF.

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Description of Function – continued

4. PWM Dimming Operation

PWM Dimming is performed with the following circuit.

The dimming cycle and ON Duty Width, can be set by values of the external components (CCRT, RCRT).

Connect the CRT pin to VIN and the DISC pin to GND or open if it is not used.

The CR timer function is activated if DC SW is OPEN. To perform PWM dimming of LED current, a triangular waveform

is generated at the CRT pin. The LED current (I_LED) is turned OFF while CRT voltage is ramp up, and LED

current(I_LED) is turned ON while CRT voltage is ramp down.

When VCRT ≥ V_{CRT_DIS1}(2.0 V(Typ)), dimming mode turns to DC Control. When VCRT > V_{CRT_DIS2}(2.4 V(Typ)), the DISC pin

ON resister changes from R_DISC1(50 Ω(Typ)) to R_DISC2(5 kΩ(Typ)), and the power consumption of the IC is reduced by

reducing the inflow current of the DISC pin.

PWM SW

ON

VIN

EN

VREG

FB

DC SW

OPEN

VREG

Control

Logic

BASE

ICRT

VREF

CRT

CCRT

RCRT

ILED

VCRT_DIS1

VCRT_DIS2

GND

DISC

RDISC1

RDISC2

Figure 12. PWM Dimming Operation

CRT Voltage

Ramp up

CRT Voltage

Ramp down

VCRT_DIS1

VCRT_CHA

2.0 V(Typ)

CRT Pin

Waveform

ΔVCRT

0.8 V(Typ)

tOFF

tON

ΔVCRT×CCRT

V

CRT_CHA

CRT_DIS1

tOFF

=

=RCHA×CCRT

tON= - (RCRT+ RDISC1)×CCRT×ln

ICRT

V

LED Current

I

LED

I

LED

I

LED

I

LED

I

LED

I

LED

OFF

ON

OFF

ON

OFF

ON

ILED

Figure 13. PWM Dimming Operation

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4. PWM Dimming Operation – continued

(1) CRT ramp up Time t_OFFand CRT ramp down Time t_ON

CRT ramp up Time t_OFFand CRT ramp down Time t_ONcan be defined from the following equations.

Make sure that t_ONis set PWM Minimum Pulse Width t_MIN10 μs or more.

∆푉

×퐶

ꢏ푅푇

푡_푂ꢃꢃ

=

= ꢉ_퐶퐻퐴× ꢐ_퐶ꢁꢑ[s]

ꢌ

ꢏ푅푇

푡_푂푁= − ꢉ_퐶ꢁꢑꢎ ꢉ_{퐷ꢌ푆퐶ꢊ}× ꢐ_퐶ꢁꢑ× 퐼ꢈ ꢒ_푉^푉^{ꢏ푅푇_ꢏꢓꢔ}ꢘ [s]

(

)

ꢏ푅푇_ꢕꢖꢗ1

where:

퐼_퐶ꢁꢑ

ꢉ_퐶퐻퐴

ꢉ_{퐷ꢌ푆퐶ꢊ}

is the CRT pin charge current, 40 μA (Typ).

is the CRT pin charge resistor, 30 kΩ (Typ).

is the DISC pin ON resistor1, 50 Ω (Typ).

is the CRT pin charge voltage, 0.8 V (Typ).

is the CRT pin discharge voltage1, 2.0 V (Typ).

ꢂ

퐶ꢁꢑ_퐶퐻퐴

ꢂ

퐶ꢁꢑ_퐷ꢌ푆ꢊ

(2) PWM Dimming Frequency f_PWM

PWM frequency is defined by t_ONand t_OFF

.

ꢊ

ꢙ

푃푊푀

=

[Hz]

ꢚ

+ꢚ

ꢛꢜ ꢛ퐹퐹

(3) ON Duty(D_ON

)

PWM ON duty is defined by t_ONand t_OFF

.

ꢚ

ꢛꢜ

ꢝ_푂푁

=

[%]

ꢚ

+ꢚ

ꢛ퐹퐹

ꢛꢜ

(Example) In case of R_CRT=3.6 kΩ, C_CRT=0.1 μF (Typ)

푡_푂ꢃꢃ= ꢉ_퐶퐻퐴× ꢐ_퐶ꢁꢑ= 30 × 0.ꢞ = 3.0 [ms]

(

)

ꢟ

_{퐶ꢁꢑ_퐷ꢌ푆ꢊ}ꢠ

푡_푂푁= − ꢉ_퐶ꢁꢑꢎ ꢉ_{퐷ꢌ푆퐶ꢊ}× ꢐ_퐶ꢁꢑ× 퐼ꢈ ꢂ_{퐶ꢁꢑ_퐶퐻퐴}/ꢂ

(

)

(

)

= − 3.6 ꢎ 50 × 0.ꢞ × 퐼ꢈ 0.8/ꢡ.0 = 0.334 [ms]

ꢙ

푃푊푀

= ꢞ/(푡_푂푁ꢎ 푡_푂ꢃꢃ) = ꢞ/(3.0 ꢎ 0.334) = 300 [Hz]

ꢝ_푂푁= 푡_푂푁/(푡_푂푁ꢎ 푡_푂ꢃꢃ) = 0.334/(3.0 ꢎ 0.334) = ꢞ0.0 [%]

[PWM Dimming Operation Using External Signal]

In case external PWM input to the CRT pin, make sure that input pulse high voltage ≥ 2.2 V and pulse low voltage ≤ 0.6

V. Also please open the DISC pin or connect to GND.

VIN

EN

VREG

FB

Control

Logic

VREG

BASE

ICRT

VREF

μ-Con

or

CRTIMER

CRT

ILED

GND

DISC

Figure 14. PWM Dimming Operation Using External Signal

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4. PWM Dimming Operation – continued

●About deviation of CRT ramp up/down time with a reverse connection protection diode

If this LSI is used to drive LED like below schematic, there is a possibility of occur CRT ramp up/down time deviation

due to characteristics of reverse current Ir diode (D2, D3) .

Consider to choose a diode (D2, D3) which is recommended by Rohm or Ir value 1 μA (Max) or less.

Since reverse current flows even with the recommended diodes, connect a resistor of R_DCINof 10 kΩ or less between

Point A and GND so that the voltage at point A does not rise.

Mechanism of deviation of CRT ramp up/down time from set values.

①

↓

During the PWM dimming operation mode, Point A on Figure 15 is Hi-Z.

②

Reverse current Ir of D2 and D3 goes to Point A.

(Power supply voltage is being input into the cathode of D2, so mainly reverse current of D2 goes into C1.)

→Reverse current Ir of D3 is added to the CRT pin charge current and discharge current, so CRT ramp

up/down time deviates from the settings.

↓

③

C1 gets charged, voltage at Point A rises.

Point A voltage ≥ the CRT pin voltage of each IC.

Vf occurs in the diodes D3.

↓

④

↓

⑤

↓

⑥

D3 circulate forward current If

→Forward current If of D3 is added to the CRT pin charge current and discharge current, so CRT ramp

up/down time deviates from the settings.

↓

⑦

Repetition of ➁ to ➅.

D1

D2

VIN

EN

FB

BASE

Point A

BD18342FV-M

Ir

D3

CRT

If

RDCIN

C1

Vf

GND

DISC

Figure 15. How Reverse Protection Diode Affects the CRT Pin Ramp Up/Down Time

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Description of Function – continued

5. LED Open Detection Function

In case any one of the LEDs is in the open state, the IC can detect LED open condition when the OP pin voltage (V_OP

)

meets the following condition: V_OP≥ V_IN-1.2 V (Typ). As soon as V_OP≥ V_IN-1.2 V (Typ) condition is achieved, the D pin

source current (230 μA (Typ)) turns on and starts charging the disable LED open detection time setting capacitor (C_D).

Once the D pin voltage (V_DH) becomes 1.0 V (Typ) or more and 1 μs (Typ) elapses, the BASE pin sink current (I_BASE) is

latched OFF and the PBUS pin voltage (V_PBUS) is switched to Low.

[Base Current Limit Resistance (R_LIM)]

The OP pin voltage V_OPat LED open is defined by the following formula:

(Note that the external PNP Tr. goes into the saturation mode when the collector is open, it becomes the following

formula.)

(

)

ꢂ_푂푃= ꢂ − { ꢉ_ꢃꢄꢊꢎ ꢉ_ꢃꢄꢋ× 퐼_ꢄ퐴푆퐸

ꢎ ꢂ

}

[V]

ꢌ푁

퐶퐸

ꢤꢜꢤ

ꢢꢔꢣ

퐼_{ꢄ퐴푆퐸_푀퐴푋}= 6.0ꢂ/ꢉ_퐿ꢌ푀[A]

ꢟ

ꢠ

퐼_{ꢄ퐴푆퐸_푀퐴푋}< 80 푚ꢥ

where:

ꢉ_ꢃꢄꢊ, ꢉ_ꢃꢄꢋis the LED current setting resistance.

퐼_{ꢄ퐴푆퐸_푀퐴푋}is the maximum BASE pin sink current.

ꢉ_퐿ꢌ푀

ꢂ

is the resistor for limiting BASE pin current.

is the external PNP Tr. Collector-emitter voltage (Note: I_CE=I_OP(23 μA (Max))).

퐶퐸_푃푁푃

Please determine the BASE current limit resistance R_LIMto ensure that the OP pin voltage when the LED is open should

meet the following condition: V_OP> V_IN-1.2 V (Typ).

Also note that the BASE current limit resistance must meet the following condition in order to obtain the BASE current to

be needed during normal LED operation.

4.0/ꢉ_퐿ꢌ푀> 퐼_퐿퐸퐷/ℎꢙ푒_{_푀ꢌ푁}[A]

where:

ℎꢙ푒_{_푀ꢌ푁}

is the minimum external PNP Tr. hfe.

For the D pin, it is possible to set the disable time t_Dfrom when the OP pin voltage meets the condition “V_OP> V_IN-1.2 V

(Typ)” until the BASE pin sink current (I_BASE) is latched off, according to the following formula. Note that the disable

time must be shorter than or equal to the ON pulse width of the PWM dimming t_ON

.

퐶 ×푉

ꢕ

ꢕꢓ

푡_푂푁> 푡_퐷=

[s]

ꢌ

ꢕꢗꢛ푈푅ꢏꢀ

where:

푡_푂푁

ꢐ_퐷

ꢂ_퐷퐻

is the ON pulse width of the PWM dimming(CRT ramp down time).

is the disable LED open detection time setting capacitor.

is the D pin input threshold voltage, 1.0 V (Typ).

퐼_{퐷푆푂ꢦꢁ퐶퐸}is the D pin source current, 230 μA (Typ).

To reset the latched off LED current, EN must be turned-on again (The time when the EN Pin is “L” since the power is

turned on again: 50 μs or more) or the condition “UVLO (V_IN≤ 4.10 V or V_REG≤ 3.75 V)” must be fulfilled.

VIN

LED

OPEN

Discharge Co

by the OP pin input current(21μA)

RFB1

RFB2

OP Pin

Voltage

VOP

VIN

FB

-

1.2 V(Typ)

VF_LED

DRV

PBUS

BASE

PBUS

VCE_PNP

RLIM

LED Open

Detection

Comparator

Output

IBASE

OPEN

Control

Logic

LED OPEN

OP

VOP

1.0

V

230 μA

1.2 V

(Typ)

D Pin

Voltage

VD

1

μs

(Typ)

CLED

VD

CD x

230 μA

1.0 V

D

D COMP

1.0 V

ILED

1 μs

Filter

CD

PBUS Pin

Voltage

VPBUS

I

BASE

Latch Release Condtion

EN: -> Lor UVLO: detect

: OFF(DRV: OFF)

GND

I

BASE:

ON

(DRV: ON)

:

H

Figure 16. LED Open Detection Timing Chart

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Description of Function – continued

6. Disable LED Open Detection Function at Reduced-Voltage

The disable LED open detection function serves to prevent false detection of LED open at the reduced-voltage during

the ramp-up/ramp-down of the VIN pin voltage. Even though LED is in the open state, LED open will not be detected

until the VIN pin voltage becomes more than Disable Open Detection Voltage at Reduced-Voltage (V_{IN_OPM}). Once

V_{IN_OPM}is surpassed, the LED current will be latched OFF (The BASE pin sink current (I_BASE) is latched OFF) and the

PBUS voltage will be switched to Low following the sequence explained in Description of Function 5.

V_{IN_OPM}must be defined by the following formula. (The OPM pin voltage must be set between 1.0 V and 2.2 V.)

ꢂ

≥ ꢂ

[V]

ꢌ푁_푂푃푀

ꢌ푁_푂푃퐸ꢁꢁ

VIN

where:

ꢂ

is the VIN pin disable open detection voltage

at reduced-voltage.

ꢌ푁_푂푃푀

FB

Control

Logic

ꢂ

is the VIN pin open erroneous detection

voltage at reduced-voltage.

ꢌ푁_푂푃퐸ꢁꢁ

VCE_PNP

VREG

BASE

IOPM

VREF

(

)

ꢂ

= ꢂ_푂푃푀× 6.0 ꢧ푦푝

[V]

ꢌ푁_푂푃푀

OPM

OPEN

MASK

LED OPEN

OP

Vf_LED×N

ꢂ_푂푃푀= 퐼_푂푃푀× ꢉ_푂푃푀[V]

= ꢂ × ꢍ ꢎ ꢂ_푂푃퐷[V]

ROPM

VOPD=1.2 V

ꢂ

ꢌ푁_푂푃퐸ꢁꢁ

푓_퐿퐸퐷

GND

where:

Figure 17. Disable LED Open Detection Function

at Reduced-Voltage

ꢂ_푂푃푀is the OPM pin voltage.

퐼_푂푃푀is the pin source current, 40 μA (Typ)

ꢉ_푂푃푀is the OPM pin connection resistance.

ꢂ

푓_퐿퐸퐷

is the LED Vf.

ꢍ

is the number of rows of LED.

ꢂ_푂푃퐷is the LED open-circuit detection voltage, 1.2 V (Typ)

●When connecting resistor for heat dispersion, or connecting resistor or diodes between the OP pin and LED

anode

The formula to calculate V_{IN_OPERR}will be different from the one above when the current flowing the LED is large and it

is necessary to connect a resistor for heat dispersion in series with the LED to reduce the heat generation from the

external PNP Tr., when multiple rows of the LEDs are driven, or when connecting a resistor to adjust the threshold

voltage for detecting the LED open-circuit. Please read the Application Note of BD1834xFV-M series for details.

VIN_OPERR

VIN_OPM

VIN_OPERR

VIN >

Vf_LED × N + VCE_PNP + VFBREG

VIN

Controllable Range of

constant current

Disable

LED Open

Detection

Area

Disable

LED Open

Detection

Area

VIN

VOPD =VIN -1.2 V

LED Open

Detection

Area

LED Open

Detection

Area

VOP

VOP = Vf_LED × N

ILED

4.5 V

VPBUS

Figure 18. VIN Pin Disable LED Open Detection Voltage at Reduced-Voltage

and LED Open Erroneous Detection Voltage at Reduced-Voltage

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Description of Function – continued

7. Short Circuit Protection (SCP)

Short Circuit Protection function will be activated by decreasing the SCP pin voltage when the collector of the external

PNP Tr. is short to GND. After a lapse of the short circuit protection delay time(t_SCP)(20 μs(Typ)) following the drop of the

SCP pin voltage(V_SCP) is 1.2 V(Typ) or less, the external PNP Tr. is turned OFF to prevent its thermal destruction, and it

can be notify the abnormally to the outside by changing the PBUS pin output to low.

In order to avoid malfunction since the power is turned on, the Short Circuit Protection function will not be activated until

V_CRT> 2.0 V(Typ) after UVLO is reset.

If it is in the short circuit state (V_SCP< 1.2 V(Typ)) since the power is turned on, the Short Circuit Protection function will

be activated when V_CRT> 2.0 V(Typ) condition is reached and 60 µs(Typ) passes, after UVLO is reset.

VIN

FB

BASE

EN

VREG

VREF

VIN

PBUS

Control

Logic

PBUS

ILED

SCP

SHORT

GND

20 µs

Filter

1.20 V ⇔1.25 V

Short

Circuit

Short Circuit

4.5 V

VIN

2.0 V

V

CRT

SCP

1.25 V

ON

1.25 V

ON

1.20 V

V

ON

60 μs

20 μs

OFF

High

OFF

Low

OFF

ILED

High

Low

VPBUS

Figure 19. Short Circuit Protection (SCP)

●SCP Pin Source Current

The SCP pin sources the current (1 mA(Typ)) once its voltage (V_SCP) drops under 1.3 V in order to prevent the

malfunction of the short circuit protection.

VIN

FB

EN

1.3 V (Typ)

VREG

BASE

VSCP

VREF

0 V

PBUS

GND

PBUS

VIN

Control

Logic

SCP

1.3 V

1.0 mA (Typ)

0 mA

SCP

ISCP

20 µs

Filter

ISCP

1.2 V⇔1.25 V

Figure 20. SCP Pin Source Current

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Description of Function – continued

8. About the Capacitor of Connecting LED Anode

There is a zone which the output (LED anode) will become high impedance (Hi-Z) at PWM dimming Mode. During this

time noise^{(Note 1)}can couple on to this pin and cause false detection of SHORT condition.

To prevent this, it is necessary to connect a Capacitor C_LEDbetween LED anode and GND pin nearby pin.

Make sure that the capacitor of connecting LED anode is the following equation:

0.ꢞ ≤ ꢐ_퐿퐸퐷≤ 0.68 [µF]

In case C_LEDis set the range from 0.1 μF to 0.68 μF, the I_LEDcurrent becomes dull, so please evaluate I_LEDwaveform in

PWM mode operation.

About the example of evaluation, please see evaluation example on page 21.

In case a capacitor exceeding the recommended range is connected to LED anode, there is a possibility that delay time

of start-up will reach about several ten ms, so special attention is needed.

(Note 1) Conducted noise, Radiated noise, Crosstalk of connecter and PCB pattern etc…

VIN

EN

VREG

FB

Control

Logic

VREG

BASE

ICRT

VREF

CRT

CLED

GND

DISC

ILED

Figure 21. About the Capacitor of Connecting LED Anode

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Description of Function – continued

Evaluation example (I_LEDpulse width at PWM Dimming operation)

Condition: +B=13 V

Ta=25 °C

LED=1 Strings

C_CRT=0.01 μF

R_DISC=1.0 kΩ

PWM Dimming Mode

I_LED=50 mA

I_LED=500 mA

C_LED=0.1 μF

C_LED=0.47 μF

I_LED=50 mA

I_LED=200 mA

C_LED=0.1 μF

C_LED=0.47 μF

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Description of Function – continued

9. PBUS Function

The PBUS pin is the pin to input and output an error signal.

When abnormality such as LED open or output ground fault occurs, it can notify the abnormality to the outside by

changing the PBUS pin output from high to low. In addition, by externally controlling the PBUS pin from high to low, the

LED current is turned off. When using multiple LSIs to drive multiple LEDs, it is possible to turn off all LED lines at once

by connecting the PBUS pins of each CH as shown in the figure below, even if LED open or output ground fault occurs.

Caution of using the PBUS pin

Do not connect to the PBUS pins other than BD1834xFV-M series due to the difference of ratings, internal

threshold voltages, and so on.

FB

VIN

EN

VIN

EN

BASE

BD18342FV-M

CH 1

BD18342FV-M

CH 2

OP

SCP

PBUS

GND

LED

OPEN

LED

OFF

communication each other by PBUS

Figure 22. PBUS Function

▼Example of Protective Operation due to LED Open Circuit

①CH1 LED

Open

CH1 PNP Tr.

Collector

Voltage

ON

CH1 ILED

OFF

②After CH1LED Open Detection Mask time

LED：Latch OFF

I

V

PBUS：High→Low

V

PBUS

CH2 PNP Tr.

Collector

③VPBUS：High→Low

CH2 PNP Tr. : OFF

Voltage

ON

CH2 ILED

OFF

Figure 23. Example of Protective Operation

If LED OPEN occurs, the PBUS pin of CH1 is switched from High to Low output. As the PBUS pin becomes Low, LED

drivers of other CH detect the condition and turns OFF their own LEDs. The collector voltage of PNP transistor clamps

to 1.3 V (Typ) during the OFF period, in order to prohibit ground fault detection.

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Description of Function – continued

10. Over Voltage Mute Function (OVM)

Once the VIN pin voltage (V_IN) goes above 22.0 V (Typ), the over voltage mute function is activated to decrease the LED

current (I_LED) in order to suppress heat generation from the external PNP Tr.

The FB pin voltage V_FBREGwhich controls the LED current (I_LED) will decay at -25 mV/V (Typ).

VIN

FB

BASE

EN

VREG

Over

Voltage

Mute

VREF

GND

VFBREG [mV]

22.0 V(Typ)

650

-25 mV/V(Typ)

Output current is

muted by power

supply overvoltage

0

VOVMS

VIN [V]

Figure 24. Overvoltage Mute Function (OVM)

11. Under Voltage Lockout (UVLO)

UVLO is a protection circuit to prevent malfunction of the IC when the power is turned on or when the power is suddenly

shut off.

This IC has two UVLO circuits; UVLO VIN for V_INand UVLO VREG for V_REG

.

As soon as UVLO status is detected, the BASE pin sink current will be turned off and switch OFF the LED current (I_LED).

The following shows the threshold conditions of both UVLO circuits.

Detection Conditions

LED Current

Operating Mode

PBUS Pin

(I_LED

)

[Detect]

[Release]

High

4.5 V (Typ)

UVLO VIN

OFF^{(Note 1)}

V_IN≤ 4.10 V (Typ)

V_IN≥ 4.50 V (Typ)

High

4.5 V (Typ)

UVLO VREG

V_REG≤ 3.75 V (Typ) V_REG≥ 4.00 V (Typ)

(Note 1) The BASE pin sink current is turned OFF to switch OFF the LED current (I_LED).

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Timing Chart

(Unless otherwise specified Ta=25 °C, VIN=13 V, Transistor PNP=2SAR573DFHG, LED 2 strings, and values are Typical.)

PWM Dimming Mode

DC Mode

EN

reclosing

EN

reclosing

OUTPUT

GND

OUTPUT

GND

LED

OPEN

SHORT

OPEN

SHORT

13V

4.5V

VIN

4.1V

VEN

2.4V

0.6 V

2.4V

0.6V

4.0V

V

REG

CRT

13V

V

1.0V

1.0 V

VD

VIN-1.2 V

VIN-1.2V

1.25 V

V

OP

SC P

1.25V

1.20V

1.25 V

1.25V

1.20V

20μs

20 μs

V

PBU S

V

FBREG

ILED

Output

Latch OFF

Output

Latch OFF

Figure 25. Timing Chart

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Application Examples

(1) I_LED=120 mA

RFB1

RFB2

DC_in

VIN

EN

FB

D1

ZD1

CVIN1

CVIN2

BASE

Q1

CRT

OP

U1

SCP

C^LED

DISC

D

BD18342FV-M

VREG

OPM

CD

CVREG

ROPM

PBUS

GND

Figure 26. Application Example 1

(I_LED120 mA, LED white 2 strings)

Recommended Parts List 1 (I_LED120 mA, LED white 2 strings)

Parts

IC

No

U1

Parts Name

BD18342FV-M

Value

-

Unit

Product Maker

ROHM

-

D1

RFN2LAM6STF

-

ROHM

Diode

Z_D1

TND12H-220KB00AAA0

2SAR573DFHG

-

NIPPON CHEMICON

ROHM

Transistor PNP

Q1

-

R_FB1

R_FB2

R_OPM

C_VIN1

C_VIN2

C_VREG

C_D

LTR10EVHFL2R70

2.7

39

4.7

0.1

1.0

0.01

0.1

Ω

ROHM

Resistor

LTR10EVHFL2R70

Ω

ROHM

MCR03EZPFX3902

GCM32ER71H475KA40

GCM155R71H104KE37

GCM188R71E105KA49

GCM155R11H103KA40

GCM155R71H104KE37

kΩ

μF

ROHM

murata

Capacitor

murata

C_LED

murata

(Note 1) About Z_D1, please place according to test standard of battery line.

Please note the following

1. External PNP transistor

For external PNP transistor, please use the recommended device 2SAR573DFHG for this IC.

While using non-recommended device, validate the design on actual board with sufficient confirmation of the parts

specifications (hfe, parasitic capacitance).

Please check hfe of the part when designing base current limit resistor. (See Features Description, section 5). As for

parasitic capacitance (C_LEDconnected at LED anode), the smaller it is, the smaller its overshoot is. Use devices that has

smaller parasitic capacitance than that of recommended device. Also parasitic capacitance is possible to be varied by PCB

layout so please evaluate overshoot of I_LEDon actual board. (See Features Description, Section 8 -Evaluation example, I_LED

pulse width at PWM Dimming operation).

2. Power supply steep variation

This IC is validated with test conditions as per ISO7637-2 standards.

There is possibility of unexpected LED regulation (peak current of output etc.) due to sudden transients outside the

specification range standards in input power supply. Please check the maximum ratings of LED and evaluate on actual

board for any unexpected LED regulation.

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Application Examples - continued

(2) I_LED=120 mA, PWM ON Duty=10 %

RFB1

RFB2

VIN

EN

FB

PWM_in

D1

ZD1

CVIN1

CVIN2

BASE

Q1

D2

CRT

OP

DC_in

D3

CCRT

RCRT

U1

SCP

CLED

DISC

D

BD18342FV-M

RDCIN

VREG

OPM

CD

CVREG

ROPM

PBUS

GND

Figure 27. Application Example 2

(I_LED120 mA, LED white 2 strings, PWM ON Duty: 10 %(Pulse width: 0.334 ms), PWM frequency: 300 Hz)

Recommended Parts List 2

(I_LED120 mA, LED white 2 strings, PWM ON Duty: 10 %(Pulse width: 0.334 ms), PWM frequency: 300 Hz)

Parts

IC

No

U1

Parts Name

BD18342FV-M

Value

-

Unit

-

Product Maker

ROHM

D1, D2

D3

RFN2LAM6STF

-

ROHM

Diode

RFN1LAM6STF

-

ROHM

Z_D1

TND12H-220KB00AAA0

2SAR573DFHG

-

NIPPON CHEMICON

ROHM

Transistor PNP

Q1

-

R_FB1

R_FB2

R_CRT

R_OPM

R_DCIN

C_VIN1

C_VIN2

C_VREG

C_CRT

C_D

LTR10EVHFL2R70

MCR03EZPFX3601

MCR03EZPFX3902

ESR10EZPF2001

2.7

3.6

39

2

Ω

ROHM

Ω

ROHM

Resistor

kΩ

μF

ROHM

GCM32ER71H475KA40

GCM155R71H104KE37

GCM188R71E105KA49

GCM155R71H104KE37

GCM155R11H103KA40

GCM155R71H104KE37

4.7

0.1

1.0

0.1

0.01

0.1

murata

Capacitor

murata

C_LED

murata

(Note 1) About Z_D1, please place according to test standard of battery line.

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Application Examples - continued

(3) I_LED=524 mA, PWM ON Duty=10 %

RFB1

R^FB2

VIN

EN

FB

PWM_in

D1

ZD1

CVIN1

CVIN2

BASE

Q1 to Q3

D2

CRT

OP

DC_in

D3

CCRT

RCRT

U1

SCP

CLED

DISC

D

BD18342FV-M

RDCIN

VREG

OPM

CD

CVREG

ROPM

PBUS

GND

Figure 28. Application Example 3

(I_LED524 mA, LED white 2 strings, PWM ON Duty: 10 %(pulse width: 0.334 ms), PWM frequency: 300 Hz)

Recommended Parts List 3

(I_LED524 mA, LED white 2 strings, PWM ON Duty: 10 %(pulse width: 0.334 ms), PWM frequency: 300 Hz)

Parts

IC

No

U1

Parts Name

BD18342FV-M

Value

-

Unit

-

Product Maker

ROHM

D1, D2

D3

RFN2LAM6STF

-

ROHM

Diode

RFN1LAM6STF

-

ROHM

Z_D1

TND12H-220KB00AAA0

2SAR573DFHG

-

NIPPON CHEMICON

ROHM

Transistor PNP

Q1 to Q3

R_FB1

-

LTR10EVHFLR620

MCR03EZPFX3601

MCR03EZPFX3902

ESR10EZPF2001

0.62

3.6

39

2

Ω

ROHM

R_FB2

Ω

ROHM

Resistor

R_CRT

R_OPM

R_DCIN

C_VIN1

C_VIN2

C_VREG

C_CRT

C_D

kΩ

μF

ROHM

GCM32ER71H475KA40

GCM155R71H104KE37

GCM188R71E105KA49

GCM155R71H104KE37

GCM155R11H103KA40

GCM155R71H104KE37

4.7

0.1

1.0

0.1

0.01

0.1

murata

Capacitor

murata

C_LED

murata

(Note 1) About Z_D1, please place according to test standard of battery line.

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Application Examples - continued

(4) I_LED=150 mA, Three Rows Drive, PWM ON Duty=10 %

RFB11

RFB12

RFB21

RFB22

RFB31

RFB32

VIN

FB

PWM_in

D1

R1

R2

R3

RLIM

ZD1

CVIN1

CCRT

CVIN2

EN

BASE

Q1

Q2

Q3

D2

D3

D4

D5

D6

CRT

OP

SCP

DC_in

RCRT

U1

DISC

D

BD18342FV-M

RDCIN

VREG

OPM

CLED1

CLED2

CLED3

CD

CVREG

ROPM

PBUS

GND

ILED1

ILED2

ILED3

Figure 29. Application Example 4

(I_LED1to I_{LED 3}150 mA, LED white 2 strings x 3, PWM ON Duty: 10 %( pulse width: 0.334 ms), PWM frequency: 300 Hz)

Refer to Application Note of BD1834xFV-M series for details about the multiple rows drive such as the one above.

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Power Dissipation

Thermal design should meet the following equation.

ꢨ_푑> ꢨ_퐶

ꢟ

ꢠ

ꢟ

ꢠ ꢟ

ꢠ

ꢟ

ꢠ

− ꢧ_ꢑ

ꢨ_푑= ꢞ/휃_퐽퐴× ꢧ

− ꢧ 표푟 ꢞ/훹 × ꢧ

푗ꢩ푎푥

푎

퐽ꢑ

푗ꢩ푎푥

ꢨ_퐶= ꢂ × 퐼_푉ꢌ푁ꢋꢎ ꢂ

× 퐼_ꢄ퐴푆퐸

ꢌ푁

ꢄ퐴푆퐸

where:

ꢨ_푑

is the power dissipation.

ꢨ_퐶

ꢂ

ꢌ푁

is the power consumption.

is the VIN pin voltage.

퐼_푉ꢌ푁ꢋis the circuit current at normal mode.

is the BASE pin voltage.

ꢂ

ꢄ퐴푆퐸

퐼_ꢄ퐴푆퐸is the BASE pin sink current.

휃_퐽퐴is the thermal resistance of junction to ambient.

훹

퐽ꢑ

is the thermal characterization parameter of junction to center case surface.

ꢧ

푗ꢩ푎푥

is the maximum junction temperature(150 °C).

ꢧ

ꢧ_ꢑ

is the ambient temperature.

푎

is the case surface temperature.

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I/O Equivalence Circuits

No.

Name

I/O Equivalence Circuit

No.

I/O Equivalence Circuit

Name

VIN

VREG

(Pin 16)

(Pin 10)

1 kΩ (Typ)

FB

(Pin 1)

5.6 kΩ (Typ)

1

FB

9

OPM

10 kΩ (Typ)

OPM

(Pin 9)

GND

(Pin 6)

GND

(Pin 6)

VIN

(Pin 16)

1 kΩ

(Typ)

BASE

(Pin 2)

VREG

(Pin 10)

2

3

4

BASE

N.C.

OP

10

11

12

VREG

N.C.

D

370 kΩ

(Typ)

10 kΩ (Typ)

92.5 kΩ

(Typ)

GND

(Pin 6)

GND

(Pin 6)

VIN

(Pin 16)

VREG

(Pin 10)

OP

(Pin 4)

D

100 kΩ (Typ)

(Pin 12)

100 kΩ (Typ)

GND

(Pin 6)

GND

(Pin 6)

VIN

VREG

(Pin 16)

(Pin 10)

100 kΩ (Typ)

SCP

(Pin 5)

CRT

(Pin 13)

5

6

7

8

SCP

GND

PBUS

N.C

13

CRT

100 kΩ (Typ)

GND

(Pin 6)

GND

(Pin 6)

DISC

(Pin 14)

-

VREG

(Pin 10)

14

DISC

5 kΩ

(Typ)

5.2V

(Typ)

PBUS

(Pin 7)

100 kΩ (Typ)

10Ω

(Typ)

GND

(Pin 6)

GND

(Pin 6)

EN

(Pin 15)

260 kΩ

(Typ)

150 kΩ

(Typ)

1 kΩ (Typ)

15

16

EN

5.2V

(Typ)

5.2V

(Typ)

1080 kΩ

(Typ)

1333 kΩ

(Typ)

143 kΩ

(Typ)

GND

(Pin 6)

-

VIN

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

6. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 30. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

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Ordering Information

B D 1

8

3

4

2

F

V -

M E 2

Product Name

Package

FV: SSOP-B16

Product Rank

M: for Automotive

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

SSOP-B16(TOP VIEW)

Part Number Marking

18342

LOT Number

Pin 1 Mark

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Physical Dimension and Packing Information

Package Name

SSOP-B16

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Revision History

Date

Revision

001

Changes

18.Sep.2018

New Release

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.003


型号：	BD18342FV-M
厂家：	ROHM
描述：	本产品是面向车载LED灯的70V高耐压恒流控制器。一个本IC最多可驱动10个外置PNP晶体管。同时还内置待机功能，可为降低灯组功耗做贡献。内置LED开路检测、输出短路保护、过电压保护、LED异常状态输入输出功能，可实现高可靠性。驱动控制器晶体管
文件：	总38页 (文件大小：2989K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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