BD6042GUL [ROHM]
Silicon Monolithic Integrated Circuit; 硅单片集成电路
| 型号： | BD6042GUL |
| 厂家： | 
ROHM |
| 描述： | Silicon Monolithic Integrated Circuit |
| 文件： | 总5页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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STRUCTURE
Silicon Monolithic Integrated Circuit
PRODUCT NAME
Overvoltage Protection Controller with Internal FET
MODEL NAME
FEATURES
BD6042GUL
●Overvoltage Protection up to 28V
●Internal Low Ron (125mΩ) FET
●Over voltage Lockout (OVLO)
●Under voltage Lockout(UVLO)
●Internal 2msec Startup Delay
●Over Current Protect
●Thermal Shut Down
●Small package: VCSP50L1(1.6mm x 1.6mm, height=0.55mm)
●Absolute maximum ratings (Ta=25℃)
Contents
Input supply voltage 1
Input supply voltage 2
Power dissipation
Operating temperature range
Storage temperature range
Symbol
Vmax1
Vmax2
Pd
Rating
-0.3～30
-0.3～7
725
-35～+85
-55～+150
Unit
V
Conditions
IN
V
mW
℃
other
Topr
Tstr
℃
※1 When using more than at Ta=25℃, it is reduced 5.8 mW per 1℃.
ROHM specification board 50mm× 58mm mounting.
●Operating range (Ta=-35～+85℃)
Parameter
Input voltage range
Symbol
Vin
Range
Unit
V
Usage
2.2～28
※
This product is not especially designed to be protected from radioactivity.
Status of this document.
The Japanese version of this document is the formal specification.
A customer may use this translation version only for reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
REV. A
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● Electrical Characteristics (Unless otherwise noted, Ta = 25°C, IN=5V)
Rating
Typ.
Parameter
Symbol
Unit
Conditions
Min.
-
Max.
● ELECTRICAL
Input Voltage Range
Supply Quiescent Current
Under Voltage Lockout
Under Voltage Lockout Hysteresis
Over Voltage Lockout
Over Voltage Lockout Hysteresis
Current limit
VIN
ICC
-
45
2.65
100
6.2
100
-
125
-
-
28
90
V
μA
V
mV
V
mV
A
mΩ
mV
μA
V
UVLO
UVLOh
OVLO
OVLOh
ILM
2.53
50
6.0
50
1.2
-
2.77
150
6.4
150
-
150
400
1
IN=decreasing
IN=increasing
IN=increasing
IN=decreasing
Vin vs. Vout Res.
RON
OK Output Low Voltage
OK Leakage Current
EN input voltage (H)
EN input voltage (L)
EN input current
OKVO
OKleak
ENH
ENL
ENC
-
-
SINK=1mA
EN=1.5V
1.45
-
12
-
-
25
-
0.5
50
V
μA
● TIMINGS
Start Up Delay
Ton
Tok
Toff
Tovp
-
-
-
-
2
10
2
4
msec
msec
μsec
μsec
OK Going Up Delay
Output Turn Off Time
Alert Delay
15
10
10
1.5
* This product is not especially designed to be protected from radioactivity.
REV. A
3/4
● Block Diagram
● PIN number/PIN name
Pin
Pin name
number
A2
A3
B2
B3
A1
B1
C3
C1
C2
IN1
IN2
IN3
IN4
OUT1
OUT2
GND
OK
EN
● PIN DESCRIPTIONS
PIN
A2, A3
B2, B3
A1, B1
C1
NAME
IN1, 2,
3, 4
FUNCTION
Input voltage Pin. A 1μF low ESR capacitor,
or larger must be connected between this pin and GND
OUT1, 2 Output Voltage Pin
OK
GND
EN
Active-low open drain output to signal if the adapter voltage is correct
C3
C2
Ground Pin
Enable input Drive EN high to turn off OUT (Hi-z output)
● Package Dimensions (VCSP50L1)
6042
LOT No.
REV. A
4/4
●Use-related Cautions
(1) Absolute maximum ratings
If applied voltage (VDD, VIN), operating temperature range (Topr), or other absolute maximum ratings are exceeded, there is a risk of
damage.Since it is not possible to identify short, open, or other damage modes, if special modes in which absolute maximum ratings are exceeded
are assumed, consider applying fuses or other physical safety measures.
(2) Recommended operating range
This is the range within which it is possible to obtain roughly the expected characteristics. For electrical characteristics, it is those that are
guaranteed under the conditions for each parameter. Even when these are within the recommended operating range, voltage and temperature
characteristics are indicated.
(3) Reverse connection of power supply connector
There is a risk of damaging the LSI by reverse connection of the power supply connector. For protection from reverse connection, take measures
such as externally placing a diode between the power supply and the power supply pin of the LSI.
(4) Power supply lines
In the design of the board pattern, make power supply and GND line wiring low impedance.
When doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and
analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns.
Similarly take pattern design into account for GND lines as well.
Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND pins, when using
electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for
various characteristics of the capacitors used.
(5) GND voltage
Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm that there are no pins
for which the potential becomes less than a GND by actually including transition phenomena.
(6) Shorts between pins and misinstallation
When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is installed erroneously, there
is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a power
supply or GND.
(7) Operation in strong magnetic fields
Be careful when using the LSI in a strong magnetic field, since it may malfunction.
(8) Inspection in set board
When inspecting the LSI in the set board, since there is a risk of stress to the LSI when capacitors are connected to low impedance LSI pins, be
sure to discharge for each process. Moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off the
power supply, perform the inspection, and remove it after turning off the power supply. Furthermore, as countermeasures against static electricity,
use grounding in the assembly process and take appropriate care in transport and storage.
(9) Input pins
Parasitic elements inevitably are formed on an LSI structure due to potential relationships. Because parasitic elements operate, they give rise to
interference with circuit operation and may be the cause of malfunctions as well as damage. Accordingly, take care not to apply a lower voltage
than GND to an input pin or use the LSI in other ways such that parasitic elements operate. Moreover, do not apply a voltage to an input pin
when the power supply voltage is not being applied to the LSI. Furthermore, when the power supply voltage is being applied, make each input
pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics.
(10) Ground wiring pattern
When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND pattern and small signal
GND pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the
pattern wiring and large currents do not cause the small signal GND voltage to change. Take care that the GND wiring pattern of externally
attached components also does not change.
(11) Externally attached capacitors
When using ceramic capacitors for externally attached capacitors, determine constants upon taking into account a lowering of the rated capacitance
due to DC bias and capacitance change due to factors such as temperature.
(12) Thermal shutdown circuit (TSD)
When the junction temperature reaches the defined value, the thermal shutdown circuit operates and turns a switch OFF. The thermal shutdown
circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI.
Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation.
(13) Thermal design
Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use.
REV. A
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-
sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
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use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no re-
sponsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-
tronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
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Appendix-Rev4.0
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