BD7220FV-C_技术文档

Datasheet

Precision Coulomb Counter /

Low Side Current Monitor

for High-current Applications

BD7220FV-C

General Description

Key Specifications

BD7220FV-C is a coulomb counter IC for high-current

applications. The product integrates a high-accuracy

operational amp, a current accumulation logic circuit and

a 16-bit ΔΣADC to perform current accumulation with

high precision. The current sense input supports shunt

resistors and output current sensors, and uses the SPI

communication interface. BD7220FV-C only requires SPI

commands to carry out the calibration necessary for

high-precision measurement, so it can also get current

accumulation information for battery state-of-charge

estimation.

 Input Voltage Range

VCC Input Voltage Range 4.5 V to 5.5 V

VDD Input Voltage Range 2.5 V to 5.5 V

 Operating Temperature

-40 °C to +125 °C

Applications

 Battery Current Sense for EV

 Electricity Storage Systems

 Automated Guided Vehicle (AGV)

 Robot

Package

Features

W (Typ) x D (Typ) x H (Max)

6.5 mm x 6.4 mm x 1.45 mm

 AEC-Q100 Qualified ^{(Note 1)}

 16-bit ΔΣADC

SSOP-B20

 Flexible Noise Filter (4 settings)

 Automatic Calibration via SPI

 High-accuracy Op-amp with 3 Gain Settings

(5 V/V, 25 V/V, 51 V/V)

 Supports Current Sensing Using Shunt Resistors

 Supports Current Sensing Using Current Output Type

Current Sensors

 SPI I/F (Optional CRC)

 Coulomb Counter Function with SPI External

Communication

 Accumulation Current Counter which Counts Charge

and Discharge Independently

SSOP-B20

 Adjustable Current Detection Interruption (3 settings)

 4 Operation Modes

(NORMAL, SLEEP, SSHDN, OFF)

 Wake Up Current Detection Function

 UVLO

(Note 1) Grade 1

Typical Application Circuit

5V

AMPOUT

ADINP

VCC

VREF15

VREFCAL

VREF25

VDD

CSB

SDI

VCC

SHDNB

SPI/IF

VREF15

VREFCAL

VREF25

SDO

SCK

VCC

ALARMB

VREF15

VCC

VREF15

INP

INN

INTB

Current

Sense

+

-

Alarm output

ΔΣ

ADC

Accumulator

Data Register

OSC

EXADIN

ADINM GND

VREF25

DGND

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Pin Configuration

VREF15

DGND

SCK

1

2

GND

20

19

18

17

16

15

14

13

12

11

VREFCAL

VCC

3

SDO

4

VREF25

ADINM

INN

SDI

5

CSB

6

INTB

7

INP

VDD

8

AMPOUT

ADINP

EXADIN

ALARMB

SHDNB

9

10

SSOP-B20 (TOP VIEW)

Pin Description

Pin No.

Pin Name

I/O

Function

LDO output for internal power

Digital ground

1

2

VREF15

DGND

SCK

O

-

SPI clock input

3

I

SPI data output

4

SDO

O

I

SPI data input

5

SDI

SPI chip select input

Event interrupt output open drain

Power supply for SPI I/F

Alarm output open drain

6

CSB

I

7

INTB

O

-

8

VDD

9

ALARMB

SHDNB

EXADIN

ADINP

AMPOUT

INP

O

I

Shutdown Input (H: operating, L: shutdown)

Delta sigma ADC select input

Delta sigma ADC monitor input

Internal amp output

10

11

12

13

14

15

16

17

18

19

20

I

O

I

Internal amp non-inverting input

Internal amp inverting input

INN

I

Delta sigma ADC reference input

Internal reference output

ADINM

VREF25

VCC

I

O

-

Power supply

Reference output for calibration in BD7220FV-C shipment process

Analog ground

VREFCAL

GND

O

-

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Application Example

SHDNB

VDD

EXADIN

VREF25

ADINM

INTB

ADINP

ALARMB

AMPOUT

INP

CSB

SDI

INN

SDO

SCK

VCC

VREF15

VREFCAL

GND

DGND

Block Diagram

AMPOUT

VREF25

ADINP

VCC

VREF15

VREFCAL

VDD

CSB

SDI

SDO

SCK

VCC

SHDNB

SPI/IF

VREF15

VREFCAL

VREF15

VREF25

VCC

ALARMB

VREF15

INP

INN

INTB

+

-

Alarm output

ΔΣ

ADC

Accumulator

Data Register

OSC

EXADIN

GND

ADINM

DGND

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Absolute Maximum Ratings (Ta = 25 °C)

Item

Symbol

Limit

Unit

Voltage Range1 (VCC, VDD)

Voltage Range2 (VREF15)

V_{AMR_1}

V_{AMR_2}

-0.3 to +7.0

-0.3 to +2.1

V

Voltage Range3

(VREF25, VREFCAL, INP, INN, EXADIN,

SHDNB, INTB, ALARMB, AMPOUT, ADINP,

ADINM, CSB, SDI, SDO, SCK)

V_{AMR_3}

-0.3 to +7.0

V

Maximum Junction Temperature

Storage Temperature Range

Tjmax

Tstg

150

°C

-55 to +150

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance ^{(Note 2)}

Thermal Resistance(Typ)

Parameter

Symbol

Unit

1s ^{(Note 4)}

2s2p ^{(Note 5)}

SSOP-B20

Junction to Ambient

Junction to Top Characterization Parameter ^{(Note 3)}

θ_JA

115.4

10

57.3

8

°C/W

Ψ_JT

(Note 2) Based on JESD51-2A (Still-Air)

(Note 3) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 4) Using a PCB board based on JESD51-3

(Note 5) Using a PCB board based on JESD51-7.

Layer Number of

Measurement Board

Material

Board Size

Single

FR-4

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Material

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

4 Layers

FR-4

Top

Copper Pattern

Bottom

Copper Pattern

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

Recommended Operating Condition

Limit

Item

Symbol

Unit

Max

Condition

Min

Typ

Voltage Range1 (VCC)

Voltage Range2 (VDD)

Operating Temperature

V_{OPR_1}

V_{OPR_2}

Topr

4.5

2.5

-40

5.0

3.3

5.5

V

+25

+125

°C

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Electrical Characteristics

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

VREF15

Output Voltage1

Output Voltage2

V_{O15_1}

V_{O15_2}

C_VO15

1.470

1.450

0.4

1.500

-

1.530

1.550

2.0

V

Io = 0 mA, Ta= +25 °C

Io = 0 mA, Ta= -40 °C to +125 °C

Effective Output Capacitance

μF

Recommended Nominal Capacitor:1 μF

VREF25

Output Voltage1

Output Voltage2

V_{O25_1}

V_{O25_2}

C_VO25

2.450

2.400

0.4

2.500

-

2.550

2.600

2.0

V

Io = 0 mA, Ta= +25 °C

Io = 0 mA, Ta= -40 °C to +125 °C

Recommended Nominal Capacitor:1 μF

Effective Output Capacitance

μF

OSC

Frequency1

Frequency2

Start up Time

f_{OSC_1}

f_{OSC_2}

8110

8028

-

8192

50

8274

8356

200

kHz

μs

Ta= +25 °C

Ta= -40 °C to +125 °C

t_WAKEOSC

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

Current Consumption

SHDNB = L, MODE_SEL [1:0] = 2'bXX

VREF15 = OFF, VREF25 = OFF

AMP = OFF, ΔΣADC = OFF

Shutdown Current 1_1

(OFF) = HSHDN

I_{QVB1_1}

I_{QVB1_2}

I_{QVB2_1}

I_{QVB2_2}

I_{QVB3_1}

I_{QVB3_2}

-

0

5

μA

OSC = OFF, Ta= +25 °C

SHDNB = L, MODE_SEL [1:0] = 2'bXX

VREF15 = OFF, VREF25 = OFF

AMP = OFF, ΔΣADC = OFF

OSC = OFF, Ta= -40 °C to +125 °C

SHDNB = H, MODE_SEL [1:0] = 2'b11

VREF15 = ON, VREF25 = OFF

AMP = OFF, ΔΣADC = OFF

Shutdown Current 1_2

(OFF) = HSHDN

10

Shutdown Current 2_1

(Soft Shutdown Mode) = SSHDN

20

40

μA

OSC = OFF, Ta= +25 °C

SHDNB = H, MODE_SEL [1:0] = 2'b11

VREF15 = ON, VREF25 = OFF

AMP = OFF, ΔΣADC = OFF

OSC = OFF, Ta= -40 °C to +125 °C

SHDNB = H, MODE_SEL [1:0] = 2'b01

VREF15 = ON, VREF25 = ON

AMP = ON, ΔΣADC = ON

Shutdown Current 2_2

(Soft Shutdown Mode) = SSHDN

20

200

3.75

7.50

μA

Operating Current 1_1

(NORMAL Mode)

2.50

mA

OSC = ON, Ta= +25 °C

SHDNB = H, MODE_SEL [1:0] = 2'b01

VREF15 = ON, VREF25 = ON

AMP = ON, ΔΣADC = ON

Operating Current 1_2

(NORMAL Mode)

OSC = ON, Ta= -40 °C to +125 °C

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Electrical Characteristics – continued

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b00,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

Operating Current 2_1

(SLEEP Mode)

I_{QVB4_1_1}

-

700

1050

μA

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= +25 °C

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b00,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

Operating Current 2_2

(SLEEP Mode)

I_{QVB4_1_2}

I_{QVB4_2_1}

I_{QVB4_2_2}

I_{QVB4_3_1}

I_{QVB4_3_2}

I_{QVB4_4_1}

I_{QVB4_4_2}

-

700

600

540

500

1250

μA

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= -40 °C to +125 °C

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b01,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

Operating Current 3_1

(SLEEP Mode)

900

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= +25 °C

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b01,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

Operating Current 3_2

(SLEEP Mode)

1100

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= -40 °C to +125 °C

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b10,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

Operating Current 4_1

(SLEEP Mode)

810

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= +25 °C

SHDNB = H, MODE_SEL [1:0] = 2'b10,

SLEEP_INTERVAL [1:0] = 2'b10,

SLEEP_SAMPLING_TIME [1:0] = 2'b00,

VREF15 = ON, VREF25 = Intermittent Operation

AMP = Intermittent Operation,

ΔΣADC = Intermittent Operation, OSC = ON,

Ta= -40 °C to +125 °C

SHDNB=H, MODE_SEL[1:0]=2'b10,

SLEEP_INTERVAL[1:0]=2'b11,

SLEEP_SAMPLING_TIME[1:0]=2'b00,

VREF15=ON, VREF25=Intermittent Operation

AMP=Intermittent Operation,

ΔΣADC=Intermittent Operation, OSC = ON,

Ta= +25 °C

SHDNB=H, MODE_SEL[1:0]=2'b10,

SLEEP_INTERVAL[1:0]=2'b11,

SLEEP_SAMPLING_TIME[1:0]=2'b00,

VREF15=ON, VREF25=Intermittent Operation

AMP=Intermittent Operation,

Operating Current 4_2

(SLEEP Mode)

1010

Operating Current 5_1

(SLEEP Mode)

750

Operating Current 5_2

(SLEEP Mode)

950

ΔΣADC=Intermittent Operation, OSC = ON,

Ta= -40 °C to +125 °C

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Electrical Characteristics – continued

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

AMP Block

Analog Input Valtage Range 1

Analog Input Valtage Range 2

Analog Input Valtage Range 3

V_AIN1

V_AIN2

-200

-80

-40

-

+400

+80

+40

1.5

mV

ms

AMP_GAIN [1:0] = 2'b00(Gain = 5 V/V)

AMP_GAIN [1:0] = 2'b01(Gain = 25 V/V)

AMP_GAIN [1:0] = 2'b10(Gain = 25 V/V)

V_AIN3

AMP_GAIN [1:0] = 2'b11(Gain = 51 V/V)

Gain Setting Time

t_GAINSET

ADC Block

Resolution

-

16

bit

ms

V

MCIC_R [1:0] = 2'b00

(Down sampling value = 32)

MCIC_R [1:0] = 2'b01

(Down sampling value = 128)

MCIC_R [1:0] = 2'b10

(Down sampling value = 256)

MCIC_R [1:0] = 2'b11

ADC Conversion Time 1

ADC Conversion Time 2

ADC Conversion Time 3

ADC Conversion Time 4

EXADIN Valtage Range

t_CONV1

t_CONV2

t_CONV3

t_CONV4

V_EXADIN

0.20

0.80

1.60

6.40

0.5

0.25

1.00

2.00

8.00

-

0.30

1.20

2.40

9.60

4.5

(Down sampling value = 1024)

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

UVLOꢀ(VCC)

VCC UVLO Detect Voltage

V_{CC_UVLOD}

V_{CC_UVLOR}

2.700

2.717

2.800

3.000

2.900

3.283

V

VCC = Sweep down

VCC = Sweep up

VCC UVLO Release

UVLOꢀ(VREF15)

VREF15 UVLO Detect Voltage

V_{REF15_UVLOD}

1.352

1.380

1.408

V

VREF15 = Sweep down

UVLOꢀ(VDD)

VDD UVLO Detect Voltage

VDD UVLO Release

V_{DD_UVLOD}

V_{DD_UVLOR}

1.550

1.650

1.700

1.800

1.850

1.950

V

VDD = Sweep down

VDD = Sweep up

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Electrical Characteristics - continued

(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 5.0 V, VDD = 3.3 V)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

IO Interface

SHDNB Input "H" Level

V

VCCx0.7

-

VCC+0.3

V

IH_SHDNB

SHDNB Input "L" Level

V

-0.3

-1

0

+VCCx0.3

+1

IL_SHDNB

SHDNB Input Leak Current

INTB Output "L" Level Voltage1

INTB Output "L" Level Voltage2

INTB Output Off Leak Current

ALARMB Output "L" Level Voltage1

ALARMB Output "L" Level Voltage2

I_{OFF_SHDNB}

μA

V

V_{OL_INTB1}

V_{OL_INTB2}

0.4

I_O= 1 mA, Ta= +25 °C

0

0.5

V

I_O= 1 mA, Ta= -40 °C to +125 °C

INTB = 5.5 V

I_{OLK_INTB}

-1

0

+1

μA

V

V_{OL_ALARMB1}

V_{OL_ALARMB2}

I_{OLK_ALARMB}

0.4

I_O= 1 mA, Ta= +25 °C

I_O= 1 mA, Ta= -40 °C to +125 °C

ALARMB = 5.5 V

0

0.5

V

ALARMB Output Off Leak Current

-1

+1

μA

SPI Bus Interface

CSB, SDI, SCK Input "H" Level Voltage

CSB, SDI, SCK Input "L" Level Voltage

SDO Output "L" Level Voltage

SDO Output "H" Level Voltage

CSB, SDI, SCK Input Leak Current

SDO Output Off Leak Current

CSB-SCK Setup Time

V

VDDx0.7

-0.3

0

-

VDD+0.3

V

IH_SPI

V

+VDDx0.3

IL_SPI

V_{OL_SDO}

V_{OH_SDO}

I_{OLK_SPI}

I_{OLK_SDO}

t_CSS

-

0.4

V

I_OL= 1 mA

VDD-0.2

-1

-

VDD

V

I_OH= -100 μA

0

-

+1

μA

ns

-1

+1

1000

150

-

SCK-CSB Hold Time

t_CSH

-

SCK "H" Pulse Width Time

SCK "L" Pulse Width Time

SCK-SDI Setup Time

t_WH

-

t_WL

-

t_DIS

-

SCK-SDI Hold Time

t_DIH

-

400

-

SCK-SDO Delay Time

t_DOD

-

CSB "H" Pulse Width Time

t_CS

500

-

t_CSS

t_CS

CSB

SCK

SDI

t_WHt_WL

t_CSH

t_DIS

t_DIH

t_DOD

SDO

Figure 1. SPI Timing Chart

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Typical Performance Curve (Reference Data)

20

Gain5

15

10

5

Gain25

Gain51

0

-5

-10

-15

-20

-50

0

50

100

150

Temperature [℃]

Figure 2. Output Offset vs Temperature

(VCC = 5 V)

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Description of Blocks

1.

Current Accumulator

1.1

Summary

This product performs accumulation current operation (Coulomb count) by monitoring the battery charge/discharge current.

The Coulomb count value obtained is used for battery state-of-charge estimation. It can obtain both the current accumulation

level and the current value itself.

1.1.1

Features

Reading current converted to voltage by an external resistor as a digital value

Accumulation current counters which monitors the charge/discharge current value

Independent monitoring of charge and discharge values

Current value monitoring via SPI

Fixed-interval average current read function (interval can be adjusted in 4 stages)

Overwrite function of accumulated current data via SPI I/F

1.1.2

Composition

The Current Accumulator block is comprised of 3 sub-blocks. (See figure 1-1)

Differential op-amp (AMP)

The AMP sub-block monitors the voltage converted by the external resistor R_SNSat the INP and INN pins. The voltage

difference between INP and INN is then amplified to a voltage suitable for the ΔΣADC input.

Address 00h (AMP_GAIN [1:0]) can be used to adjust voltage amplification gain to 5 V/V, 25 V/V, or 51 V/V. Take note that

the input voltage range changes with this gain setting.

ΔΣADC

The 16-bit ΔΣADC has an analog-to-digital conversion rate of 4 kHz using the standard setting.

A digital filter determines the ADC’s output rate and frequency response. This filter has 4 settings, accessible through

address 00h (MCIC_R [1:0]). Please set an appropriate value considering the influence of the current’s frequency response,

agitation noise, and the like.

Accumulator

The accumulator operates by using the current value in digital form from the ΔΣADC output.

Chapter 1.3 details the calculation function of the Accumulator, while Chapter 3 describes the interrupt function.

VREF25

VCC

VREF15

INP

INN

+

-

R_SNS

ΔΣ

ADC

Accumulator

VREF25

C

B

A

Figure 1-1. Accumulation Current Block Diagram

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1.2

Register Structure

Regarding resister structure for current measurement, refer to Figure 1-2.

Measurement

or Calcuration

Measurement

Current

Current Detection

Interrupt Threshold

Voltage

16bit

OCURTHR1_DIR + OCURTHR1[14:0]

OCURTHR2_DIR + OCURTHR2[14:0]

OCURTHR3_DIR + OCURTHR3[14:0]

18bit

Possible to select the bit width

of valid data (18 to 11 bit)

from measured 18 bit data.

(lower 0 to 7 bit can be masked)

Mask Bit Select

11-18ｂ

CCNTD_MASK[2:0]

8bit

Current Value

CURCD_DIR

+ CURCD[14:0]

Wake Up Current Detection

WAKE_CURCD_TH[7:0]

Relax State Detection

REX_CURCD_TH[7:0]

Discharge

Accumulation

Current

Charge

Accumulation

Current

Charge+Discharge

Accumulation

Current

Accumulation Current Detection

CC_BATCAP1_TH[23:0]

CC_BATCAP2_TH[23:0]

CC_BATCAP3_TH[23:0]

CC_BATCAP4_TH[23:0]

24bit

Fixed Average Current

AVE_CURCD_DIR

+ AVE_CURCD[14:0]

DIS_CCNTD[31:0]

CHG_CCNTD[31:0]

CC_CCNTD[31:0]

Figure 1-2. Register Structure for Current Measurement

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BD7220FV-C

1.3

Function Description

Current Measurement

1.3.1

BD7220FV-C measures current by monitoring the difference in voltage between the ends of the external current sense

resistor (R_SNS) connected to the differential op-amp inputs INP and INN. The op-amp amplifies the differential input biased on

2.5 V (VREF25) as a reference voltage. The amplified voltage is then used as input to the ΔΣADC. For example, for a

difference of 100 mV between the INP and INN pins and a 5 V/V gain setting:

2.5 [V] + 100 [mV] × 5 = 3.0 [V]

In this calculation, 3.0 V is input to the ΔΣADC. (ADINP = 3.0 V, ADINM = 2.5 V, ΔV = 0.5 V)

At shipment, the ΔΣADC input voltage is defined as ΔV = 4.5 V. (ADINP=0.25 V to 4.75 V)

퐴: ΔΣ 퐼푛푝푢푡 퐿푆퐵 푉표푙푡푎푔푒 = 4.5 ÷ 2^ꢀ6≈ ±ꢁ8.ꢁꢁ455 [µV]

The CURCD register indicates the current value and is defined as [sign bit] + [15 bits] based on the computed LSB voltage.

Table 1-1 shows current unit information for each gain setting.

The LSB voltage input for the differential amplifier (Figure 1-1C) is the ΔΣADC input LSB voltage divided by the amplifier gain

setting (Figure 1-1B). The current flowing through the sense resistor R_SNSis calculated using the 1LSB voltage and the

sense resistor value.

The data in Table 1-1 is calculated with the assumption that R_SNS= 0.2 mΩ. If, for example, R_SNS= 0.1 mΩ, the current value

(and, the measurement current range is same) in the table 1-1 is doubled.

Table 1-1. Current Monitor Unit

Available

Measurement

Current Range

OPamp Input

1LSB Current

(@R_SNS= 0.2 mΩ)

[mA]

ΔΣADC Input

1LSB Voltage

[μV]

OPamp Input

Voltage Range

[mV]

AMP_GAIN [1:0]

Gain

[times]

1LSB Voltage

(INP-INN)

[μV]

register

(@R_SNS= 0.2 mΩ)

[A]

2'b00

2'b01, 2'b10

2'b11

5

68.66

13.73

2.75

1.35

68.66

13.73

6.73

-200 to +400

±80

-1000 to +2000

25

51

±400

±200

±40

Op-amp input LSB voltage

LSB current

Current measurement range

= ΔΣADC input LSB voltage ÷ gain setting value

= Op-amp input LSB voltage ÷ external current sense resistance (R_SNS

= Op-amp input voltage range ÷ external current sense resistance (R_SNS

)

Figure 1-3 shows the structure of the CURCD register.

The MSB indicates the direction of the current and shows a current value using the remaining 15 bits.

Sign

CURCD_H

CURCD_L

15 14

8

7

0

Figure 1-3. CURCD Register

When the current is 100 A, CURCD reads 1C71 [Hex] under the 25 V/V gain setting.

100 [A] ÷ 13.7329 [mA] ≈ 7281.78 ≈ 7281 [DEC] = 1C71 [HEX]

= 15’h1C71

The lower bits that comprise the fractional value will be truncated.

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BD7220FV-C

1.3.2

Unit of Accumulation Current

BD7220FV-C can calculate and output accumulation current value based on the measured current. To enable this function,

please set the CCNTEN register (address 00h) = 1. (Refer to 1.3.1 Current Measurement) The accumulation current value

can be found in the 32-bit register CC_CCNTD. The LSB and MSB values are computed as below. The accumulation current

value is calculated with higher precision than the CC_CCNTD register’s LSB value.

(

퐿푆퐵 푓표푟 푖푛푡푒푟푛푎푙 푎푐푐푢푚푢푙푎푡푖표푛 푐푢푟푟푒푛푡 = 푐푢푟푟푒푛푡 퐿푆퐵 × 퐴퐷 푐표푛푣푒푟푠푖표푛 푡푒푟푚 [s] ÷

)

3ꢁ00

−6

(

)

푒푥. )퐺퐴퐼푁 = 5 ∶ ꢁ8.ꢁꢁ [mA] × 250 × 10 ÷ 3ꢁ00 ≈ 4.77 [nAh]

퐿푆퐵 푓표푟 퐶퐶_{퐶퐶푁푇퐷}푟푒푔푖푠푡푒푟 =

푖푛푡푒푟푛푎푙 푎푐푐푢푚푢푙푎푡푖표푛 푐푢푟푟푒푛푡 퐿푆퐵 × 푖푛푡푒푟푛푎푙 푎푑푗푢푠푡푚푒푛푡(ꢁ푏푖푡푠)

푒푥. )퐺퐴퐼푁 = 5 ∶ 4.77 [nAh] × 2⁶≈ 0.3052 [µAh]

푀푆퐵 푣푎푙푢푒 푓표푟 퐶퐶_{ꢂꢂꢃꢄꢅ}푟푒푔푖푠푡푒푟 = 퐶퐶_{ꢂꢂꢃꢄꢅ}푟푒푔푖푠푡푒푟 퐿푆퐵 × 2^ꢆꢀ= ꢁ55.3ꢁ [Ah]

Figure 1-4 shows structure of the CC_CCNTD register and approximate accumulation current.

CC_CCNTD register

for internal calclation

CC_CCNTD_3

81.92

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

31

24 23

5.12

16 15

20m

8

7

0

655.4

78μ

4.9μ

0.3μ

4.7n

[Ah]

320ｍ

1.25ｍ

Figure 1-4. Structure of CC_CCNTD Register (CC_UNDIV=0)

To cancel the variation of current LSB in each amplifier gain setting, the current value can be scaled and accumulated in

CC_CCNTD register in the logic. This makes the LSB of accumulation current constant regardless of amplifier gain.

For example, when current of 70 mA flows in R_SNS, the CURCD register reading is 15’h0001 under a 5 V/V gain setting.

Under a 25 V/V setting, CURCD reading is 15’h0005. At 25 V/V gain, not to accumulate 5 times larger from actual value, the

logic accumulates the CURCD value divided by 5 to get the equivalent value at 5 V/V gain. At 51 V/V, the divisor is 10.2. The

CC_UNDIV register (address 01h) allows the user to enable or disable CURCD value scaling. Using scaling (CC_UNDIV =

“0”) introduces a small amount of error but allows the user to change three amplifier gain settings. Disabling scaling

(CC_UNDIV = “1”) requires that the amplifier setting be fixed, but ensures that errors are not introduced. However, the

accumulation current capacity changes depending on the gain setting. Comparing to the value of 5 V/V setting, it is 1/5 when

the setting is 25 V/V, and 1/10.2 when the setting is 51 V/V. It is possible to write the value of accumulation current into

CC_CCNTD resister. Please execute write operation after setting “0” to CCNTEN resister and current accumulating is

disabled. When CCNTEN resister is “0”, update of accumulation current is discarded.

Table 1-2. Unit of CC_CCNTD Register Accumulation (R_SNS= 0.2 mΩ)

AMP_GAIN [1:0]

2'b00(5 V/V)

CC_UNDIV = 0

(Variable Gain)

2'b01(25 V/V)

2'b10(25 V/V)

2'b11(51 V/V)

―

UNIT

CC_UNDIV = 1

(Fixed Gain)

2'b01(25 V/V)

2'b10(25 V/V)

0.95

2'b00(5 V/V)

2'b11(51 V/V)

Internal Accumulation 1LSB

CC_CCNTD_0 LSB

CC_CCNTD_1 LSB

CC_CCNTD_2 LSB

CC_CCNTD_3 LSB

CC_CCNTD_3 MSB

Maximum Accumulation Current

4.77

0.3052

78.125

20.00

5.12

655.36

1310.41

0.47

0.0299

7.659

1.96

0.50

64.25

128.47

[nAh]

[μAh]

[mAh]

[Ah]

0.0610

15.625

4.00

1.02

131.07

262.08

[Ah]

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BD7220FV-C

Unit of Accumulation Current – continued

In addition, BD7220FV-C can accumulate charging accumulation current (via CHG_CCNTD) and discharging accumulation

current (via DIS_CCNTD) separately. Please refer to Figure 1-5 and Figure 1-6 about the structure of CHG_CCNTD and

DIS_CCNTD resister and their relationship with CC_CCNTD.

CHG_CCNTD is shifted 2 bits to the left from CC_CCNTD. Accumulation scaling in internal logic for CHG_CCNTD and

DIS_CCNTD is the same as in CC_CCNTD, so the unit of accumulation current is the same regardless of the amplifier gain

setting. Thus, the value of LSB is greater, but CHG_CCNTD and DIS_CCNTD capacities are 4 times that of CC_CCNTD.

The maximum battery capacity of CC_CCNTD is around 1310[Ah], so CHG_CCNTD and DIS_CCNTD can accumulate up to

5240[Ah].

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

31

24 23

16 15

8

7

0

CHG_CCNTD_3

CHG_CCNTD_2

CHG_CCNTD_1

CHG_CCNTD_0

31

24 23

16 15

8

7

0

Figure 1-5. Relation between CC_CCNTD and CHG_CCNTD

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

31

24 23

16 15

8

7

0

DIS_CCNTD_3

DIS_CCNTD_2

DIS_CCNTD_1

DIS_CCNTD_0

31

24 23

16 15

8

7

0

Figure 1-6. Relation between CC_CCNTD and DIS_CCNTD

COUNT

VALUE

■Charge and Discharge Accumulation

●Charge Accumulation

No Charge or

DIscharge

▲Discharge Accumulation

Charge

Discharge

Charge

No Charge

or Discharge

TIME

Figure 1-7. Difference between charge accumulation current and charge/discharge accumulation current

The values of CC_CCNTD, CHG_CCNTD and DIS_CCNTD can be cleared by writing “1” to their reset registers.

Resetting is valid regardless of the CCNTEN setting. The reset register is automatically cleared to “0” after writing “1”.

Table 1-3. CCNTD Registers and Reset Registers

Register Name

CC_CCNTD

CHG_CCNTD

Address

Bit

Bit Name

Function

Charge and discharge accumulation current

Charge accumulation current only

Discharge accumulation current only

Reset CC_CCNTD

17h to 1Ah [7] to [0] CC_CCNTD [31:0]

1Bh to 1Eh [7] to [0] CHG_CCNTD [31:0]

1Fh to 22h [7] to [0] DIS_CCNTD [31:0]

DIS_CCNTD

CC_TRG_RST_CMD

02h

[0]

[1]

[2]

CCNTRST

CHG_CCNTD_RST

DIS_CCNTD_RST

Reset CHG_CCNTD

Reset DIS_CCNTD

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BD7220FV-C

1.3.3

Fixed-Interval Average Current

BD7220FV-C can output average current at fixed intervals set using registers. Moving average is not used.

The AVE_CURCD_DIR register denotes the current direction and the AVE_CURCD [14:0] register represents the current

value. The fixed interval is determined by the ΔΣADC digital filter setting (address 00h: MCIC_R [1:0]), OSR setting (address

01h: OSR [1:0]), and sampling time setting (address 01h: AVE_CURCD_COUNT [1:0]). Table 1-4 contains details regarding

the fixed interval setting.

For MCIC_R [1:0] = 2’b00, OSR [1:0] = 2’b00, and AVE_CURCD_COUNT [1:0] = 2’b10, ADC sampling time is 0.25 ms and

the fixed interval is 0.25 ms x 64 = 16 ms.

Table 1-4. Fixed interval setting (listed by OSR [1:0] setting)

OSR [1:0] = 2'b00(32) or 2'b11(32)

MCIC_R [1:0]

2'b00(32) 2'b01(128) 2'b10(256) 2'b11(1024)

ADC Conversion Timeꢀ[ms]

0.25

1

2

8

Mearsurement

Averaging Time[ms]

Count

4

16

AVE_CURCD_COUNT [1:0] = 2'b00

AVE_CURCD_COUNT [1:0] = 2'b01

AVE_CURCD_COUNT [1:0] = 2'b10

AVE_CURCD_COUNT [1:0] = 2'b11

1

4

8

32

128

512

1024

16

32

64

128

16

32

64

128

256

(Note) "Averaging Time" = "ADC Conversion Time" x "Muasurement Count"

OSR [1:0] = 2'b01(128)

MCIC_R[1:0]

2'b00(32) 2'b01(128) 2'b10(256) 2'b11(1024)

ADC Conversion Timeꢀ[ms]

0.25

0.5

2

Mearsurement

Averaging Time[ms]

Count

4

16

AVE_CURCD_COUNT [1:0] = 2'b00

AVE_CURCD_COUNT [1:0] = 2'b01

AVE_CURCD_COUNT [1:0] = 2'b10

AVE_CURCD_COUNT [1:0] = 2'b11

1

4

1

4

2

8

32

128

256

64

128

16

32

16

32

64

(Note) "Averaging Time" = "ADC Conversion Time" x "Muasurement Count"

OSR [1:0] = 2'b10(512)

MCIC_R[1:0]

2'b00(32) 2'b01(128) 2'b10(256) 2'b11(1024)

ADC Conversion Timeꢀ[ms]

0.25

0.5

Mearsurement

Averaging Time[ms]

Count

4

16

AVE_CURCD_COUNT [1:0] = 2'b00

AVE_CURCD_COUNT [1:0] = 2'b01

AVE_CURCD_COUNT [1:0] = 2'b10

AVE_CURCD_COUNT [1:0] = 2'b11

1

4

1

4

1

4

2

8

32

64

128

16

32

16

32

16

32

(Note) "Averaging Time" = "ADC Conversion Time" x "Muasurement Count"

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BD7220FV-C

1.3.4

Bit Mask Function of Accumulation Current

The current measured by BD7220FV-C is 18 bits valid data and it is stored in the 16 bits CURCD register (see 1.3.1. Current

Measurement).In the default setting, 16 bits’ width of current value same with CURCD register is accumulated to

CC_CCNTD resister, CHG_CCNTD resister and DIS_CCNTD resister, and it can select to mask lower bits of current (fixing

lower bits to “0” in accumulation) by setting CCNTD_MASK resister. With this bit mask function, it is possible to reduce the

affection from noise in measuring minute current and accumulation.

Note that this function fixing lower bits to “0” in accumulation. This means current is rounded down when sign is positive, and

current is rounded up when sign is negative since it is expressed by two’s complement. And, complement by user’s MCU is

recommended, because accumulation current has constant error following to mask lower bits of current. (see next page)

Note that this function affects only the accumulation from CURCD to CC_CCNTD/CHG_CCNTD/DIS_CCNTD. This does not

affect CURCD itself. CURCD does not have bit mask function and so always contains the full 16 bits of data.

Fixed time average

16bits Fixed

CURCD_DIR

AVE_CURCD_DIR

+ AVE_CURCD[14:0]

+ CURCD[14:0]

18bits output from ΔΣADC

ΔΣADC

38bit

32bit

CC_CCNTD[31:0]

CC_CCNTD(internal)

+

CCNTD_MASK[2:0]

38bit

32bit

CHG_CCNTD[31:0]

000：7bits Mask(11bits valid)ꢀ100：3bits Mask(15bits valid)

001：6bits Mask(12bits valid)ꢀ101：2bits Mask(16bits valid)

010：5bits Mask(13bits valid)ꢀ110：1bits Mask(17bits valid)

011：4bits Mask(14bits valid)ꢀ111：No Mask(18bits valid)

CHG_CCNTD(Internal)

38bit

32bit

DIS_CCNTD[31:0]

DIS_CCNTD(Internal)

Image of bits mask

Sign

CURCD_H

CURCD_L

Accumulation with selectable bit width from 11bits to 18bits

Sign

15 14

8

7

0

8

7

0

Selectable lower 8bits masking

Example of Internal 18bits valid data

Figure 1-8. Bit Mask Function of Accumulation Current

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BD7220FV-C

1.3.4

Bit Mask Function of Accumulation Current - continued

This is the example of CCNTD error complement with bit mask function.

(1) Adding manual offset to CURCD

In the case that measuring minute current value is less than ±1LSB of bit mask, positive sign current data becomes zero

and negative sign current data becomes –LSB with bit mask function. Adding manual offset (OFST10: address0Bh) to

shift CURCD only positive sign data, current data becomes zero and it saves unintended current accumulation with

measuring minute current. But it needs CCNTD error complement, because this offset is added constantly.

Figure 1-9. Image of Adding Manual Offset to CURCD

(2) Adding error complement to CCNTD

Below is the formula of CCNTD error complement for (1) CURCD manual offset and for increasing lower bits of bit mask

function.

Table 1-5. Formula of CCNTD Error Complement

item

Resistor

Formula of Error Complement

{ -OFST × (TC / AD_conversion_term) / internal_bits_adjustment } = { -OFST × 4000 / 2⁶

CC_CCNTD

}

Complement of CURCD

manual offset

CHG_CCNTD { -OFST × (TC / AD_conversion_term) / internal_bits_adjustment } = { -OFST × 4000 / (2⁶/ 2²) }

DIS_CCNTD { -OFST × (TC / AD_conversion_term) / internal_bits_adjustment } = { -OFST × 4000 / (2⁶/ 2²) }

CC_CCNTD

{ 2^N-3× (TC / AD_conversion_term) / internal_bits_adjustment } = { 2^N-3× 4000 / 2⁶

}

Complement of bit mask

function

CHG_CCNTD { 2^N-3× (TC / AD_conversion_term) / internal_bits_adjustment } = { 2^N-3× 4000 / (2⁶/ 2²) }

DIS_CCNTD { 2^N-3× (TC / AD_conversion_term) / internal_bits_adjustment } = { 2^N-3× 4000 / (2⁶/ 2²) }

(Note) OFST: Manual Offset Value, TC: CCNTD Read Term, N: Bit Mask Width

(Note) Condition: N > 2, CC_UNDIV=1, CCNTD Read Term = 1 [s]

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BD7220FV-C

1.3.5

Setting of ΔΣADC Digital Filter

The ΔΣADC digital filter can be set to one of four filter characteristics depending on the purpose. Using the wideband filter

makes it possible to measure steep current changes. While this is not possible using the narrowband filter, using the

narrowband filter helps suppress environmental noise.

The characteristic of the Digital Filter is changed using MCIC_R register (address 00h MCIC_R [1:0]). Because the

conversion time depends on the MCIC_R register setting, attention is necessary. (Refer to Table 1-6, Table 1-7)

ADC sampling period (AD_SAMP)

-Time to convert 1 sampling. The average current of this period is output to CURCD register, and accumulated to

CC_CCNTD register.

ADC conversion latency (AD_LATE) consists of the following wait times.

-Transaction time from OFF to ON in intermittent action

-Reshuffle time for EXADIN pin input voltage measurement action

-After calibration, time to convert initial data from ΔΣADC startup condition

During this period, it cannot output measurement current.

Table 1-6. ADC Sampling Period [ms] (MCIC_R [1:0] / OSR [1:0])

Address 01h

Address 00h

MCIC_R[1:0]

OSR[1:0]

2'b00(32)

2'b11(32)

2'b01(128) 2'b10(512)

2'b11(1024)

2'b10(256)

2'b01(128)

2'b00(32)

8

2

1

2

0.5

0.25

0.5

0.25

Table 1-7. ADC Conversion Latency [ms] (MCIC_R [1:0] / OSR [1:0])

Address 01h

Address 00h

MCIC_R [1:0]

OSR [1:0]

2'b00(32)

2'b11(32)

96.5

2'b01(128) 2'b10(512)

2'b11(1024)

2'b10(256)

2'b01(128)

2'b00(32)

24.5

6.5

3.5

1.5

6.5

2.5

1.5

24.5

12.5

3.5

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BD7220FV-C

2.

Operation Modes

Features

2.1

Automatic power on by supplying input voltage (VCC)

Recall of OTP memory automatically in power on sequence

High accuracy of calculation and accumulation of current in the Normal mode

Low current consumption thanks to intermittent operation of AMP and ΔΣADC in SLEEP mode

(The timing of the intermittent operation and ON time duration can be set by register)

Retention of internal registers in SSHDN mode

SHDNB pin which can turn all blocks off (OFF state, data in internal registers are cleared)

2.2

Structure

BD7220FV-C starts to operate as soon as input power is supplied.

After the reference voltage turns on (WAKE), OTP settings (including calibration settings) are recalled. Then, BD7220FV-C

becomes ready for SPI communication (IDLE). With finished recall from OTP, “1” is set to OTP_DL_FIN register. There are

three other operating modes from the IDLE state. Using SPI commands, it is possible to freely change between these modes.

After 0.3ms passed

from WAKE to OTP

transition

NORMAL

After 1.2ms passed

from OFF to WAKE

transition

M

E

O

D

)

E

e

(SHDNB = L)

or (VCC < 2.8V)

or (VREF15 < 1.38V)

The voltage is Typ value

(OTP Down Load)

t

_

o

S

N

(

E

L

M

"

O

=

1

"

D

0

1

"

0

=

_

"

(

L

S

E

N

o

"

E

H

S

_

1

L

l

=

”

t

=

e

a

E

=

E

D

(SHDNB = H)

and (VCC > 3.0V)

and (VREF15 > 1.43V)

The voltage is Typ value

"

)

n

L

0

1

N

g

I

i

B

O

F

_

s

"

A

l

(

M

T

N

a

L

S

n

r

o

D

_

C

t

_

P

e

t

)

n

S

I

T

O

L

WAKE

OTP

IDLE

OFF

SLEEP

M

O

)

D

e

t

E

o

_

)

S

N

e

t

(

E

"

o

L

0

=

N

1

(

"

1

"

=

1

L

"

1

"

E

(

N

=

S

L

E

_

o

t

E

e

S

D

)

_

O

E

M

D

O

M

SSHDN

MODE_SEL="10" (Note)

(Note) VDD > 2.5V is required to input SPI commands.

Figure 2-1. Operating Modes Transition Diagram

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Operating Modes Transition Diagram and Modes Structure - continued

NORMAL mode (MODE_SEL [1:0] = “01”)

AMP and ΔΣADC are ON in this mode. The current is measured and the value is accumulated continuously with high

accuracy.

SLEEP mode (MODE_SEL [1:0] = “10”)

AMP, ΔΣADC and VREF25 operate intermittently and the current consumption is reduced. The current cannot be measured

during off time but the accumulation error can be reduced by accumulating a certain fixed value during off time. Using the

SLEEP_CC_SEL register, the fixed accumulation value can be set to:



Average current measured during ON time

Last measured current during ON time

This mode is valid for systems when current do not change frequently. Please refer to the Figure 2-3 for the detailed

operation timing.

During intermittent operation, ON time to OFF time ratio in an intermittent period can be set through SLEEP_INTERVAL (03h

CC_SET3 [3:2]), and the number of measurement times in ON time can be set through SLEEP_SAMPLING_TIME [1:0] (03h

CC_SET3 [5:4]). Each register has 4 settings. Note that as the number of measurement times increase by setting

SLEEP_SAMPLING_TIME register, ON time is extended proportionally.

SSHDN mode (MODE_SEL [1:0] = “11”)

Only VREF15, power supply for internal digital circuit, is ON. Internal register settings can be retained by VREF15. Current

consumption of BD7220FV-C can be minimized in SSHDN as all blocks other than VREF15 are turned off.

Table 2-1 describes which blocks are turned ON and OFF in each operating mode.

Table 2-1. State of Blocks under each Operating Mode

SHDNB

(Pin)

OSC

SPI

MODE

MODE_SEL[1:0]

VREF15 VREF25

AMP

ΔΣADC

(8.192MHz) access

OFF

( VCC < 2.8V )

OFF

( SHDNB = L )

WAKE

(Reference Wake-up)

OTP

-

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

Invalid

Valid

-

L

-

H

-

ON

(OTP Auto Loading)

IDLE

-

ON

NORMAL

SLEEP

2'b01

2'b10

2'b11

ON

Valid

Inter-

mittent

Inter-

mittent

Inter-

mittent

ON

Valid

SSHDN

(Soft Shutdown)

OFF

Valid

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2.3

Function Description

2.3.1 NORMAL Mode

BD7220FV-C enters NORMAL mode when MODE_SEL [1:0] (00h CC_SET1 [1:0]) is set to “01”. VREF25, AMP, ΔΣADC and

OSC turn on and start current measurement when in Normal mode. The actual time for current measurement from writing to

the register depends on INI_WAIT [1:0], MCIC_R [1:0] and OSR [1:0] settings.

The INI_WAIT register configures the time delay for VREF25 and AMP startup. The lead time for initial data conversion after

ΔΣADC turns on is set by the MCIC_R and OSR registers. Please refer to Table 1-6.

When INI_WAIT [1:0] = 2’b00 (1.5 ms), MCIC_R [1:0] = 2’b00 (down sampling value = 32), and OSR [1:0] = 2’b00, the actual

lead time to measure current is 5.0 ms.

To enable the function for accumulating current, “1” needs to be written to CCNTEN. The current can be measured and

CURCD register is updated even when the CCNTEN register value is “0”, but CC_CCNTD, CHG_CCNTD and DIS_CCNTD

registers are not updated.

VCC

SHDNB

VDD

SHDNB reset voltage

SHDNB>VCC*0.7

Start to turn on at SHDNB reset

VCC>3.00V (rise)

BGR (Internal reference)

VCC_UVLO (Internal signal)

VREF15

Internal Delay

(Typ=300μs)

VREF15>1.43V (rise)

VREF15UVLO (Internal signal)

LOGIC_RESET (Internal signal)

OSC (Internal signal)

Operating mode

VDD_UVLO (Internal signal)

Register setting

LOGIC_RESET = VCC_UVLO ∩ VREF15_UVLO

OTP

NORMAL

WAKE

IDLE

OFF

Internal Delay

(Typ=1.2ms)

OTP Recall

(Typ=300μs)

VDD>1.80V (rise)

Operating mode=IDLE state ∩ VDD_UVLO=H: SPI communication is valid

Register

setting

SPI communication is invalid

2'bXX

2'b00

2'b01

MODE_SEL[1:0]

CCNTEN (Internal signal)

WAIT time

CHG_TERM

default=3.0ms+0.5ms

INI_WAIT[1:0]

def ault=1.5ms

2.5V

VREF25

OFF

ON

AMP

OFF

Initial DATA conversion

ON

ADC

0 (charge)

1 (discharge)

CURCD_DIR

A

B

C

D

E

CURCD[14:0]

+A

+B

+C

-D

-E

CC_CCNTD[31:0]

Figure 2-2. OFF to Normal Mode Power ON Sequence

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2.3.2 SLEEP Mode

The BD7220FV-C enters SLEEP mode when “10” is written to MODE_SEL [1:0] (00h CC_SET1 [1:0]). In SLEEP mode, the

current consumption can be reduced since VREF25, AMP, and ΔΣADC operate intermittently. The timing of intermittent

operation can be configured using the SLEEP_INTERVAL register. All available ratios of ON time to OFF time in intermittent

operation are listed in Table 2-2.

Table 2-2. Ratio of ON Time to OFF Time in Intermittent Operation in SLEEP Mode

ON Time OFF Time

SLEEP_INTERVAL [1:0]=2'b00

SLEEP_INTERVAL [1:0]=2'b01

SLEEP_INTERVAL [1:0]=2'b10

SLEEP_INTERVAL [1:0]=2'b11

※Ratio when ON time is taken as '1'

1

7

15

31

127

The ON time during intermittent operation is calculated by the following formula:

푂푁 푡푖푚푒 = 퐼푁퐼_푊퐴퐼푇 + 퐴퐷_퐿퐴푇퐸 + (퐴퐷퐶_푆퐴푀푃 × 푆퐿퐸퐸푃_푆퐴푀푃퐿퐼푁퐺_푇퐼푀퐸)

INI_WAIT [1:0] (38h):

This is the wait time for VREF25 and AMP startup. The wait time is configurable from 1.5 ms (default) to 12 ms.

AD_LATE (ADC conversion latency):

This is the wait time before outputting digital conversion value after a signal is input into the ADC. It is configured by the

digital filter (MCIC_R) and OSR settings. For details, please refer to Table 1-6.

AD_SAMP (ADC sampling period):

This is the time required for one AD conversion. It is configured by the digital filter (MCIC_R) and OSR settings. For details,

please refer to Table 1-5.

SLEEP_SAMPLING_TIME [1:0] (03h):

This register determines how many times current measurement is done during ON time of intermittent operation. The

number is configured by the digital filter (MCIC_R) and OSR settings. For details, please refer to Table 2-3.

<4 steps of settings>

SLEEP_INTERVAL[1:0]

ON time：OFF time = 1:7/1:15/1:31/1:127

ON time

ADC_SAMP

・・・

OFF time

・・・・

INI_WAIT + AD_LATE

<4 settings>

ADC sampling time depends on sampling period (ADC_SAMP) setting.

ADC_SAMP ≥ 2ms --> 1 / 2 / 4 / 8 [times]

ADC_SAMP < 2ms --> 1 / 16 / 32 / 64 [times]

SLEEP_SAMPLING_TIME[1:0]

Figure 2-3. Intermittent Operation in SLEEP Mode

ON time and OFF time in default settings are calculated as following;

(

)

푂푁 푡푖푚푒 = 1.5 [ms] + 3.5 [ms] + 250 [µs] × 1 푡푖푚푒 = 5.25 [ms]

푂퐹퐹 푡푖푚푒 = 5.25 [ms] × 7 푡푖푚푒푠 = 3ꢁ.75 [ms]

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SLEEP Mode – continued

Table 2-3. Measurement Count during Intermittent Operation (ON Time) in SLEEP Mode

OSR[1:0] = 2'b00(32) or 2'b11(32)

MCIC_R[1:0]

2'b00(32)

0.25

2'b01(128)

1

2'b10(256)

2

2'b11(1024)

8

ADC Conversion Time[ms]

Measurement Count [times]

SLEEP_SAMPLING_TIME[1:0] = 2'b00

SLEEP_SAMPLING_TIME[1:0] = 2'b01

SLEEP_SAMPLING_TIME[1:0] = 2'b10

SLEEP_SAMPLING_TIME[1:0] = 2'b11

1

2

4

8

1

2

4

8

16

32

64

16

32

64

OSR[1:0] = 2'b01(128)

MCIC_R[1:0]

2'b00(32)

0.25

2'b01(128)

0.25

2'b10(256)

0.5

2'b11(1024)

2

ADC Conversion Time[ms]

Measurement Count [times]

SLEEP_SAMPLING_TIME[1:0] = 2'b00

SLEEP_SAMPLING_TIME[1:0] = 2'b01

SLEEP_SAMPLING_TIME[1:0] = 2'b10

SLEEP_SAMPLING_TIME[1:0] = 2'b11

1

2

4

8

16

32

64

16

32

64

16

32

64

OSR[1:0] = 2'b10(512)

MCIC_R[1:0]

2'b00(32)

0.25

2'b01(128)

0.25

2'b10(256)

0.25

2'b11(1024)

0.5

ADC Conversion Time[ms]

Measurement Count [times]

SLEEP_SAMPLING_TIME[1:0] = 2'b00

SLEEP_SAMPLING_TIME[1:0] = 2'b01

SLEEP_SAMPLING_TIME[1:0] = 2'b10

SLEEP_SAMPLING_TIME[1:0] = 2'b11

1

16

32

64

16

32

64

16

32

64

16

32

64

In SLEEP mode, current measurement is enabled only during ON time. Current is never measured during OFF time

(VREF25, APM, and ΔΣADC are OFF) but a fixed current value configured by the SLEEP_CC_SEL register is accumulated.

The values of related registers are updated as below.

CURCD:

The current value measured just before turning off is retained. The register value is not updated.

CC_CCNTD, CHG_CCNTD, DIS_CCNTD:

The current value measured in ON time is accumulated during OFF time.

Average value of current measured during ON time or the last value of ON time can be selected as the current value to be

accumulated, using the SLEEP_CC_SEL register (03h CC_SET3 [6]).

SLEEP_CC_SEL (03h):

0: The last measured current during the previous ON time is accumulated during OFF time.

1: Average current measured during ON time is accumulated during OFF time.

Please don’t change the configuration of the registers related to ON time / OFF time setting (INI_WAIT, MCIC_R, OSR,

SLEEP_SAMPLING_TIME, SLEEP_INTERVAL) and SLEEP_CC_SEL in SLEEP mode operating.

Ratio of ON time and OFF time is

configured using SLEEP_INTERVAL[1:0]

OFF time

ON time

INI_WAIT+

AD_LATE

INI_WAIT+

AD_LATE

Measuring current

OFF

Measurement condition

CURCD[14:0]

・・・

A

B

C

D

E

F

G

H

I

J

・・・

ꢀ・・・

・・

Number of measurements during ON time is

configured using SLEEP_SAMPLING_TIME[1:0]

Z=(A+B+C+D+E+F+G+H)/8

SLEEP_CC_SEL=1 ;

(Accumulate average current)

+Z

+H

+Z

+H

+Z

+H

+I

+J

CC_CCNTD[31:0]

・・・

・・

SLEEP_CC_SEL=0 ;

(Accumulate prev ious current)

+H

・・・

Figure 2-4. Accumulation Current during OFF Time

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2.3.3 SSHDN Mode

BD7220FV-C enters SSHDN mode when “11” is written to MODE_SEL [1:0] (00h CC_SET1 [1:0]).

In SSHDN mode, the minimum function blocks to retain register settings are turned on. For details, please refer to Table 2-1.

The CURCD register which shows current value is reset to “0” but the CCNTD register which shows accumulation current

keeps the value measured at the end.

2.3.4 OFF State

BD7220FV-C is turned off when the SHDNB pin is in “L” state.

In OFF state, all blocks are turned off and the current consumption is at minimum. Note that register settings are cleared and

OTP settings are recalled at next power on. The register value of calibration needs to be written again. (Refer to section

4.2.1.)

Finished to recall from OTP at restart from OFF state, “1” is set to OTP_DL_FIN register. The data set to OTP_DL_FIN

register is latched and cleared by writing “1” to it. So, to clear OTP_DL_FIN register after startup and monitoring the register

value regularly enables to detect unexpected reset of BD7220FV-C.

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3.

Interrupts

3.1

Summary

6 types of interrupt can be generated through the open-drain INTB pin. All interrupt settings can be masked or unmasked

through the register settings.

3.1.1

Features



4 types of threshold can be configured for interrupt by the accumulation current [CC_CCNTD]

3 types of threshold can be configured for interrupt by the measured current [CURCD]

Interrupt by the current the configured threshold or more

Interrupt by detecting battery relaxation

Interrupt by SPI CRC error detection

Interrupt by completing the calibration

3.1.2

Structure

BD7220FV-C can generate interrupt signals from multiple sources by asserting the INTB pin low. Each interrupt source has

associated status register and enable register. The status register indicates the status of each interrupt source and the

enable register allows to output the interruption to the external open drain pin “INTB”.

Regardless of the setting of its enable register, status register corresponding to the source of interrupt is set “1” when

detecting each interrupt source event. The status register is latched and is not cleared automatically even if released from

the interrupt source. To clear the enable register, write “1” to the register. Only the enabled interrupt event can assert the

INTB pin low and announcing the interrupt occurred.

The INTB pin is kept asserted low until all enabled status registers are cleared when multiple interrupt sources occur. The

INTB pin goes into Hi-z state when all enabled status registers are cleared. As “0” written in status registers is ignored, write

“0” in other bits to clear only one interrupt source.

After power on or restart from OFF state, all status registers are “0” (non-detected) and all enable registers are “0” (interrupt

assertion to the INTB pin is disabled). To enable interrupt assertion, configure the interrupt function by SPI.

Please refer to the Table 3-1 for more details about interrupt registers.

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3.2

Register Descriptions

The list of interrupt registers are as follows.

Table 3-1. List of Interrupt Registers

Register Map

Enable Status/Clear

Register

Name

Bit Name

Function

Address

bit

Detection of Charging Current Accumulation Value1

(Threshold Setting)

Detection of Discharging Current Accumulation Value1

(Threshold Setting)

Detection of Charging Current Accumulation Value2

(Threshold Setting)

Detection of Discharging Current Accumulation Value2

(Threshold Setting)

Detection of Charging Current Accumulation Value3

(Threshold Setting)

Detection of Discharging Current Accumulation Value3

(Threshold Setting)

Detection of Charging Current Accumulation Value4

(Threshold Setting)

Detection of Discharging Current Accumulation Value4

(Threshold Setting)

Alarm Output for Detection of Charging Current

(ALARMB Terminal Output for OCUR1_DET)

Alarm Output for Detection of Discharging Current

(ALARMB Terminal Output for OCUR1_RES)

Detection of Charging Current1

(Threshold/Number of Detection Setting)

Detection of Discharging Current1

(Threshold/Number of Detection Setting)

Detection of Charging Current2

(Threshold/Number of Detection Setting)

Detection of Discharging Current2

(Threshold/Number of Detection Setting)

Detection of Charging Current3

(Threshold/Number of Detection Setting)

Detection of Discharging Current3

(Threshold/Number of Detection Setting)

Detection of Over Wake-Up Current

(Threshold/Number of Detection Setting)

Detection of Under Wake-Up Current

(Threshold/Number of Detection Setting)

Detection of Relax State

INT_REQ1

INT_REQ2

INT_REQ3

CC_MON1_DET

CC_MON1_RES

CC_MON2_DET

CC_MON2_RES

CC_MON3_DET

CC_MON3_RES

CC_MON4_DET

CC_MON4_RES

ALARM_OCUR1_DET

ALARM_OCUR1_RES

OCUR1_DET

39h

3Ah

3Bh

0

3Ch

3Dh

3Eh

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

4

6

1

2

3

4

5

6

7

2

3

2

3

4

5

6

7

0

1

2

4

6

OCUR1_RES

OCUR2_DET

OCUR2_RES

OCUR3_DET

OCUR3_RES

WAKE_DET

WAKE_RES

REX_DET

(Threshold/Time of Detection Setting)

CRCERR_DET

CALIB_FIN

Detection of CRC Error

Detection of Calibration Finish

(Note) Inside () indicate configurable parameters

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3.3

Function Description

Interrupt by Accumulation Current

3.3.1

Interrupt can be generated by detecting the configured threshold crossing to the accumulation current measurement

(CC_CCNTD). 4 thresholds can be configured through CC_BATCAP#_TH (# = 1 to 4). CC_BATCAP#_TH are 24-bit

registers those are compared to the upper 24 bits (out of 32) of CC_CCNTD.

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

31

23

24 23

16 15

8

0

7

0

CC_BATCAP#_TH2

CC_BATCAP#_TH1

CC_BATCAP#_TH0

8

7

Figure 3-1. Relationship between CC_CCNTD and CC_BAT_CAP_TH

(When CC_UNDIV = 0: scaling in every gain setting is enabled)

LSB of CC_BATCAP1_TH = 78.125 μAh

MSB of CC_BATCAP1_TH = 655.36 Ah

When CC_UNDIV=1: scaling in every gain setting is disabled and in that case LSB / MSB varies.

For example, the threshold of the accumulation current is configured to 1Ah, register value is as below.

1[Ah] / 78.125[µAh] = 12800 => 퐶퐶_퐵퐴푇퐶퐴푃1_푇퐻[23: 0] = 24′ℎ003200(24′푑12800)

Please refer to section 1.3.2 for more details about CC_CCNTD.

Table 3-2. The List of Accumulation Current and Threshold Registers

Address

Register Name

Description

17h to 1Ah

CC_CCNTD [31:0]

Accumulated Current Value

Interrupt Threshold for Current Accumulation 1

It is compared with the upper 24 bits [31:8] in CC_CCNTD [31:0] register.

Interrupt Threshold for Current Accumulation 2

It is compared with the upper 24 bits [31:8] in CC_CCNTD [31:0] register.

Interrupt Threshold for Current Accumulation 3

It is compared with the upper 24 bits [31:8] in CC_CCNTD [31:0] register.

Interrupt Threshold for Current Accumulation 4

23h to 25h

26h to 28h

29h to 2Bh

2Ch to 2Eh

CC_BATCAP1_TH [23:0]

CC_BATCAP2_TH [23:0]

CC_BATCAP3_TH [23:0]

CC_BATCAP4_TH [23:0]

It is compared with the upper 24 bits [31:8] in CC_CCNTD [31:0] register.

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3.3.2

Interrupt for Current Measurement

Interrupt can be generated by detecting the configured threshold crossing for current measurement (CURCD). 3 thresholds

can be configured through OCURTHR#_DIR (# = 1 to 3) and OCURTHR# (# = 1 to 3). OCURTHR# is a 15-bit register that is

compared to the 15 bits of CURCD. OCURDUR# (# = 1 to 3) configures the number of consecutive detections required to

generate the interrupt. For example, if set to 4 times, an interrupt is generated only after 4 consecutive detections. The

counter starts over from 0 if enough time passes without reaching the set number of consecutive detections.

Only specific to OCURTHR1, interrupts can also be notified through the dedicated ALARMB pin. Unlike interrupt notifications

through INTB, the ALARMB interrupt source can be easily identified even without checking the status registers.

Sign

CURCD_H

CURCD_L

15 14

8

7

0

Sign

OCURTHR#_H

OCURTHR#_L

15 14

Figure 3-2. Relationship of CURCD and OCURTHR

Table 3-3. List of Current Detection Interrupt Setting Registers

Address

Register Name

Description

13h

13h to 14h

2Fh

CURCD_DIR

CURCD [14:0]

Current Direction (0:charging 1:discharging)

Measured Current Value

OCURTHR1_DIR

OCURTHR1 [14:0]

OCURTHR2_DIR

OCURTHR2 [14:0]

OCURTHR3_DIR

OCURTHR3 [14:0]

OCURDUR1 [1:0]

OCURDUR2 [1:0]

OCURDUR3 [1:0]

OCURTHR1 [14:0] Current Direction(0:charging 1:discharging)

Interrupt Threshold for Current Measurment 1

2Fh to 30h

31h

OCURTHR2 [14:0] Current Direction(0:charging 1:discharging)

Interrupt Threshold for Current Measurment 2

31h to 32h

33h

OCURTHR3 [14:0] Current Direction(0:charging 1:discharging)

Interrupt Threshold for Current Measurment 3

33h to 34h

35h

Crossing Detection Threshold for OCURTHR1 (00: 1 time, 01: 4 times, 10: 8 times, 11: 16 times)

Crossing Detection Threshold for OCURTHR2 (00: 1 time, 01: 4 times, 10: 8 times, 11: 16 times)

Crossing Detection Threshold for OCURTHR3 (00: 1 time, 01: 4 times, 10: 8 times, 11: 16 times)

35h

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3.3.3

Interrupt by Battery Relaxation and Wakeup Current Detection

Relaxation state Interrupt can be generated when a relaxation state of the battery is detected. The detection threshold can

be configured through REX_CURCD_TH. REX_CURCD_TH is an 8-bit register and set to the lower 8 bits (out of 15) of

CURCD. REX_CURCD_TH cannot be set the CURCD_DIR register indicate the sign of the current value. A Relax Timer

starts counting up when REX_CURCD_TH is set to 100 mA and the value of CURCD is within -100 mA to +100 mA. The

counter resets once the current increases higher than the threshold. REX_EN should be set to “1” to enable the Relax Timer.

Writing “0” to the REX_EN stops the timer and resets the timer counter to “0”. Once the Relax Timer is expired and the

counter needs to be reset, writing REX_EN = 1→0→1 is required. Relax timer detect time can be configured in 4 steps from

30 min to 120 min through the REX_DUR register. Relaxation state interrupt is generated when relax timer is over the detect

time.

Wakeup current interrupt is generated when an occurrence of charge or discharge current toward the battery is detected.

The detection threshold can be configured through WAKE_CURCD_TH an 8-bit register which is set to the lower 8 bits (out

of 15) of CURCD. WAKE_CURCD_TH cannot be set the CURCD_DIR register indicate the sign of the current value. An

interrupt is generated when WAKE_CURCD_TH is set to 100 mA and the value of CURCD is less than -100 mA or greater

than +100 mA. The WAKE_COUNT register configures the number of consecutive detections required to generate the

interrupt. For example, if set to 4 times, an interrupt is generated only after 4 consecutive detections are detected. The

counter starts over from 0 if enough time passes without reaching the set number of consecutive detections.

Current

Charging

REX_CURCD_TH

direction

0[A]

Discharging

direction

REX_CURCD_TH

※REX_EN=”1"→”0"→”1"

※Relaxation timer is valid

when REX_EN=”1"

REX_EN

OFF

Relaxation timer

COUNT

OFF

COUNT

Count re-starts when

Measurement current

<REX_CURCD_TH

OFF

Count starts when current is

within the current range

configured by REX_CURCD_TH

INTB

Issue an interrupt

When REX_DET_EN is valid

Relaxation related signals

REX_DET

Retain “H” until interrupt is cleared

Detect relaxation state after

configured time passed being

Relaxation state

within configured current range is cleared

MCU

Current

Charging

direction

WAKE_CURCD_TH

0[A]

Discharging

direction

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

Wake counter

250us

WAKE_RES turns to “H” when

current<WAKE_CURCD_TH

during successive 4 times

Wake related signals

WAKE_DET turns to “H” when

current>WAKE_CURCD_TH

during successive 4 times

WAKE_DET

WAKE_RES

MCU

Retain “H” until interrupt is cleared

WAKE_RES turns to “L”

when interrupt is cleared

WAKE_DET turns to “L”

when interrupt is cleared

Figure 3-3. Relaxation State and Wake Up Current Detection Interrupt Timing Chart

Table 3-4. List of Relaxation State / Wake Up Interrupt Setting Registers

Address

Register Name

Description

13h to 14h

03h

CURCD [14:0]

REX_EN

Measured Current Value

Relax State Detection Timer Enable (0：Timer OFF（0 Clear）ꢀ１：Timer ON)

35h

REX_DUR [1:0]

Relax State Detection Time (00：30 minutes ꢀ01：60 minutesꢀ10：90 minutesꢀ11：120 minutes）

Relaxation State Detection Threshold

It is compared with the lower 8bits[7:0] of the CURCD [14:0] register.

Wake up Detection Threshold

It is compared with the lower 8bits[7:0] of the CURCD [14:0] register.

Number of Detection times for Wake up (00：1 timeꢀ01：4 timesꢀ10：8 timesꢀ11：16 times）

36h

REX_CURCD_TH [7:0]

37h

38h

WAKE_CURCD_TH [7:0]

WAKE_COUNT [1:0]

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3.3.4

Interrupt for Detection of CRC Error

The BD7220FV-C incorporates SPI interface.

It is possible to add CRC code to the transmission and reception of SPI commands. Having CRC code or not is selectable by

the leading EC bit of the data. For details, please refer to the section of 5.

CRC error can trigger interrupt.

In case of Data write:

Please add a CRC bit to the command when it is transmitted from the MCU.

When CRC error is detected at the time of the command reception, a CRC error triggers interrupt.

Please write “1” to CRCERR_DET_EN register to produce an interrupt signal through INTB.

In case of Data read:

CRC bits cannot be added to a read command from the MCU.

Please judge the CRC error on the MCU side as CRC bit is added to all transmitted and received data as a result of

BD7220FV-C sending “read data” and “read command”.

3.3.5

Interrupt for Completion of Calibration

The BD7220FV-C has two calibration modes. (For details, please refer to section 4.1.2.)

When calibration is completed with mode 2, interrupt is triggered. Please write “1” to CALIB_FIN_EN register to produce an

interrupt signal through INTB.

Customer’s product shipment:

It is assumed that the calibration is executed with the condition where the BD7220FV-C and external components are

mounted in the process. Dispersion of external components can be considered when the calibration is executed with a

mounted external current detection device such as a shunt resistor or current sensor.

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4.

Calibration

4.1

Summary

By communicating with SPI, BD7220FV-C can calibrate the variation of gain and offset. There are an auto calibration by SPI

communication and a manual calibration by setting the calibration value into the registers. Because BD7220FV-C has a

sequence circuit and a calculation circuit for calibration, it can output a calibration value automatically only by setting the input

information and inputting a trigger signal. However, non-volatile memory is not built-in for this product. To be able to store

values generated from automatic and manual calibration, it is necessary to use and maintain external memory.

Figure 4-1 shows the flow chart of calibration.

4.1.1

Features

Calibration in BD7220FV-C shipment process:

The calibration values are kept in the built-in OTP and are downloaded automatically

Calibration in customer’s product shipment:

The calibration (gain and offset calibration) including the external current detection element in customer’s process

Manual calibration enabled to set the calibration value externally

4.1.2

Structure

BD7220FV-C can calibrate gain and offset error.

The three available calibration modes are explained below.

4.1.2.1

Calibration Mode 1 (in BD7220FV-C shipment process)

This calibration is carried out at the shipment of BD7220FV-C. Calibration is done with the internal regulator VREFCAL for

calibration as a reference. An external capacitor at VREFCAL pin is not needed on customer’s product, so please make

the pin open. The external current detection element (shunt resistor or current sensor) is not calibrated. Only the gain and

offset error of the built in AMP and ΔΣADC are calibrated. The calibration values are kept in the built in OTP in

BD7220FV-C, and are read back automatically at startup. Offset calibration is tuned to the 25 V/V AMP gain setting by

default, so it is necessary to use Mode 2 and Mode 3 for 5 V/V and 51 V/V settings.

4.1.2.2

Calibration Mode 2 (in customer’s product process)

Calibration mode 2 is the calibration used in the customer’s product shipment. This calibration includes the external

current detection element.

It is possible to measure a highly precise current by carrying out the calibration when the external current detection

element (shunt resistor or current sensor) is connected. To carry out this calibration, it is necessary to force as much

current as will be used in the actual application. Mode 2 or Mode 3 offset calibration is necessary when using an AMP gain

of 5 V/V or 51 V/V. If measurement will be performed using multiple AMP gain settings, Mode 2 calibration needs to be

performed on each setting to be used.

BD7220FV-C outputs the calibration value after automatic operation. However, as BD7220FV-C does not have

non-volatile memory, external memory is required to store the calibration values used. These values should be rewritten

each time BD7220FV-C is reset.

4.1.2.3

Calibration Mode 3 (manual calibration)

This calibration is carried out manually by calculating the calibration value using MCUs or other methods.

Mode 3 can be used to compensate gain or offset variations caused by the measurement environment, such as the

temperature. The value to be set for gain calibration is calculated by following the equation written later. The value to set

for offset calibration is calculated referring to Table 1-1. Mode 2 or Mode 3 offset calibration is needed when using the 5

V/V and 51 V/V AMP gain settings, or for each gain setting used when measuring using multiple gain settings. However,

as BD7220FV-C does not have non-volatile memory, external memory is required to store the calibration values used.

These values should be rewritten each time BD7220FV-C is reset.

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Calibration Mode 3 (manual calibration) – continued

POWER ON

(RESET)

GAIN

Setting

NO

Setting

Charging direction current input

Discharging direction current input

YES

GAIN10[17:0]

by Auto Calculation

Need OFFSET Settings

after GAIN10 Setting

0A current input

YES

OFFSET

Setting

OFST10[15:0]

By Auto Calculation

NO

If skip GAIN10&OFST10

setting, calibration setting

is valid only for the

Internal block of IC.

(Shunt resister or etc.

are not calibrated)

Write

Need OFFSET&GAIN10 Setting

by AMP_GAIN setting

Nonvolatile

memory

GAIN10=0x00

YES

Other GAIN

Setting

Other GAIN

OFST10=0x00

(Initialize)

NO

Measurement

START

Re-write

AMP_GAIN

Change

GAIN10&OFST10

AMP_GAIN

GAIN10&OFST10

Setting

from Nonvolatile memory

GAIN

Re-Setting

GAIN30[17:0]

by MCU calculation

GAIN

Need OFFSET Re-Settings

after GAIN30 Setting

Not 0A current input

OFFSET

Re-Setting

Setting

Method

OFST10

Re-Setting

by MCU Calculation

0A current input

OFST10=0x00

(Initialize)

OFST10

by Auto Calculation

Measurement

FINISH

Figure 4-1. Flow Chart of Calibration

High accuracy input is necessary

for the high accuracy calibration.

VREF25

2.5V

5V

1.5V

+

-

ADC_DATA

ΔΣ

ADC

VREF25

Calibration mode 1(in shipment process)

Calibration mode 2(in customer’s product shipment including the external component)

Calibration mode 3(manual calibration on the set)

Figure 4-2. Calibration (Mode 1, Mode 2 and Mode 3)

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4.2

Function Description

Calibration Mode 2

4.2.1

At customer’s shipment, gain and offset error can be calibrated using Calibration Mode 2.

The calibration is carried out while forcing a certain differential voltage across the INP and INN pins. Calibrating with an

external current detection element (such as a shunt resistor) enables higher accuracy current measurement. Note that in

Mode 2, Gain Calibration must be performed before Offset Calibration. The calibration values in the register are discarded

when BD7220FV-C is reset, so please write these to external memory and rewrite when BD7220FV-C starts up.

4.2.1.1

Calibration Mode2: Gain Calibration

Gain calibration is carried out by forcing voltage that correspond to 2 points of current value, one of charging current, PFS

(current direction of INP voltage is positive); the other of discharging current, MFS (current direction of INP voltage is

negative). Please set the data of differential voltage between PFS and MFS into the CALVIN_DIFF register. Please refer to

Figure 4-3 for the relationship between PFS, MFS and CALVIN_DIFF registers. The current values in the figure are a 25

V/V AMP gain setting and R_SNSof 0.2 mΩ.

output code

ideal

32767

measured value

(w/o calibration of mode 2)

②Force PFS

0

③Force MFS

①Setting range of CALVIN_DIFF

Vin

-32768

-400A

+400A

Current

Figure 4-3. Force Setting for Gain Calibration

The flow of calibration is as follows.

1. Setting CALVIN_DIFF register (Data of differential voltage between PFS and MFS)

2. Forcing charging current PFS and executing calibration (writing “1” to CALIB_TRG register)

3. Forcing discharging current MFS and executing calibration (writing “1” to CALIB_TRG register)

Notice 1

Please carry out the calibration for each gain if you will measure with changing amp gain settings. The value set to

GAIN10 register is needed with each amp gain setting.

Notice 2

Calibrating discharge current before charge current results in a wrong calibration value, so the order of calibrating charge

current before discharge current must be strictly followed. If the calibration order was not followed, please reset

BD7220FV-C.

The data of differential input voltage is set in CALVIN_DIFF [11:0] register.

The value to set is determined by the value of the external shunt resistor R_SNSand the amp gain setting as in the following

equation. The differential current between PFS and MFS is over the possible setting range when calculated result is a

negative value.

(

)

⊿퐼 × 푅_ꢇꢃꢇ× 퐴푀푃_퐺퐴퐼푁

4.5

퐶퐴퐿푉퐼푁_퐷퐼퐹퐹 푣푎푙푢푒 = {2^ꢀꢆ×

푅_ꢇꢃꢇ: 푟푒푠푖푠푡푎푛푐푒 표푓 푠ℎ푢푛푡 [Ω]

} ꢈ 2^ꢀꢉ

Please refer to Table 4-1 for the possible setting range of CALVIN_DIFF for each amp gain setting.

For an AMP gain of 25 V/V and R_SNSof 0.2 mΩ, the range of CALVIN_DIFF is from 450 A to 800 A and the step is 109.86

mA. Please force 225 A for PFS and -225 A for MFS when CALVIN_DIFF is 450 A.

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Calibration Mode2: Gain Calibration - continued

The minimum setting of differential current ΔI_MINbetween PFS and MFS is changed by the value of R_SNSand gain setting.

It is calculated with the following equation.

⊿퐼_ꢊꢋꢃ= 2.25 / (퐴푀푃_퐺퐴퐼푁 × 푅_ꢇꢃꢇ

)

푅_ꢇꢃꢇ: 푟푒푠푖푠푡푎푛푐푒 표푓 푠ℎ푢푛푡 [Ω]

Table 4-1. Unit of CALVIN_DIFF Register Setting Current

AMP_GAIN = 5 times

AMP_GAIN = 25 times

AMP_GAIN = 51 times

AMP Input

Differential

Current

AMP Input

Differential

Current

AMP Input

Differential Current

AMP Input

Differential

Voltage

AMP Input

UNIT Differential

Voltage

AMP Input

UNIT Differential

Voltage

UNIT

(R_SNS= 0.2 mΩ)

Minimum Setting

Maximum Setting

Step Width

450.00

599.96

109.86

mV

μV

2250.00

2999.82

549.32

A

90.00

160.00

21.97

mV

μV

450.00

800.02

109.86

A

44.12

80.01

10.77

mV

μV

220.59

400.03

53.85

A

mA

For example, considering an amp gain setting is 25 V/V, PFS = +300 A and MFS = -300 A, the differential current between

PFS and MFS is 600 A. The differential current is within the possible setting range from 450 A to 800 A in Table 4-1, so it is

possible to carry out calibration. If the differential current is outside the range, adjustment of input current is needed. The

value to set to CALVIN_DIFF register is calculated as following.

(

)

⊿퐼 × 푅_ꢇꢃꢇ× 퐴푀푃_퐺퐴퐼푁

4.5

퐶퐴퐿푉퐼푁_퐷퐼퐹퐹 푣푎푙푢푒 = {2^ꢀꢆ×

} ꢈ 2^ꢀꢉ

푅_ꢇꢃꢇ: 푟푒푠푖푠푡푎푛푐푒 표푓 푠ℎ푢푛푡[Ω]

퐶퐴퐿푉퐼푁_퐷퐼퐹퐹 = ꢌ2^ꢀꢆ× (ꢁ00[A] × 0.2 × 10^−ꢆ× 25) / 4.5ꢍ ꢈ 2^ꢀꢉ= 13ꢁ5[DEC]

= 555[HEX]

Table 4-2 shows the flow of SPI communication in carrying out Gain Calibration.

After setting the register configurations and input voltage between INP and INN, you can carry out the calibration by writing

“1” to CALIB_TRG register. After writing “1” to CALIB_TRG, the value will automatically clear to “0”.

To complete gain calibration, 2 times trigger input for charge and discharge is needed.

Table 4-2. Calibration Mode 2: Flow of SPI Communication in Carrying Out Gain Calibration

SPI

Item

Register

Description

INP-INN Input

REG

ADDR ADDR

CONT

R/W

DATA

CALVIN_DIFF_H = XXXX

CALVIN_DIFF_L = XXXX

Configuration of Diffrential Input Between

INP and INN

W

0Fh

10h

1Eh

20h

0Xh

XXh

Configure AMP_GAIN as Actual Use

(For Higher Accurate Calibration, Configure

MCIC_R Resister 2'b11 Regardless of Actual

Use)

Initial Configuration

-

AMP_GAIN = XX

MCIC_R = 11

W

00h

X0h

GAIN_CAL_FS = 1,

CALIB_MODE = 001

Forcing Charge Current

Configure CALIB_MODE

Charge Configuration

Charge Calibration

W

04h

02h

04h

08h

04h

08h

09h

20h

01h

Input Differential Voltage of Charge

CALIB_TRG = 1

Trigger Input to Start Calibration

GAIN_CAL_FS = 0,

CALIB_MODE = 001

Forcing Discharge Current

Configure CALIB_MODE

Discharge Configuration

Discharge Calibration

Input Differential Voltage of Discharge

-

CALIB_TRG = 1

Trigger Input to Start Calibration

W

R

02h

05h

06h

07h

04h

0Bh

0Dh

0Fh

20h

read GAIN10_2

-

Read Calibration Output in GAIN10

Resister

Read Calibration Output

read GAIN10_1

read GAIN10_0_GAIN30_2

REG ADDR: Addresses in register map of BD7220FV-C

CONT ADDR: The first 1 byte data in SPI communication

Ex.1) Write REG ADDR = 0Fh → 8’b0000 1111 → 0(EC) + 6b’001111 + 0(Write) = 1Eh (EC Bit = 0, CRC is invalid)

Ex.2) Read REG ADDR = 02h → 8’b0000 0010 → 0(EC) + 6’b000010 + 1(Read) = 05h (EC Bit = 0, CRC is invalid)

*Calibration finishes (Detection of CALIB_FIN interrupt)

You will know when calibration is finished by using the CALIB_FIN register for interrupt. CALIB_FIN turns to “1” when

Mode 2 Calibration is completed, so please clear the CALIB_FIN register before carrying out calibration. To validate the

interrupt of INTB pin, please write CALIB_FIN_EN register “1”.

If you need to perform Mode 2 Gain Calibration again, please do so after resetting GAIN10, OFST10 and GAIN30

registers to “0”.

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4.2.1.2

Calibration Mode2: Offset Calibration

Offset Calibration is carried out by input differential voltage without drawing current between the INP and INN pins. Write

“1” to CALIB_TRG under forcing differential voltage and Offset Calibration is automatically carried out.

The flow of calibration is only one step:

1. After input differential voltage without drawing current between the INP and INN pins, and carry out calibration (Write

“1” to CALIB_TRG)

Notice 1

Please carry out the calibration for each gain if you will measure with multiple amp gain settings.

Table 4-3 shows the flow of SPI communication in carrying out Offset Calibration.

Table 4-3. Calibration Mode 2: Flow of SPI Communication in Carrying Out Offset Calibration

SPI

Item

Register

Description

INP-INN Input

REG

ADDR ADDR

CONT

R/W

W

DATA

X0h

Configure AMP_GAIN as Actual Use

(For Higher Accurate Calibration, Configure

MCIC_R Resister 2'b11 Regardless of Actual

Use)

AMP_GAIN = XX

MCICR = 11,

00h

Input Differntial Voltage

at No Current Flow

(INP and INN Shorted)

Initial Configuration

Offset Calibration

CALIB_MODE = 010

CALIB_TRG = 1

read OFST10_H

read OFST10_L

Configure CALIB_MODE

W

R

04h

02h

0Ah

0Bh

08h

04h

15h

17h

02h

Trigger Input to Start Calibration

20h

-

Read Calibration Output in OFST10

Read Caliration Output

-

R

* The way of to check if calibration is finished is the same as in Gain Calibration.

If you need to perform Mode 2 Offset Calibration again, please do so after resetting OFST10 to “0”.

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4.2.2

Under typical usage conditions, gain and offset error can be calibrated using Calibration Mode 3.

4.2.2.1 Calibration Mode 3: Manual Calibration

Calibration Mode 3: Manual Calibration

Manual gain calibration uses the GAIN30 and GAIN31 registers. GAIN30 register is for configuration of the calibration

value. Writing in the value calculated from an equation written later, gain is calibrated. GAIN31 register is a read-only

register for reading the gain calibration configuration contained in the IC. When in Calibration Mode 2, the IC automatically

calculates the needed gain adjustment ratio and sets the calibration value, but in Mode 3, you can calibrate by setting the

configuration of gain adjustment ratio from 0.8x to 1.2x by 0.006% step. Gain adjustment ratio is calculated with the forced

current value of 2 points, IP and IM, the corresponds output value of CURCD, PD and MD, the value of the external shunt

resistor R_SNSand the amp gain setting in the following equation. Any combinations of current polarity are possible to be

used, and not restricted to the combination of charge and discharge.

퐼푃 ꢈ 퐼푀 × 푅_ꢇꢃꢇ× 퐴푀푃_퐺퐴퐼푁 × (2^ꢀꢎꢈ 1)

)

(

퐺푎푖푛 푎푑푗푢푠푡푚푒푛푡 푟푎푡푖표 =

푅_ꢇꢃꢇ: 푟푒푠푖푠푡푎푛푐푒 표푓 푠ℎ푢푛푡[Ω]

(푃퐷 ꢈ 푀퐷) × 2.25

For example, considering an amp gain setting is x25 V/V, external shut resister value is 0.2 mΩ, forced current IP=+100 A

and IM=-250 A, values of CURCD PD=7645 and MD=-19113, gain adjustment ratio is calculated as following.

100 ꢈ (ꢈ250) × 0.2 × 10^−ꢆ× 25 × (2^ꢀꢎꢈ 1)

ꢌ

ꢍ

퐺푎푖푛 푎푑푗푢푠푡푚푒푛푡 푟푎푡푖표 =

= 0.95244

ꢌ

ꢍ

7ꢁ54 ꢈ (ꢈ19113) × 2.25

The value to set in GAIN30 register is calculated with the value of GAIN31 and the ratio of gain adjustment in the following

equation. If the adjustment ratio is less than 1x, set the negative value as a 2’s complement representation.

ꢌ

(

)ꢍ

퐺퐴퐼푁30 푣푎푙푢푒 = 퐺퐴퐼푁31[DEC] × 퐺푎푖푛 푎푑푗푢푠푡푚푒푛푡 푟푎푡푖표 ꢈ 퐺퐴퐼푁31[DEC]

For example, when GAIN31 register is 0xBD2C (48428[DEC]) and Gain Adjustment Ratio is 1.05x,

ꢌ

ꢍ

퐺퐴퐼푁30 푣푎푙푢푒 = 48428[DEC] × 1.05 ꢈ 48428 = 2421[DEC] = 975[HEX]

And in case of the adjustment ratio is less than 1x as above example, calculation is as following.

ꢌ

ꢍ

퐺퐴퐼푁30 = 48428 × 0.95244 ꢈ 48428 = ꢈ2303[DEC] = 3퐹701[HEX]

Notice 1

Please write registers for manual gain calibration in IDLE state or SSHDN mode, and do not write when measuring

current.

Notice 2

If you operate Mode 3 Gain Calibration again, please re-calculate the value to set after resetting GAIN30 register to “0”

and reading the value of GAIN31 register.

Notice 3

The value of GAIN31 register changes depending on the configuration of amp gain. So, if you will measure with multiple

AMP gain configurations, the value of GAIN30 register must be calculated for each gain configuration. Please read

GAIN31 register again and re-calculate the value after resetting GAIN30 register when gain configuration is changed.

Notice 4

The value of GAIN31 register changes depending on the calibration value obtained from Mode 2 Calibration (and stored in

GAIN10 register.) If Mode 2 Calibration is to be performed again, please read GAIN31 register and re-calculate the value

after resetting GAIN30 register.

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4.2.2.2

Calibration Mode 3: Manual Offset Calibration

Manual Offset Calibration uses the OFST10 register. Writing OFST10 with the value added or subtracted corresponding to

the amount of current you want to adjust, will calibrate the offset. To convert from current to adjust to register value, please

refer to LSB current in Table 1-1. The value to set to OFST10 register is calculated with the original value of OFST10

register and adjustment current as in the following equation.

푂퐹푆푇10 푣푎푙푢푒

(

)

= 표푟푖푔푖푛푎푙 푂퐹푆푇10 푟푒푔푖푠푡푒푟 푣푎푙푢푒[DEC] + (푎푑푗푢푠푡푚푒푛푡 푐푢푟푟푒푛푡[DEC])

In the case that the original value of OFST10 register is 16’h012C (=16’d300), the external current sense resistance is 0.2

mΩ, configuration of amp gain is 25 V/V, and adjust current is +5 A, LSB current is 13.73 mA. And the converted register

value corresponding to the adjust current and setting value of OFST10 register is calculated as following.

푎푑푗푢푠푡 푐푢푟푟푒푛푡[DEC] = 5[A] ÷ 13.73[mA] ≈ 3ꢁ4.17 ≈ 3ꢁ4[DEC]

푂퐹푆푇10 푣푎푙푢푒[DEC] = 300[DEC] + 3ꢁ4[DEC] = ꢁꢁ4[DEC] = 298[HEX]

Notice 1

Please write registers for manual offset calibration in IDLE state or SSHDN mode, and do not write when measuring

current.

Notice 2

If you operate Mode 3 Offset Calibration again, please overwrite OFST10 register with added/subtracted value

corresponding to the additional adjust current.

Notice 3

When the configuration of amp gain is changed, please re-calculate OFST10 register value because of changing LSB

current.

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5.

SPI Interface

5.1

Summary

BD7220FV-C is equipped with 500 kHz (Max) SPI interface. And also, it has the selectable (with/without) CRC code to

improve the reliability of the communication (Mode 0 correspondence).

5.1.1

Features



SPI Interface

“Data write” carried out for every 1byte unit

“Data read” carried out for every consecutive byte unit (setting number of bytes).

Selectable with/without CRC cord (by the EC bit MSB of the control address)

CRC polynomial: X⁸+X²+X+1

5.1.2

Constitution

BD7220FV-C has SPI interface.

Power supply of the SPI interface is the VDD pin.

SPI interface is enabled by turning the CSB pin to “L” level. The IC takes in the MSB-first input data on the SDI pin

synchronous to the rising edges of SCK clock. Output- data is supplied on the SDO pin in the MSB-first order synchronous to

the falling edges of SCK clock. SPI interface is disabled with “H” level input on the CSB pin and returns to the initial state.

The CSB pin should be fixed to “H” level every time after one data write/read operation is completed. (Regarding the data

reading, consecutive read in byte is available.)

CSB

SCK

SDI

Hi-Z

SDO

Hi-Z

Figure 5-1. SPI Timing Chart

Configurations and controls can be done by reading/writing corresponding addresses in the control register. Write data is

one-byte length, while read data length is specified in read commands. Set the RW bit to “0” for data write and “1” for data

read. Also, set the EC bit to “1” if the CRC code for detecting a communication error is required or to “0” otherwise.

7

6

5

4

3

2

1

0

"0"

"1"

without

CRC

with

CRC

Control register address

EC

RW

EC

RW

write

read

Figure 5-2. Control Address Constitution

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5.2

Function Description

The below figures show the communication format of the data read/write with/without CRC

5.2.1 Data Write Communication Format without CRC

CSB

SCK

EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0

SDI

Control Register

Address

Write Data

for Write = “0”

without

CRC = “0”

Figure 5-3. Data Write Communication Format without CRC

5.2.2

Data Read Communication Format without CRC

CSB

SCK

SDI

EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0

Control Register

Address

Data Byte Length

O7 O6 O5 O4

O3 O2 O1 O0

Hi-Z

SDO

without

CRC = “0”

for Read = “1”

Read Data

Figure 5-4. Data Read Communication Format without CRC

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5.2.3

Data Write Communication Format with CRC

CSB

SCK

SDI

EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0

Control Register

Address

Write Data

CRC Code

with CRC = “1”

for Write = “0”

Figure 5-5. Data Write Communication Format with CRC

If a communication with CRC is selected (EC = “1”), 1-byte CRC (Cyclic Redundancy Code) is generated according to an

X⁸+X²+X+1 equation, and added at the end of each communication data. Set the CSB pin to “H” level to initialize CRC

computation to the default FFh.

Data write is performed on the specified control register only if the result from CRC computation matches the received CRC.

Otherwise, data write is not performed. CRC error flag is set when CRC error is detected, and an interrupt signal is output to

MCU from the INTB pin. Refer to the chapter 3 about detail interrupt explanation.

5.2.4

Data Read Communication Format with CRC

CSB

SCK

SDI

EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0

Control Register

Address

Data Byte Length

Hi-Z

O7 O6 O5 O4 O3 O2 O1 O0 O7 O6 O5 O4 O3 O2 O1 O0 C7 C6 C5 C4 C3 C2 C1 C0

Hi-Z

SDO

with CRC = “1”

for Read = “1”

Read Data

CRC Code

Figure 5-6. Data Read Communication Format with CRC

The CRC computation is also performed for each transmitted/received data during data read operation and the result is

appended at the end of the read data. The external MCU can detect any communication errors by comparing the CRC

computation result and the received CRC. The CRC code is not included in the data byte length.

The above figure is the example that the number of the read byte data is 2 bytes (data of read byte’s number : 02h).

5.3

Multi Bytes Data Reading

The values of CURCD, AVE_CURCD, CC_CCNTD, CHG_CCNTD, DIS_CCNTD and EXADIN_VALUE registers are

updated on current measurement and current accumulation and when EXADIN_TRG is triggered.

Please start reading from MSB address regarding these registers. By reading MSB address of multiple bytes’ data, the value

is retained in the internal buffer. This avoids updating the read data while reading over multiple address. Reading from LSB

address may cause updating the data before finish reading all bytes.

If an access to another address is performed before reach to LSB address, read start from MSB address again. In this case,

the read data is the value at the time of starting to read MSB again.

Ex.) CURCD Reading

Correct order

Incorrect order : address 14h CURCD_L

: address 13h CURCD_H

→ address 14h CURCD_L

→ address 13h CURCD_H

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6.

EXADIN

6.1

Summary

ΔΣADC in BD7220FV-C has an input channel selectable function. A current value is monitored through AMP in normal

operation. It can also monitor the voltage of the outside EXADIN pin by a setting signal from SPI.

It is possible to measure a value such as voltage of a battery or a thermistor by time sharing by this EXADIN function. (During

the EXADIN pin measurement, it cannot measure a current value)

6.1.1

Features

The EXADIN pin which can A-D convert the analog data besides current is available (EXADIN Input voltage range: 0.5 V to

4.5 V)

6.1.2

Structure

Figure 6-1 indicates the connection and structure of the EXADIN pin.

AMPOUT

ADINP

Note)

VREF25

No current monitor during voltage

monitor from EXADIN

VCC

VREF15

VCC

INP

+

Current

Sense

INN

ΔΣ

ADC

-

Voltage Monitor

（When EXADIN_TRG enter）

EXADIN

ADINM

VREF25

Figure 6-1. EXADIN Block Diagram

6.2

Function Description

To monitor of the EXADIN pin voltage is carried out by writing in “1” to EXADIN_TRG register (address 02h

CC_TRG_RST_CMD [3]). After “1” was written in, EXADIN_TRG becomes “0” automatically.

2'b01（NORMAL)

MODE_SEL[1:0]

AMP

ON

OFF

ON

OFF

ON

ꢀ

First data conversion

ON

ADC

0(charge) 1(discharge)

0(charge)

1(discharge)

CURCD_DIR

CURCD[14:0]

CC_CCNTD[31:0]

Target to measure

Wait time

A

B

D

C (keep the last measured value during EXADIN measurement)

+A

-B

+C

-D

Stop accumulation of CCNTD during EXADIN measurement

current

nothing

voltage

nothing

current

INI_WAIT

CHG_TERM

INI_WAIT

CHG_TERM

-

ꢀ

-

EXADIN_TRG

EXADIN_VALUE[15:0]

Update the voltage measurement value

Y

Z

Figure 6-2. EXADIN Monitor Timing Chart

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7.

Register Map

Register

Initial

Value

Access

(R, R/W)

address

(dec)

address

(Hex)

Register Name

D7

D6

D5

D4

D3

D2

D1

D0

0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

CC_SET1

AMP_GAIN[1:0]

OSR[1:0]

MCIC_R[1:0]

-

CCNTEN

MODE_SEL[1:0]

80h

05h

00h

01h

00h

40h

00h

R/W

R

1

CC_SET2

CC_UNDIV

AVE_CURCD_COUNT[1:0]

CCNTD_MASK[2:0]

CHG_CCNTD_RST

-

2

CC_TRG_RST_CMD

CC_SET3

-

CALIB_TRG

-

EXADIN_TRG

DIS_CCNTD_RST

CCNTRST

REX_EN

3

SLEEP_CC_SEL

SLEEP_SAMPLING_TIME[1:0]

SLEEP_INTERVAL[1:0]

GAIN_CAL_FS

4

ADC_CALIB

-

CALIB_MODE[2:0]

5

GAIN10_2

GAIN10[17:14]

6

GAIN10_1

GAIN10[13:6]

7

GAIN10_0_GAIN30_2

GAIN30_1

GAIN10[5:0]

GAIN30[17:16]

8

GAIN30[15:8]

GAIN30[7:0]

OFST10[15:8]

OFST10[7:0]

9

GAIN30_0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

OFST10_H

OFST10_L

GAIN31_2

-

GAIN31[17:16]

GAIN31_1

GAIN31[15:8]

GAIN31[7:0]

R

GAIN31_0

R

CALVIN_DIFF_H

CALVIN_DIFF_L

EXADIN_VALUE_H

EXADIN_VALUE_L

CURCD_H

-

CALVIN_DIFF[11:8]

R/W

R

CALVIN_DIFF[7:0]

EXADIN_VALUE[15:8]

EXADIN_VALUE[7:0]

R

CURCD_DIR

CURCD[14:8]

R

CURCD_L

CURCD[7:0]

AVE_CURCD[14:8]

AVE_CURCD[7:0]

R

AVE_CURCD_H

AVE_CURCD_L

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

CHG_CCNTD_3

CHG_CCNTD_2

CHG_CCNTD_1

CHG_CCNTD_0

DIS_CCNTD_3

DIS_CCNTD_2

DIS_CCNTD_1

DIS_CCNTD_0

CC_BATCAP1_TH_2

CC_BATCAP1_TH_1

CC_BATCAP1_TH_0

CC_BATCAP2_TH_2

CC_BATCAP2_TH_1

CC_BATCAP2_TH_0

CC_BATCAP3_TH_2

CC_BATCAP3_TH_1

CC_BATCAP3_TH_0

CC_BATCAP4_TH_2

CC_BATCAP4_TH_1

CC_BATCAP4_TH_0

OCURTHR1_H

OCURTHR1_L

OCURTHR2_H

OCURTHR2_L

OCURTHR3_H

OCURTHR3_L

CC_SET4

AVE_CURCD_DIR

R

CC_CCNTD[31:24]

CC_CCNTD[23:16]

R/W

CC_CCNTD[15:8]

CC_CCNTD[7:0]

CHG_CCNTD[31:24]

CHG_CCNTD[23:16]

CHG_CCNTD[15:8]

CHG_CCNTD[7:0]

DIS_CCNTD[31:24]

DIS_CCNTD[23:16]

DIS_CCNTD[15:8]

DIS_CCNTD[7:0]

CC_BATCAP1_TH[23:16]

CC_BATCAP1_TH[15:8]

CC_BATCAP1_TH[7:0]

CC_BATCAP2_TH[23:16]

CC_BATCAP2_TH[15:8]

CC_BATCAP2_TH[7:0]

CC_BATCAP3_TH[23:16]

CC_BATCAP3_TH[15:8]

CC_BATCAP3_TH[7:0]

CC_BATCAP4_TH[23:16]

CC_BATCAP4_TH[15:8]

CC_BATCAP4_TH[7:0]

OCURTHR1_DIR

OCURTHR2_DIR

OCURTHR3_DIR

OCURTHR1[14:8]

OCURTHR1[7:0]

OCURTHR2[14:8]

OCURTHR2[7:0]

OCURTHR3[14:8]

OCURTHR3[7:0]

REX_DUR[1:0]

OCURDUR3[1:0]

INI_WAIT[1:0]

OCURDUR2[1:0]

OCURDUR1[1:0]

REX_CURCD_TH

WAKE_CURCD_TH

CC_SET5

REX_CURCD_TH[7:0]

WAKE_CURCD_TH[7:0]

-

CC_MON4_RES_EN

OCUR3_RES_EN

-

WAKE_COUNT[1:0]

CC_MON1_RES_EN CC_MON1_DET_EN

ALARM_OCUR1_RES_ENALARM_OCUR1_DET_EN 00h

INT_EN1

CC_MON4_DET_EN

OCUR3_DET_EN

CALIB_FIN_EN

CC_MON4_DET

OCUR3_DET

CALIB_FIN

CC_MON3_RES_EN

OCUR2_RES_EN

-

CC_MON3_DET_EN

OCUR2_DET_EN

CRCERR_DET_EN

CC_MON3_DET

OCUR2_DET

CRCERR_DET

-

CC_MON2_RES_EN

CC_MON2_DET_EN

OCUR1_DET_EN

REX_DET_EN

CC_MON2_DET

OCUR1_DET

REX_DET

INT_EN2

OCUR1_RES_EN

INT_EN3

-

WAKE_RES_EN

CC_MON1_RES

-

WAKE_DET_EN

CC_MON1_DET

-

00h

INT_REQ1

CC_MON4_RES

OCUR3_RES

-

CC_MON3_RES

OCUR2_RES

OTP_DL_FIN

-

CC_MON2_RES

INT_REQ2

OCUR1_RES

INT_REQ3

-

WAKE_RES

WAKE_DET

PAGE_SEL

HOSC_ON

-

PAGE_SEL[1:0]

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Address 00h: CC_SET1 Register (R/W)

Address

(Index)

Register Name

CC_SET1

R/W

80h

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

CCNTEN

0

Bit1

Bit0

0

AMP_GAIN[1:0]

MCIC_R[1:0]

-

MODE_SEL[1:0]

00h

Initial Value

1

0

Bit 7-6 : AMP_GAIN[1:0]

00: 5 V/V

Differential amplifier gain

reshuffling register

Depending on the measurement current range, it is necessary to choose an appropriate

amplifier gain setting. Reference measurement current range when attaching

a shunt resistance of 0.2 mΩ is as follows. (Refer to Table 1-1)

-1000 A to +2000 A -> 5 V/V

01: 25 V/V

10: 25 V/V (default)

11: 51 V/V

±400 A -> 25 V/V

±200 A -> 51 V/V

Bit 5-4 : MCIC_R[1:0]

00: 32 (default)

01: 128

Built-in digital filter of Δ Σ ADC

(down sampling)

Changing the sampling time and filter response of built-in digital filter for ADC.

The parameters that change under the influence of MCIC_R are as follows.

10: 256

CURCD[14:0]

11: 1024

CURCD data are updated every ADC sampling time, based on Table 1-5.

AVE_CURCD[14:0]

AVE_CURCD data are updated every Average time, based on Table 1-4.

CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0]

According to Table 2-3, the number of measurements during SLEEP mode is changed by MCIC_R.

CC_CCNTD, CHG_CCNTD, DIS_CCNTD data update is constant (250μs).

Bit 2 :

CCNTEN

Enable Coulomb counter

CCNTEN=1 enables current accumulation.

0: Coulomb counter OFF (default)

1: Coulomb counter ON

Based on CURCD data (refer to section 1.3.1), current accumulation and

output current accumulation data. (refer to section 1.3.2) Current accumulation data can read via SPI.

There are 3 kinds of current accumulation data: CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0]

CCNTEN=0 to disables current accumulation.

When disabled, CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0] keep the last data written.

When CCNTEN = 0, CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0] can overwrite

by SPI command.

Whether CCNTEN = 0 or 1, CC_CCNTD[31:0] is reset to “0” by CCNTRST=1.

Whether CCNTEN = 0 or 1, CHG_CCNTD[31:0] is reset to “0” by CHG_CCNTD_RST=1.

Whether CCNTEN = 0 or 1, DIS_CCNTD[31:0] is reset to “0” by DIS_CCNTD_RST=1.

Bit 1-0 : MODE_SEL[1:0]

00: (default) which does not shift

Operation mode choice

Operation mode can be changed from IDEL to any of three mode in left, NORMAL, SLEEP and SSHDN.

In the NORMAL, SLEEP and SSHDN mode, transition is possible by SPI command freely.

Operation mode is not changed by writing “00”. (Remaining current mode)

01: NORMAL

10: SLEEP

11: SSHDN

Address 01h: CC_SET2 Register (R/W)

Address

(Index)

Register Name

CC_SET2

R/W

05h

Bit7

0

Bit6

0

Bit5

CC_UNDIV

0

Bit4

Bit3

Bit2

1

Bit1

Bit0

1

OSR[1:0]

AVE_CURCD_COUNT[1:0]

CCNTD_MASK[2:0]

0

01h

Initial Value

0

Bit 7-6 : OSR[1:0]

00: 32(OSF=128kHz) (default)

Over sampling rate setting

※OSF=Over Sampling Frequency

Over sampling rate settings for built in Δ Σ ADC.

The parameters to change under the influence of OSR are as follows.

01: 128(OSF=512kHz)

10: 512(OSF=2.048MHz)

11: 32(OSF=128kHz)

CURCD[14:0]

CURCD data are updated every ADC sampling time of table 1-5.

AVE_CURCD[14:0]

AVE_CURCD data are updated every average time of table 1-4.

CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0]

According to setting of table 2-3, the Number of measurement during SLEEP mode

is changed by MCIC_R setting. CC_CCNTD, CHG_CCNTD, DIS_CCNTD data update

is constant in every 250 μs.

Bit 5 :

CC_UNDIV

0: Enable (default)

1: Disable

Enable scaled accumulation

To cancel the variation of LSB current in each gain setting, built-in calculation logic

circuit can perform scaled calculation of current accumulation.

So, LSB of current accumulation is constant regardless of gain setting.

CC_UNDIV controls if this function is enabled.

Under the configulation of CC_UNDIV = 0, scaled calculation, gain setting can

be changed with small error.

Under the configulation of CC_UNDIV = 1, not scaled caluclation, gain setting is

fixed but there is no error caused by scaling.

Note that, compare to the capacity at 5 V/V gain, the current accumulation capacity

is reduced depending on setting of gain, 1/5 at 25 V/V and 1/10.2 at 51 V/V.

( LSB of current accumulation is changed)

Bit 4-3 : AVE_CURCD_COUNT[1:0]

00: 4 times (default)

01: 16 times

Measurement count for average current

calculation of a fixed time interval

The current measurement value of each fixed time interval can be calculated as an average

value. It is not a moving average.

AVE_CURCD_COUNT sets the number of measurements to be averaged.

Average is caluculated from accumulating the A-D converted data for the times

configured in AVE_CURCD_COUNT.

10: 64 times

11: 128 times

Fixed interval is configured with the setting of digital filter (address 00h:MCIC_R[1:0]),

the setting of OSR(address 00h:OSR[1:0]), and the setting of measurement number

(address 01h: AVE_CURCD_COUNT[1:0])

Bit 2-0 : CCNTD_MASK[2:0]

000: 7bits mask (effective 11bits)

001: 6bits mask (effective 12bits)

010: 5bits mask (effective 13bits)

011: 4bits mask (effective 14bits)

100: 3bits mask (effective 15bits)

Bit mask function for current accumulation

CCNTD_MASK sets the lower bit masked from the measurement current

value during current accumulation. When masked, these bits are set to “0”.

101: 2bits mask (effective 16bits) (default)

110: 1bit mask (effective 17bits)

111: 0bit mask (effective 18bits)

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Address 02h: CC_TRG_RST_CMD Register (R/W)

Address

(Index)

Register Name

CC_TRG_RST_CMD

Initial Value

R/W

00h

Bit7

Bit6

Bit5

CALIB_TRG

0

Bit4

Bit3

EXADIN_TRG

0

Bit2

Bit1

Bit0

CCNTRST

0

DIS_CCNTD_RST CHG_CCNTD_RST

-

02h

0

Bit 5 :

CALIB_TRG

0: No trigger for calibration

1: Calibration start trigger

Calibration trigger

※After “1” is written, value returns to “0” automatically

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

EXADIN_TRG

0: Current measurement

1: Switch Δ Σ ADC input to EXADIN (EXADIN pin voltage reading)

Δ Σ ADC input signal change trigger

DIS_CCNTD_RST

0: No Reset

1: Reset DIS_CCNTD

Discharge current accumulation

(DIS_CCNTD) reset

※After “1” is written, value returns to “0” automatically

CHG_CCNTD_RST

0: No Reset

1: Reset CHG_CCNTD

Charge current accumulation

(CHG_CCNTD) reset

CCNTRST

0: No Reset

Current accumulation

(CC_CCNTD) reset

1: Reset CC_CCNTD

Address 03h: CC_SET3 Register (R/W)

Address

(Index)

Register Name

CC_SET3

R/W

01h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

REX_EN

1

SLEEP_CC_SEL

0

-

SLEEP_SAMPLING_TIME[1:0]

SLEEP_INTERVAL[1:0]

-

03h

Initial Value

0

Bit 6 :

SLEEP_CC_SEL

Current accumulation method in SLEEP mode, during the OFF period

0: Accumulate the last current measurement taken during the ON period. (default)

1: Accumulate the average of measurements taken during the ON period.

Bit 5-4 : SLEEP_SAMPLING_TIME[1:0]

Number of current accumulation when ON

during SLEEP mode.

The parameters that change under the influence of SLEEP_SAMPLING_TIME are

as follows. CC_CCNTD[31:0], CHG_CCNTD[31:0], DIS_CCNTD[31:0]

The number of current accumulations in SLEEP mode are decided as in Table 2-3.

The current accumulation data update is constant for every 250ꢀμs.

If ADC sampling period < 2 [ms]:

00: 1 (default)

01: 16

10: 32

11: 64

If ADC sampling period ≥2 [ms]:

00: 1 (default)

01: 2

10: 4

11: 8

Bit 3-2 : SLEEP_INTERVAL[1:0]

00: ON/OFF=1:7 (default)

01: ON/OFF=1:15

ON/OFF time ratio during SLEEP mode

10: ON/OFF=1:31

11: ON/OFF=1:127

Bit 0 :

REX_EN

0: RELAX timer OFF

1: RELAX timer ONꢀ(default)

Relax state detection timer enable

When REX_EN=1, if CURCD[14:0](13h+14h) ≤ { 7'd0, REX_CURCD_TH[7:0](36h)},

the relax timer starts.

If REX_EN = 1 → 0 is set while the timer is counting, the timer counter is reset to 0.

(Note that not keep the value but reset)

If REX_EN= 0 → 1 again, start counting from value = 0.

Address 04h: ADC_CALIB Register (R/W)

Address

(Index)

Register Name

ADC_CALIB

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

0

Bit1

Bit0

0

-

GAIN_CAL_FS

0

CALIB_MODE[2:0]

0

04h

0

Bit 3 :

GAIN_CAL_FS

0: Negative full scale (MFS) direction

1: Positive full scale (PFS) direction

Input polarity for GAIN calibration

Calibration mode setting

Bit 2-0 : CALIB_MODE[2:0]

000: Normal operation (default)

*Do not use any of the “Reserved” modes. (011, 100, 101, 110, 111)

001: Mode2 (GAIN)

010: Mode2 (OFFSET)

011: Reserved

Calibration revision value may shift.

100: Reserved

101: Reserved

110: Reserved

111: Reserved

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Address 05h: GAIN10_2 Register (R/W)

Address

(Index)

Register Name

GAIN10_2

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

0

Bit2

Bit1

0

Bit0

0

-

GAIN10[17:14]

05h

Initial Value

0

Address 06h: GAIN10_1 Register (R/W)

Address

(Index)

Register Name

GAIN10_1

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

GAIN10[13:6]

06h

Initial Value

Address 07h: GAIN10_0_GAIN30_2 Register (R/W)

Address

(Index)

Register Name

GAIN10_0_GAIN30_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

Bit0

0

GAIN10[5:0]

GAIN30[17:16]

07h

0

GAIN10[17:0]

Mode 2 gain calibration value

※Register data is cleared on reset (SHDNB=L or VCC UVLO).

Please keep register data in nonvolatile memory on the system and rewrite

after IC restarts.

Address 08h: GAIN30_1 Register (R/W)

Address

(Index)

Register Name

GAIN30_1

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

GAIN30[15:8]

08h

Initial Value

Address 09h: GAIN30_0 Register (R/W)

Address

(Index)

Register Name

GAIN30_0

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

GAIN30[7:0]

09h

Initial Value

GAIN30[17:0]

Mode 3 gain calibration value

※Register data is cleared on reset (SHDNB=L or VCC UVLO).

Please keep register data in nonvolatile memory on the system and rewrite

after IC restarts.

Address 0Ah: OFST10_H Register (R/W)

Address

(Index)

Register Name

OFST10_H

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

OFST10[15:8]

Bit3

0

Bit2

0

Bit1

0

Bit0

0

0Ah

0

Address 0Bh: OFST10_L Register (R/W)

Address

(Index)

Register Name

OFST10_L

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

OFST10[7:0]

0Bh

Initial Value

OFST10[15:0]

Mode 2 offset calibration value

※Register data is cleared on reset (SHDNB=L or VCC UVLO).

Please keep register data in nonvolatile memory on the system and rewrite

after IC restarts.

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Address 0Ch: GAIN31_2 Register (R)

Address

(Index)

Register Name

GAIN31_2

R/W

R

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

Bit0

0

-

GAIN31[17:16]

0Ch

Initial Value

00h

0

Address 0Dh: GAIN31_1 Register (R)

Address

(Index)

Register Name

GAIN31_1

R/W

R

Bit7

0

Bit6

1

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

GAIN31[15:8]

0Dh

Initial Value

40h

Address 0Eh: GAIN31_0 Register (R)

Address

(Index)

Register Name

GAIN31_0

R/W

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

R

GAIN31[7:0]

0Eh

Initial Value

00h

GAIN31[17:0]

Register for the GAIN30 operation

(GAIN30 is register for the manual setting)

Address 0Fh: CALVIN_DIFF_H Register (R/W)

Address

(Index)

Register Name

CALVIN_DIFF_H

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

0

Bit2

Bit1

0

Bit0

0

-

CALVIN_DIFF[11:8]

0Fh

0

Bit2

0

Address 10h: CALVIN_DIFF_L Register (R/W)

Address

(Index)

Register Name

CALVIN_DIFF_L

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit1

0

Bit0

0

CALVIN_DIFF[7:0]

10h

0

CALVIN_DIFF[11:0]

Mode 2 calibration setting register

Input differential voltage information between INP and INN for GAIN calibration

Address 11h: EXADIN_VALUE_H Register (R)

Address

(Index)

Register Name

EXADIN_VALUE_H

Initial Value

R/W

R

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

EXADIN_VALUE[15:8]

11h

00h

0

Address 12h: EXADIN_VALUE_L Register (R)

Address

(Index)

Register Name

EXADIN_VALUE_L

Initial Value

R/W

R

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

EXADIN_VALUE[7:0]

12h

00h

0

EXADIN_VALUE[15:0]

Measurement value of EXADIN input

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Address 13h: CURCD_H Register (R)

Address

(Index)

Register Name

CURCD_H

R/W

Bit7

CURCD_DIR

0

Bit6

0

Bit5

0

Bit4

0

Bit3

CURCD[14:8]

0

Bit2

0

Bit1

0

Bit0

0

R

13h

Initial Value

00h

Bit 7:

CURCD_DIR

0: Charge

Current direction bit

(INP pin voltage > INN pin voltage)

1: Discharge

(INP pin voltage < INN pin voltage)

Address 14h: CURCD_L Register (R)

Address

(Index)

Register Name

CURCD_L

R/W

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

R

CURCD[7:0]

14h

Initial Value

00h

0

CURCD[14:0]

Current value

LSB unit of CURCD depending on the gain setting is described in Chapter 1.3.1.

The reference level when attaching an external 0.2 mΩ resistance is as follows.

(see Table 1-1)

5 V/V gain: LSB current ≈ 68.66 mA

25 V/V gain: LSB current ≈13.73 mA

51 V/V gain: LSB current ≈ 6.73 mA

ex.) When a 1,000 mA current flows, the register level is as follows.

5 V/V gain: 1000/LSB current ≈ 1000/68.66≈14 => CURCD=15'h000E

25 V/V gain: 1000/LSB current ≈ 1000/13.73≈72 => CURCD=15'h0048

51 V/V gain: 1000/LSB current ≈ 1000/6.73≈148 => CURCD=15'h0094

Address 15h: AVE_CURCD_H Register (R)

Address

(Index)

Register Name

AVE_CURCD_H

Initial Value

R/W

R

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

AVE_CURCD_DIR

0

AVE_CURCD[14:8]

0

15h

00h

Bit 7:

AVE_CURCD_DIR

0: Charge

Average current direction bit

(INP pin voltage > INN pin voltage)

1: Discharge

(INP pin voltage <INN pin voltage)

Address 16h: AVE_CURCD_L Register (R)

Address

(Index)

Register Name

AVE_CURCD_L

Initial Value

R/W

R

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

AVE_CURCD[7:0]

16h

00h

0

AVE_CURCD[14:0]

Average Current value

Number of averaging is set in AVE_CURCD_COUNT(01h)

LSB unit of CURCD depending on the gain setting is described in Chapter 1.3.1.

The reference level when attaching an external 0.2 mΩ resistance is as follows.

(see Table 1-1)

5 V/V gain: LSB current ≈ 68.66 mA

25 V/V gain: LSB current ≈13.73 mA

51 V/V gain: LSB current ≈ 6.73 mA

ex.) When a 1,000 mA current flows, the register level is as follows.

5 V/V gain: 1000/LSB current ≈ 1000/68.66≈14 => CURCD=15'h000E

25 V/V gain: 1000/LSB current ≈ 1000/13.73≈72 => CURCD=15'h0048

51 V/V gain: 1000/LSB current ≈ 1000/6.73≈148 => CURCD=15'h0094

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Address 17h: CC_CCNTD_3 Register (R/W)

Address

(Index)

Register Name

CC_CCNTD_3

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

CC_CCNTD[31:24]

17h

0

Address 18h: CC_CCNTD_2 Register (R/W)

Address

(Index)

Register Name

CC_CCNTD_2

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_CCNTD[23:16]

18h

0

Address 19h: CC_CCNTD_1 Register (R/W)

Address

(Index)

Register Name

CC_CCNTD_1

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

CC_CCNTD[15:8]

19h

0

Address 1Ah: CC_CCNTD_0 Register (R/W)

Address

(Index)

Register Name

CC_CCNTD_0

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_CCNTD[7:0]

1Ah

0

CC_CCNTD[31:0]

Current Accumulation register

LSB unit of CC_CCNTD depending on the gain setting is described in Chapter 1.3.2.

The reference level when attaching an external 0.2 mΩ resistance and

CC_UNDIV=0 is as follows.

ꢀLSB level ≈ 0.3052 μAh

ꢀMSB level = 655.36 Ah

When CC_UNDIV=1, the current accumulation unit varies depending on setting

of AMP_GAIN. (see table 1-2)

Address 1Bh: CHG_CCNTD_3 Register (R/W)

Address

(Index)

Register Name

CHG_CCNTD_3

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CHG_CCNTD[31:24]

1Bh

0

Address 1Ch: CHG_CCNTD_2 Register (R/W)

Address

(Index)

Register Name

CHG_CCNTD_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CHG_CCNTD[23:16]

1Ch

0

Address 1Dh: CHG_CCNTD_1 Register (R/W)

Address

(Index)

Register Name

CHG_CCNTD_1

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CHG_CCNTD[15:8]

1Dh

0

Address 1Eh: CHG_CCNTD_0 Register (R/W)

Address

(Index)

Register Name

CHG_CCNTD_0

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

CHG_CCNTD[7:0]

1Eh

0

CHG_CCNTD[31:0]

Charge Current Accumulation register

※see Chapter 1.3.2

CC_CCNTD_3

CC_CCNTD_2

16 15

CC_CCNTD_1

CC_CCNTD_0

31

24 23

8

7

0

CHG_CCNTD_3

CHG_CCNTD_2

CHG_CCNTD_1

CHG_CCNTD_0

31

24 23

16 15

8

7

0

LSB of CHG_CCNTD is equivalent to bit[2] of CC_CCNTD.

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Address 1Fh: DIS_CCNTD_3 Register (R/W)

Address

(Index)

Register Name

DIS_CCNTD_3

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

DIS_CCNTD[31:24]

1Fh

0

Address 20h: DIS_CCNTD_2 Register (R/W)

Address

(Index)

Register Name

DIS_CCNTD_2

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

DIS_CCNTD[23:16]

20h

0

Address 21h: DIS_CCNTD_1 Register (R/W)

Address

(Index)

Register Name

DIS_CCNTD_1

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

DIS_CCNTD[15:8]

21h

0

Address 22h: DIS_CCNTD_0 Register (R/W)

Address

(Index)

Register Name

DIS_CCNTD_0

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

DIS_CCNTD[7:0]

22h

0

DIS_CCNTD[31:0]

Discharge Current Accumulation register

※see chapter 1.3.2

CC_CCNTD_3

CC_CCNTD_2

16 15

CC_CCNTD_1

CC_CCNTD_0

31

24 23

8

7

0

DIS_CCNTD_3

DIS_CCNTD_2

DIS_CCNTD_1

DIS_CCNTD_0

31

24 23

16 15

8

7

0

LSB of DIS_CCNTD is equivalent to bit[2] of CC_CCNTD.

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Address 23h: CC_BATCAP1_TH_2 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP1_TH_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP1_TH[23:16]

23h

0

Address 24h: CC_BATCAP1_TH_1 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP1_TH_1

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP1_TH[15:8]

24h

0

Address 25h: CC_BATCAP1_TH_0 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP1_TH_0

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0

CC_BATCAP1_TH[7:0]

25h

0

7

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

CC_BATCAP1_TH[23:0]

Threshold of current

accumulation detection1

31

23

24 23

16 15

8

0

CC_BATCAP#_TH2

CC_BATCAP#_TH1

CC_BATCAP#_TH0

16 15

8

7

For higher 24bit of CC_CCNTD, set the detection of current accumulation threshold.

(The setting method is the same for CC_BATCAP1 to 4_TH)

LSB level of CC_BATCAP1_TH and the MSB levels are as follows

(when CC_UNDIV=0)

LSB level =78.125 μAh

MSB level =655.36 Ah

The LSB value and MSB value of CC_CCNTD are as follows. (Refer to section 1.3.2)

LSB level ≈0.3052 μAh

MSB level =655.36 Ah

ex.) To set the detection threshold of current accumulation to 1Ah,

the register values are as follows.

1[Ah]/78.125[μAh]=12800 => CC_BATCAP1_TH[23:0]=24'h003200(24'd12800)

The threshold range is as follows.

Thresholding range =78.125 μAh to 1310.72 Ah

When CC_UNDIV=1, unit of current accumulation varies depending on setting of

AMP_GAIN. (see Table 1-2)

Address 26h: CC_BATCAP2_TH_2 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP2_TH_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP2_TH[23:16]

26h

0

Address 27h: CC_BATCAP2_TH_1 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP2_TH_1

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP2_TH[15:8]

27h

0

Address 28h: CC_BATCAP2_TH_0 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP2_TH_0

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP2_TH[7:0]

28h

0

CC_BATCAP2_TH[23:0]:

Threshold of current accumulation detection2

※Refer to CC_BATCAP1_TH for the setting

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Address 29h: CC_BATCAP3_TH_2 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP3_TH_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP3_TH[23:16]

29h

0

Address 2Ah: CC_BATCAP3_TH_1 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP3_TH_1

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP3_TH[15:8]

2Ah

0

Address 2Bh: CC_BATCAP3_TH_0 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP3_TH_0

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP3_TH[7:0]

2Bh

0

CC_BATCAP3_TH[23:0]

Threshold of current accumulation detection3

※Refer to CC_BATCAP1_TH for the setting

Address 2Ch: CC_BATCAP4_TH_2 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP4_TH_2

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP4_TH[23:16]

2Ch

0

Address 2Dh: CC_BATCAP4_TH_1 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP4_TH_1

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP4_TH[15:8]

2Dh

0

Address 2Eh: CC_BATCAP4_TH_0 Register (R/W)

Address

(Index)

Register Name

CC_BATCAP4_TH_0

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

CC_BATCAP4_TH[7:0]

2Eh

0

CC_BATCAP4_TH[23:0]

Threshold of current accumulation detection4

※Refer to CC_BATCAP1_TH for the setting

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BD7220FV-C

Address 2Fh: OCURTHR1_H Register (R/W)

Address

(Index)

Register Name

OCURTHR1_H

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

OCURTHR1_DIR

0

OCURTHR1[14:8]

0

2Fh

Bit 7:

OCURTHR1_DIR:

0: Charge

Current direction setting of OCURTHR1

(INP pin voltage > INN pin voltage)

1: Discharge

(INP pin voltage <INN pin voltage)

Address 30h: OCURTHR1_L Register (R/W)

Address

(Index)

Register Name

OCURTHR1_L

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

OCURTHR1[7:0]

30h

0

OCURTHR1[14:0]:

Threshold of measurement current detection1

LSB unit of CURCD depending on the gain setting is described in Chapter 1.3.1.

The reference level when attaching an external 0.2mΩ resistance is as follows.

(Refer to table 1-1)

5 V/V gain: LSB electric current level ≈ 68.66 mA

25 V/V gain: LSB electric current level ≈ 13.73 mA

51 V/V gain: LSB electric current level ≈ 6.73 mA

Sign

CURCD_H

CURCD_L

0

15 14

8

7

Sign

OCURTHR#_H

OCURTHR#_L

0

ex.) When a current value of 1,000mA flows, the register level is as follows.

OCCURTHR1_DIR = 0 and

15 14

7

5 V/V gain: 1000/LSB current ≈ 1000/68.66≈14 => OCURTHR1=15'h000E

25 V/V gain: 1000/LSB current ≈ 1000/13.73≈72 => OCURTHR1=15'h0048

51 V/V gain: 1000/LSB current ≈ 1000/6.73≈148 => OCURTHR1=15'h0094

The thresholding ranges are as follows.

5 V/V gain: Thresholding range ≈ -1000 A to +2000 A

25 V/V gain: Thresholding range ≈ -400A to +400 A

51 V/V gain: Thresholding range ≈ -200 A to +200 A

Threshold range is different from measurement current range.

When OCURTHR1_DIR = 0, detection of charging direction of measurement

current interrupt be set. An interrupt occurs when:

OCUR1_DET_EN (3Ah) = 1 and

CURCD (13h + 14h) > OCURTHR1 (2Fh + 30h) and

over the consecutive detection setting by OCURDUR1[1:0](35h)

OCUR1_RES_EN (3Ah) = 1 and

CURCD (13h + 14h) ≤ OCURTHR1 (2Fh + 30h) and

over the consecutive detection setting by OCURDUR1[1:0](35h)

When OCURTHR1_DIR = 1, detection of discharging direction of measurement

current interrupt be set.An interrupt occurs when:

OCUR1_DET_EN (3Ah) = 1 and

CURCD (13h + 14h) > OCURTHR1 (2Fh + 30h) and

over the consecutive detection setting by OCURDUR1[1:0](35h)

OCUR1_RES_EN (3Ah) = 1 and

CURCD (13h + 14h) ≤ OCURTHR1 (2Fh + 30h) and

over the consecutive detection setting by OCURDUR1[1:0](35h)

Address 31h: OCURTHR2_H Register (R/W)

Address

(Index)

Register Name

OCURTHR2_H

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

OCURTHR2_DIR

0

OCURTHR2[14:8]

0

31h

Bit 7:

OCURTHR2_DIR

0: Charge

Current direction setting of OCURTHR2

(INP pin voltage > INN pin voltage)

1: Discharge

(INP pin voltage <INN pin voltage)

Address 32h: OCURTHR2_L Register (R/W)

Address

(Index)

Register Name

OCURTHR2_L

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

OCURTHR2[7:0]

32h

0

OCURTHR2[14:0]

Threshold of measurement current detection2

Refer to OCURTHR1 for the setting

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Address 33h: OCURTHR3_H Register (R/W)

Address

(Index)

Register Name

OCURTHR3_H

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

OCURTHR3_DIR

0

OCURTHR3[14:8]

0

33h

Bit 7:

OCURTHR3_DIR

0: Charge

Current direction setting of OCURTHR3

(INP pin voltage > INN pin voltage)

1: Discharge

(INP pin voltage <INN pin voltage)

Address 34h: OCURTHR3_L Register (R/W)

Address

(Index)

Register Name

OCURTHR3_L

Initial Value

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

0

OCURTHR3[7:0]

34h

0

OCURTHR3[14:0]

Threshold of measurement current detection3

Refer to OCURTHR1 for the setting

Address 35h: CC_SET4 Register (R/W)

Address

(Index)

Register Name

CC_SET4

R/W

00h

Bit7

Bit6

0

Bit5

Bit4

0

Bit3

0

Bit2

Bit1

Bit0

0

REX_DUR[1:0]

OCURDUR3[1:0]

OCURDUR2[1:0]

OCURDUR1[1:0]

35h

Initial Value

0

Bit 7-6:

Bit 5-4:

Bit 3-2:

Bit 1-0:

REX_DUR[1:0]

00:30 minutes(default)

01:60 minutes

10:90 minutes

11:120 minutes

Relaxation state detection time

Refer to REX_CURCD_TH for the relaxation state detection setting

OCURDUR3[1:0]

00:1 time(default)

01:4 times

10:8 times

11:16 times

Count for detection of measurement current

ex. If CURDUR3 = 4 times, when detect over or under current value 4times,

interrupt occurs.

Refer to OCURTHR1, OCUR1_DET_EN, OCUR1_RES_EN

OCURDUR2[1:0]

00:1 time(default)

01:4 times

10:8 times

11:16 times

ex. If CURDUR2 = 4 times, when detect over or under current value 4times,

interrupt occurs.

Refer to OCURTHR1, OCUR1_DET_EN, OCUR1_RES_EN

OCURDUR1[1:0]

00:1 time(default)

01:4 times

ex. If CURDUR1 = 4 times, when detect over or under current value 4times,

interrupt occurs.

Refer to OCURTHR1, OCUR1_DET_EN, OCUR1_RES_EN

10:8 times

11:16 times

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Address 36h: REX_CURCD_TH Register (R/W)

Address

(Index)

Register Name

REX_CURCD_TH

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

REX_CURCD_TH[7:0]

36h

0

REX_CURCD_TH[7:0]

Threshold of the relaxation state detection

measurement current

Refer to REX_EN about relax timer setting

(Relaxation timer is enable when REX_EN=1)

REX_CURCD_TH can be set in the lower 8 bits of CURCD. (unsigned 8 bits expression)

Sign

15 14

CURCD_H

CURCD_L

0

LSB unit of CURCD depending on the gain setting is described in Chapter 1.3.1.

The reference level when attaching an external 0.2mΩ resistance is as follows.

(Refer to Table 1-1)

5 V/V gain: LSB current ≈ 68.66 mA

25 V/V gain: LSB current ≈ 13.73 mA

8

7

REX_CURCD_TH

0

51 V/V gain: LSB current ≈ 6.73 mA

ex.) When a 1,000mA current flows, the register level is as follows.

5 V/V gain: 1000/LSB current ≈ 1000/68.66 ≈ 14 => REX_CURCD_TH=15'h000E

25 V/V gain: 1000/LSB current ≈ 1000/13.73 ≈ 72 => REX_CURCD_TH=15'h0048

51 V/V gain: 1000/LSB current ≈ 1000/6.73 ≈ 148 => REX_CURCD_TH=15'h0094

The threshold ranges are as follows.

5 V/V gain: Threshold range ≈ 0 to 17.51 A

25 V/V gain: Threshold range ≈ 0 to 3.50 A

51 V/V gain: Threshold range ≈ 0 to 1.72 A

An interrupt occurs when:

REX_DET_EN(3Bh) = 1 and

CURCD[14:0] (13h + 14h) ≤ { 7'd0, REX_CURCD_TH[7:0] (36h) } and

Relaxation state detection time over the setting by REX_DUR[1:0](35h)

Address 37h: WAKE_CURCD_TH Register (R/W)

Address

(Index)

Register Name

WAKE_CURCD_TH

Initial Value

R/W

00h

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

WAKE_CURCD_TH[7:0]

37h

0

WAKE_CURCD_TH[7:0]

CURCD_H

Threshold of wake-up current detection

WAKE_CURCD_TH can be set in the lower 8 bits of CURCD. (unsigned 8 bits expression)

LSB unit of CURCD depending on the gain setting is described in Chapter 1.3.1.

The reference level when attaching an external 0.2 mΩ resistance is as follows.

(Refer to Table 1-1)

5 V/V gain: LSB current ≈ 68.66 mA

25 V/V gain: LSB current ≈ 13.73 mA

Sign

15 14

CURCD_L

0

8

7

WAKE_CURCD_TH

51 V/V gain: LSB current ≈ 6.73 mA

0

ex.) When a 1,000 mA current flows, the register level is as follows.

5 V/V gain: 1000/LSB current ≈ 1000/68.66≈14 => WAKE_CURCD_TH=15'h000E

25 V/V gain: 1000/LSB current ≈ 1000/13.73≈72 => WAKE_CURCD_TH=15'h0048

51 V/V gain: 1000/LSB current ≈ 1000/6.73≈148 => WAKE_CURCD_TH=15'h0094

The threshold ranges are as follows.

5V/V gain: Threshold range ≈ 0 to 17.51A

25V/V gain: Threshold range ≈ 0 to 3.50A

51V/V gain: Threshold range ≈ 0 to 1.72A

The WAKE_RES interrupt occurs when:

WAKE_RES_EN(3Bh) = 1 and

CURCD[14:0] (13h + 14h) ≤ { 7'd0, WAKE_CURCD_TH[7:0] (37h) } and

Wake up current detection over the setting by WAKE_COUNT[1:0](38h)

The WAKE_DET interrupt occurs when:

WAKE_DET_EN(3Bh) = 1 and

CURCD[14:0] (13h + 14h) > { 7'd0, WAKE_CURCD_TH[7:0] (37h) } and

Wake up current detection over the setting by WAKE_COUNT[1:0](38h)

Address 38h: CC_SET5 Register (R/W)

Address

(Index)

Register Name

CC_SET5

R/W

00h

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

Bit0

-

INI_WAIT[1:0]

-

WAKE_COUNT[1:0]

38h

Initial Value

0

Bit 5-4 : INI_WAIT[1:0]

00: 1.5ms(default)

Initial wait time setting

The INI_WAIT register sets initial wait time for start of VREF25 and AMP

01: 3.0ms

10: 6.0ms

11: 12.0ms

Bit 1-0 : WAKE_COUNT[1:0]

00: 1 time(default)

01: 4 times

Wake up current detection count

Refer to WAKE_CURCD_TH for the wake up current detection setting

10: 8times

11: 16times

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Address 39h: INT_EN1 Register (R/W)

Address

(Index)

Register Name

INT_EN1

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CC_MON4_RES CC_MON4_DET CC_MON3_RES CC_MON3_DET CC_MON2_RES CC_MON2_DET CC_MON1_RES CC_MON1_DET

_EN

0

_EN

0

_EN

0

_EN

0

_EN

0

_EN

0

_EN

0

_EN

0

39h

Initial Value

Bit 7 :

CC_MON4_RES_EN

CC_MON4_DET_EN

CC_MON3_RES_EN

CC_MON3_DET_EN

CC_MON2_RES_EN

CC_MON2_DET_EN

CC_MON1_RES_EN

CC_MON1_DET_EN

Interrupt Enable :

Detection of discharging direction

current accumulation value4

1: Enableꢀ0: Disable

CC_MON4_RES_EN=1: CC_MON4_RES=1 -> INTB=L,CC_MON4_RES=0 -> INTB=Hi-z

CC_MON4_RES_EN=0: INTB=Hi-z (regardless of CC_MON4_RES)

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

Interrupt Enable :

Detection of charging direction

current accumulation value4

1: Enableꢀ0: Disable

CC_MON4_DET_EN=1: CC_MON4_DET=1 -> INTB=L, CC_MON4_DET=0 -> INTB=Hi-z

CC_MON4_DET_EN=0: INTB=Hi-z (regardless of CC_MON4_DET)

Interrupt Enable :

Detection of discharging direction

current accumulation value3

1: Enableꢀ0: Disable

CC_MON3_RES_EN=1: CC_MON3_RES=1 -> INTB=L,CC_MON3_RES=0 -> INTB=Hi-z

CC_MON3_RES_EN=0: INTB=Hi-z (regardless of CC_MON3_RES)

Interrupt Enable :

Detection of charging direction

current accumulation value3

1: Enableꢀ0: Disable

CC_MON3_DET_EN=1: CC_MON3_DET=1 -> INTB=L,CC_MON3_DET=0 -> INTB=Hi-z

CC_MON3_DET_EN=0: INTB=Hi-z (regardless of CC_MON3_DET)

Interrupt Enable :

Detection of discharging direction

current accumulation value2

1: Enableꢀ0: Disable

CC_MON2_RES_EN=1: CC_MON2_RES=1 -> INTB=L, CC_MON2_RES=0 -> INTB=Hi-z

CC_MON2_RES_EN=0: INTB=Hi-z (regardless of CC_MON2_RES)

Interrupt Enable :

Detection of charging direction

current accumulation value2

1: Enableꢀ0: Disable

CC_MON2_DET_EN=1: CC_MON2_DET=1 -> INTB=L, CC_MON2_DET=0 -> INTB=Hi-z

CC_MON2_DET_EN=0: INTB=Hi-z (regardless of CC_MON2_DET)

Interrupt Enable :

Detection of discharging direction

current accumulation value1

1: Enableꢀ0: Disable

CC_MON1_RES_EN=1: CC_MON1_RES=1 -> INTB=L, CC_MON1_RES=0 -> INTB=Hi-z

CC_MON1_RES_EN=0: INTB=Hi-z (regardless of CC_MON1_RES)

Interrupt Enable :

1: Enableꢀ0: Disable

Detection of charging direction

current accumulation value1

CC_MON1_DET_EN=1: CC_MON1_DET=1 -> INTB=L, CC_MON1_DET=0 -> INTB=Hi-z

CC_MON1_DET_EN=0: INTB=Hi-z (regardless of CC_MON1_DET)

Address 3Ah: INT_EN2 Register (R/W)

Address

(Index)

Register Name

INT_EN2

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ALARM_OCUR1 ALARM_OCUR1

OCUR3_RES_EN OCUR3_DET_EN OCUR2_RES_EN OCUR2_DET_EN OCUR1_RES_EN OCUR1_DET_EN

_RES_EN

0

_DET_EN

0

3Ah

Initial Value

0

Bit 7 :

OCUR3_RES_EN

Interrupt Enable :

1: Enableꢀ0: Disable

Detection of discharging direction

current measurement value3

OCUR3_RES_EN=1: OCUR3_RES=1 -> INTB=L, OCUR3_RES=0 -> INTB=Hi-z

OCUR3_RES_EN=0: INTB=Hi-z (regardless of OCUR3_RES)

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

OCUR3_DET_EN

OCUR2_RES_EN

OCUR2_DET_EN

OCUR1_RES_EN

OCUR1_DET_EN

ALARM_OCUR1_RES_EN

Interrupt Enable :

Detection of charging direction

current measurement value3

1: Enableꢀ0: Disable

OCUR3_DET_EN=1: OCUR3_DET=1 -> INTB=L, OCUR3_DET=0 -> INTB=Hi-z

OCUR3_DET_EN=0: INTB=Hi-z (regardless of OCUR3_DET)

Interrupt Enable :

Detection of discharging direction

current measurement value2

1: Enableꢀ0: Disable

OCUR2_RES_EN=1: OCUR2_RES=1 -> INTB=L, OCUR2_RES=0 -> INTB=Hi-z

OCUR2_RES_EN=0: INTB=Hi-z (regardless of OCUR2_RES)

Interrupt Enable :

Detection of charging direction

current measurement value2

1: Enableꢀ0: Disable

OCUR2_DET_EN=1: OCUR2_DET=1 -> INTB=L, OCUR2_DET=0 -> INTB=Hi-z

OCUR2_DET_EN=0: INTB=Hi-z (regardless of OCUR2_DET)

Interrupt Enable :

Detection of discharging direction

current measurement value1

1: Enableꢀ0: Disable

OCUR1_RES_EN=1: OCUR1_RES=1 -> INTB=L, OCUR1_RES=0 -> INTB=Hi-z

OCUR1_RES_EN=0: INTB=Hi-z (regardless of OCUR1_RES)

Interrupt Enable :

Detection of charging direction

current measurement value1

1: Enableꢀ0: Disable

OCUR1_DET_EN=1: OCUR1_DET=1 -> INTB=L, OCUR1_DET=0 -> INTB=Hi-z

OCUR1_DET_EN=0: INTB=Hi-z (regardless of OCUR1_DET)

Alarm output Enable :

1: Enableꢀ0: Disable

Alarm detection of discharging direction

current measurement value1

ALARM_OCUR1_RES_EN=1:

OCUR1_RES=1 -> ALARMB=L, OCUR1_RES=0 -> ALARMB=Hi-z

ALARM_OCUR1_RES_EN=0: ALRMB=Hi-z (regardless of OCUR1_RES)

Bit 0 :

ALARM_OCUR1_DET_EN

Alarm output Enable :

1: Enableꢀ0: Disable

Alarm detection of charging direction

current measurement value1

ALARM_OCUR1_DET_EN=1:

OCUR1_DET=1 -> ALARMB=L, OCUR1_DET=0 -> ALARMB=Hi-z

ALARM_OCUR1_DET_EN=0: ALRMB=Hi-z (regardless of OCUR1_DET)

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Address 3Bh: INT_EN3 Register (R/W)

Address

(Index)

Register Name

INT_EN3

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CRCERR_DET_EN

0

-

CALIB_FIN_EN

0

-

REX_DET_EN WAKE_RES_EN WAKE_DET_EN

3Bh

Initial Value

0

Bit 6 :

CALIB_FIN_EN

Interrupt Enable :

1: Enableꢀ0: Disable

Detection of calibration finish

CALIB_FIN_EN=1: CALIB_FIN=1 -> INTB=L, CALIB_FIN=0 -> INTB =Hi-z

CALIB_FIN_EN=0: INTB=Hi-z (regardless of CALIB_FIN)

Bit 5 :

Bit 4 :

Bit 2 :

Reserved

When writing this register, "0" must be written

CRCERR_DET_EN

REX_DET_EN

Interrupt Enable :

Detection of CRC Error

1: Enableꢀ0: Disable

CRCERR_DET_EN=1: CRCERR_DET=1 -> INTB=L, CRCERR_DET=0 -> INTB=Hi-z

CRCERR_DET_EN=0: INTB=Hi-z (regardless of CRCERR_DET)

Interrupt Enable :

1: Enableꢀ0: Disable

Detection of Relax state

REX_DET_EN=1: REX_DET=1 -> INTB=L, REX_DET=0 -> INTB=Hi-z

REX_DET_EN=0: INTB=Hi-z (regardless of REX_DET)

Bit 1 :

Bit 0 :

WAKE_RES_EN

WAKE_DET_EN

Interrupt Enable :

Detection of under wake-up current measurement

1: Enableꢀ0: Disable

WAKE_RES_EN=1: WAKE_RES=1 -> INTB=L, WAKE_RES=0-> INTB=Hi-z

WAKE_RES_EN=0: INTB=Hi-z (regardless of WAKE_RES)

Interrupt Enable :

1: Enableꢀ0: Disable

Detection of over wake-up current measurement

WAKE_DET_EN=1: WAKE_DET=1 -> INTB=L, WAKE_DET=0 -> INTB=Hi-z

WAKE_DET_EN=0: INTB=Hi-z (regardless of WAKE_DET)

Address 3Ch: INT_REQ1 Register (R/W)

Address

(Index)

Register Name

INT_REQ1

R/W

R/W CC_MON4_RES CC_MON4_DET CC_MON3_RES CC_MON3_DET CC_MON2_RES CC_MON2_DET CC_MON1_RES CC_MON1_DET

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

3Ch

Initial Value

0

Bit 7 :

CC_MON4_RES

Read:

Interrupt Status for Detection of

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

discharging direction current accumulation value4

CC_CCNTD[31:8](17h+18h+19h+1A) ≤ CC_BATCAP4_TH[24:0](2Ch+2Dh+2Eh)

Write:

1: Clear 0: Not Clear

Interrupt status clear

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

CC_MON4_DET

CC_MON3_RES

CC_MON3_DET

CC_MON2_RES

CC_MON2_DET

CC_MON1_RES

CC_MON1_DET

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) ≤ CC_BATCAP4_TH[24:0](2Ch+2Dh+2Eh)

Interrupt Status for Detection of

charging direction current accumulation value4

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) ≤ CC_BATCAP3_TH[24:0](29h+2Ah+2Bh)

Interrupt Status for Detection of

discharging direction current accumulation value3

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) > CC_BATCAP3_TH[24:0](29h+2Ah+2Bh)

Interrupt Status for Detection of

charging direction current accumulation value3

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) ≤ CC_BATCAP2_TH[24:0](26h+27h+28h)

Interrupt Status for Detection of

discharging direction current accumulation value2

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) > CC_BATCAP2_TH[24:0](26h+27h+28h)

Interrupt Status for Detection of

charging direction current accumulation value2

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) ≤ CC_BATCAP1_TH[24:0](23h+24h+25h)

Interrupt Status for Detection of

discharging direction current accumulation value1

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Interrupt Status for Detection of

charging direction current accumulation value1

Bit is set to “1” when detect below condition

CC_CCNTD[31:8](17h+18h+19h+1A) > CC_BATCAP1_TH[24:0](23h+24h+25h)

Write:

1: Clear 0: Not Clear

Interrupt status clear

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Address 3Dh: INT_REQ2 Register (R/W)

Address

(Index)

Register Name

INT_REQ2

R/W

00h

Bit7

OCUR3_RES

0

Bit6

OCUR3_DET

0

Bit5

OCUR2_RES

0

Bit4

OCUR2_DET

0

Bit3

OCUR1_RES

0

Bit2

OCUR1_DET

0

Bit1

Bit0

-

3Dh

Initial Value

0

Bit 7 :

OCUR3_RES

Read:

Interrupt Status for Detection of

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

discharging direction current measurement3

CURCD_DIR+CURCD(13h+14h) ≤ OCURTHR3_DIR+OCURTHR3(33h+34h) and

over the consecutive detection setting by OCURDUR3[1:0](35h)

Write:

1: Clear 0: Not Clear

Interrupt status clear

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

OCUR3_DET

OCUR2_RES

OCUR2_DET

OCUR1_RES

OCUR1_DET

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CURCD_DIR+CURCD(13h+14h) > OCURTHR3_DIR+OCURTHR3(33h+34h) and

over the consecutive detection setting by OCURDUR3[1:0](35h)

Interrupt Status for Detection of

charging direction current measurement3

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CURCD_DIR+CURCD(13h+14h) ≤ OCURTHR2_DIR+OCURTHR2(31h+32h) and

over the consecutive detection setting by OCURDUR2[1:0](35h)

Interrupt Status for Detection of

discharging direction current measurement2

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CURCD_DIR+CURCD(13h+14h) > OCURTHR2_DIR+OCURTHR2(31h+32h) and

over the consecutive detection setting by OCURDUR2[1:0](35h)

Interrupt Status for Detection of

charging direction current measurement2

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CURCD_DIR+CURCD(13h+14h) ≤ OCURTHR1_DIR+OCURTHR1(2Fh+30h)

over the consecutive detection setting by OCURDUR1[1:0](35h)

Interrupt Status for Detection of

discharging direction current measurement1

Write:

Interrupt status clear

1: Clear 0: Not Clear

Read:

1: Event occurred 0: No event

Interrupt Status for Detection of

charging direction current measurement1

Bit is set to “1” when detect below condition

CURCD_DIR+CURCD(13h+14h) > OCURTHR1_DIR+OCURTHR1(2Fh+30h) and

over the consecutive detection setting by OCURDUR1[1:0](35h)

Write:

1: Clear 0: Not Clear

Interrupt status clear

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Address 3Eh: INT_REQ3 Register (R/W)

Address

(Index)

Register Name

INT_REQ3

R/W

00h

Bit7

Bit6

CALIB_FIN

0

Bit5

Bit4

Bit3

Bit2

REX_DET

0

Bit1

WAKE_RES

0

Bit0

WAKE_DET

0

-

OTP_DL_FIN CRCERR_DET

-

3Eh

Initial Value

0

Bit 7:

Reserved

Bit 6 :

CALIB_FIN

Read:

1: Event occurred 0: No event

Interrupt Status for calibration finish

Write:

1: Clear 0: Not Clear

Interrupt status clear

Bit 5 :

Bit 4 :

Bit 2 :

OTP_DL_FIN

CRCERR_DET

REX_DET

Read:

1: Event occurred 0: No event

1: Clear 0: Not Clear

Status for OTP data download finish

Write:

Interrupt status clear

Read:

1: Event occurred 0: No event

1: Clear 0: Not Clear

Interrupt status for CRC Error

Write:

Interrupt status clear

Read:

1: Event occurred 0: No event

Interrupt status for Relax state

Bit is set to “1” when detect below condition

CURCD[14:0](13h+14h) ≤ { 7'd0, REX_CURCD_TH[7:0](36h) } and

after detection time setting by REX_DUR[1:0](35h)

Write:

1: Clear 0: Not Clear

Interrupt status clear

Bit 1 :

WAKE_RES

WAKE_DET

Read:

1: Event occurred 0: No event

Bit is set to “1” when detect below condition

CURCD[14:0](13h+14h) ≤ { 7'd0, WAKE_CURCD_TH[7:0](37h) } and

over the consecutive detection setting by WAKE_COUNT[1:0](38h)

Interrupt status for Detection of

under wake-up current

Write:

Interrupt status clear

1: Clear 0: Not Clear

Bit 0 :

Read:

1: Event occurred 0: No event

Interrupt status for Detection of

over wake-up current

Bit is set to “1” when detect below condition

CURCD[14:0](13h+14h) > { 7'd0, WAKE_CURCD_TH[7:0](37h) } and

over the consecutive detection setting by WAKE_COUNT[1:0](38h)

Write:

1: Clear 0: Not Clear

Interrupt status clear

Address 3Fh: PAGE_SEL Register (R/W)

Address

(Index)

Register Name

PAGE_SEL

Initial Value

R/W

00h

Bit7

HOSC_ON

0

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

0

Bit0

-

Reserved

3Fh

0

Bit 7 :

HOSC_ON

Built-in OSC force enable

Force Built-in OSC to turn on when HOSC_ON=1.

0: Built-in OSC normal operation (default)

1: Built-in OSC turns ON by force

Before transitioning from SSHDN mode to another mode, set HOSC_ON = 1

and the built-in OSC will turn ON.

When HOSC_ON=0, built-in OSC operate normally.

The built-in OSC will turn on in WAKE, OTP, IDLE, NORMAL, SLEEP modes.

(Refer to Table 2-1)

Bit 1-0:

Reserved[1:0]

When writing this register, always write “00” to these bits.

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I/O Equivalence Circuit

VCC

VDD

VCC

GND

VREF15

VREF25

VREFCAL

SHDNB

EXADIN

CSB

SDI

SCK

VDD

VCC

to ΔΣADC

GND

INTB

ALARMB

ADINP

ADINM

SDO

VCC

VDD

VCC

INN

VREF25

to AMP

AMP

OUT

GND

to AMP

DGND

GND

INP

VCC

VDD

INN

AMPOUT

GND

DGND

Figure 7. I/O Equivalence Circuit

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Layout

Optimum performance of this product cannot be achieved without taking the circuit board layout into consideration.

The following points are important.

(1) Place CREF15 as close as possible to the VREF15 pin and GND.

(2) Place CVDD as close as possible to the VDD pin and GND.

(3) Place COUT as close as possible to the AMPOUT pin and GND.

(4) Place CINP as close as possible to the INP pin and GND.

(5) Place CINN as close as possible to the INN pin and GND.

(6) Place CREF25 as close as possible to the VREF25 pin and GND.

(7) Place CVCC as close as possible to the VCC pin and GND.

(8) Place CREFC as close as possible to the VREFCAL pin and GND.

(9) Connect the ADINP pin and the AMPOUT pin as close as possible.

(10) Connect the ADINM pin and the VREF25 pin as close as possible.

(11) Draw a line the INP pin and the INN pin as equal as possible.

(12) Draw a ground line as thick as possible for the low impedance.

(2)

(6)

(1)

(7)

(8)

(3)

(12)

(4)

(5)

(9)

(10)

(11)

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Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3.

4.

Ground Voltage

Except for pins the output and the input of which were designed to go below ground, ensure that no pins are at a

voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7.

8.

9.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes -continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 8. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

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Ordering Information

B D 7

2

0

F

V

-

C E 2

Part Number

Package

FV: SSOP-B20

Product rank

C: for Automotive applications

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

SSOP-B20 (TOP VIEW)

Part Number Marking

LOT Number

7 2 2 0 F V

Pin 1 Mark

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Physical Dimension and Packing Information

Package Name

SSOP-B20

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BD7220FV-C

Revision History

Revision

Number

Date

Description

17. Dec. 2019

001

New Release

Page.16, Page.17 Bit Mask Function of Accumulation Current

Corrected Figure 1-8 typo of “image of bits mask” and updated Figure 1-8.

Add explanatory text.

24. Sep. 2020

002

Add explanatory of example for CCNTD error complement.

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD7220FV-C
厂家：	ROHM
描述：	BD7220FV-C是适用于大电流检测应用的库仑计IC。不仅内置16位ΔΣADC，还内置了高精度运算放大器和电流累加逻辑电路，因此可以高精度地计算电流累加值。电流检测输入支持分流电阻器和电流输出型电流传感器，并且采用SPI作为通信I/F。高精度测量所需的校准可以仅使用SPI命令执行，因此只使用本IC即可获取预测剩余电量所需的电流累加信息。通信放大器运算放大器传感器电阻器
文件：	总68页 (文件大小：1909K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD7220FV-C [ROHM]

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