BD86852MUF-C [ROHM]
BD86852MUF-C is a power management IC with primary buck converter (DC/DC1), secondary buck converters (DC/DC2 and DC/DC3), external linear regulator control block and the power-on reset function for CMOS sensor and image sensing power supply. Output voltage and sequence are selectable and applicable to various image sensor power supply. This device adopts small package VQFN24FV4040 which is optimal for camera module. In addition, this device has a pin that can be programmed to turn on/off the spread spectrum providing a lower noise regulated outputs.;
| 型号： | BD86852MUF-C |
| 厂家： | 
ROHM |
| 描述： | BD86852MUF-C is a power management IC with primary buck converter (DC/DC1), secondary buck converters (DC/DC2 and DC/DC3), external linear regulator control block and the power-on reset function for CMOS sensor and image sensing power supply. Output voltage and sequence are selectable and applicable to various image sensor power supply. This device adopts small package VQFN24FV4040 which is optimal for camera module. In addition, this device has a pin that can be programmed to turn on/off the spread spectrum providing a lower noise regulated outputs. |
| 文件： | 总46页 (文件大小：2248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Automotive Power Management IC
PMIC for Automotive Camera
BD86852MUF-C
General Description
Key Specifications
BD86852MUF-C is a power management IC with primary
buck converter (DC/DC1), secondary buck converters
(DC/DC2 and DC/DC3), external linear regulator control
block and the power-on reset function for CMOS sensor
and image sensing power supply. Output voltage and
sequence are selectable and applicable to various image
sensor power supply.
This device adopts small package VQFN24FV4040 which
is optimal for camera module. In addition, this device has
a pin that can be programmed to turn on/off the spread
spectrum providing a lower noise regulated outputs.
Power Supply Voltage Rating:
Power Supply Voltage Range:
Output Voltage:
20 V (Max)
4.0 V to 18 V
VO1:
VO2:
VO3:
3.3 V or 3.9 V (±2 %)
1.1 V or 1.2 V (±2 %)
1.8 V (±2 %)
Output Current:
VO1:
2 A (Max)
1 A (Max)
1 A (Max)
VO2:
VO3:
Switching Frequency:
Stand-by Current:
2.2 MHz (±200 kHz)
0 μA (Typ)
Operating Ambient Temperature Range:
-40 °C to +125 °C
Features
AEC-Q100 Qualified(Note 1)
Package
VQFN24FV4040
W (Typ) x D (Typ) x H (Max)
4.0 mm x 4.0 mm x 1.0 mm
Functional Safety Supportive Automotive Products
Primary DC/DC (VO1)
DC/DC with built-in FET
High Efficiency with Synchronous Rectification
Dual Secondary DC/DC (VO2, VO3)
DC/DC with built-in FET
High Efficiency with Synchronous Rectification
Each Protection Function
Spread Spectrum for EMC
Fail Detection Pin (for each output)
Selectable Output Voltage and Sequence
VQFN24FV4040
Wettable Flank Package
(Note 1) Grade 1
Applications
ADAS
Camera System (Automotive Camera and Security
Camera) using CMOS Sensor
Typical Application Circuit
VCC
VO2
PVCC
VCC
VO1
VS2
SW2
VO2
EN
PGND23
SW3
VO3
VREG
VS3
VO3
VO1
BOOT1
SW1
EN_LDO
FB_LDO
VO4
External
LDO
VO1
PGND1
VO1
VO3
RT
SSCG
PGOOD
MODE2
MODE1
MODE0
GND
〇Product structure: Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD86852MUF-C
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Contents .........................................................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Block Diagrams...............................................................................................................................................................................4
Description of Blocks ......................................................................................................................................................................6
Absolute Maximum Ratings ..........................................................................................................................................................11
Thermal Resistance......................................................................................................................................................................11
Recommended Operating Conditions...........................................................................................................................................12
Electrical Characteristics...............................................................................................................................................................12
Typical Performance Curves.........................................................................................................................................................15
Function Explanations ..................................................................................................................................................................19
Application Examples ...................................................................................................................................................................24
Power Loss...................................................................................................................................................................................37
Operational Notes.........................................................................................................................................................................38
Ordering Information.....................................................................................................................................................................41
Marking Diagrams.........................................................................................................................................................................41
Physical Dimension and Packing Information...............................................................................................................................42
Revision History............................................................................................................................................................................43
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Pin Configuration
(TOP VIEW)
18
17
16
15
14
13
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
PGOOD
FB_LDO
VO1
SSCG
RT
EXP-PAD
BOOT1
SW1
8
MODE2
MODE1
7
PGND1
1
2
3
4
5
6
Pin Descriptions
Pin No.
Pin Name
PVCC
VCC
Function
Pin No.
13
Pin Name
VO2
Function
1
2
3
Power supply for DC/DC1
Power supply
DC/DC2 output voltage feedback
DC/DC2 switching output
14
SW2
EN
Enable control input
15
VS2
Power supply for DC/DC2
Power ground for DC/DC2 and
DC/DC3
4
GND
Ground
16
PGND23
5
6
7
8
9
VREG
MODE0
MODE1
MODE2
RT
Internal regulator output
Mode select 0(Note 1)
17
18
19
20
21
VS3
SW3
Power supply for DC/DC3
DC/DC3 switching output
Mode select 1(Note 1)
VO3
DC/DC3 output voltage feedback
External LDO voltage feedback
DC/DC1 output voltage feedback
Mode select 2(Note 1)
FB_LDO
VO1
Adjust switching frequency
DC/DC1 high side driver supply
pin
10
11
12
-
SSCG
PGOOD
EN_LDO
-
SSCG setting(Note 2)
22
23
24
-
BOOT1
SW1
Power Good (Note 3)
(N-channel open-drain)
External LDO enable control
output
DC/DC1 switching output
Power ground for DC/DC1
PGND1
EXP-PAD
The EXP-PAD connect to GND,
PGND1 and PGND23.
-
(Note 1) Connect to the GND pin or the VREG pin.
(Note 2) If not in use, connect to the GND pin.
(Note 3) If not in use, open.
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BD86852MUF-C
Block Diagrams
1. Top Block Diagram
VCC
UVLO_VCC
UVLO
EN1
EN
EN1
VREG
VREG
CTL1
UVLO_VREG
UVLO
TSD
VREF2
VS2
TSD
VREF1
EN2
VREF1
VREF2
EN2
OSC
(SSCG)
CLK1
CLK2
CLK3
SSCG
RT
UVLO
UVLO_VS
UVLO_VCC
UVLO_VREG
UVLO_VS
VSOVP
LVD1
PGOOD
VREG
OVD1
LVD2
CTL1
CTL2
CTL3
CONTROL
LOGIC
OVD2
LVD3
VS2
OVD3
OCP1
EN_LDO
CTL4
OCP2
OCP3
VREG
TSD
LVD4
OVD4
FB_LDO
LDO_CNT
MODE0
MODE1
MODE2
MODE<2:0>
VO2
VS2
SW2
PVCC
BOOT1
SW1
CTL2
LVD2
OVD2
CLK2
DC/DC2
MODE<2:0>
OCPH2
CTL1
CLK1
LVD1
OVD1
PGND23
SW3
PGND1
VO1
DC/DC1ꢀ
MODE<2:0>
OCPH1
CTL3
CLK3
LVD3
OVD3
VSOVP
VS3
VO3
ꢀDC/DC3ꢀ
MODE<2:0>
OCPH3
GND
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BD86852MUF-C
Block Diagrams – Continued
2. DC/DC1 Block Diagram
BOOT1
SW1
VREG
BOOT1
PVCC
CUR_
SENSE
CLK1
SLP
+
VO1
CLK1
SS
+
-
OCPH1
MODE
<2:0>
VREF1
BOOT1
BOOT_CTL
＋
－
RST
－
＋
＋
HS_CTL
SW1
PWM
MODE
<2:0>
ERRAMP
SW1
CLK1
DRV
LOGIC
CTL1
VREG
VS3
VSOVP
＋
－
＋
－
－
＋
VREF2
LS_CTL
OCPN1
VSOVP
OVD1
LVD1
PGND1
+
-
PGND1
3. DC/DC2 and DC/DC3 Block Diagram (i = 2, 3)
VSi
CUR_
CLKi
SLP
+
SENSE
VOi
CLKi
SS
+
-
OCPHi
MODE
<2:0>
VREF1
VSi
＋
－
RST
－
＋
＋
HS_CTL
PWM
CLKi
MODE
<2:0>
PGND23
ERRAMP
SWi
DRV
LOGIC
CTLi
VSi
VSOVP
VREF2
LS_CTL
OCPNi
PGND23
+
-
＋
－
－
＋
OVDi
LVDi
PGND23
Dischage
CTLi
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BD86852MUF-C
Description of Blocks
Internal Regulator (VREG) Block
VREG is the linear regulator for PMIC use only (Do not use it for other purposes.).
The VREG pin needs an appropriate external bypath capacitor. This is controlled by the EN1 internal signal.
When the EN pin voltage is more than 2.6 V, the EN1 signal becomes high, and when it’s less than 0.8 V, the EN1 signal
becomes low.
VREG stops when the EN1 signal and the CTL1 internal signal are low.
Reference Voltage (VREF1 and VREF2) Block
Two independent reference voltages, one for the output voltage and the other for the voltage detections.
Under Voltage Lock-Out Block for VCC (UVLO_VCC, UVLO_VREG and UVLO_VS)
Input low-voltage detections for the VCC, VREG and VS2 pins.
If any one of these input low-voltages are detected, the device goes into the UVLO state (See below for more details).
UVLO_VCC and UVLO_VREG
When UVLO is detected from these pins, all the outputs (VO1 to VO3 and EN_LDO) turn off immediately. And then,
the PGOOD pin changes to low. Once the UVLO condition is removed, the device waits 200 µs (Typ) and starts VO1
rail power-up.
UVLO_VS
When UVLO is detected from VS2 pins, the secondary outputs (VO2, VO3 and EN_LDO) turn off immediately. And
then, the PGOOD pin changes to low. Once the UVLO condition is removed, VO2, VO3 and EN_LDO turn on by the
normal sequence.
Thermal Shutdown Protection (TSD) Block
To prevent IC from causing thermal destruction and thermal runaway, the TSD operates when chip temperature reaches
175 °C (Typ) or more. When TSD operates, all of the outputs (VO1 to VO3 and EN_LDO) turn off at the same time, and
PGOOD changes low. IC resumes by sequence after chip temperature decreases to certain temperature.
However, this thermal protection circuit is designed to protect IC itself from destruction. Do not exceed the chip temperature
Tjmax = 150 °C.
Oscillator (OSC) Block
OSC generates clock for DC/DC1, 2, 3 and CONTROL block. The DC/DC1 operates in phase with the DC/DC3, and the
DC/DC2 operates 180 degrees out of phase to reduce the input ripple current.
Spread Spectrum Clock Generator (SSCG) Block
OSC block built in spread spectrum clock generator (SSCG) function. Insert a capacitor of 3300 pF between SSCG pin
and GND, it enables the spread-spectrum function. In this mode, the frequency is reduced by 5 % from the RT programmed
center frequency and is modulated by ±3 % with 2.5 kHz modulation frequency.
External LDO Controller (LDO_CNT) Block
This IC outputs the control signal to External LDO from the EN_LDO pin. The power supply of the EN_LDO output buffer
is VS2. When detection (LVD4 and OVD4) of external LDO output is necessary, short the external LDO output and FB_LDO.
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Description of Blocks – continued
Error Amplifier (ERRAMP) Block
Error Amplifier with reference voltage and VO voltage divider input.
Controls On Duty width of switching pulse by output of ERRAMP.
Capacitor and resistor for phase compensation are fixed.
Slope (SLP) Block
The saw tooth wave generator for the duty modulation. The summation of the saw tooth waveform and the upper FET
current information will be sent to PWM.
Current Comparator (CUR_SENSE) Block
The CUR_SENSE block outputs a waveform depending on the current of the inductance.
Soft Start (SS) Block
The SS block slows down the rise of output voltage during start-up. This reduces inrush current during start-up and the
overshoot of the output. The soft start ramp is generated by CLK and digital-to-analog converter (DAC).
PWM Comparator (PWM) Block
The PWM block compares the output of ERRAMP with the synthetic waveform of SLP and CUR_SENSE, and adjusts duty
for switching operation.
Driver Logic (DRV LOGIC) Block and Driver (DRV) Block
The DRV_LOGIC block control BOOT_CTL, HS_CTL and LS_CTL. The DRV blocks drive Power FET.
Over Voltage Protection (VSOVP) Block at DC/DC1
When the VS3 pin voltage exceeds the threshold of VSOVP, high side FET and low side FET turn off.
Over Voltage Detection (OVD1, OVD2, OVD3 and OVD4)
PGOOD is an open-drain output which pull-up resistor is required when usage.
The VO1, VO2, VO3 and FB_LDO pins have the over voltage detection feature. Any one of these over voltage detection
can make the PGOOD pin to pull low. Once the over voltage is removed, the PGOOD pin follows in 10 ms (Typ). This timer
is dependent on the programmed operating frequency. The PGOOD pin is an open-drain pin and needs an external pull-
up resistor.
Lower Voltage Detection (LVD1, LVD2, LVD3 and LVD4)
PGOOD is open-drain output which pull-up resistor is required when usage.
The VO1, VO2, VO3 and FB_LDO pins have the lower voltage detection feature. Any one of these lower voltage detection
can make the PGOOD pin to pull low. Once the lower voltage is removed, the PGOOD pin follows in 10 ms (Typ). This
timer is dependent on the programmed operating frequency. The PGOOD pin is open-drain pins and need an external pull-
up resistor.
Over Current Protection (OCPH1, OCPH2, OCPH3, OCPN1, OCPN2 and OCPN3)
The over current protection feature limits the FET current and successfully protects all the FETs from the permanent
damage.
This feature is intended for an accidental short only minimizing secondary disasters. In the application, the continuous
usage of this feature is not allowed.
OCPH1, OCPH2 and OCPH3
When DC/DC1, DC/DC2 and DC/DC3 high-side FET peak current cross the threshold, the high-side FET turns off
immediately and this protection limits high-side FET ON time. When ON time is limited, the current of output is limited
and the voltage of output decreases.
OCPN1, OCPN2, OCPN3 (The incoming/sink over current.)
When DC/DC1, DC/DC2 and DC/DC3 low-side FET peak negative current cross the threshold, the low-side FET
turns off immediately and this protection limits low-side FET ON time.
Discharge Block at DC/DC2 and DC/DC3
When DC/DC control internal signal CTL2 or CTL3 is low, discharge block works.
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Description of Blocks – continued
CONTROL LOGIC Block
This block controls CTL1, CTL2, CTL3, and CTL4, ON/OFF sequence, PGOOD and each protection.
When the EN2 internal signal is high and UVLO_VCC and UVLO_VREG are released, CONTROL_LOGIC block is active.
When UVLO_VCC or UVLO_VREG is detected, CONTROL LOGIG Block will reset and initialize.
Output voltage and the sequence are decided by the combination of MODE pin (MODE0, MODE1 and MODE2) logic.
It is necessary to connect the MODE pins to VREG or GND. The following table is details of output voltage and ON/OFF
sequences.
Table 1. Mode Setting Description
MODE Pin
External
LDO
(VO4)
(Note 1)
Mode
name
DCDC1
(VO1)
DCDC2
(VO2)
DCDC3
(VO3)
ON Sequence
OFF Sequence
Protect
2
L
1
L
0
L
DCDC2 -> DCDC3 -> EN_LDO
EN_LDO -> DCDC3 -> DCDC2
A-mode
B-mode
C-mode
D-mode
E-mode
F-mode
G-mode
H-mode
3.3 V
3.3 V
3.3 V
3.9 V
3.3 V
3.3 V
3.3 V
3.3 V
1.2 V
1.2 V
1.2 V
1.2 V
1.1 V
1.1 V
1.2 V
1.2 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
2.7 V
2.8 V
2.9 V
3.3 V
2.9 V
2.9 V
2.8 V
2.8 V
Self-Restart
Self-Restart
Self-Restart
Self-Restart
Self-Restart
Timer-Latch
Self-Restart
Self-Restart
EN_LDO -> DCDC3 -> DCDC2
DCDC2 -> DCDC3 -> EN_LDO
L
L
H
L
DCDC2 -> DCDC3 -> EN_LDO
EN_LDO -> DCDC3 -> DCDC2
L
H
H
L
DCDC2 -> DCDC3 -> EN_LDO
EN_LDO -> DCDC3 -> DCDC2
L
H
L
DCDC2 -> DCDC3 -> EN_LDO
EN_LDO -> DCDC3 -> DCDC2
H
H
H
H
DCDC2 -> DCDC3 -> EN_LDO
EN_LDO -> DCDC3 -> DCDC2
L
H
L
DCDC3 -> EN_LDO -> DCDC2
DCDC2 -> EN_LDO -> DCDC3
H
H
DCDC3 -> DCDC2 -> EN_LDO
EN_LDO -> DCDC2 -> DCDC3
H
(Note 1) L: GND short, H: VREG short
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BD86852MUF-C
Description of Blocks - continued
CONTROL LOGIC Block (Protection of Self-Restart)
When the EN pin is 0.8 V or less, IC is in the state of stand-by. In this state, the internal regulator and all outputs are off,
and secondary DC/DC rails discharge function is active.
The following table shows the relation of protection (Self-Restart).
Table 2. Protection of Self-Restart
Protection
PGOOD
Notice
UVLO_VCC
UVLO_VREG
UVLO_VS
TSD
Low
Low
Low
Low
All output is off.
All output is off.
ALL
VO2, VO3 and EN_LDO are off.
All output is off.
High side FET is off.
Self-Restart after 10 ms.
OCPH
OCPN
VSOVP
Low(Note 1)
-
Low side FET is off.
High and Low sides FET are off.
Self-Restart after 10 ms.
DC/DC1
(VO1)
Low
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
LVD
Low
Low
OVD
High side FET is off.
Self-Restart after 10 ms.
OCPH
OCPN
LVD
Low(Note 1)
-
Low side FET is off.
DC/DC2
(VO2)
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
Low
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
OVD
Low
High side FET is off
Self-Restart after 10 ms.
OCPH
OCPN
LVD
Low(Note 1)
-
Low side FET is off.
DC/DC3
(VO3)
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
Low
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
When more than 10 ms, all output is off.
Self-Restart after 10 ms.
OVD
LVD
Low
Low
Low
External
LDO
OVD
(Note 1) When protection detection is more than 10 ms, PGOOD turn into low.
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Description of Blocks - continued
CONTROL LOGIC Block (Protection of Timer-Latch)
When the protection detection passes for 10 ms (Typ) or more, “Timer-Latch” works and all output turns off and PGOOD
turns to low. The cancellation method of “Timer-Latch” is to activate either UVLO_VCC, UVLO_VREG or TSD, or to turn
EN low.
The following table shows the relation of protection (Timer-Latch).
Table 3. Protection of Timer-Latch
Protection
PGOOD
Low
Notice
All output is off.
Release Timer-Latch
UVLO_VCC
All output is off.
Release Timer-Latch
UVLO_VREG
UVLO_VS
TSD
Low
Low
Low
ALL
When protection detect 8 times, Timer-Latch works.
All output is off.
Release Timer-Latch
High side FET is off.
Timer-Latch after 10 ms.
OCPH
OCPN
VSOVP
Low(Note 1)
-
Low side FET is off.
DC/DC1
(VO1)
High and Low sides FET are off
Timer-Latch after 10 ms.
Low
LVD
Low
Low
Timer-Latch after 10 ms.
Timer-Latch after 10 ms.
OVD
High side FET is off.
Timer-Latch after 10 ms.
OCPH
Low(Note 1)
DC/DC2
(VO2)
OCPN
LVD
-
Low side FET is off.
Low
Low
Timer-Latch after 10 ms.
Timer-Latch after 10 ms.
OVD
High side FET is off.
Timer-Latch after 10 ms.
OCPH
Low(Note 1)
DC/DC3
(VO3)
OCPN
LVD
-
Low side FET is off.
Low
Low
Low
Low
Timer-Latch after 10 ms.
OVD
LVD
Timer-Latch after 10 ms.
Timer-Latch after 10 ms.
External
LDO
OVD
When more than 10 ms, Timer-Latch works.
(Note 1) When protection detection is more than 10 ms, PGOOD turn into low.
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BD86852MUF-C
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Power Supply Voltage(Note 1)
EN Pin Voltage(Note 2)
Power Supply Voltage(Note 1)
VO Pin Voltage
VVCC, VPVCC
VEN
-0.3 to +20
-0.3 to +20
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
V
V
V
V
V
V
VVS2, VVS3
VVO1, VVO2, VVO3
VFBLDO
FB_LDO Pin Voltage
PGOOD Pin Voltage
VPGOOD
VMODE0, VMODE1
VMODE2
,
MODE Pin Voltage
-0.3 to +6
V
Storage Temperature Range
Tstg
-55 to +150
+150
°C
°C
Maximum Junction Temperature
Tjmax
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Do not exceed maximum junction temperature.
(Note 2) The VCC and EN pin start-up is sequence free if it is within guaranteed operating voltage range.
Thermal Resistance(Note 3)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 5)
2s2p(Note 6)
VQFN24FV4040
Junction to Ambient
Junction to Top Characterization Parameter(Note 4)
θJA
111.6
19
39.9
12
°C/W
°C/W
ΨJT
(Note 3) Based on JESD51-2A (Still-Air)
(Note 4) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 5) Using a PCB board based on JESD51-3.
(Note 6) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70μm
Footprints and Traces
Thermal Via(Note 7)
Layer Number of
Measurement Board
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
Footprints and Traces
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 7) This thermal via connects with the copper pattern of all layers.
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BD86852MUF-C
Recommended Operating Conditions
Parameter
Symbol
Min
4.0(Note 2)
3.2
Typ
6.0
-
Max
18.0
4.0
Unit
V
Notice
Power Supply Voltage(Note 1)
Power Supply Voltage(Note 1)
VVCC
-
VS2 and VS3 must be
short to VO1
VVS2, VVS3
V
Output Current(Note 1)
Output Current(Note 1)
Output Current(Note 1)
Switching Frequency
Operating Temperature
IVO1
IVO2
IVO3
fOSC
Topr
-
-
-
-
2
1
A
A
-
-
-
-
-
-
-
1
A
1.8
-40
2.2
+25
2.4
+125
MHz
°C
(Note 1) Do not exceed the maximum junction temperature rating.
(Note 2) If differences between Power Supply Voltage of VCC and VO1 Output Voltage are small, VO1 Output Voltage may drop.
Electrical Characteristics
(Unless otherwise specified,
Tj = -40 to +150 °C, VVCC = VPVCC = 4.0 V to 18.0 V, VVS2 = VVS3 = 3.2 V to 4.0 V, VEN = 4.0 V, VSSCG = 0 V)
Parameter
Stand-by Current1
Symbol
Min
Typ
Max
Unit
Conditions
ISTB1
ISTB2
-
-
0
-
10
50
μA
μA
Tj = 25 °C, VEN = 0 V
Tj = 150 °C, VEN = 0 V
Stand-by Current2
VVCC = VPVCC = 6.0 V,
VVO1, VVO2, VVO3 and
VLDO_FB is setting voltage x
1.1
Operating Current
ICC1
-
3
6
mA
VCC UVLO Operating Voltage
VCC UVLO Hysteresis Voltage
VREG Output Voltage
VUVLOVCC_ON
VUVLOVCC_HYS
VREG
3.30
300
-
3.45
350
4.9
3.60
400
-
V
mV
V
VCC pin voltage
VCC pin voltage
VCC = 5.0 V to 18 V
VREG pin voltage
VREG pin voltage
VS2 pin voltage
VS2 pin voltage
VREG UVLO Operating Voltage
VREG UVLO Release Voltage
VS UVLO Operating Voltage
VS UVLO Release Voltage
Switching Frequency1
VUVLOVREG_ON
VUVLOVREG_OFF
VUVLOVS_ON
VUVLOVS_OFF
fOSC1
2.71
-
2.98
3.10
2.65
2.75
2.2
3.25
3.44
2.88
3.05
2.4
V
V
2.42
-
V
V
2.0
MHz RRT = 27 kΩ, VSSCG = 0 V
RRT = 27 kΩ
MHz
Switching Frequency2
fOSC2
1.8
2.1
fOSC1
CSSC = 3300 pF
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BD86852MUF-C
Electrical Characteristics - continued
(Unless otherwise specified,
Tj = -40 to +150 °C, VVCC = VPVCC = 4.0 V to 18.0 V, VVS2 = VVS3 = 3.2 V to 4.0 V, VEN = 4.0 V, VSSCG = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
<CH1 Output, Primary DC/DC1>
VO1 Output Voltage Accuracy
VO1 Input Current
VVO1
-2.0
4.0
-
+2.0
13.0
%
-
IVO1_CUR
7.3
μA
VVO1 = 3.9 V
VO1
x 0.73
VO1
x 0.80
VO1
x 0.87
VO1 LVD Operating Voltage
VO1 LVD Release Voltage
VO1 OVD Operating Voltage
VO1 OVD Release Voltage
VLVD11
VLVD12
VOVD11
VOVD12
VO1 pin voltage
VO1
x 0.86
-
-
VO1 pin voltage
VO1 pin voltage
VO1 pin voltage
VO1
x 1.10
VO1
x 1.20
VO1
x 1.30
V
V
VO1
x 1.15
-
-
VS OVP Operating Voltage
VS OVP Release Voltage
VVSOVP_ON
VVSOVP_OFF
5.1
5.5
5.9
V
V
VS3 pin voltage
VS3 pin voltage
4.95
5.35
5.75
ISW1 = -20 mA
5.0 V ≤ VVCC ≤ 18 V
High Side FET ON Resistance 1
Low Side FET ON Resistance 1
High Side FET ON Resistance 2
Low Side FET ON Resistance 2
RONH_SW1_1
RONL_SW1_1
RONH_SW1_2
RONL_SW1_2
-
-
-
-
200
200
250
250
350
350
400
400
mΩ
mΩ
mΩ
mΩ
ISW1 = +20 mA
5.0 V ≤ VVCC ≤ 18 V
ISW1 = -20 mA
4.0 V ≤ VVCC < 5.0 V
ISW1 = +20 mA
4.0 V ≤ VVCC < 5.0 V
<CH2 Output, Secondary DC/DC2>
VO2 Output Voltage Accuracy
VO2 Input Current
VVO2
-2.0
-
-
+2.0
2.8
%
IVO2_CUR
1.8
μA
VVO2 = 1.2 V
VO2
x 0.73
VO2
x 0.80
VO2
x 0.87
VO2 LVD Operating Voltage
VO2 LVD Release Voltage
VO2 OVD Operating Voltage
VO2 OVD Release Voltage
VLVD21
VLVD22
VOVD21
VOVD22
V
V
V
V
VO2 pin voltage
VO2
x 0.86
-
-
VO2 pin voltage
VO2 pin voltage
VO2 pin voltage
VO2
x 1.1
VO2
x 1.2
VO2
x 1.3
VO2
x 1.15
-
-
High Side FET ON Resistance
Low Side FET ON Resistance
VO2 Discharge Resistance
RONH_SW2
RONL_SW2
RVO2DIS
-
-
-
220
190
150
390
330
400
mΩ
mΩ
Ω
ISW2 = -20 mA
ISW2 = +20 mA
ISW2 = +1 mA
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BD86852MUF-C
Electrical Characteristics - continued
(Unless otherwise specified,
Tj = -40 to +150 °C, VVCC = VPVCC = 4.0 V to 18.0 V, VVS2 = VVS3 = 3.2 V to 4.0 V, VEN = 4.0 V, VSSCG = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
<CH3 Output, Secondary DC/DC3>
VO3 Output Voltage Accuracy
VO3 Input Current
VVO3
-2.0
-
-
+2.0
3.9
%
IVO3_CUR
2.5
μA
VVO3 = 1.8 V
VO3
x 0.73
VO3
x 0.80
VO3
x 0.87
VO3 LVD Operating Voltage
VO3 LVD Release Voltage
VO3 OVD Operating Voltage
VO3 OVD Release Voltage
VLVD31
VLVD32
VOVD31
VOVD32
V
V
V
V
VO3 pin voltage
VO3 pin voltage
VO3 pin voltage
VO3 pin voltage
VO3
x 0.86
-
-
VO3
x 1.1
VO3
x 1.2
VO3
x 1.3
VO3
x 1.15
-
-
High Side FET ON Resistance
Low Side FET ON Resistance
VO3 Discharge Resistance
RONH_SW3
RONL_SW3
RVO3DIS
-
-
-
220
190
150
390
330
400
mΩ
mΩ
Ω
ISW3 = -20 mA
ISW3 = +20 mA
ISW3 = +1 mA
<CH4 Operating, Secondary LDO_CNT>
FB_LDO Input Current
IFBLDO_CUR
2.0
4.4
6.8
μA
V
VFB_LDO = 3.3 V
VO4
x 0.89
VO4
x 0.92
VO4
x 0.95
VO4 LVD Operating Voltage
VLVD41
VLVD42
VOVD41
VOVD42
FB_LDO pin voltage
VO4
x 0.94
VO4 LVD Release Voltage
VO4 OVD Operating Voltage
VO4 OVD Release Voltage
-
-
V
V
V
FB_LDO pin voltage
FB_LDO pin voltage
FB_LDO pin voltage
VO4
x 1.045
VO4
x 1.080
VO4
x 1.115
VO4
x 1.06
-
-
<PGOOD Output>
PGOOD Resistance
PGOOD Delay Time
<Others>
RON_PG
tPGOOD
-
-
250
Ω
IPGOOD = +1 mA
fOSC2 = 2.1 MHz
8.5
10.0
11.5
ms
EN1 Threshold Voltage
EN2 Threshold Voltage
EN Input Current
VTH_EN1
VTH_EN2
0.8
1.5
5
1.7
1.7
25
-
2.6
2.6
45
V
V
For VREG
For output
IEN
μA
Ω
VEN = 5 V
EN_LDO High Side Resistance
EN_LDO Low Side Resistance
RON1_ENLDO
RON2_ENLDO
-
200
200
IEN_LDO = -1 mA
IEN_LDO = +1 mA
-
-
Ω
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BD86852MUF-C
Typical Performance Curves
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
6
5
4
3
2
1
0
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
0
5
10
15
20
0
5
10
15
20
Power Supply Voltage : VVCC [V]
Power Supply Voltage : VVCC [V]
Figure 1. Stand-by Current vs Power Supply Voltage
Figure 2. Operating Current vs Power Supply Voltage
2.4
2.35
2.3
3.36
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
3.34
3.32
3.3
2.25
2.2
2.15
2.1
3.28
3.26
3.24
2.05
2
0
0.5
1
1.5
2
-40 -25 -10 5 20 35 50 65 80 95 110125
VO1 Output Current [A]
Temperature [℃]
Figure 3. Switching Frequency1 vs Temperature
(RRT = 27 kΩ, SSCG = GND)
Figure 4. VO1 Output Voltage vs VO1 Output Current
(VO1 Load Regulation)
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BD86852MUF-C
Typical Performance Curves – continued
1.22
1.83
1.82
1.81
1.8
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
1.215
1.21
1.205
1.2
1.195
1.19
1.79
1.78
1.77
1.185
1.18
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
VO2 Output Current [A]
VO3 Output Current [A]
Figure 5. VO2 Output Voltage vs VO2 Output Current
(VO2 Load Regulation)
Figure 6. VO3 Output Voltage vs VO3 Output Current
(VO3 Load Regulation)
3.36
100
90
80
70
60
50
40
Ta = -40 ℃
Ta = +25 ℃
Ta = +125 ℃
3.34
3.32
3.3
3.28
3.26
3.24
30
VCC = 5 V
20
10
0
VCC = 6 V
VCC = 9 V
VCC = 12 V
4
6
8
10
12
14
16
18
0.01
0.1
VO1 Output Current [A]
1
Power Supply Voltage : VVCC [V]
Figure 7. VO1 Output Voltage vs Power Supply Voltage
(VO1 Line Regulation)
Figure 8. DC/DC1 Efficiency vs VO1 Output Current
(VO1 = 3.3 V)
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BD86852MUF-C
Typical Performance Curves – continued
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
VCC = 5 V
VS = 3.3 V
VS = 3.9 V
20
10
0
VCC = 6 V
VCC = 9 V
VCC = 12 V
0.01
0.1
VO1 Output Current [A]
1
0.01
0.1
VO2 Output Current [A]
1
Figure 9. DC/DC1 Efficiency vs VO1 Output Current
(VO1 = 3.9 V)
Figure 10. DC/DC2 Efficiency vs VO2 Output Current
(VO2 = 1.2 V)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VS = 3.3 V
VS = 3.9 V
VS = 3.3 V
VS = 3.9 V
20
20
10
10
0
0
0.01
0.1
VO2 Output Current [A]
1
0.01
0.1
VO3 Output Current [A]
1
Figure 11. DC/DC2 Efficiency vs VO2 Output Current
(VO2 = 1.1 V)
Figure 12. DC/DC3 Efficiency vs VO3 Output Current
(VO3 = 1.8 V)
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BD86852MUF-C
Typical Performance Curves – continued
VO1 : 2 V/Div
VO1 : 2 V/Div
VO2 : 1 V/Div
VO2 : 1 V/Div
VO3 : 1 V/Div
VO3 : 1 V/Div
EN_LDO : 2 V/Div
EN_LDO : 2 V/Div
1 ms/Div
1 ms/Div
Figure 13. Start-up Waveform
(A-MODE)
Figure 14. Start-up Waveform
(B-MODE)
VO1 : 2 V/Div
VO1 : 2 V/Div
VO2 : 1 V/Div
VO3 : 1 V/Div
VO2 : 1 V/Div
VO3 : 1 V/Div
EN_LDO : 2 V/Div
EN_LDO : 2 V/Div
1 ms/Div
1 ms/Div
Figure 15. Start-up Waveform
(G-MODE)
Figure 16. Start-up Waveform
(H-MODE)
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BD86852MUF-C
Function Explanations
Timing Chart of Start and Stop using EN (A, C, D, E, F-mode)
VCC
VTH_EN 2
VTH_EN 1
EN
VUVLOVREG_OFF
VREG
200 μs (Typ)
SS1 finish
4576 clk
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
Internal SS2 (DC/DC2)
VO2 (DC/DC2)
SS2 finish
4576 clk
VLVD22
VLVD21
VO2 discharge
SS3 finish
4576 clk
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
VLVD32
VLVD31
VO3 discharge
EN_LDO
VLVD42
VLVD41
VO4 (EXT_LDO) = FB_LDO
tPG OOD = 10 ms
PGOOD
Figure 17. Output Timing Chart (EN Start-up and Stop)
Output power up sequence
1. EN high input -> Internal regulator (VREG) starts up -> VREG power good.
2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up.
3. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up.
4. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up.
5. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42).
6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2
.
Output power down sequence
1. EN low input -> PGOOD low and EN_LDO low -> VO4 (External LDO) falls.
2. LVD4 power bad or 10 ms (Typ) after EN low input -> stop VO3 (DC/DC3) operation and start discharging VO3.
3. LVD3 power bad or 10 ms (Typ) after VO3 discharge start -> stop VO2 (DC/DC2) operation and start
discharging VO2.
4. LVD2 power bad or 10 ms (Typ) after VO2 discharge start -> stop VO1 (DC/DC1) operation including the
internal regulators (VREG).
PGOOD operation is dependent on LVD1 to 4 conditions. The “10 ms” time depends on fOSC2.
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BD86852MUF-C
Function Explanations – continued
Timing Chart of Start and Stop using VCC ULVO (A, C, D, E, F-mode)
VUVLOVCC_ON
VTH_EN 2
VUVLOVCC_ON + VUVLOVCC_HYS
VTH_EN 1
VCC = EN
VREG
200 μs (Typ)
SS1 finish
4576 clk
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
SS2 finish
4576 clk
Internal SS2 (DC/DC2)
VLVD22
VO2 (DC/DC2)
VO2 discharge
SS3 finish
4576 clk
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
VLVD32
VO3 discharge
EN_LDO
VLVD42
VO4 (EXT_LDO) = FB_LDO
tPG OOD = 10 ms
PGOOD
Figure 18 .Timing Chart (using VCC UVLO)
Output power up sequence
1. VCC (EN) reaches its UVLO threshold -> Internal regulator (VREG) starts up -> VREG power good.
2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up.
3. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up.
4. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up.
5. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42).
6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2
7. PGOOD operation is dependent on conditions of LVD1 to 4.
.
Output power down sequence
1. VCC (EN) falls and crosses its falling UVLO threshold
2. PGOOD becomes low and stops operation of all outputs (VO1 to VO4) including the internal regulator (VREG).
3. Start discharging VO2 and VO3.
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BD86852MUF-C
Function Explanations – continued
Timing Chart of Start and Stop using EN (B-mode)
VCC
VTH_EN 2
VTH_EN 1
EN
VUVLOVREG_OFF
VREG
200 μs (Typ)
SS1 finish
4576 clk
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
Internal SS2 (DC/DC2)
VO2 (DC/DC2)
SS2 finish
4576 clk
VLVD22
VLVD21
VO2 discharge
SS3 finish
4576 clk
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
VLVD31
VLVD32
VO3 discharge
EN_LDO
VLVD41
VLVD42
VO4 (EXT_LDO) = FB_LDO
tPG OOD = 10 ms
PGOOD
Figure 19. Output Timing Chart (EN Start-up and Stop)
Output power up sequence
1. EN high input -> Internal regulator (VREG) starts up -> VREG power good.
2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up.
3. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42).
4. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up.
5. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up.
6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2
.
Output power down sequence
1. EN low input -> PGOOD low -> stop VO2 (DC/DC2) operation and discharging VO2.
2. LVD2 power bad or 10 ms (Typ) after VO2 discharge start -> stop VO3 (DC/DC3) operation and start
discharging VO3.
3. LVD3 power bad or 10 ms (Typ) after VO3 discharge start -> VO4 (External LDO) falls.
4. LVD4 power bad or 10 ms (Typ) after EN_LDO low -> stop VO1 (DC/DC1) operation including the internal
regulators (VREG).
PGOOD operation is dependent on LVD1 to 4 conditions. The “10 ms” time depends on fOSC2.
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BD86852MUF-C
Function Explanations – continued
Timing Chart of Start and Stop using EN (G-mode)
VCC
VTH_EN 2
VTH_EN 1
EN
VUVLOVREG_OFF
VREG
200 μs (Typ)
SS1 finish
4576 clk
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
Internal SS2 (DC/DC2)
VO2 (DC/DC2)
SS2 finish
4576 clk
VLVD22
VLVD21
VO2 discharge
SS3 finish
4576 clk
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
VLVD31
VLVD32
VO3 discharge
EN_LDO
VLVD42
VLVD41
VO4 (EXT_LDO) = FB_LDO
tPG OOD = 10 ms
PGOOD
Figure 20. Output Timing Chart (EN Start-up and Stop)
Output power up sequence
1. EN high input -> Internal regulator (VREG) starts up -> VREG power good.
2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up.
3. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up.
4. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42).
5. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up.
6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2
.
Output power down sequence
1. EN low input -> PGOOD low -> stop VO2 (DC/DC2) operation and discharging VO2.
2. LVD2 power bad or 10 ms (Typ) after VO2 discharge start -> VO4 (External LDO) falls.
3. LVD4 power bad or 10 ms (Typ) after EN_LDO low -> stop VO3 (DC/DC3) operation and start discharging VO3.
4. LVD3 power bad or 10 ms (Typ) after VO3 discharge start -> stop VO1 (DC/DC1) operation including the
internal regulators (VREG).
PGOOD operation is dependent on LVD1 to 4 conditions. The “10 ms” time depends on fOSC2.
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Function Explanations – continued
Timing Chart of Start and Stop using EN (H-mode)
VCC
VTH_EN 2
VTH_EN 1
EN
VUVLOVREG_OFF
VREG
200 μs (Typ)
SS1 high
4576clk (Typ)
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
Internal SS2 (DC/DC2)
VO2 (DC/DC2)
SS2 high
4576clk (Typ)
VLVD21
VLVD22
VO2 discharge
SS3 high
4576clk (Typ)
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
VLVD31
VO3 discharge
VLVD32
EN_LDO
VLVD42
VLVD41
VO4 (EXT_LDO) = FB_LDO
tPG OOD = 10 ms (Typ)
PGOOD
Figure 21. Output Timing Chart (EN Start-up and Stop)
Output power up sequence
1. EN high input -> Internal regulator (VREG) starts up -> VREG power good.
2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up.
3. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up.
4. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up.
5. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42).
6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2
.
Output power down sequence
1. EN low input -> PGOOD low and EN_LDO low -> VO4 (External LDO) falls.
2. LVD4 power bad or 10 ms (Typ) after EN low input -> stop VO2 (DC/DC2) operation and start discharging VO2.
3. LVD2 power bad or 10 ms (Typ) after VO2 discharge start -> stop VO3 (DC/DC3) operation and start
discharging VO3.
4. LVD3 power bad or 10 ms (Typ) after VO3 discharge start -> stop VO1 (DC/DC1) operation including the
internal regulators (VREG).
PGOOD operation is dependent on LVD1 to 4 conditions. The “10 ms” time depends on fOSC2.
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Application Examples
1. Caution on PCB Layout
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN 23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN 1
C5
CIN 0
Figure 22.Circuits Example
I.
II.
Connect line in bold as short as possible with wide pattern.
Place input capacitor CIN0, CIN1, CIN23 and C5 close to IC as much as possible.
Especially distance between CIN0 and IC must be connected in top layer not through via.
III. Place CSSC and RRT near IC as much as possible.
IV. Sense line of VO1, VO2, VO3 and FB_LDO must be placed far from L1, L2 and L3 as much as possible.
V. Connect all GND pin (GND, PGND1 and PGND23) and EXP-PAD as short as possible in top layer.
VI. Connect EXP-PAD directly to the GND pin.
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1. Caution on PCB Layout – continued
Top Layer
2nd Layer
Bottom Layer
3rd Layer
Figure 23. Recommendation Layout Pattern
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Application Examples – continued
2. Selection of Components Externally Connected
2.1 Selection of the Inductor L (L1, L2 and L3)
When the switching regulator supplies current continuously to the load, the LC filter is necessary to smooth the output
voltage. The inductor ripple current ΔIL that flows to the inductor becomes small when an inductor with a large
inductance value is selected. Consequently, the voltage of the output ripple also becomes small.
Refer to "Circuit Example" for the recommended inductors.
Maximum ΔIL is shown in the following equation.
(푉ꢀ퐶퐶ꢁ푀퐴푋) − 푉ꢀ푂ꢂ × 푉ꢀ푂
[A]
∆퐼퐿
=
ꢃ × 푉ꢀ퐶퐶ꢁ푀퐴푋) × 푓
푆푊
Where:
VVCC(MAX) is the maximum input voltage. DC/DC1 is PVCC, DC/DC2 is VS2, and DC/DC3 is VS3.
fSW is switching frequency.
L is the value of inductor.
It contributes to the miniaturization of the application if the inductance value is small. The disadvantages are the
increase in the voltage of output ripple. It contributes to the small voltage of the output ripple if the inductance value
is large. The disadvantages are the increase in the size of inductor.
The maximum output electric current is limited to the overcurrent protection working current as shown in the following
equation.
∆퐼퐿
[A]
퐼표 푀퐴푋 = 퐼
+
)
푆푊 푀퐴푋
ꢁ
)
ꢁ
2
Where:
IO(MAX) is the maximum output current.
ISW(MAX) is the maximum SW load current.
2.2 Selection of the Output Capacitor CO (CO1, CO2, CO3
)
The voltage of output ripple ΔVPP is shown in the following equation.
1
∆푉푃푃 = ∆퐼퐿 × ꢄ푅퐸푆ꢅ
+
ꢇ
[V]
8 × ꢆ푂 × 푓
푆푊
Where:
RESR is the equivalent series resistance of output capacitor.
CO is the value of output capacitor.
ΔVPP can be reduced by using a capacitor with a small ESR. The ceramic capacitor is the best option that meets
this requirement. Confirm frequency characteristic of ESR from the datasheet of the manufacturer, and consider ESR
value to be low in the switching frequency being used. It is necessary to consider the ceramic capacitor, because the
DC biasing characteristic is remarkable. By selecting these high voltage ratings, it is possible to reduce the influence
of DC bias characteristics.
Refer to "Circuit Example" for the recommended output capacitors.
These capacitors are rated in ripple current. The RMS values of the ripple current that can be obtained in the following
equation must not exceed the ratings ripple current.
∆퐼퐿
[A]
퐼ꢁ
ꢅ푀푆
=
)
12
√
Where :
RESR is the equivalent series resistance of output capacitor.
CO is the value of output capacitor.
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BD86852MUF-C
2. Selection of Components Externally Connected – continued
2.3 Selection of the Output Capacitor C5
A ceramic capacitor is needed for the internal regulator VREG pin. Moreover, in order to maintain good temperature
characteristics, the one with the X7R characteristic or better is recommended. The voltage rating is recommended to
3 times or more the output voltage. Refer to "Circuit Example" for the recommended output capacitor.
2.4 Selection of Input Capacitor CIN (CIN0, CIN1, CIN23
)
The input capacitor is usually required for two types of decoupling capacitors, the CIN and the bulk capacitors. Ceramic
capacitors are effective by being placed as close as possible to the VCC (PVCC, VS2 and VS3) pin and the GND
(PGND1 and PGND23) pin. Voltage rating is recommended to 1.2 times or more the maximum input voltage.
Refer to "Circuit Example" for the recommended input capacitors. Also, the IC might not function properly when the
PCB layout or the position of the capacitor is not good. Refer to “Caution on PCB Layout”.
The bulk capacitor is an option. The bulk capacitor prevents the decrease in the line voltage and serves a backup
power supply to keep the input potential constant. The RMS value of the input ripple electric current is obtained in
the following equation. In that case, consider not to exceed the rated ripple current of the capacitor. The RMS value
of the input ripple electric current is obtained in the following equation.
푉ꢀ푂
푉ꢀ푂
∆퐼퐿ꢉ
12
× {퐼푂ꢉ × ꢄ1 −
ꢇ +
}
[A]
ꢈ
퐼ꢀ퐶퐶 ꢅ푀푆
=
ꢁ
)
푉ꢀ퐶퐶
푉ꢀ퐶퐶
Where:
IVCC(RMS) is the RMS value of the input ripple electric current.
VVCC is the input voltage. DC/DC1 is PVCC, DC/DC2 is VS2, and DC/DC3 is VS3.
VVO is the output voltage. DC/DC1 is VO1, DC/DC2 is VO2, and DC/DC3 is VO3.
2.5 Selection of Capacitor CB1
The CB1 is the capacitor between the BOOT1 pin and the SW1 pin for bootstrapping. The voltage of the CB1 and
SW1 is same as VREG. The recommended capacitor type is a ceramic capacitor. The CB1 must be set to 47 nF.
Moreover, the X7R or better capacitor is recommended.
2.6 Selection of Resistor at the EN Pin
The EN pin node potentially have unexpected short to VCC or GND on the assumption of accidental foreign objects
that physically shorts pin-to-pin. The resistor in series to the EN pin can minimize the fatal damage for the external
components. If the destructive damage is expected by the external components, use the resistor in series to the EN
pin to limit the current. The resistance is 20 kΩ or less.
VCC
CIN
CIN0
EN
Figure 24. EN Pin Resistance
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BD86852MUF-C
2. Selection of Components Externally Connected – continued
2.7 Selection of SSCG Pin Capacitor
The SSCG pin must be short to GND, if the spread spectrum feature is not used. The capacitor (CSSC) is
necessary to SSCG pin, if the spread spectrum feature is used. Use 3300 pF for fm_SSCG = 2.5 kHz (Typ)
modulation. (No other options)
VTH_SSCG = 1.7V (Typ)
fm_sscg =2.5kHz (Typ)
VSSCG
Figure 25. SSCG pin function
2.8 Selection of Resistor at RT Pin
Switching frequency depends on resistor value connected to the RT pin. RT resister must be set to 27 kΩ. The
resistor tolerance must be ±1 % or less. (No other options)
2.9 Selection of External LDO
External LDO (IC1) recommends BUxxJA2MNVX-C a miniature package. Please select external LDO by referring to
“Mode Setting Description”. If output current of VO4 exceed the following table value, adjust VO1 voltage to secure
input/output voltage differences, or selecting LDO with better drop out voltage characteristic is recommended.
Please refer Application circuit example (Using the VO1 resistance) for the method to adjust VO1 voltage.
External LDO
VO1 Voltage (typ.)
3.3 V
VO4 Voltage (typ.)
2.8 V
VO4 output current
≤ 120 mA
BU28JA2MNVX-C
BU29JA2MNVX-C
BU33JA2MNVX-C
3.3 V
3.9 V
2.9 V
3.3 V
≤ 90 mA
≤ 140 mA
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Application Examples – continued
3. Circuit Example
3.1 Parts Functional Description
Item
IC1
RRT
RPG
L1
Note
Item
CSSC
CIN1
CO1
Note
External LDO
Setting to spread spectrum ratio
VO1 input capacitor
Setting to switching frequency resistor
PGOOD pull-up resistor
VO1 output coil
VO1 output capacitor
CB1
VO1 boot strap capacitor
VO2 and VO3 input (VO1 output)
capacitor
L2
VO2 output coil
CIN23
L3
CIN0
C5
VO3 output coil
CO2
CO3
-
VO2 output capacitor
VCC input capacitor
VREG output capacitor
VO3 output capacitor
-
3.2 Circuit Diagram
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN 23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
VO3
EN_LDO
RPG
11
10
9
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN 1
C5
CIN 0
Figure 26. Application Circuits Example
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3. Circuit Example - continued
3.3
Component Coefficient (No.1)
Case1 (Light load model)
Output Current
-
≤ 0.3 A (Note 1)
≤ 0.25 A
≤ 0.25 A
Case2 (Light load model)
Output Current
-
≤ 0.3 A (Note 1)
≤ 0.25 A
≤ 0.25A
VVCC
VO1
VO2
VO3
4.0 V to 18 V
3.3 V
VVCC
VO1
VO2
VO3
5.0 V to 18 V
3.9 V
1.1 V or 1.2 V
1.8 V
1.2 V
1.8 V
(Note 1) Include VO2, VO3 and VO4 current.
(Note 1) Include VO2, VO3 and VO4 current.
Value
Item
UNIT
Parts No.
Size
Maker
Min
Max
Typ
(Note 1)
(Note 2)
IC
IC1
-
-
-
-
-
-
-
BD86852MUF-C
BUxxJA2MNVX-C
4.0 mm x 4.0 mm
1.0 mm x 1.0 mm
1005
-
ROHM
RRT
RPG
CIN0
C5
26.4
9
27.0
10
27.6
11
kΩ
kΩ
µF
µF
µF
pF
µF
nF
µF
µF
µF
µH
µH
µH
MCR01MZPF2702
MCR01MZPJ103
1005
0.05
0.5
2.0
2300
5
0.10
1.0
4.7
3300
10
0.15
3.3
15.0
4400
21
CGA2B3X7R1E104K
CGA3E1X7R1C105K
CGA4J1X7R1E475K
CGA2B2X7R1H332K
CGA4J1X7R0J106K
CGA2B2X7R1C473K
CGA4J3X7R1C225K
CGA4J1X7R0J106K
CGA4J1X7R0J106K
MLD2016S3R3MTD25
TFM201610ALMA1R5M
TFM201610ALMA1R5M
1005
1608
CIN1
CSSC
2012
1005
(Note 3)
CO1
CB1
2012
22
1.2
5
47
70
1005
TDK
(Note 3)
CIN23
2.2
10
6.0
35
2012
CO2
CO3
L1
2012
5
10
35
2012
(Note 4)
-
3.3
1.5
1.5
4.2
3.0
3.0
2016
(Note 5)
(Note 5)
L2
-
-
2016
L3
2016
(Note 1) Consider tolerance, temperature characteristic and DC bias properties not to become less than the minimum
(Note 2) Consider tolerance and temperature characteristic not to become bigger than the maximum.
(Note 3) Total capacity attached to VO1 node must not exceed 40 uF.
(Note 4) Choose an inductor of 3.3 µH (Typ). It must not become less than 2.0 µH including tolerance, temperature characteristic and DC
superposition characteristics.
(Note 5) Choose an inductor of 1.5 µH (Typ) or 2.2 µH (Typ). It must not become less than 1.0 µH including tolerance, temperature characteristic
and DC superposition characteristics.
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BD86852MUF-C
3. Circuit Example - continued
3.4
Component Coefficient (No.2)
Case3 (Middle load model)
Output Current
-
≤ 1.0 A(Note 1)
Case4 (Middle load model)
Output Current
-
≤ 1.0 A(Note 1)
VVCC
VO1
VO2
VO3
4.5 V to 18 V
3.3 V
VVCC
VO1
VO2
VO3
5.5 V to 18 V
3.9 V
1.1 V or 1.2 V
1.8 V
≤ 0.7 A
1.2 V
≤ 0.7 A
≤ 0.5 A
1.8 V
≤ 0.5 A
(Note 1) Include VO2, VO3 and VO4 current.
(Note 1) Include VO2, VO3 and VO4 current.
Case5 (Heavy load model)
Output Current
Case6 (Heavy load model)
Output Current
VVCC
VO1
VO2
VO3
5.0 V to 18 V
3.3 V
-
VVCC
VO1
VO2
VO3
6.0 V to 18 V
3.9 V
-
≤ 2.0 A(Note 1)
≤ 1.0 A
≤ 1.0 A
≤ 2.0 A(Note 1)
≤ 1.0 A
≤ 1.0 A
1.1 V or 1.2 V
1.2 V
1.8 V
1.8 V
(Note 1) Include VO2, VO3 and VO4 current.
(Note 1) Include VO2, VO3 and VO4 current.
Value
Item
UNIT
Parts No.
Size
Maker
Min
Max
Typ
(Note 1)
(Note 2)
IC
IC1
-
-
-
-
-
-
-
BD86852MUF-C
BUxxJA2MNVX-C
4.0 mm x 4.0 mm
1.0 mm x 1.0 mm
1005
-
ROHM
RRT
RPG
CIN0
C5
26.4
9
27.0
10
27.6
11
kΩ
kΩ
µF
µF
µF
pF
µF
nF
µF
µF
µF
µH
µH
µH
MCR01MZPF2702
MCR01MZPJ103
1005
0.05
0.5
2.0
2300
5
0.10
1.0
4.7
3300
10
0.15
3.3
15.0
4400
21
CGA2B3X7R1E104K
CGA3E1X7R1C105K
CGA4J1X7R1E475K
CGA2B2X7R1H332K
CGA4J1X7R0J106K
CGA2B2X7R1C473K
CGA4J3X7R1C225K
CGA4J1X7R0J106K
CGA4J1X7R0J106K
TFM252012ALMA3R3M
TFM201610ALMA1R5M
TFM201610ALMA1R5M
1005
1608
CIN1
CSSC
2012
1005
(Note 3)
CO1
CB1
2012
22
1.2
5
47
70
1005
TDK
(Note 3)
CIN23
2.2
10
6.0
35
2012
CO2
CO3
L1
2012
5
10
35
2012
(Note 4)
-
3.3
1.5
1.5
4.2
3.0
3.0
2520
(Note 5)
(Note 5)
L2
-
-
2016
L3
2016
(Note 1) Consider tolerance, temperature characteristic and DC bias properties not to become less than the minimum
(Note 2) Consider tolerance and temperature characteristic not to become bigger than the maximum.
(Note 3) Total capacity attached to VO1 node must not exceed 40 uF.
(Note 4) Choose an inductor of 3.3 µH (Typ). It must not become less than 2.0 µH including tolerance, temperature characteristic and DC
superposition characteristics.
(Note 5) Choose an inductor of 1.5 µH (Typ) or 2.2 µH (Typ). It must not become less than 1.0 µH including tolerance, temperature characteristic
and DC superposition characteristics.
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3. Circuit Example - continued
3.5 Application Circuit Example (FB_LDO and EN_LDO Not Connect)
When FB_LDO and EN_LDO are not connected to external LDO, connect FB_LDO to EN_LDO.
In this case, LVD and OVD of VO4 are not detected. And sequence of VO4 cannot be controlled.
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN 23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN 1
C5
CIN 0
Figure 27. Application Circuit Example (FB_LDO and EN_LDO not connect)
3.6 Application Circuit Example (FB_LDO Not Connect)
When FB_LDO is not connected to external LDO, connect FB_LDO to EN_LDO.
In this case, LVD and OVD of VO4 are not detected.
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN 23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN 1
C5
CIN 0
Figure 28. Application Circuit Example (FB_LDO not connect)
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3. Circuit Example - continued
3.7 Application Circuit Example (EN_LDO Not Connect)
When EN_LDO is not connected to external LDO, open EN_LDO pin.
In this case, sequence of VO4 cannot be controlled.
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN 23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN 1
C5
CIN 0
Figure 29. Application Circuit Example (EN_LDO not connect)
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3. Circuit Example - continued
3.8
Application Circuit Example (Using the EN Resistance)
When VCC input voltage is high enough, by using resistance division resistance (REN1, REN2) of VCC, it's possible to
turn off the output voltage in turn without externally controlling the EN pin.
VO4
VO1
VO3
VO2
IC1
CO3
CO2
VO1
L2
L3
CIN23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
CSSC
EXP-PAD
RRT
BOOT1
SW1
CB1
VO1
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN1
C5
REN1
REN2
CIN0
Figure 30. Application Circuit Example (Using the EN resistance)
It is necessary to make VEN more than VTH_EN1 at power up sequence, and less than VTH_EN2 before VUVLOVCC turns
ON at power down sequence.
Please choose REN1, REN2 to satisfy the following expressions.
(푉ꢀ퐶퐶ꢁ푀ꢊ푁) × 푅퐸푁ꢉ − 푅퐸푁ꢋ × 푅퐸푁ꢉ × 퐼퐸푁ꢁ푀퐴푋)
ꢂ
푉퐸푁
=
≥ 푉푇퐻_퐸푁ꢋꢁ푀퐴푋)
푅퐸푁ꢋ + 푅퐸푁ꢉ
(푉푈ꢀ퐿푂ꢀ퐶퐶_푂푁ꢁ푀퐴푋) × 푅퐸푁ꢉ − 푅퐸푁ꢋ × 푅퐸푁ꢉ × 퐼퐸푁ꢁ푀ꢊ푁)
ꢂ
푉퐸푁
=
≤ 푉푇퐻_퐸푁ꢉꢁ푀ꢊ푁)
푅퐸푁ꢋ + 푅퐸푁ꢉ
Where:
VVCC(MIN) is the minimum input voltage.
IEN(MAX): 45 µA
VTH_EN1(MAX): 2.6 V
VUVLOVCC_ON(MAX): 3.6 V
IEN(MIN): 5 µA
VTH_EN2(MIN): 1.5 V
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3.8
Application Circuit Example (Using the EN Resistance) - continued
It is necessary that each output voltage is OFF before VUVLOVCC turns ON to make outputs sequentially OFF.
Discharge time after each output turns OFF to LVD starts can be calculated by the following expressions.
푉
퐿ꢀ퐷푖
푡푖 = − ꢆ푂푖 × 푅ꢀ푂푖퐷ꢊ푆 // 푅퐿푂퐴퐷푖 × lnꢁ
)
푉푂푖
Li
VOi
SWi
RVOiDIS
COi
RLOADi
Figure 31. Discharge Resister
Where:
RVOiDIS: Discharge resistor (DCDC2, DCDC3)
VLVDi: LVD Operating Voltage
RLOADi: Load resistor
Co: Output capacitor
Vo: Output Voltage
DCR of Li is not considered
VCC
VUVLOVCC_ON
VTH_EN2
EN
VTH_EN1
VUVLOVREG_OFF
VREG
200 μs (Typ)
SS1 finish
4576 clk
Internal SS1 (DC/DC1)
VLVD12
VUVLOVS_OFF
VO1 (DC/DC1) = VS2, VS3, VS4
Internal SS2 (DC/DC2)
VO2 (DC/DC2)
SS2 finish
4576 clk
t2:VO2 Discharge Time
VLVD22
VLVD21
SS3 finish
4576 clk
Internal SS3 (DC/DC3)
VO3 (DC/DC3)
t3:VO3 Discharge Time
VLVD32
VLVD31
EN_LDO
VO4 Discharge Time
VLVD42
VLVD41
VO4 (EXT_LDO) = FB_LDO
tPGOOD = 10 ms
PGOOD
Figure 32. Output Timing Chart (Using the EN Resistance)
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3. Circuit Example - continued
3.9
Application Circuit Example (Using the VO1 Resistance)
It's possible to adjust input voltage of DCDC2, DCDC3 and Ext LDO (VVO1_adj) by the following dividing resistance
(RVO1A, RVO1B).
ꢁ
)
푅ꢀ푂ꢋ퐴 + 푅ꢀ푂ꢋ퐵
푉ꢀ푂ꢋ_푎푑푗
=
× ꢁ푉ꢀ푂ꢋ + 푅ꢀ푂ꢋ퐴 × 퐼ꢀ푂ꢋ_퐶푈ꢅ)
푅ꢀ푂ꢋ퐵
Where:
RVO1A: Please select resistance value less than 5 kΩ.
I VO1_CUR: VO1 Input current
Please choose RVO1A and RVO1B so that VVO1_adj does not exceed 4.0 V.
VO4
VO1_adj
VO3
VO2
IC1
CO3
CO2
VO1_adj
L2
L3
CIN23
18
17
16
15
14
13
VO3
19
20
21
22
23
24
12
11
10
9
VO3
EN_LDO
RPG
FB_LDO
VO1
PGOOD
SSCG
RT
RVO1B
CSSC
EXP-PAD
RRT
RVO1A
BOOT1
SW1
CB1
VO1_adj
8
MODE2
MODE1
L1
CO1
7
PGND1
1
2
3
4
5
6
CIN1
C5
CIN0
Figure 33. Application Circuit Example (Using the VO1 Resistance)
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BD86852MUF-C
Power Loss
Use good margin to keep the Ta and Tj operating range in the thermal design below.
Do not exceed the temperature specification of Ta and Tj at any time by design.
1. Ambient temperature Ta < 125 °C
2. Chip junction temperature Tj < 150 °C
Chip junction temperature Tj can be estimated by the following two ways.
I. Estimate Tj based on the package top center temperature Tt in actual usage.
ꢌꢍ = ꢌ푡 + 휓퐽푇 × ꢎ
II. Estimate Tj based on the ambient temperature Ta.
ꢌꢍ = ꢌꢏ + 휃ꢍꢏ × ꢎ
Power dissipation W of the IC is calculated by the following equation.
ꢎ = 퐼퐶퐶 × 푉퐶퐶 + ꢎ + ꢎ + ꢎ
ꢋ
ꢉ
3
Where:
ICC is circuit current.
VCC is input voltage.
W1 is power dissipation of DC/DC1.
W2 is power dissipation of DC/DC2.
W3 is power dissipation of DC/DC3.
Power loss of DC/DC W1 to W3
I. Loss of Tr
ꢉꢋ ꢌ × 푉 × 퐼푂 × 푓
푟
푆
푟푒푞
ꢀ
ꢐ
ꢉ
II. Loss of High Side FET ON resistance
푅푂푁퐻 × 퐼푂
×
ꢀ
ꢑ
III. Loss of Tf
ꢉꢋ ꢌ × 푉 × 퐼푂 × 푓
ꢒ
푆
푟푒푞
IV. Loss of body diode
푉퐹 × 퐼푂 × 2 × 푡푂퐹퐹 × 푓
푟푒푞
(When using external SBD, loss will not be included in IC.)
푅푂푁퐿 × 퐼푂 × ꢓꢀ ꢔꢀꢐ − 2 × 푡푂퐹퐹 × 푓 ꢕ
ꢉ
ꢑ
V. Loss of Low Side FET ON resistance
푟푒푞
ꢀ
ꢑ
Where:
VS is input voltage.
VO is output voltage.
IO is output current.
Tr/Tf is the rising/falling time of the switching voltage transition.
Freq is oscillation frequency.
RONH is RON of high side FET.
RONL is RON of low side FET.
VF is body diode of low side FET.
tOFF is dead time.
VS
Ⅱ
SW wave form
GND
Ⅰ
Ⅲ
Ⅳ
Ⅴ
Ⅳ
Figure 34. Power Loss of DC/DC
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BD86852MUF-C
Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
6.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
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Operational Notes – continued
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 35. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
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BD86852MUF-C
Operational Notes – continued
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
14. Disturbance Light
In a device where a portion of silicon is exposed to light such as in a WL-CSP and chip products, IC characteristics
may be affected due to photoelectric effect. For this reason, it is recommended to come up with countermeasures that
will prevent the chip from being exposed to light.
15. Functional Safety
“ISO 26262 Process Compliant to Support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in
the datasheet.
“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional Safety Supportive Automotive Products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
(Note) “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
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Ordering Information
B D 8
6
8
5
2 M U F -
CE 2
Package
Packaging and forming specification
MUF: VQFN24FV4040 C: for Automotive
E2: Embossed tape and reel
Marking Diagrams
VQFN24FV4040 (TOP VIEW)
Part Number Marking
8 6 8 5 2
LOT Number
Pin 1 Mark
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BD86852MUF-C
Physical Dimension and Packing Information
Package Name
VQFN24FV4040
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Revision History
Date
Revision
001
Changes
03.Mar.2020
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
相关型号：
BD868A0MUF-C
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ROHM
BD868C1MUF-C
PMIC BD868XXMUF-C系列产品内置有一次侧DC-DC、两个二次侧DC-DC、CMOS传感器用的二次侧线性稳压器和图像传感电源。该系列IC采用小型封装VQFN20FV3535，非常适用于需要小型电路板的摄像头模块。另外，该系列产品还具有展频功能，可提供更低噪声的稳压输出。
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BD868D0MUF-C
PMIC BD868XXMUF-C系列产品内置有一次侧DC-DC、两个二次侧DC-DC、CMOS传感器用的二次侧线性稳压器和图像传感电源。该系列IC采用小型封装VQFN20FV3535，非常适用于需要小型电路板的摄像头模块。另外，该系列产品还具有展频功能，可提供更低噪声的稳压输出。
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BD87007FJ
BD87007FJ是用于二次侧输出端的同步整流型控制器。内置低功耗高精度分流稳压器，可减少待机功耗。另外，在连续模式工作时，无需输入一次侧的开关同步信号即可工作，更加节省空间。工作电源电压宽达2.7V～32.0V，可支持各种输出的应用。另外，采用高耐压120V（Max）工艺，可直接监测漏极电压。
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BD87524FV-LB (开发中)
This is the product guarantees long time support in industrial market. And it is suitable for usage of industrial applications. BD87524FV-LB is input/output Rail-to-Rail CMOS operational amplifier. An operating voltage range is wide with 4V to 15V. This operational amplifier is the most suitable for industrial requirements such as sensor amplifier, battery-powered equipment and so on because it has features of high output drive. Furthermore, they have the advantage of EMI tolerance. It makes easier replacing with conventional products or simpler designing EMI.
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BD87554YFV-C
BD87554YFV-C是一款输入输出轨到轨CMOS运算放大器。具有工作电压范围宽（4V～15V）、输出驱动能力出色等特点，适用于传感器放大器、引擎控制单元、EPS、ABS等各种车载应用。
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BD87581YG-C
BD87581YG-C是输入输出Rail-to-Rail的CMOS运算放大器。具有宽动作电压范围4V～14V、以及高转换速率、低输入偏置电流等特点，尤其适用于传感器放大器、发动机控制单元、EPS、ABS等所有车载用途。并且，EMI耐受力具有优势，便于替换现有产品以及进行EMI设计。
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BD87582YFVM-C
BD87582YFVM-C是输入输出轨到轨的CMOS运算放大器。具有4V～14V的大动作电压范围、以及高转换速率、低输入偏置电流等特点，尤其适用于传感器放大器、发动机控制单元、EPS、ABS等各种车载用途。并且，EMI耐受力具有优势，便于替换现有产品以及进行EMI设计。
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