BD94130MUF-M (新产品) [ROHM]
BD94130MUF-M is embedded 24-channel constant current drivers with 12bit PWM dimming and max 8-line switch controllers. This device can set LED constant current value by setting external ISET resistor. Communication with μ-controller via SPI is feasible.;
| 型号： | BD94130MUF-M (新产品) |
| 厂家： | 
ROHM |
| 描述： | BD94130MUF-M is embedded 24-channel constant current drivers with 12bit PWM dimming and max 8-line switch controllers. This device can set LED constant current value by setting external ISET resistor. Communication with μ-controller via SPI is feasible. |
| 文件： | 总77页 (文件大小：3056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Automotive LED Driver Series
24-channel Constant Current Drivers and 8-
line Switch Controllers Embedded Backlight
LED Driver
BD94130MUF-M BD94130EFV-M
General Description
Key Specification
BD94130MUF-M/BD94130EFV-M are embedded 24-
channel constant current drivers with 12bit PWM dimming
and max 8-line switch controllers. This device can set
LED constant current value by setting external ISET
resistor. Communication with μ-controller via SPI is
feasible.
◼ Power Supply Voltage Range:
◼ LEDCHn Pin Voltage (n = 1 to 24):
◼ Maximum LED Output Current:
3.0 V to 5.5 V
20 V
80 mA
◼ Operating Temperature Range: -40 °C to +125 °C
Features
Package
W (Typ) x D (Typ) x H (Max)
8.0 mm x 8.0 mm x 1.0 mm
18.5 mm x 9.5 mm x 1.0 mm
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
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◼
◼
◼
AEC-Q100 Qualified(Note 1)
(BD94130MUF-M)
VQFN56FCV080
(BD94130EFV-M)
HTSSOP-B54
Functional Safety Supportive Automotive Products
Integrated 24-channel LED Constant Current Drivers
Integrated 4/6/8-line Switch Controllers
SPI Interface (Cascade Connection Feasible)
12bit PWM Dimming
LED Constant Current Setting by ISET Resistor
Phase Shift Function
6bit Dot Correct (50 % to 100 %)
LED Open Detection and LED Short Detection
Adjacent LEDCH Short Detection
PGATE Short Protection
VINSW Over Voltage Protection
Slew Rate Control for PMOS Gate Driver
Abnormality Output FAILB Pin
VQFN56FCV080
HTSSOP-B54
(Note 1) Grade 1
Application
◼
◼
Cluster, Center Infotainment Display
Other Automotive Backlights
Typical Application Circuit
DC/DC
VCC
VINSW
BD94130MUF
BD94130EFV
VREG15
ISET
EN
SW8
PGATE8
LSPSET
FB
SW2
PGATE2
PGATE1
SUMFB
SW1
VIO
LEDCELL
LEDCELL
L
LEDCELL
L
SCSB
SDI
LEDCH24
LEDCH23
SCLK
LEDCELL
LEDCELL
L
LEDCELL
L
SDO
MCU
VSYNC
HSYNC
VIO
LEDCELL
LEDCELL
L
LEDCELL
L
FAILB
LEDCH1
TEST1
TEST2
GND
LGND
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD94130MUF-M BD94130EFV-M
Pin Configuration
VQFN56FCV080 (TOP VIEW)
HTSSOP-B54 (TOP VIEW)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
(N.C.) 43
LEDCH13 44
LEDCH14 45
LEDCH15 46
LEDCH16 47
LEDCH17 48
28 (N.C.)
27 LEDCH12
26 LEDCH11
25 LEDCH10
24 LEDCH9
23 LEDCH8
22 LEDCH7
21 LGND
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
LEDCH18 49
EXP-PAD
LGND 50
LEDCH19 51
LEDCH20 52
LEDCH21 53
LEDCH22 54
LEDCH23 55
LEDCH24 56
20 LEDCH6
19 LEDCH5
18 LEDCH4
17 LEDCH3
16 LEDCH2
15 LEDCH1
EXP-PAD
1
2
3
4
5
6
7
8
9 10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Pin Description
VQFN56FCV080
1
HTSSOP-B54
48
Pin Name
Function
SUMFB
GND
Control DCDC feedback voltage
Common GND
2
49
50
51
53
54
1
3
EN
Enable input pin
4
VREG15
VCC
Output of 1.5 V voltage regulator for digital block
Power supply pin
6
7
FAILB
Abnormal operation detection output pin
VSYNC signal input pin
8
VSYNC
HSYNC
VIO
9
2
HSYNC signal input pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
3
Power supply pin for I/O
4
SDO
SPI data output pin
5
SCLK
SPI CLK input pin
6
SDI
SPI data input pin
7
SCSB
SPI device select setting pin
Output constant current channel 1
Output constant current channel 2
Output constant current channel 3
Output constant current channel 4
Output constant current channel 5
Output constant current channel 6
Analog GND for constant current driver block
Output constant current channel 7
Output constant current channel 8
Output constant current channel 9
Output constant current channel 10
8
LEDCH1
LEDCH2
LEDCH3
LEDCH4
LEDCH5
LEDCH6
LGND
9
10
11
12
13
14
15
16
17
18
LEDCH7
LEDCH8
LEDCH9
LEDCH10
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BD94130MUF-M BD94130EFV-M
Pin Description – continued
VQFN56FCV080
26
HTSSOP-B54
19
Pin Name
Function
Output constant current channel 11
LEDCH11
27
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
49
50
51
52
53
54
55
56
-
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
-
LEDCH12
FB
Output constant current channel 12
Control external DCDC feedback voltage
LED constant current setting pin
ISET
TEST1
Test pin 1
PGATE1
PGATE2
PGATE3
PGATE4
VINSW
Gate control 1 of external PMOS FET
Gate control 2 of external PMOS FET
Gate control 3 of external PMOS FET
Gate control 4 of external PMOS FET
Power supply for gate controller block
Gate control 5 of external PMOS FET
Gate control 6 of external PMOS FET
Gate control 7 of external PMOS FET
Gate control 8 of external PMOS FET
Test pin 2. Use this pin as an open pin.
LED short protection voltage setting for external adjustable
Output constant current channel 13
Output constant current channel 14
Output constant current channel 15
Output constant current channel 16
Output constant current channel 17
Output constant current channel 18
Analog GND for constant current driver block
Output constant current channel 19
Output constant current channel 20
Output constant current channel 21
Output constant current channel 22
Output constant current channel 23
Output constant current channel 24
The EXP-PAD is connected to GND
PGATE5
PGATE6
PGATE7
PGATE8
TEST2
LSPSET
LEDCH13
LEDCH14
LEDCH15
LEDCH16
LEDCH17
LEDCH18
LGND
LEDCH19
LEDCH20
LEDCH21
LEDCH22
LEDCH23
LEDCH24
EXP-PAD
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BD94130MUF-M BD94130EFV-M
Block Diagram
VCC
VINSW
VREF
EN
VCCUVLO
TSD
VINSWOVP
internal reference
voltage
EN
VCCUVLO
TSD
EN
Gate Controller
VREG
VINSW
EN
EN
VCCUVLO
TSD
VREG15
1.5 V
VCCUVLO
TSD
VREG15UVL O
PGATE8
VINSW - 4.5 V
PGATE Short
Detection
VREG15UVLO
VREG15UVLO
PGATE2
PGATE1
VIOUVLO
VIOUVLO
VIO
Current Driver
SCSB
SDI
PWM1・・・24
Dot correct 1 ・・・192
LEDCH24
LEDCH23
curent driver control
EN
VCCUVLO
TSD
SCLK
SDO
VREG15UVL O
Digital
LGND
LED OPEN/SHORT
Detection
VSYNC
HSYNC
LEDCHn to LEDCHn
Detection
LGND
・ ・ ・
EN
VCCUVLO
VREG15UVL O
FAILB
-
-
LEDCH1
ISET
-
+
ERRREF
LGND
FB
Soft Start
FB control
ISET
OPEN/SHORT
ISET
Driver
FB control
EN
VCCUVLO
TSD
VREG15UVLO
SUMFB
LSPSET
GND
TEST1 TEST2 LGND
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BD94130MUF-M BD94130EFV-M
Description of Blocks
If there is no description, the mentioned values are typical value.
The suffixes m of the symbol represent the number of gate control (m = 1 to 8), and the suffixes n represent the number of
current driver (n = 1 to 24), respectively. For example, LEDCHn means LEDCH1, LEDCH2,,,LEDCH24. PGATEm means
PGATE1, PGATE2,,,PGATE8. This expression is applicable to the whole of this datasheet.
1. Power Supply (VCC)
The VCC pin has UVLO function (VCCUVLO), and it starts operation at VCC ≥ 2.65 V (Typ) and stops operation at
VCC ≤ 2.55 V (Typ). About the condition to release/detect VCC UVLO, refer to Table 53. Connect a ceramic capacitor
(CVCC) to the VCC pin for stable operation. CVCC range is 1 µF to 22 µF and recommended value is 2.2 µF. If the CVCC
is not connected, unstable operation might occur e.g. oscillation.
2. Power Supply (VIO)
It supplies power to FAILB, SCSB, SCLK, SDI, SDO, VSYNC, and HSYNC input / output from the VIO pin. Connect a
ceramic capacitor (CVIO) to the VIO pin for stable operation. CVIO range is 1 µF to 4.7 µF and recommended value is
2.2 µF. If the CVIO is not connected, unstable operation might occur e.g. oscillation.
3. Power Supply (VINSW)
It supplies power to the output of PGATE1 to PGATE8 from the VINSW pin. Connect a ceramic capacitor (CVINSW) to
the VINSW pin to ensure stability of LED anode voltage. CVINSW range is 1 µF to 100 µF and recommended value is
10 µF. If the CVINSW value is not enough, the LED output might become unstable e.g. flicker.
4. Reference Voltage (VREG15)
VREG15 block generates 1.5 V from VCC, and outputs 1.5 V to the VREG15 pin. It supplies this power (VVREG15) to
the internal digital circuit. The VREG15 pin has UVLO function (VREG15UVLO), and it starts operation at VVREG15
≥
1.35 V (Typ) and stops operation at VVREG15 ≤ 1.30 V (Typ). It cannot be used to supply power to external components
from this IC. About the condition to release/detect VREG15 UVLO, refer to Table 53. Connect a ceramic capacitor
(CVREG15) to the VREG15 pin for phase margin. CVREG15 range is 1 µF to 4.7 µF and recommended value is 2.2 µF. If
the CVREG15 is not connected, unstable operation might occur e.g. oscillation.
5. Gate Controller
PGATEm pins connect to the gate of external PMOS transistors and this block controls power source timing to LED
array. Each PGATEm pin turns on in order from PGATE1 to PGATE8 in one period of VSYNC. The number of
PGATEm’s ON in one period of VSYNC can be set by PWMFREQ register, refer to PWMFREQ register. PGATEm
output HIGH level is VVINSW (Typ) and its LOW level is VVINSW – 4.5 V (Typ).
6. Current Driver
This device has integrated 24-channel constant current driver. Maximum LED current level ILEDMAX (<80 mA) of all
channels is set by the external resistor RISET of the ISET pin. The dot corrected current ILEDCHn (50 % to 100 %) is set
by the register IREVmn[5:0]. And the PWM dimming is set by the register DTYmn[11:0]. (m = 1 to 8, n = 1 to 24)
VSYNC
PGATE1
PGATE2
・
・
・
ILEDMAX: Maximum current level by RISET < 80 mA
Dot Correnction (50 % to 100 %) by the register IREVmn[5:0]
LEDCHn
current
ILEDCHn
PWM dimming by the register DTYmn[11:0]
Figure 1. LED Current Setting Method for Dimming
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BD94130MUF-M BD94130EFV-M
6. Current Driver – continued
(1) Output Current Setting
ILEDMAX and ILEDCHn can be calculated by the following equation.
Recommended ILEDMAX setting range is from 8.5 mA to 80 mA.
1440푘
퐼퐿퐸퐷푀퐴푋
=
[푚ꢁ]
푅ꢀ푆퐸푇
where RISET is the external resistor value of the ISET pin.
(퐼푅ꢂ푉푚ꢃ[5: 0] + 64)
퐼퐿퐸퐷퐶퐻푛 = 퐼퐿퐸퐷푀퐴푋
(2) Local PWM Dimming Control
×
[푚ꢁ]
127
PWM dimming frequency and pulse width are set by SPI commands. Constant current driver can be controlled
synchronized to the internal signal PWMn (n = 1 to 24) for each channel set by SPI.
However, the constant current driver’s minimum pulse width is limited to 0.6 µs. For example, in Matrix application
with HSYNC frequency 8 MHz, 12bit resolution is minimum 125 ns in 8-line controller. The controllable range is
from 5 to 4095.
The accurate average current of LEDCHn is expressed as follows, considering the deadtime of line controller.
ꢉ
퐼퐿퐸퐷_푎푣푒 = 퐼퐿퐸퐷퐶퐻푛 × ∑ (ꢄꢅ푌푚ꢃ + 1)/ (4,096 + 32 × 2푁푂푂ꢆ퐿퐴푃ꢇ + 32 × 2푁푂푂ꢆ퐿퐴푃ꢈ) × 8
{
[푚ꢁ]
}
ꢊꢋꢇ
where NOOVLAP1 = 0 to 3, NOOVLAP2 = 0 to 3, MULSEL = 0
(3) Delay Control
This IC integrates 12bit global delay function and 12bit local (each channel) delay function. In case HSYNC
frequency is 8 MHz, the shift rate (global) can be set by 1.0 µs steps in 8-line controller.
If the length of the local delay and duty is more than the period, the remaining “ON” width is output at the next
VSYNC period as shown on LEDCH24 of Figure 2. Refer to Delay Setting for details of this function.
VSYNC
global delay setting (GDLY)
PGATE1
PGATE2
PGATE3
PGATE4
PGATE5
PGATE6
PGATE7
PGATE8
delay setting (DLY01)
DTY101 DTY201 DTY301 DTY401 DTY501 DTY601 DTY701DTY801
LEDCH1
current
delay setting (DLY02)
DTY101 DTY201 DTY301 DTY401 DTY501 DTY601 DTY701DTY801
LEDCH2
current
delay setting (DLY24)
DTY101 DTY201 DTY301 DTY401 DTY501 DTY601DTY701 DTY801
LEDCH24
current
Figure 2. Delay Control
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6. Current Driver - continued
(4) LED Open Detection, LED Short Detection
This IC has LED Open Detection and LED Short Detection.
When LED Open/Short is detected and PWM = HIGH, it outputs FAILB = LOW and the status of LED Open/Short
Detection is updated.
LED Open Detection Voltage = VOPDET
LED Short Detection Voltage = VSHDET
(LED Short Detection Voltage can be set with SPI or the external resistor of the LSPSET pin. Refer to LEDSH
resister)
This IC can automatically detect or release Error condition (FAILB output, Error register) during PWMn = HIGH. The
error condition is retained during PWMn = LOW.
7. FB Control
DC/DC output and LEDCHn voltage is controlled by the FB pin. If the minimum LEDCHn voltage is lower than the
Feedback Reference Voltage, the FB sink current increases. If the minimum LEDCHn voltage is higher than the
Feedback Reference Voltage, the FB sink current decreases.
FB sink current is controlled by FBDAC[7:0]. The output is updated at the PGATE1 = ON in every VSYNC period
indicated by Figure 4. The minimum step current is 0.78 μA (Typ) and maximum sink current is 200 μA (Typ). The
resistor network between this device and DC/DC should be set appropriately by considering the current ability.
During the boot interval, the soft start function works. Please refer the register SSTIM[2:0] (Address 0x000: SRSST).
Table 1. Feedback Reference Voltage
Feedback
LED Current
Setting
FBREF[2:0]
Register
Reference
Voltage
LEDCH.1....LEDCH24
.....
DC/DC VOUT
8.5 mA
to 20 mA
20 mA
to 30 mA
30 mA
to 40 mA
40 mA
to 60 mA
60 mA
to 80 mA
Min
Voltage
Selector
0x0
0x1
0.45 V
0.53 V
0.60 V
0.75 V
0.90 V
1.5 V
FB
DC/DC
FBDAC[7:0]
FB Logic
DC/DC FB
0x2
0x3
0x4 to 0x7
Figure 3. FB Control Block Diagram
VSYNC
PGATE1
PGATE2
PGATE8
LEDCH1
current
LEDCH24
current
FBDAC[7:0]
UP
DOWN
DOWN
When even one LEDCHn pin is lower than the
feedback reference voltage.
When all LEDCHn pins are higer than the feedback
reference voltage.
Figure 4. FB Control Timing
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BD94130MUF-M BD94130EFV-M
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
VCC
Rating
-0.3 to +7
Unit
V
Power Supply Voltage Range 1
Power Supply Voltage Range 2
Power Supply Voltage Range 3
VREG15 Pin Voltage Range
VVIO
-0.3 to +4
V
VVINSW
-0.3 to +20
V
VVREG15
-0.3 to +1.65
-0.3 to +20
V
LEDCHn Pin Voltage Range
VLEDCHn
V
PGATEm Pin Voltage Range
FAILB, ISET Pin Voltage Range
FB, TEST2 Pin Voltage Range
EN, LSPSET, TEST1 Pin Voltage Range
VPGATEm
-0.3 to VVINSW+0.3 ≤ +20
-0.3 to +7
V
VFAILB, VISET
VFB, VTEST2
VEN, VLSPSET, VTEST1
V
-0.3 to +20
V
-0.3 to VCC+0.3
V
SCSB, SCLK, SDI, SDO, VSYNC, HSYNC,
SUMFB Pin Voltage Range
VSCSB, VSCLK, VSDI, VSDO
VVSYNC, VHSYNC, VSUMFB
,
-0.3 to VVIO+0.3 ≤ +4
V
Maximum Junction Temperature
Storage Temperature Range
Maximum LED Output Current
Tjmax
Tstg
150
°C
°C
-55 to +150
85(Note 1)(Note 2)
ILEDCHn
mA
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Wide VF variation of LED increases loss at the driver, which results in rise in package temperature. Therefore, the board needs to be designed with
attention paid to heat radiation.
(Note 2) This current value is per 1ch. It needs be used within a range not exceeding power dissipation.
Thermal Resistance (Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
VQFN56FCV080
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
72.7
4.0
24.3
3.0
°C/W
°C/W
ΨJT
HTSSOP-B54
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
55.8
4.0
20.6
2.0
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface
of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70 μm
Footprints and Traces
Layer Number of
Measurement Board
Thermal Via(Note 5)
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
Footprints and Traces
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 5) This thermal via connect with the copper pattern of layers 1,2, and 4. The placement and dimensions obey a land pattern.
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BD94130MUF-M BD94130EFV-M
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Operating Temperature
Topr
VCC
-40
3.0
1.6
3
-
5.0
-
+125
5.5
3.5
20
°C
V
Power Supply Voltage 1
V
Power Supply Voltage 2
VVIO
VVINSW
Power Supply Voltage 3
-
V
1.0
1.0
1
2.2
2.2
10
-
22.0
4.7
100
16
μF
μF
μF
V
VCC Pin Connection Capacitance
VIO Pin Connection Capacitance
VINSW Pin Connection Capacitance
CVCC
CVIO
CVINSW
0
FB Pin Operation Voltage
VFB
VREG15 Pin Connection Capacitance
CVREG15
1.0
18
-
2.2
-
4.7
170
20
μF
kΩ
MHz
%
ISET Resistance
RISET
HSYNC Frequency
fHSYNC
-
HSYNC Duty
fHSYNCDUTY
fVSYNC1
40
-
60
VSYNC Frequency
(8-line switch controller)
VSYNC Frequency
(6-line switch controller)
VSYNC Frequency
(4-line switch controller)
MULSEL = 0x0
PWMFREQ = 0
MULSEL = 0x2
PWMFREQ = 0
MULSEL = 0x1
PWMFREQ = 0
50
50
50
-
-
-
500
750
Hz
Hz
Hz
fVSYNC2
1000
fVSYNC3
tVSYNCMIN
tPWMMIN
VSYNC Minimum Pulse Width
50
0.6
8.5
8.5
0
-
-
-
-
-
-
-
-
μs
μs
PWM Minimum Pulse Width
LED Output Current 1
-
ILEDMAX1
ILEDMAX2
CLEDCH
70.0
80.0
0.1
1.8
500
mA
mA
μF
V
3.0 V ≤ VCC < 5.5 V
LED Output Current 2
3.5 V ≤ VCC < 5.5 V
(Note 1)
LEDCHn Pin Connection Capacitance
LSPSET Pin Voltage
VLSPSETDET
RFAILB
0.5
LSHEXT = 1
FAILB Pin Pull Up Resistance
10
kΩ
(Note 1) CLEDCH affects the transient response of LEDCHn pin. Please check the LED current waveform of the narrow PWM duty, the time margin of the LED
short detection, the short check of the adjacent LEDCHn pin, the pull up charge. Please refer the register ERRMASK (0x003), PRCEN (0x005), LEDSH
(0x006), LSHEXE (0x006)
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Electrical Characteristics
(Unless otherwise specified VCC = 3.0 V to 5.5 V, VVINSW = 10 V, VVIO = 1.8 V, Ta = -40 °C to +125 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
[Device Overview]
EN = LOW
VCC Circuit Current 1
VCC Circuit Current 2
ICCVCC1
-
-
0
20
μA
HSYNC = LOW
All Current driver OFF
VSYNC = 240 Hz
HSYNC = 7,987,200 Hz
MULSEL = 0
ICCVCC2
10.5
18.0
mA
Duty = 50 %
VINSW Circuit Current 1
VINSW Circuit Current 2
ICCVINSW1
ICCVINSW2
-
-
35
60
μA
μA
EN = LOW
EN = HIGH,
PGATEm = HIGH
220
400
SCSB = HIGH,
VIO Circuit Current
ICCVIO
-
0
5
μA
SDI = SCLK = VSYNC =
HSYNC = LOW, EN = LOW
[VREG15 Block]
VREG15 Pin Output Voltage
[PROTECT LOGIC Block]
VCCUVLO Detection Voltage
VCCUVLO Release Voltage
VCCUVLO Hysteresis Voltage
VIOUVLO Detection Voltage
VIOUVLO Release Voltage
VIOUVLO Hysteresis Voltage
VREG15UVLO Detection Voltage
LED Open Detection Voltage
VVREG15
1.400
1.470
1.540
V
IVREG15 = 0 mA
VVCCUVLO1
VVCCUVLO2
VVCCUHYS
VVIOUVLO1
VVIOUVLO2
VVIOUHYS
2.40
-
2.55
2.65
100
1.41
1.46
50
2.70
-
V
V
VCC = SWEEP DOWN
50
200
1.51
-
mV
V
1.31
-
VVIO = SWEEP DOWN
V
30
90
mV
V
VVREG15UVLO
VOPDET
1.22
0.05
1.30
0.15
1.38
0.25
VVREG15 = SWEEP DOWN
V
VLEDCHn = SWEEP DOWN
VLEDCHn = SWEEP UP
LEDSH[1:0] = 0x0
VLEDCHn = SWEEP UP
LEDSH[1:0] = 0x1
VLEDCHn = SWEEP UP
LEDSH[1:0] = 0x2
VLEDCHn = SWEEP UP
LEDSH[1:0] = 0x3
VLSPSET = 0.8 V
LED Short Detection Voltage 1
LED Short Detection Voltage 2
LED Short Detection Voltage 3
LED Short Detection Voltage 4
VSHDET1
VSHDET2
VSHDET3
VSHDET4
2.6
5.6
3.0
6.0
3.4
6.4
V
V
V
V
8.6
9.0
9.4
11.6
12.0
12.4
LED Short Detection Voltage 5
LSPSET Pin Leak Current
VLSPSETDET
ILSPSETLEAK
RISETSP
7.6
8.0
0
8.4
1
V
LSHEXT = 1
-
-
μA
kΩ
VLSPSET = 0.8 V
ISET Pin GND Short Detection
Resistance
-
16
ISET Pin Open Detection
Resistance
RISETOPEN
340
-
-
kΩ
VINSW Over Voltage Detection 1
VINSW Over Voltage Detection 2
VINSW Over Voltage Detection 3
VINSW Over Voltage Detection 4
VVINSWOVP1
VVINSWOVP2
VVINSWOVP3
VVINSWOVP4
7.5
8.0
8.5
V
V
V
V
VINSWOVPREF[1:0] = 0x0
VINSWOVPREF[1:0] = 0x1
VINSWOVPREF[1:0] = 0x2
VINSWOVPREF[1:0] = 0x3
11.4
15.2
17.1
12.0
16.0
18.0
12.6
16.8
18.9
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BD94130MUF-M BD94130EFV-M
Electrical Characteristics – continued
(Unless otherwise specified VCC = 3.0 V to 5.5 V, VVINSW = 10 V, VVIO = 1.8 V, Ta = -40 °C to +125 °C)
Parameter
[Constant Current Driver Block]
ISET Voltage
Symbol
Min
Typ
Max
Unit
Condition
VISET
1.38
-
1.50
4.5
1.62
9.0
V
LEDCHn Pin ON Resistance
RLEDCHn
Ω
ISET resistor = 48 kΩ
PWM = 100 %
ISET resistor = 48 kΩ
PWM = 100 %
ISET resistor = 48 kΩ
PWM = 100 %
LED Output Current
ILEDCHn
ΔILEDCHn
ΔILEDC1
-
30
-
-
mA
%
LED Output Current Error
-6
-6
+6
+6
LED Constant Current Error1
(channel to channel)(Note 1)
-
%
LED = OFF
ILEDCHn = -100 μA
3.5 V ≤ VINSW
VINSW-1.4 VINSW-1.2 VINSW-1.0
Pull Up Voltage
VPULLUP
V
[Feedback Control Block]
Feedback Reference Voltage 1
Feedback Reference Voltage 2
Feedback Reference Voltage 3
Feedback Reference Voltage 4
Feedback Reference Voltage 5
VFB1
VFB2
VFB3
VFB4
VFB5
0.36
0.44
0.50
0.64
0.78
0.45
0.53
0.60
0.75
0.90
0.54
0.62
0.70
0.86
1.02
V
V
V
V
V
FBREF[2:0] = 0x0
FBREF[2:0] = 0x1
FBREF[2:0] = 0x2
FBREF[2:0] = 0x3
FBREF[2:0] = 0x4 to 0x7
FBDAC[7:0] = 0xFF
VFB = 2.0 V
FB Maximum Sink Current
IFBMAX
170
200
230
μA
VLEDCHn = 0.5 V
FB OFF Current
IFBOFF
RFB
RSUMFBL
RSUMFBH
-
0
1
μA
kΩ
Ω
VLEDCHn = 1.2 V, EN = LOW
FB ON Resistance
-
5.5
160
100
9.0
290
150
SUMFB ON Resistance
SUMFB Pull-up Resistance to VIO
[Gate Controller Block]
PGATEm PMOS ON Resistance
10
50
IFAILB = +1 mA
kΩ
RPONR
10
50
40
130
200
Ω
Ω
IPGATEm = -1 mA to -5 mA
IPGATEm = +1 mA to +5 mA
PGSRCNT[1:0] = 0x0
IPGATEm = +10 μA to +500 μA
PGSRCNT[1:0] = 0x1
IPGATEm = +10 μA to +120 μA
PGSRCNT[1:0] = 0x2
IPGATEm = +1 μA to +12 μA
PGSRCNT[1:0] = 0x3
PGATEm NMOS ON Resistance 1
PGATEm NMOS ON Resistance 2
PGATEm NMOS ON Resistance 3
PGATEm NMOS ON Resistance 4
RNONR1
100
RNONR2
RNONR3
1.0
5
1.4
10
2.5
15
200
-
kΩ
kΩ
kΩ
V
RNONR4
50
100
PGATEm to VSINSW Short
Detection Voltage 1
PGATEm to GND Short Detection
Voltage 1
PGATEm to VSINSW Short
Detection Voltage 2
VINSW-2.2 VINSW-1.5
VPGATEVIN1
VPGATEGND1
VPGATEVIN2
VINSW = 10 V
VINSW = 10 V
VINSW = 3.5 V
VINSW-2.5 VINSW-0.8
VINSW-1.3 VINSW-1.0
-
V
-
V
PGATEm to GND Short Detection
Voltage 2
VINSW-1.3 VINSW-0.8
VPGATEGND2
VLGATEm
-
V
V
VINSW = 3.5 V
VINSW = 10 V
PGATEm LOW Level
3.8
5.6
7.4
[LOGIC Input Block (SCSB, SCLK, SDI, VSYNC, HSYNC)]
0.75
×VVIO
VVIO
+0.2
0.2
Input HIGH Voltage
Input LOW Voltage
VINH
VINL
IIN
-
-
V
V
-0.2
×VVIO
VVIO = 3.3 V
LOGIC Pins Input Current
-
0
1
µA
LOGIC Input = 3.3 V
(Note 1)
ΔILEDC1 = (ILEDn / ILED_AVE - 1) x 100
ILEDn is either pin of LED1 to LED24 current.
ILED_AVE is the average current of LED1 to LED24.
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BD94130MUF-M BD94130EFV-M
Electrical Characteristics – continued
(Unless otherwise specified VCC = 3.0 V to 5.5 V, VVINSW = 10 V, VVIO = 1.8 V, Ta = -40 °C to +125 °C)
[Input Pin (EN)]
Input Pin HIGH Voltage
Input Pin LOW Voltage
Pin Input Current
VENH
VENL
IEN
1.6
-0.2
-
-
-
VCC
+0.4
60
V
V
33
µA
VEN = 3.3 V
[Input Pin (TEST1)] Typical Condition
Input Pin HIGH Voltage
Input Pin LOW Voltage
[LOGIC Output Block (SDO)]
Output HIGH Voltage
VTEST1H
VTEST1L
1.6
-
-
VCC
V
V
-0.2
+0.4
VVIO
-0.2
VVIO
0.2
VOUTH
VOUTL
-
-
V
V
IOL = -1 mA
IOL = +1 mA
Output LOW Voltage
-
[FAILB Output Block]
FAILB Pin ON Resistance
RFAILB
10
110
230
Ω
IFAILB = +1 mA
VFAILB = 5.0 V
FAILB Pin Leak Current
ILEAKFAILB
-
0
1
µA
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BD94130MUF-M BD94130EFV-M
Application Example
DC/DC
VCC
VINSW
BD94130MUF
BD94130EFV
VREG15
ISET
EN
SW8
PGATE8
LSPSET
FB
SW2
PGATE2
PGATE1
SUMFB
SW1
VIO
LEDCELL
L
LEDCELL
LEDCELL
L
SCSB
SDI
LEDCH24
LEDCH23
SCLK
LEDCELL
L
LEDCELL
LEDCELL
L
SDO
MCU
VSYNC
HSYNC
VIO
LEDCELL
L
LEDCELL
LEDCELL
L
FAILB
LEDCH1
TEST1
TEST2
GND
LGND
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BD94130MUF-M BD94130EFV-M
Functions of Logic Block
1. Serial Interface and AC Electrical Characteristics
Serial Peripheral Interface (SPI) controls the IC with SCSB, SCLK, SDI, and SDO signals.
Start the SPI communication with the initial value of SCSB is HIGH, and that of SCLK and SDI is LOW.
When using several devices, connect the SDO pin to the SDI pin of the next device to make cascade connection. SDO signal
outputs the SDI input after 16 SCLK pulses. Example of the N address write is shown in the following.
The initial value of SDO is LOW, until it is used to output the signal.
SCSB
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th
SCLK
SDI
･･････････
･･････････
･･････････
DT DT DT DT DT DT DT DT
DT DT
DT DT DT DT DT
DA DA DA DA DA DA
[5] [4] [3] [2] [1] [0]
ND ND ND
ND ND ND ND ND ND
RA RA RA RA RA RA RA RA RA
DT
RW
B
S
0
0
0
0
[12] [11] [10] [9]
[7] [6]
[4] [3] [2] [1] [0]
[8] [7] [6] [5] [4] [3]
[2] [1] [0]
[8] [7] [6] [5] [4] [3] [2] [1] [0] [15] [14] [13]
[8]
[5]
Data[15:0]
16bits
RegAddr[8:0]
16bits
DevAddr[5:0]
NumOfData[8:0]
16bits
16bits
ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0]
ND ND ND
RA RA RA RA RA RA RA RA RA
DT
[8] [7] [6] [5] [4] [3] [2] [1] [0] [15]
DA DA DA DA DA DA
[5] [4] [3] [2] [1] [0]
0
0
0
RW
B
S
SDO
[8] [7] [6]
･･････････
･･････････
B:
S:
RW:
DA[5:0]:
ND[8:0]:
RA[8:0]:
DT[15:0]:
Broadcast
Single
Read / Write
Device Address
Number Of Data
Register Address
Data
DT DT DT DT DT DT DT DT DT DT
[10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DT
･･････････
Data[15:0]
DT
DT
[0] [15]
DT DT DT DT DT DT DT DT DT
[9] [8] [7] [6] [5] [4] [3] [2] [1]
･･････････
Figure 5. SPI Protocol (Write)
SCSB
SCLK
SDI
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th
･･････････
･･････････
･･････････
ND ND ND
[8] [7] [6]
ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0]
RA RA RA RA RA RA RA RA RA
[8] [7] [6] [5] [4] [3] [2] [1] [0]
DA DA DA DA DA DA
[5] [4] [3] [2] [1] [0]
RW
B
S
0
0
0
0
0
DevAddr[5:0]
NumOfData[8:0]
RegAddr[8:0]
Data[15:0]
16bits
16bits
16bits
16bits
ND ND ND
ND ND ND ND ND ND
RA RA RA RA RA RA RA RA RA
RD
[8] [7] [6] [5] [4] [3] [2] [1] [0] [15]
DA DA DA DA DA DA
[5] [4] [3] [2] [1] [0]
0
0
0
RW
B
S
SDO
[8] [7] [6] [5] [4] [3]
[2] [1] [0]
･･････････
･･････････
B:
S:
RW:
DA[5:0]:
ND[8:0]:
RA[8:0]:
RD[15:0]:
Broadcast
Single
Read / Write
Device Address
Number Of Data
Register Address
Read Data
･･････････
RD RD RD RD RD RD RD RD
RD RD
RD
RD
[0]
･･････････
[15] [14] [13] [12]
[6] [5] [4] [3] [2] [1] [0]
Figure 6. SPI Protocol (Read)
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BD94130MUF-M BD94130EFV-M
Functions of Logic Block – continued
2. SPI AC Timing
VSYNC
tSCSBVS
tSCSBVH
tSCSBHP
SCSB
High Vth
Low Vth
fSCLK
tSCSBS
tSCSBH
SCLK
tSDIH tSDIS tSDIH tSDIS
SDI
tSDOD
tSDOD
SDO
High Vth
Low Vth
SPI Recommended Operation Condition
(Unless otherwise specified Ta = -40 °C to +125 °C, VVIO = 1.8 V, VCC = 3.0 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Frequency
fSCLK
fSCLKDUTY
tSDIS
0.1
45
-
-
-
-
-
-
-
-
-
-
-
20
55
-
MHz
%
SCLK Duty
SDI Input Setup Time
10
ns
SDI Input Hold Time
tSDIH
10
-
ns
SCSB Input Setup Time
tSCSBS
100
100
-
-
ns
SCSB Input Hold Time
tSCSBH
tSDOD
-
ns
SDO Output Delay Time
40
-
ns
SCSB HIGH Pulse Width
SCSB Setup Time for VSYNC
SCSB Hold Time for VSYNC
Cascade Connection Number
(Note) Do not input VSYNC pulse during SCSB = LOW
tSCSBHP
tSCSBVS
tSCSBVH
NCASCADE
1000
10
ns
-
μs
10
-
μs
-
20
pcs
(Output load capacitance: 15 pF)
The maximum frequency of the HSYNC and VSYNC is described in the previous section “Recommended Operating Conditions”.
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Functions of Logic Block – continued
3. SPI Connection
(1) Cascade Connection
Each device can be controlled by connecting the SCLK and the SCSB pins to all devices in parallel, and by connecting
each SDO to the SDI of the next device in series. The maximum number of devices that can be cascaded is 20.
Device #1
Device #2
Device #20 (maximum)
BD94130EFV
MCU
BD94130EFV
BD94130EFV
SDI
SDO
SDI
SDO
SDI
SDO
MOSI
SCSB
SCSB
SCLK
SCSB
SCLK
SCLK
CS
CLK
MISO
Figure 7. Image of Cascade Connection
(2) Individual Connection
Each device can be controlled by connecting the SCLK and the SDI pins to all devices in parallel, and by connecting
each SCSB.
Device #1
MCU
MOSI
BD94130EFV
SDI SDO
SCSB
CS1
SCLK
MISO1
Device #2
BD94130EFV
SDI SDO
SCSB
CS2
SCLK
MISO2
Device #20 (maximum)
BD94130EFV
SDI SDO
SCSB
CS20
CLK
SCLK
MISO20
Figure 8. Image of Individual Connection
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Functions of Logic Block – continued
4. SPI Data Flow
MCU Write and Read flow is shown as follow. This IC has 4 timing schemes for updating the analog control data.
Type 1 (immediately):
Type 2 (VSYNC):
Type 3 (VSYNC+GDLY):
Type 4 (PWM):
Data is updated after SPI access.
Data is updated after SPI access and VSYNC rising edge.
Data is updated after SPI access and VSYNC rising edge and GDLY.
Data is updated after SPI access and VSYNC rising edge and PWM timing.
So there is mismatch between Read data and Control data.
Immediately
Register
VSYNC
VSYNC + GDLY
PWM
SPI write
A
(LEDENL, etc)
Control
data
B
(GDLY,etc)
MCU
Analog
Circuit
SPI read
Control
data
C
(DLYn)
buffer
Control
data
D
buffer1
buffer2
(DTYCNTmn)
(n = 1 to 24)
(m = 1 to 8)
Figure 9. SPI Data Flow
Available to access register for next frame
SPI
VSYNC
Type 1
PWMFREQ
Type 2
GDLY
(register)
update at next VSYNC
GDLY
(Control data)
Type 3
DLYn
(register)
update at next VSYNC
GDLY
DLYn
(buffer)
update at next PWM output
DLYn
(Control data)
Type 4
DTYCNTmn
(register)
update at next VSYNC
update at next PWM output
DLYn
DTYCNTmn
(buffer1)
DTYCNTmn
(buffer2)
DTYCNTmn
(Control data)
PGATE1
DTYCNTmn
LEDCHn
Figure 10. SPI Data Flow Timing
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Functions of Logic Block – continued
5. SPI Protocol
(1) Device Address
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B
S
0
DevAddr[5:0]
Value
Bit
Parameter
Broadcast
B = 1: All devices receive the data
(Write only / No Read)
B = 0: Write / Read to the Device that assigned by DevAddr[5:0]
S = 1: 1 address Write / Read mode
S = 0: Block Write / Read mode
B
S
Single
0x00: Write the same data to the same RegAddr[8:0] of all devices
(provided, B = 1)
0x01 to 0x14: Device Address
0x3F: Write the different data to the same RegAddr[8:0] of all devices
(provided, B = 1)
Device
Address
DevAddr[5:0]
DevAddr[5:0] of each device is calculated by counting the number of byte of 0x0000 data after the fall-edge of SCSB.
When the received DevAddr[5:0] matches with the calculated DevAddr[5:0] of the device, Write/Read function occurs.
When the received DevAddr[5:0] does not match the calculated DevAddr[5:0] of the device, the data is not received and is
output to SDO. Refer to each protocol for the details.
(2) Number of Transferred Byte when Block Write/Read
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
NumOfData[8:0]
Bit
Parameter
Number of transferred data
Transferred byte number = NumOfData[8:0]
Value
NumOfData[8:0]
0x002 to 0x16B
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5. SPI Protocol – continued
When S = 0 (Block Write / Read) of DevAddr[5:0], set the number of transferred byte (NumOfData) after DevAddr[5:0].
When S = 1, it skip this packet. (“Device Address” -> “Register Address” -> ….)
Please access this IC using the settings as shown in Table 2 and Table 3.
Table 2. Access Table for Write (RW = 0)
SPI Setting
Access to Devices
For All Device
Acceptable
For Single
Device
(Note)
B
0
S
0
1
0
1
DevAddr[5:0]
NumOfData[8:0]
0x002 to 0x147
Same
Different
Data
Data
0x00
0x01 to 0x14
0x15 to 0x3F
0x00
0x01 to 0x14
0x15 to 0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
-
O
-
-
O
-
-
-
-
-
-
-
-
-
-
-
O
-
-
-
-
-
-
-
-
-
X
O
X
X
O
X
O
X
O
O
X
O
Not sending
this data
0x002 to 0x147
-
O
-
O
-
1
Not sending
this data
-
-
-
-
O
(Note) X: This setting is not acceptable. Do not set this condition
Table 3. Access Table for Read (RW = 1)
SPI Setting
Access to Devices
For All Device
Acceptable
For Single
Device
(Note)
B
0
1
S
0
DevAddr[5:0]
NumOfData[8:0]
0x002 to 0x16B
Same
Different
Data
Data
0x00
0x01 to 0x14
0x15 to 0x3F
0x00
0x01 to 0x14
0x15 to 0x3F
0x00
-
O
-
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
O
X
X
O
X
X
X
X
Not sending
this data
1
0 / 1
0x01 to 0x3E
0x3F
0x002 to 0x16B
(Note) X: This setting is not acceptable. Do not set this condition.
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5. SPI Protocol – continued
(3) Register Address
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RW
0
RegAddr[8:0]
Bit
Parameter
Value
RW = 0: Write the registers
RW = 1: Read the registers
0x000 to 0x16B
RW
Read / Write
RegAddr[8:0]
Register Address
(4) Data
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Data[15:0]
Bit
Data[15:0]
Parameter
Data
Value
0x0000 to 0xFFFF
(5) Single Device, 1 Address Write (Write to Device #1)
B =
0:
Target device receives the data
S =
1:
Single
DevAddr[5:0] =
NumOfData[8:0] = -:
RW =
RegAddr[8:0] =
0x01:
Target device address
1 address access
Write
0:
0x002:
Address
SDI:
Transfer in the order of DevAddr[5:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
B
S
DevAddr[5:0] RW
RegAddr[8:0]
0 1
0x00
0x01
0
0x00
0x002
Data1[15:0]
SDI
SDO
0x0000
0 1
0x00
0x01
0
0x00
0x002
Ex) Detail of Timing Chart
SCSB
SCLK
RegAddr[8:0]
B
S
DevAddr[5:0]
Data1[15:0]
RW
SDI
16bit shift every Device
SDO
Device #1
Register
0x007
0x006
0x005
0x004
0x003
0x002 Data1
0x001
0x000
Figure 11. SPI Protocol for 1 Address Write to Device #1
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5. SPI Protocol – continued
(6) Single Device, 1 Address Write (Write to Device #3)
B =
S =
0:
1:
Target device receives the data
Single
DevAddr[5:0] =
NumOfData[8:0] = -:
RW =
RegAddr[8:0] =
0x03:
Target device address
1 address access
Write
0:
0x002:
Address
SDI:
Transfer in the order of DevAddr[5:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
DevAddr[5:0] of each device is calculated by counting the number of byte of 0x00 data after the falling-edge of SCSB.
DevAddr[5:0] = (Number of byte of 0x00 data) + 1
SCSB
SCLK
BS
DevAddr[5:0] RW
0x03 0x00
RegAddr[8:0]
0x002
01 0x00
0
Data1[15:0]
0x0000
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
01 0x00
0x03
0
0x00
0x002
Data1[15:0]
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
01 0x00
0x03
0
0x00
0x002
0x03
Data1[15:0]
0x0000
0x0000
01 0x00
0
0x00
0x002
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x007
0x006
0x005
0x004
0x003
0x002 Data1
0x001
0x000
Figure 12. SPI Protocol for 1 Address Write to Device #3
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5. SPI Protocol – continued
(7) Single Device, N Address Write (Write to the consecutive register of Device #1)
B =
S =
0:
0:
Target device receives the data
Single
DevAddr[5:0] =
NumOfData[8:0] = 0x003:
RW =
0x01:
Target device address
3 address access
Write
0:
RegAddr[8:0] =
0x002:
Address
SDI:
Transfer in the order of DevAddr[5:0], NumOfData[8:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0]
0x01
NumOfData[8:0] RW
RegAddr[8:0]
0x002
00 0x00
0x00
0x003
0
0x00
Data1[15:0]
Data2[15:0]
Data1[15:0]
Data3[15:0]
Data2[15:0]
Data1[15:0]
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
00 0x00
0x01
0x00
0x003
0
0x00
0x002
0x003
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
00 0x00
0x01
0x00
0
0x00
0x002
0x003
0x0000
0x0000
00 0x00
0x01
0x00
0
0x00
0x002
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
Data3
0x003 Data2
0x002 Data1
0x001
0x000
Figure 13. SPI Protocol for N Address Write to Device #1
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5. SPI Protocol – continued
(8) All Devices, Different 1 Address Write (Write the same 2 bytes data to the same RegAddr[8:0] of all devices)
B =
S =
1:
1:
All devices receive data
Single
DevAddr[5:0] =
NumOfData[8:0] = -:
RW =
RegAddr[8:0] =
0x3F:
All devices receive different data
1 address access
Write
0:
0x002:
Address
SDI:
Transfer in the order of DevAddr[5:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0] RW
RegAddr[8:0]
11 0x00
0x3F
0
0x00
0x002
Data1[15:0]
Data2[15:0]
Data1[15:0]
Data3[15:0]
Data2[15:0]
0x0000
Data3[15:0]
Data2[15:0]
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
11 0x00
0x3F
0
0x00
0x002
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
11 0x00
0x3F
0
0x00
0x002
0x3F
Data1[15:0]
Data3[15:0]
Data2[15:0]
0x0000
0x0000
11 0x00
0
0x00
0x002
Data1[15:0]
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x006
0x005
0x004
0x003
0x007
0x006
0x005
0x004
0x003
0x007
0x006
0x005
0x004
0x003
0x002 Data1
0x001
0x002 Data2
0x001
0x002 Data3
0x001
0x000
0x000
0x000
Figure 14. SPI Protocol for 1 Address Distinct Data Write to All Devices
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5. SPI Protocol – continued
(9) All Devices, Same 1 Address Write (Write the same 2 bytes data to the same RegAddr[8:0] of all devices)
B =
1:
All devices receive data
S =
1:
Single
DevAddr[5:0] =
RW =
0x00:
0:
All devices receive the same data
Write
NumOfData[8:0] = -:
RegAddr[8:0] = 0x002:
1 address access
Address
SDI:
Transfer in the order of DevAddr[5:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0] RW
0x00 0x00
RegAddr[8:0]
0x002
11 0x00
0
Data1[7:0]
0x0000
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
11 0x00
0x00
0
0x00
0x002
Data1[7:0]
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
11 0x00
0x00
0
0x00
0x002
0x00
Data1[7:0]
0x0000
0x0000
11 0x00
0
0x00
0x002
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x007
0x006
0x005
0x004
0x003
0x007
0x006
0x005
0x004
0x003
0x006
0x005
0x004
0x003
0x002 Data1
0x001
0x002 Data1
0x001
0x002 Data1
0x001
0x000
0x000
0x000
Figure 15. SPI Protocol for 1 Address Distinct Data Write to All Devices
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5. SPI Protocol – continued
(10) All Devices, Different N Address Write (Write the different N x 2 bytes data to the same RegAddr[8:0] of all
devices)
B =
1:
All devices receive data
S =
0:
Multi
DevAddr[5:0] =
0x3F:
All devices receive different data
NumOfData[8:0] = 0x002:
2 address access
Write
RW =
0:
RegAddr[8:0] =
0x002:
Address
SDI:
Transfer in the order of DevAddr[5:0], NumOfData[8:0], RegAddr[8:0], and Data[15:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0]
0x3F
NumOfData[8:0] RW
RegAddr[8:0]
0x002
10 0x00
0x00
0x002
0
0x00
Data1[15:0]
Data2[15:0]
Data1[15:0]
Data3[15:0]
Data2[15:0]
Data1[15:0]
Data4[15:0]
Data3[15:0]
Data2[15:0]
Data5[15:0]
Data4[15:0]
Data3[15:0]
Data6[15:0]
Data5[15:0]
Data4[15:0]
0x0000
Data6[15:0]
Data5[15:0]
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
10 0x00
0x3F
0x00
0x002
0
0x00
0x002
0x002
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
10 0x00
0x3F
0x00
0
0x00
0x002
0x002
Data6[15:0]
0x0000
0x0000
10 0x00
0x3F
0x00
0
0x00
0x002
Data1[15:0]
Data2[15:0]
Data3[15:0]
Data4[15:0]
Data5[15:0]
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x003 Data2
0x002 Data1
0x001
0x003 Data4
0x002 Data3
0x001
0x003 Data6
0x002 Data5
0x001
0x000
0x000
0x000
Figure 16. SPI Protocol for N Address Distinct Data Write to All Devices
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5. SPI Protocol – continued
(11) All Devices, Same N Address Write (Write the same N x 2 bytes data to the same RegAddr[8:0] of all devices)
B =
1:
All devices receive data
S =
0:
Multi
DevAddr[5:0] =
0x00:
All devices receive the same data
NumOfData[8:0] = 0x003:
3 address access
Write
RW =
0:
RegAddr[8:0] =
0x002:
Address
SDI:
SDO:
Transfer in the order of DevAddr[5:0], NumOfData[8:0], RegAddr[8:0], and Data[15:0].
Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0]
0x00
NumOfData[8:0] RW
RegAddr[8:0]
0x002
10 0x00
0x00
0x003
0
0x00
Data1[15:0]
Data2[15:0]
Data1[15:0]
Data3[15:0]
Data2[15:0]
Data1[15:0]
0x0000
Data3[15:0]
Data2[15:0]
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
10 0x00
0x00
0x00
0x003
0
0x00
0x002
0x003
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
10 0x00
0x00
0x00
0
0x00
0x002
0x003
Data3[15:0]
0x0000
0x0000
10 0x00
0x00
0x00
0
0x00
0x002
Data1[15:0]
Data2[15:0]
Device #3 SDO
Device #1
Device #2
Register
Device #3
Register
Register
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
Data3
Data3
Data3
0x003 Data2
0x002 Data1
0x001
0x003 Data2
0x002 Data1
0x001
0x003 Data2
0x002 Data1
0x001
0x000
0x000
0x000
Figure 17. SPI Protocol for N Address Same Data Write to All Devices
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5. SPI Protocol – continued
(12) Single Device, 1 Address Read (Read the 2 bytes data from Device #2)
B =
S =
0:
1:
Target device receive the data
Single
DevAddr[5:0] =
NumOfData[8:0] = -:
RW =
RegAddr[8:0] =
0x02:
Target device address
1 address access
Read
1:
0x003:
Address
SDI:
Transfer in the order of DevAddr[5:0] and RegAddr[8:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0] RW
RegAddr[8:0]
01 0x00
0x02
1
0x00
0x003
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
01 0x00
0x02
1
0x00
0x003
Read Data[15:0]
Data1[15:0]
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
01 0x00
0x02
1
0x00
0x003
0x02
0x0000
0x0000
0x0000
01 0x00
1
0x00
0x003
Data1[15:0]
Device #3 SDO
Device #1
Register
Device #2
Register
Device #3
Register
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x003 Data1
0x002
0x001
0x000
Figure 18. SPI Protocol for 1 Address Read from Device #2
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5. SPI Protocol – continued
(13) Single Device, N Address Read (Read the N x 2 bytes data from Device #2)
B =
S =
0:
0:
Target device receives the data
Multi
DevAddr[5:0] =
NumOfData[8:0] = 0x002:
RW =
0x02:
Target device address
2 address access
Read
1:
RegAddr[8:0] =
0x003:
Address
SDI:
Transfer in the order of DevAddr[5:0], NumOfData[8:0], and RegAddr[8:0].
SDO: Output the transferred data to the next device after SDI input by 2 bytes.
SCSB
SCLK
BS
DevAddr[5:0]
0x02
NumOfData[8:0] RW
RegAddr[8:0]
0x003
00 0x00
0x00
0x002
1
0x00
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x0000
00 0x00
0x02
0x00
0x002
1
0x00
0x003
0x002
Read Data[15:0]
Data1[15:0]
Device #2 SDO
(Device #3 SDI)
0x0000
0x0000
0x0000
00 0x00
0x02
0x00
1
0x00
0x003
0x002
Data2[15:0]
0x0000
0x0000
00 0x00
0x02
0x00
1
0x00
0x003
Data1[15:0]
Data2[15:0]
Device #3 SDO
Device #1
Device #2
Register
Device #3
Register
Register
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
0x007
0x006
0x005
0x004
0x007
0x006
0x005
0x004
0x003
0x002
0x001
0x000
Data2
0x003 Data1
0x002
0x001
0x000
Figure 19. SPI Protocol for N Address Read from Device #2
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5. SPI Protocol – continued
(14) Example (Write the data to Device #1 and Device #2)
Example of byte transfer for 2 devices in Cascade Connection.
Table 4. Byte transfer
B, S, DevAddr[5:0]
RW, NumOfData[8:0]
RegAddr[8:0]
2 bytes
2 bytes
2 bytes
Transfer setting
(2 bytes x 24 channels) x 8
Data
Data for the duty setting of Duty matrix switch x 2 devices
= 768 bytes
Dummy byte
for multi device transfer
SUM
2 bytes
776 bytes
DevAddr[5:0]
0x00
0x3F
NumOfData[8:0]
RegAddr[8:0]
48 bytes : LEDCH1 to LEDCH24 data for PGATE1 of Device #1
device #1
device #1
device #1
device #1
DTYCNT101
10
0
0x00
Number of
0x0C0 0 0x00 0x010
DTYCNT102
DTYCNT123
DTYCNT124
RegAddr of
transferred byte
for each device
DTYCNT101
Dummy byte
0x0000
48 bytes : LEDCH1 to LEDCH24 data for PGATE8 of Device #2
device #2
device #2
device #2
DTYCNT801
device #2
DTYCNT823
DTYCNT824
DTYCNT802
Figure 20. Transfer Byte Number for Multi Access
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Functions of Logic Block - continued
6. Register Map
Address
0x000
0x001
0x002
0x003
0x005
0x006
0x007
0x008
0x009
0x00A
0x00B
0x00C
0x010
0x011
to
Register Name
SRSST
TURNONWAIT
SSMASK
ERRMASK
SYSCONFIG 1
SYSCONFIG 2
SYSCONFIG 3
SYSCONFIG 4
LEDENL
LEDENM
LEDENU
GDLY
DTYCNT101
DTYCNT102
to
Description
Software reset and soft start time
Wait time after turn on
Soft start mask time
Error output mask time
System config 1
System config 2
System config 3
System config 4
Enable of LEDCH1 to LEDCH8
Enable of LEDCH9 to LEDCH16
Enable of LEDCH17 to LEDCH24
Global delay for all channel
PWM duty setting of LEDCH1 for PGATE1
Section
Here
Here
Here
Here
Here
Here
Here
Here
Here
Here
Here
Here
Here
PWM duty setting of LEDCH2 for PGATE1
to
-
DTYCNT823
DTYCNT824
DLY01
PWM duty setting of LEDCH23 for PGATE8
PWM duty setting of LEDCH24 for PGATE8
Delay setting of LEDCH1
Delay setting of LEDCH2
to
0x0CD
0x0CF
0x0D0
0x0D1
to
-
Here
DLY02
to
-
DLY23
DLY24
IREV10102
IREV10304
to
Delay setting of LEDCH23
Delay setting of LEDCH24
Current revision of LEDCH1 and LEDCH2 for PGATE1
Current revision of LEDCH3 and LEDCH4 for PGATE1
0x0E6
0x0E7
0x0E8
0x0E9
to
-
Here
to
-
IREV82122
Current revision of LEDCH21 and LEDCH22 for PGATE8
0x146
0x147
0x148
0x149
0x14A
to
IREV82324
ERLSH1L
ERLSH1H
ERLSH2L
to
Current revision of LEDCH23 and LEDCH24 for PGATE8
Error status of LED1 to LED16 short detection for PGATE1
Error status of LED17 to LED24 short detection for PGATE1
Error status of LED1 to LED16 short detection for PGATE2
to
-
Here
Here
-
ERLSH7H
Error status of LED17 to LED24 short detection for PGATE7
0x155
0x156
0x157
0x158
0x159
0x15A
to
ERLSH8L
ERLSH8H
ERLOP1L
ERLOP1H
ERLOP2L
to
Error status of LED1 to LED16 short detection for PGATE8
Error status of LED17 to LED24 short detection for PGATE8
Error status of LED1 to LED16 open detection for PGATE1
Error status of LED17 to LED24 open detection for PGATE1
Error status of LED1 to LED16 open detection for PGATE2
to
-
-
Here
Here
-
ERLOP7H
Error status of LED17 to LED24 open detection for PGATE7
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
ERLOP8L
ERLOP8H
EROTHER
ERLEDL
ERLEDH
ERPGSH
Error status of LED1 to LED16 open detection for PGATE8
Error status of LED17 to LED24 open detection for PGATE8
Other error status
Adjacent LEDCH1 to LEDCH16 short detection
Adjacent LEDCH17 to LEDCH24 short detection
PGATE VIN/GND short detection
-
-
Here
Here
Here
Here
As for the register update timing, there are 4 kinds of timing as following.
Type 1. Updated to the newest data immediately when the data is written.
Type 2. Updated to the newest data at the next VSYNC. (Rising edge trigger, after the data is written.)
Type 3. Updated to the newest data at the next VSYNC and GDLY.
Type 4. Updated to the newest data at the next PWM timing. (Rising edge trigger of VSYNC, then rising edge trigger of
PWM after the data is written.)
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Functions of Logic Block – continued
7. Description of Registers
The writing register annotated “-” is not valid.
Address 0x000: SRSST
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
-
0
Bit[6]
0
Bit[5]
SSTIM[2:0]
1
Bit[4]
Bit[3]
-
0
Bit[2]
-
0
Bit[1]
-
0
Bit[0]
SWRST
0
1
[Read / Write] Initial value: 0x0030 Update: Immediately
The register data is updated immediately when the new data is written.
SWRST is Write-only register.
Bit[6:4] SSTIM
SSTIM[2:0] is the register for setting the soft start time. It sets how the FBDAC[7:0] code changes with HSYNC.
Table 5. Soft Start Time / 1 count
SSTIM[2:0]
Count Up Time
128 HSYNC
256 HSYNC
512 HSYNC
1024 HSYNC
2048 HSYNC
4096 HSYNC
6144 HSYNC
8192 HSYNC
0
1
2
3
4
5
6
7
Bit[0] SWRST
SWRST is available when HSYNC is available, because this function uses HSYNC clock.
If SWRST = 1 is written, wait for more than 10 HSYNC pulses before accessing other registers.
Table 6. Software Reset
SWRST
Software Reset
Normal
Reset (return to ‘0’ automatically)
0
1
Address 0x001: TURNONWAIT
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
TURNONWAIT[7:0]
0
Bit[3]
Bit[2]
Bit[1]
Bit[0]
0
1
0
0
[Read / Write] Initial value: 0x0004 Update: VSYNC
The register data is updated at the next VSYNC signal rising edge after the data is written.
The mask time of PWM output is set by counting the number of VSYNC pulses.
This register value is updated at the 3rd VSYNC pulse after reset is released (UVLO, SWRST). If this register needs to be
updated, update this register before the 3rd VSYNC pulse. Write data higher than 0x04.
푡푇푈ꢌ푁푂푁푊퐴ꢀ푇 = ꢅꢍ푅ꢎꢏꢎꢐꢁ퐼ꢅ[7: 0]/푓
[푠]
(Except for waiting time until 1st VSYNC pulse)
ꢆ푆ꢑ푁퐶
Table 7. Maximum Turn on Wait Time
fVSYNC[Hz]
60
120
2,125
240
480
Maximum TURNONWAIT Time [ms]
4,250
1,062.5
531.3
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7. Description of Registers – continued
Address 0x002: SSMASK
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
1
Bit[4]
SSMASK[7:0]
1
Bit[3]
Bit[2]
Bit[1]
Bit[0]
1
1
0
0
[Read / Write] Initial value: 0x003C Update: VSYNC
The register data is updated at the next VSYNC signal rising edge after the data is written. Set the value higher than 0x02.
The mask time of ERROR detection is set by counting the number of VSYNC pulses after TURNONWAIT time.
푡푆푆푀퐴푆퐾 = ꢒꢒꢓꢁꢒꢔ[7: 0]/푓
[푠]
after TURNONWAIT time
(Except for waiting time until 1st VSYNC pulse)
ꢆ푆ꢑ푁퐶
Table 8. Maximum Soft Start Mask Time
fVSYNC[Hz]
60
120
240
480
Maximum SSMASK Time [ms]
4,250
2,125
1,062.5
531.3
Address 0x003: ERRMASK
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
1
Bit[4]
ERRMASK[7:0]
0
Bit[3]
Bit[2]
Bit[1]
Bit[0]
1
0
0
1
[Read / Write] Initial value: 0x0029 Update: VSYNC
The register data is updated at the next VSYNC signal rising edge after the data is written.
Range: over 0x03 (Set for 0x00 to 0x02 also lead to 0x03, register value = writing value)
ERROR mask time is set by counting the number of HSYNC pulses.
푡퐸ꢌꢌ푀퐴푆퐾 = ꢂ푅푅ꢓꢁꢒꢔ[7:0]/푓
[푠]
퐻푆ꢑ푁퐶
If the capacitance of LEDCHn pin CLEDCH is connected, the transient response is affected. Please set the value
considering the time margin of LED short detection.
(Example) ERRMASK = 3: mask 3 or 4 clock (PWMn = HIGH and error signal)
It reset ERRMASK counter when PWMn = LOW. Refer to HSYNC equation about the relationship between HSYNC
frequency and VSYNC frequency.
Table 9. Maximum Error Mask Time
fHSYNC[Hz]
1,996,800
127.7
3,993,600
63.8
7,987,200 15,974,400
31.9 15.9
Maximum ERRMASK Time [μs]
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7. Description of Registers – continued
Address 0x005: SYSCONFIG1
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
-
0
Bit[10]
Bit[9]
MULSEL[1:0]
0
Bit[8]
0
-
0
-
0
-
0
-
0
-
0
Bit No.
Name
Initial value
Bit[7]
PGSRCNT[1:0]
0
Bit[6]
0
Bit[5]
-
0
Bit[4]
-
0
Bit[3]
-
0
Bit[2]
-
0
Bit[1]
PRCEN
0
Bit[0]
PRCSEL
0
[Read / Write] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the new data is written.
Bit[9:8] MULSEL[1:0]
Line Switch Controller setting of external PMOS gate. Refer to PWM Delay and ON Duty setting procedure each
dimming mode. As for the HSYNC frequency for MULSEL, Refer to the register PWMFREQ. This register
prohibits changing the setting during dimming.
Table 10. Line Switch Controller of External PMOS Gate
MULSEL[1:0]
Line Switch Controller
8-line switch controller
4-line switch controller
6-line switch controller
6-line switch controller
0x0
0x1
0x2
0x3
Bit[7:6] PGSRCNT[1:0]
Fall Slew Rate Control of external PMOS gate.
Table 11. Fall Slew Rate of External PMOS Gate
PGSRCNT[1:0]
Slew Rate
0x0
0x1
0x2
0x3
100 Ω pull down
1.4 kΩ pull down
10 kΩ pull down
100 kΩ pull down
Bit[1] PRCEN
According to setting of PRCSEL, pull up charge ‘VINSW – 1.2 V’ to the LEDCHn pin.
Table 12. Pull up charge Enable Setting
PRCEN
Pull up charge Enable Setting
Pull up charge disable
0
1
Pull up charge enable
(Note) It is necessary to be careful about reverse pressure resistance.
Bit[0] PRCSEL
Pull up charge period setting of the LEDCHn pin.
Table 13. Pull up charge Period
Pull up charge Period Setting
PRCSEL
0
1
Pull up charge during PWM OFF
Pull up charge during all PGATE OFF
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7. Description of Registers – continued
Address 0x006: SYSCONFIG2
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
LSHEXE
0
Bit[12]
0
Bit[11]
FBREF[2:0]
0
Bit[10]
0
Bit[9]
Bit[8]
1
-
0
-
0
SMPTIM[1:0]
0
Bit[1]
0
Bit No.
Name
Initial value
Bit[7]
PWMFREQ[1:0]
0
Bit[6]
0
Bit[5]
-
0
Bit[4]
LSHEXT
0
Bit[3]
LOPEN
0
Bit[2]
LSHEN
0
Bit[0]
LEDSH[1:0]
0
[Read / Write] Initial value: 0x0100 Update: Immediately
The register data is updated immediately when the new data is written.
This register should be set before PWM dimming. Do not change this register value during dimming.
Bit[13] LSHEXE
Short check sequence of adjacent LEDCHn pin is executed after TURNONWAIT time if LSHEXE = 1 is written
before TURNONWAIT time.
Table 14. Short Check of Adjacent LEDCHn Pin
LSHEXE
Short Check Execution
0
1
No operation
Execute short check sequence (return to ‘0’ automatically)
Bit[12:10] FBREF
Feedback reference voltage of FB control block.
Table 15. Error Reference of FB Control Block
Feedback Reference
Voltage
FBREF[2:0]
0x0
0x1
0x2
0x3
other
0.45 V
0.53 V
0.60 V
0.75 V
0.90 V
Bit[9:8] SMPTIM
The LED channel voltage sampling timing, after PWMn goes from LOW to HIGH. It is necessary to set PWM
duty register more than 8 at the dimming.
Table 16. Sampling Time
LED Channel Voltage
SMPTIM[1:0]
Sampling Time
0x0
0x1
0x2
0x3
8 HSYNC
16 HSYNC
32 HSYNC
64 HSYNC
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Address 0x006: SYSCONFIG2 – continued
Bit[7:6] PWMFREQ (Please update this register until the 4th VSYNC pulse from RESET release.)
The register PWMFREQ defines the number of times PWM turns on during a VSYNC pulse. So the proper HSYNC
pulse number is almost proportional to the PWMFREQ. More specifically, considering the NOOVLAP1 and
NOOVLAP2 timing, which is the deadtime of PMOSm (m = 1 to 8), the necessary HSYNC pulse number is
expressed by the following equation.
푓
= 푓
× (4096 + ꢕ + 푏) × 푐 × 2(푃푊푀퐹ꢌ퐸푄[ꢇ:ꢖ])
ꢆ푆ꢑ푁퐶
퐻푆ꢑ푁퐶
NOOVLAP1 register 0: a = 32, 1: a = 64, 2: a = 128, 3: a = 256
NOOVLAP2 register 0: b = 32, 1: b = 64, 2: b = 128, 3: b = 256
MULSEL register 0: c = 8, 1: c = 4, 2: c = 6, 3: c = 6
The ratio fHSYNC/fVSYNC is noted in the Table 17. Here is the example of the register MULSEL = 0 (the case c = 8 is
substituted in the above formula)
Table 17. The example of the ratio fHSYNC/fVSYNC (the register MULSEL = 0)
NOOVLAP2
PWMFREQ[1:0] NOOVLAP1
0
1
2
3
33,280
33,536
34,048
35,072
66,560
67,072
68,096
70,144
133,120
134,144
136,192
140,288
266,240
268,288
272,384
280,576
33,536
33,792
34,304
35,328
67,072
67,584
68,608
70,656
134,144
135,168
137,216
141,312
268,288
270,336
274,432
282,624
34,048
34,304
34,816
35,840
68,096
68,608
69,632
71,680
136,192
137,216
139,264
143,360
272,384
274,432
278,528
286,720
35,072
35,328
35,840
36,864
70,144
70,656
71,680
73,728
140,288
141,312
143,360
147,456
280,576
282,624
286,720
294,912
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
The example of HSYNC pulse number is shown as VSYNC is 60 Hz, 120 Hz, 240 Hz and 480 Hz.
The maximum HSYNC frequency is 20 MHz. (Refer to frequency range of electric characteristics)
Table 18. HSYNC Frequency and PWM Frequency (NOOVLAP1 = NOOVLAP2 = 0, MULSEL = 0) (Example)
VSYNC Frequency [Hz]
PWMFREQ [1:0]
60
60
120
120
240
480
480
15,974,400
240
0
1
2
3
1,996,800
120
3,993,600
240
7,987,200
480
960
-
1,920
-
3,840
-
3,993,600
240
7,987,200
480
15,974,400
960
7,987,200
480
15,974,400
15,974,400
960
-
1,920
-
-
(Note) Upper: PWM frequency Lower: HSYNC frequency “-“ is not acceptable to set this value in PWMFREQ register
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Address 0x006: SYSCONFIG2 – continued
Bit[4] LSHEXT
External pin or internal register setting for LED short protection voltage.
Table 19. Setting for LED Short Protection Voltage
LSHEXT
Setting for LED Short Protection
Internal register LEDSH[1:0] setting
External LSPSET pin setting
0
1
As LSHEXT = 0, please connect the LSPSET pin to GND.
As LSHEXT = 1, please set the LED short protection voltage VLSPSETDET by the following equation.
푉
= 10 × 푉
퐿푆푃푆퐸푇
퐿푆푃푆퐸푇퐷퐸푇
Where VLSPSET is the LSPSET pin voltage (0.5 V to 1.8 V)
Bit[3] LOPEN
This register enables/disables LED Open Error detection.
Table 20. Enable Setting for LED Open Error Detection of LEDCHn
LOPEN
Enable Setting
0
1
LED Open Error detection is not available
LED Open Error detection is available
Bit[2] LSHEN
This register enables/disables LED Short Error detection.
Table 21. Enable Setting for LED Short Error Detection of LEDCHn
LSHEN
Enable Setting
0
1
LED Short Error detection is not available
LED Short Error detection is available
Bit[1:0] LEDSH[1:0]
This register controls the detection voltage for LED Short Error.
Table 22. LED Short Error Detection Voltage Setting
LEDSH[1:0]
Detection Voltage[V]
0
1
2
3
3.0 V
6.0 V
9.0 V
12.0 V
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7. Description of Registers – continued
Address 0x007: SYSCONFIG3
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
VINSW
OVPEN
0
Bit[9]
Bit[8]
-
-
-
-
-
VINSWOVPREF[1:0]
Initial value
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
NOOVLAP1[1:0]
0
Bit[6]
0
Bit[5]
NOOVLAP2[1:0]
0
Bit[4]
Bit[3]
Bit[2]
Bit[1]
ERRCLR
0
Bit[0]
ERRLAT
0
AUTOCLR AUTOOFF
0
0
0
[Read / Write] Initial value: 0x0000 Update: Immediately or VSYNC
The data in registers (VINSWOVPEN, VINSWOVPREF, AUTOCLR, AUTOOFF and ERRCLR) are updated immediately when
the new data is written.
The data in registers (NOOVLAP1, NOOVLAP2, ERRLAT) are updated at the next VSYNC signal rising edge after the data
is written. The data in registers (NOOVLAP1, NOOVLAP2) should be set before PWM dimming.
AUTOCLR and ERRCLR are Write-only registers.
Bit[10] VINSWOVPEN
This register enables/disables Over Voltage Detection of the VINSW pin.
Table 23. Enable Setting for Over Voltage Detection of the VINSW pin
VINSWOVPEN
Enable Setting
0
1
VINSW Over Voltage detection is not available
VINSW Over Voltage detection is available
Bit[9:8] VINSWOVPREF[1:0]
Detection voltage for over voltage of the VINSW pin.
Table 24. Detection Voltage Setting of the VINSW pin
VINSWOVPREF[1:0]
Detection Voltage[V]
8.0 V
0
1
2
3
12.0 V
16.0 V
18.0 V
Bit[7:6] NOOVLAP1 (Update this register until 4th VSYNC pulse from RESET release.)
None overlap time setting 1. Refer to None overlap function.
As for the HSYNC frequency for NOOVLAP1, please refer to the register PWMFREQ.
Table 25. None Overlap Time Setting1
NOOVLAP1[1:0]
None Overlap Time Setting 1
32 HSYNC
0
1
2
3
64 HSYNC
128 HSYNC
256 HSYNC
Bit[5:4] NOOVLAP2 (Update this register until 4th VSYNC pulse from RESET release.)
None overlap time setting 2. Refer to None overlap function.
As for the HSYNC frequency for NOOVLAP2, please refer to the register PWMFREQ.
Table 26. None Overlap Time Setting2
NOOVLAP2[1:0]
None Overlap Time Setting 2
32 HSYNC
0
1
2
3
64 HSYNC
128 HSYNC
256 HSYNC
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Address 0x007: SYSCONFIG3 – continued
Bit[3] AUTOCLR
AUTOCLR is available in AUTOOFF = 1 setting.
Table 27. AUTOOFF Condition
AUTOOFF Condition
AUTOCLR
0
No Operation
AUTOOFF condition in LEDCHn output is released
(return to ‘0’ automatically)
1
Bit[2] AUTOOFF
Control ON/OFF condition in LEDCHn output. AUTOOFF condition is latched until released by UVLO or
AUTOCLR.
Table 28. ON/OFF Condition of LEDCHn Output
AUTOOFF
ON/OFF Condition
0
1
LEDCHn does not turn OFF automatically after error is detected
LEDCHn turn OFF automatically after error is detected
Bit[1] ERRCLR
ERRCLR is available in ERRLAT = 1 setting.
Table 29. Clear Error Register
Clear Error Register
ERRCLR
0
No Operation
Clear error register and return Hi-z in FAILB output when ERRLAT = 1
(returns to ‘0’ automatically)
1
Bit[0] ERRLAT
Control error register and FAILB output when error is detected.
Table 30. Error Detection Function
ERRLAT
Error Detection Function
0
1
Error register and FAILB output return to initial condition when error is released
Error register and FAILB output is retained until ERRCLR = 1 is written
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7. Description of Registers – continued
Address 0x008: SYSCONFIG4
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
-
0
Bit[6]
0
Bit[5]
DACUP[2:0]
0
Bit[4]
Bit[3]
DACDN[1:0]
0
Bit[2]
Bit[1]
-
0
Bit[0]
MSMODE
0
1
0
[Read / Write] Initial value: 0x0010 Update: Immediately
The register data is updated immediately when the new data is written.
Bit[6:4] DACUP[2:0]
DACUP[2:0] is register for setting the FB DAC's count up step after soft start.
Table 31. FB DAC Code Count Up Step
FB DAC Code Count
DACUP[2:0]
Up Step
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
Bit[3:2] DACDN[1:0]
DACDN[1:0] is register for setting the FB DAC's count down step after soft start.
Table 32. FB DAC Code Count Down Step
FB DAC Code Count
DACDN[1:0]
Down Step
0
1
2
3
-1
-2
-3
-4
Bit[0] MSMODE
MSMODE is register for setting of FB DAC’s controller mode or target mode.
Table 33. FB DAC Mode Setting
MSMODE
FB DAC Mode Setting
Controller mode
Target mode
0
1
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7. Description of Registers – continued
Address 0x009: LEDENL
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
1
Bit[6]
1
Bit[5]
1
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
LEDEN[7:0]
1
1
1
1
1
[Read / Write] Initial value: 0x00FF Update: Immediately
Address 0x00A: LEDENM
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
1
Bit[6]
1
Bit[5]
1
Bit[4]
LEDEN[15:8]
1
Bit[3]
Bit[2]
Bit[1]
Bit[0]
1
1
1
1
[Read / Write] Initial value: 0x00FF Update: Immediately
Address 0x00B: LEDENU
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
Initial value
0
0
0
0
0
0
0
0
Bit No.
Name
Initial value
Bit[7]
1
Bit[6]
1
Bit[5]
1
Bit[4]
LEDEN[23:16]
1
Bit[3]
Bit[2]
Bit[1]
Bit[0]
1
1
1
1
[Read / Write] Initial value: 0x00FF Update: Immediately
The register data is updated immediately when the new data is written.
These registers (0x009, 0x00A, 0x00B) enable or disable each LED channel. If ‘0’ is set in LEDEN[n-1] (n = 1 to 24), the
channel n is not available. LEDCHn current is turned off, and the status of LED Open/Short Detection and FAILB output are
not affected by LEDCHn since disabled channels do not detect LED Open/Short Error.
Table 34. LEDCHn Enable Setting
LEDCHn current control,
LEDEN[n-1]
LED Open/Short Detection,
FAILB output for LEDCHn
0
1
Disable
Enable
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7. Description of Registers – continued
Address 0x00C: GDLY
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
0
Bit[8]
0
-
0
-
0
-
0
-
0
GDLY[11:8]
0
Bit[3]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
Bit[1]
0
Bit[0]
0
GDLY[7:0]
0
[Read / Write] Initial value: 0x0000 Update: VSYNC
GDLY is the delay time counted from VSYNC rising edge to PGATE1 fall-edge.
The register data is updated at the next VSYNC signal rising edge after the data is written.
MULSEL register 0: c = 8, 1: c = 4, 2: c = 6, 3: c = 6
Table 35. Global Delay Setting
GDLY[11:0]
GDLY Total Clock Number (clock width @HSYNC)
0x000
0x001
0x002
0x003
to
0xFFC
0xFFD
0xFFE
0xFFF
NGDLYa = 5 clock to 6 clock from rise-edge of VSYNC
NGDLYa + 1 x c x 2(PWMFREQ[1:0])
NGDLYa + 2 x c x 2(PWMFREQ[1:0])
NGDLYa + 3 x c x 2(PWMFREQ[1:0])
to
NGDLYa + 4092 x c x 2(PWMFREQ[1:0])
NGDLYa + 4093 x c x 2(PWMFREQ[1:0])
NGDLYa + 4094 x c x 2(PWMFREQ[1:0])
NGDLYa + 4095 x c x 2(PWMFREQ[1:0])
(Note) This count starts from VSYNC rising edge.
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7. Description of Registers – continued
Address 0x010: DTYCNT101
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
0
Bit[8]
0
-
0
-
0
-
0
-
0
DTY101[11:8]
0
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
DTY101[7:0]
0
Bit[3]
0
Bit[2]
0
Bit[1]
0
Bit[0]
0
[Read / Write] Initial value: 0x0000 Update: PWM
The register data is updated at the next PWM signal rising edge after the data is written.
Table 36. PWM Duty Setting
DTYmn[11:0]
LED Pulse Width
0x000
0x001
0x002
0x003
0x004
to
0 HSYNC clock width
1 HSYNC clock width
2 HSYNC clock width
3 HSYNC clock width
4 HSYNC clock width
to
0xFFC
0xFFD
0xFFE
0xFFF
4,092 HSYNC clock width
4,093 HSYNC clock width
4,094 HSYNC clock width
4,095 HSYNC clock width
Address 0x011 to 0x0CF: DTYCNT102 to DTYCNT824
These registers are used to set the PWM pulse width. The setting procedure is the same as that for LEDCH1 with Address
set to 0x010.
Address
Description
0x010 to 0x027
0x028 to 0x03F
0x040 to 0x057
0x058 to 0x06F
0x070 to 0x087
0x088 to 0x09F
0x0A0 to 0x0B7
0x0B8 to 0x0CF
PWM duty register for PGATE1
PWM duty register for PGATE2
PWM duty register for PGATE3
PWM duty register for PGATE4
PWM duty register for PGATE5
PWM duty register for PGATE6
PWM duty register for PGATE7
PWM duty register for PGATE8
Address 0x0D0: DLY01
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
0
Bit[8]
0
-
0
-
0
-
0
-
0
DLY01[11:8]
0
Bit[3]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
Bit[1]
0
Bit[0]
0
DLY01[7:0]
0
[Read / Write] Initial value: 0x0000 Update: VSYNC+GDLY
The register data is updated at the next VSYNC+GDLY timing after the data is written.
DLY01 is the delay time which starts to count after NOOVLAP2.
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Address 0x0D0: DLY01 (PWM Delay setting register) – continued
Table 37. Delay Setting of PWM Output
DLY01[11:0]
DLY01 Total Clock Number (clock width @HSYNC)
0x000
0x001
0x002
0x003
to
0
1
2
3
to
0xFFC
0xFFD
0xFFE
0xFFF
4092
4093
4094
4095
(Note) This count starts from NOOVLAP2 finish point.
Address 0x0D1 to 0x0E7: DLY02 to DLY24
These registers are used to set the delay width of PWM for LEDCH2 to LEDCH24. The setting procedure is the same as that
for LEDCH1 with address set to 0x0D0.
Address 0x0E8: IREV10102
Bit No
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
1
Bit[9]
1
Bit[8]
1
-
0
-
0
IREV102[5:0]
1
Bit[5]
1
1
Bit[4]
1
1
Bit[3]
1
Bit No
Name
Initial value
Bit[7]
-
0
Bit[6]
-
0
Bit[2]
Bit[1]
1
Bit[0]
1
IREV101[5:0]
1
[Read / Write] Initial value: 0x3F3F Update: immediately
IREV101 is used with current revision of LEDCH1 of PGATE1 from 50 % to 100 %.
IREV102 is used with current revision of LEDCH2 of PGATE1 from 50 % to 100 %.
IREV register prohibit changing the setting during dimming.
These LED current registers should be updated before LED turns on. The dynamic update during the dimming may affect to
the DCDC feedback.
Table 38. Current Revision Setting of LEDCHn
IREV101[5:0]
Current Revision Setting
0x3F
0x3E
0x3D
0x3C
to
ILEDDC x 100 %
ILEDDC x 99.2 %
ILEDDC x 98.4 %
ILEDDC x 97.6 %
to
0x03
0x02
0x01
0x00
ILEDDC x 52.8 %
ILEDDC x 52.0 %
ILEDDC x 51.2 %
ILEDDC x 50.4 %
[
]
(퐼푅ꢂ푉 5: 0 + 64)
ꢊ푛
퐼퐿퐸퐷퐴퐿퐿 = 퐼퐿퐸퐷퐷퐶
Address 0x0E9 to 0x147: IREVmn
×
[푚ꢁ]
127
This register is used to make setting of current revision for LEDCH3 to LEDCH24 of PGATE1 and LEDCH1 to LEDCH24 of
PGATE2 to PGATE8. The setting procedure is the same as that for LEDCH1 of PGATE1 with address set to 0x0E8.
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7. Description of Registers – continued
Address 0x148: ERLSH1L
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
ERLSH1 [15:8]
Bit[11]
0
Bit[10]
Bit[9]
0
Bit[8]
0
0
Bit[7]
0
0
Bit[6]
0
0
Bit[5]
0
0
Bit[4]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[3]
Bit[1]
0
Bit[0]
0
ERLSH1 [7:0]
0
[Read] Initial value: 0x0000 Update: Immediately
Address 0x149: ERLSH1H
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Initial value
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
ERLSH1 [23:16]
0
Bit[3]
0
Bit[2]
0
Bit[1]
0
Bit[0]
0
[Read] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the data is written.
These registers (0x148, 0x149) correspond to the status of LED Short Detection of PGATE1 of LED1 to LED24.
Table 39. Status of LED Short Detection
ERLSH1[n-1]
Status
Normal
0
1
Detected LED Short Error(Note 1)
(Note 1) ERRLAT = 0: ERLSHm[n-1] (m = 1 to 8, n = 1 to 24) turns 0, if LED Short Error is released or LEDEN[n-1] = 0 is set or LSHEN = 0 is set.
ERRLAT = 1: ERLSHm[n-1] turns 0, if ERRCLR = 1 is set.
Address 0x14A to 0x157: ERLSHm[n-1]
These registers (0x14A to 0x157) correspond to the status of LED Short Detection of PGATE2 to PGATE8 of LED1 to
LED24. The setting procedure is the same as that for LED1 to LED24 of PGATE1 with address set to 0x148 and 0x149.
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7. Description of Registers – continued
Address 0x158: ERLOP1L
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
0
Bit[10]
Bit[9]
0
Bit[8]
0
ERLOP1[15:8]
0
Bit[7]
0
0
Bit[6]
0
0
Bit[5]
0
0
Bit[4]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[3]
Bit[1]
0
Bit[0]
0
ERLOP1[7:0]
0
[Read] Initial value: 0x0000 Update: Immediately
Address 0x159: ERLOP1H
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Initial value
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
ERLOP1[23:16]
0
Bit[3]
0
Bit[2]
0
Bit[1]
0
Bit[0]
0
[Read] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the data is written.
These registers (0x158, 0x159) correspond to the status of LED Open Detection of PGATE1 of LED1 to LED24.
Table 40. Status of LED Open Detection
ERLOP1 [n-1]
Status
Normal
0
1
Detected LED Open Error(Note 2)
(Note 2) ERRLAT = 0: ERLOPm[n-1] (m = 1 to 8, n = 1 to 24) turns 0,if LED Open Error is released or LEDEN[n-1] = 0 is set or LOPEN = 0 is set.
ERRLAT = 1: ERLOPm[n-1] turns 0, if ERRCLR = 1 is set.
Address 0x15A to 0x167: ERLOPm[n-1]
These registers (0x15A to 0x167) correspond to the status of LED Short Detection of PGATE2 to PGATE8 of LED1 to
LED24. The setting procedure is the same as that for LED1 to LED24 of PGATE1 with Address set to 0x158 and 0x159.
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7. Description of Registers – continued
Address 0x168: EROTHER
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Initial value
Bit No.
Name
Bit[7]
Bit[6]
Bit[5]
EXENG
0
Bit[4]
EXEOK
0
Bit[3]
ERISET
OPEN
0
Bit[2]
ERISET
OCP
0
Bit[1]
Bit[0]
ERVINSW
OVP
-
-
-
0
0
0
0
Initial value
[Read] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the new data is written.
Bit[5]: EXENG
EXENG register correspond to the status that short check sequence of adjacent LEDCHn is not executed.
Table 41. Status of Short Check Sequence NG
EXENG
Status
Normal
0
1
Short check sequence of adjacent LEDCHn is not executed
Bit[4]: EXEOK
EXEOK register correspond to the status that short check sequence of adjacent LEDCHn is executed.
Table 42. Status of Short Check Sequence OK
EXEOK
Status
Normal
0
1
Short check sequence of adjacent LEDCHn is executed
Bit[3]: ERISETOPEN
ERISETOPEN register correspond to the status of ISET Open Detection.
Table 43. Status of ISET Open Detection
ERISETOPEN
Status
Normal
0
1
Detected ISET Open Error(Note 3)
Bit[2]: ERISETOCP
ERISETOCP register correspond to the status of ISET Over Current Detection.
Table 44. Status of ISET Over Current Detection
ERISETOCP
Status
Normal
0
1
Detected ISET Over Current Error(Note 3)
Bit[0]: ERVINSWOVP
ERVINSWOVP register correspond to the status of VINSW Over Voltage Detection.
Table 45. Status of VINSW Over Voltage Detection
ERVINSWOVP
Status
Normal
0
1
Detected VINSW Over Voltage Error(Note 3)
(Note 3) ERRLAT = 0: ERISETOPEN, ERISETOCP and ERVINSWOVP turns 0, if error condition is released. ERRLAT = 1: ERISETOPEN, ERISETOCP
and ERVINSWOVP turns 0, if ERRCLR = 1 is set.
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7. Description of Registers – continued
Address 0x169: ERLEDL
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
0
Bit[10]
Bit[9]
0
Bit[8]
0
ERLED[15:8]
0
Bit[7]
0
0
Bit[6]
0
0
Bit[5]
0
0
Bit[4]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[3]
Bit[1]
0
Bit[0]
0
ERLED[7:0]
0
[Read] Initial value: 0x0000 Update: Immediately
Address 0x16A: ERLEDH
Bit No.
Name
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
-
Bit[8]
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Initial value
Bit No.
Name
Initial value
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
ERLED[23:16]
0
Bit[3]
0
Bit[2]
0
Bit[1]
0
Bit[0]
0
[Read] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the data is written.
These registers (0x169, 0x16A) correspond to the status of Short Detection of adjacent LEDCHn.
Table 46. Status of Short Detection of Adjacent LEDCHn
ERLED[n-1]
(n = 1 to 24))
Status
0
1
Normal
Detected Short Detection Error of Adjacent LEDCHn(Note 4)
Address 0x16B: ERPGSH
Bit No.
Name
Initial value
Bit[15]
Bit[14]
Bit[13]
Bit[12]
ERPGVINSH[7:0]
Bit[11]
Bit[10]
Bit[9]
0
Bit[8]
0
0
Bit[7]
0
0
Bit[6]
0
0
Bit[5]
0
0
0
Bit[3]
0
0
Bit[2]
0
Bit No.
Name
Initial value
Bit[4]
ERPGGSH[7:0]
0
Bit[1]
0
Bit[0]
0
[Read] Initial value: 0x0000 Update: Immediately
The register data is updated immediately when the data is written.
Bit[15:8]: ERPGVINSH[7:0]
This register correspond to the status of Short Detection between the PGATEm pin and the VINSW pin.
Table 47. Status of Short Detection between the PGATEm pin and the VINSW pin
ERPGVINSH[m-1]
(m = 1 to 8)
Status
0
1
Normal
Detected Short Error to the VINSW pin(Note 4)
Bit[7:0]: ERPGGSH[7:0]
This register correspond to the status of Short Detection between the PGATEm pin and the GND.
Table 48. Status of Short Detection between the PGATEm pin and GND
ERPGGSH[m-1]
(m = 1 to 8)
Status
0
1
Normal
Detected Short Error to GND(Note 4)
(Note 4) ERLED[n-1], ERPGVINSH[m-1] and ERPGGSH[m-1] turn 0, if ERRCLR = 1 is set.
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Application Circuit Diagram
1. The Example of Basic Application
DC/DC
VCC
VINSW
BD94130MUF
BD94130EFV
VREG15
ISET
EN
SW8
PGATE8
LSPSET
FB
SW2
PGATE2
PGATE1
SUMFB
SW1
VIO
LEDCELL
LEDCELL
LEDCELL
SCSB
SDI
LEDCH24
LEDCH23
SCLK
LEDCELL
LEDCELL
LEDCELL
SDO
MCU
VSYNC
HSYNC
VIO
LEDCELL
LEDCELL
LEDCELL
FAILB
LEDCH1
TEST1
TEST2
GND
LGND
2. The Plural BD94130 Usage (the common SPI and the common DCDC)
DC/DC
VCC
VINSW
BD94130MUF
BD94130EFV
VREG15
ISET
EN
EN
SW8
PGATE8
LSPSET
FB
SW2
PGATE2
PGATE1
SUMFB
SW1
VIO
SCSB
SDI
LEDCELL
LEDCELL
LEDCELL
SCSB
SDI
LEDCH24
LEDCH23
SCLK
SCLK
SDO
LEDCELL
LEDCELL
LEDCELL
SDO
MCU
VSYNC
HSYNC
VSYNC
HSYNC
VIO
LEDCELL
LEDCELL
LEDCELL
FAILB
FAILB
LEDCH1
TEST1
TEST2
GND
LGND
VCC
VINSW
BD94130MUF
BD94130EFV
VREG15
ISET
EN
SW8
PGATE8
LSPSET
FB
SW2
PGATE2
PGATE1
SUMFB
SW1
VIO
LEDCELL
LEDCELL
LEDCELL
SCSB
SDI
LEDCH24
LEDCH23
SCLK
L
E
D
CE
L
L
L
E
D
CE
L
L
LEDCELL
SDO
VSYNC
HSYNC
L
E
D
CE
L
L
L
E
D
CE
L
L
LEDCELL
FAILB
LEDCH1
TEST1
TEST2
GND
LGND
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Timing Chart
1. Boot Sequence
(1) SPI Command Mode
VCCUVLO
VCCUVLO
VCC
[9]
[1]
VINSW
[2]
[8]
VIOUVLO
VIO
VIOUVLO
EN
[3]
[7]
VREG15UVLO
VREG15
VREG15UVLO
RESET= VCCUVLO or VIOUVLO or EN or VREG15UVLO or Register
RESET (internal)
VSYNC
HSYNC
[4]
[5]
[6]
SPI
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
LEDCHn current
status
TURNONWAIT
OFF
dimming
OFF
output disable
output disable
Enlarged view
Enlarged view
Enlarged view
Initial setting
Duty setting
SPI
OFF setting
SPI
SPI
Register SRSST
TURNONWAIT
LEDENL
Register DTYCNTmn
Register LEDENL
LEDENM
LEDENM
LEDENU
GDLY
SSMASK
ERRMASK
LEDENU
SYSCONFIG1
SYSCONFIG2
SYSCONFIG3
SYSCONFIG4
DTYCNTmn
DLYn
IREVmn
Figure 21. The Boot Sequence for SPI Command Mode
Turn ON Sequence
[1] Power on VCC and VCCUVLO is released. And power on VINSW.
[2] Power on VIO and VIOUVLO is released.
[3] After the EN pin is H, VREG15 turn on. The signal RESET is expressed by the following equation. After RESET
is released, the registers can be accessed.
RESET = VCCULVO or VIOUVLO or EN or VREG15UVLO or Register
[4] Set the initial registers until 4th VSYNC period from RESET release. 4th VSYNC period is adjustable by the
register TURNONWAIT[7:0]. During the state TURNONWAIT, the IC keeps LEDs off.
[5] The duty register DTYCNTmn are updated in every VSYNC period for dimming.
Turn OFF Sequence
[6] Set the register LEDENL, LEDENM and LEDENU registers to 0.
[7] VREG15 turn off after the EN pin is L. The registers cannot be accessed during RESET = L.
[8] Power off VIO and VIOUVLO is detected.
[9] Power off VINSW and VCC.
The first turn on and the last turn off are VCC. And the order of the VIO, EN can be exchanged.
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1. Boot Sequence – continued
(2) PWM Direct Control Mode (without SPI command)
VCCUVLO
VCCUVLO
VCC
[9]
[1]
VINSW
[2]
[8]
VIOUVLO
VIO
VIOUVLO
[7]
EN
[3]
VREG15UVLO
VREG15
VREG15UVLO
RESET= VCCUVLO or VIOUVLO or EN or VREG15UVLO or Register
RESET (internal)
TEST1
[4]
[5]
[6]
VSYNC
HSYNC
Low
High
Low
Low
SCSB
SCLK
SDI
LEDCHn current
TURNONMASK
counter
0x00
1
2
3
4
0xFF
PGATE1
PGATE2
・
・
・
PGATE8
TURNONWAIT
status
OFF
dimming
OFF
output disable
Figure 22. The boot Sequence for PWM Direct Control Mode
Turn ON Sequence
[1] Power on VCC and VCCUVLO is released. And power on VINSW.
[2] Power on VIO and VIOUVLO is released.
[3] After the EN pin is H, VREG15 turn on. The signal RESET is expressed by the following equation. After RESET
is released, the VSYNC signal becomes valid. And the TEST1 pin must be H.
RESET = VCCULVO or VIOUVLO or EN or VREG15UVLO or Register
[4] Until 4th VSYNC period from RESET release, the IC keeps LEDs off, as TURNONWAIT.
[5] Input PWM pulse to VSYNC for dimming. VSYNC signal can control LED current directly. PGATEm are all on.
Turn OFF Sequence
[6] Stop PWM dimming pulse input to VSYNC.
[7] VREG15 turn off after the EN pin is L.
[8] Power off VIO and VIOUVLO is detected.
[9] Power off VINSW and VCC.
The first turn on and the last turn off are VCC. And the order of the VIO, EN can be exchanged.
About PWM Direct Control Mode
If 8 HSYNC clocks counts, PWM Direct Control Mode is shifted to SPI Command Mode.
Even if error is detected, LED keeps ON, and FAILB signal is still HIGH.
RESET (internal)
HSYNC
BITCNT[3:0]
(internal signal)
0
1
2
3
4
5
6
7
8
0
operating mode
PWM Direct Control
SPI Command Mode
PWM Direct Control
Figure 23. SPI Command Mode / PWM Direct Control Mode
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Timing Chart – continued
2. Matrix Operation and PWM Dimming Setting
(1) Matrix Operation Setting (the line number of gate controller)
The register MULSEL[1:0] controls the number of active PGATE as shown in Figure 24. The unused PGATE5 to PGATE8
asserts always OFF. The selectable gate number is 4, 6, and 8. The necessary HSYNC clock number is depend on the
register MULSEL[1:0].
8 Line Gate controller (MULSEL[1:0] = 0x0)
4 Line Gate Controller (MULSEL[1:0] = 0x1)
VSYNC
VSYNC
GDLY
GDLY
PGATE1
PGATE1
PGATE2
PGATE3
PGATE2
PGATE3
PGATE4
PGATE5
PGATE4
PGATE5
PGATE6
PGATE7
PGATE6
PGATE7
PGATE8
PGATE8
No delay
No delay
LEDCH1
current
DLY02
LEDCH1
current
DLY02
LEDCH2
current
LEDCH2
current
DLY24
DLY24
LEDCH24
current
LEDCH24
current
Figure 24. Dimming Mode
(2) Matrix Operation Setting (PWM frequency)
The register PWMFREQ[1:0] controls the repeated number of active PGATE for VSYNC period. The figure 25 show the
example of the one repeat and two repeats. The selectable repeated number is 1, 2, 4, and 8. The necessary HSYNC
clock number is depend on the register PWMFREQ[1:0].
PWMFREQ = 0 LEDCHn output frequency = VSYNC×１
PWMFREQ = 1 LEDCHn output frequency = VSYNC×2
VSYNC
HSYNC
VSYNC
HSYNC
PGATE1
PGATE1
PGATE2
PGATE2
PGATE7
PGATE8
PGATE7
PGATE8
LEDCH1
current
LEDCH1
current
Figure 25. PWMFREQ vs LEDCHn output
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2. Matrix Operation and PWM Dimming Setting – continued
(3) PWM Delay Setting
There are 2 kinds of delay setting.
The register GDLY set the interval from VSYNC to PGATE1, and the GDLY delay affects all PGATEm accordingly.
The register DLYn (n = 1 to 24) set the interval from PGATE = ON to the current rising of LEDCHn. (That interval is
expressed NOOVLAP2 + DLYn in detail.)
By shifting the starting timing of each LED current, the transient response of the total current is averaged.
NOOVLAP1
NOOVLAP2
the interval PGATE1 = off is omitted
VSYNC
PGATE1
PGATE2
GDLY
・
・
・
・
・
・
PGATE8
DLY01
DLY01
LEDCH1
current
LEDCH1 PWM = 100 % interval
・
・
・
・
・
・
DLY24
DLY24
LEDCH24
current
LEDCH24 PWM = 100 % interval
Figure 26. PWM delay setting
Figure 26 shows the delay setting over 1 PGATE in 8 Line Gate Controller. The setting in the figure is 75 % Duty and
50 % Delay for LEDCH1.
If the LED current is finished within the single period of PGATE = ON, the delay setting of DTYmn is expressed as
following.
0 ≤ ꢄꢗ푌 < 4095
푛
ꢄꢅ푌ꢊ푛 + ꢄꢗ푌 ≤ 4095
푛
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2. Matrix Operation and PWM Dimming Setting – continued
(4) PWM Duty Setting
VCC
VIO
present VSYNC period
next VSYNC period
VSYNC
HSYNC
SCSB
SPI
[1]
status
dimming
DTYmn
(register)
[2]
[3]
[4]
DTYmn
(buffer1)
DTYmn
(buffer2)
DTYmn
(control data)
GLDY
DLY1
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
DTYmn is reflected.
LEDCHn
current
Enlarged view
duty setting
SPI
DTYmn
Register
Figure 27. Dimming Sequence for Normal Operation
[1] The register DTYmn access is finished within the present VSYNC period to reflect in the next VSYNC period. If that
access is not finished by the VSYNC, the register is not reflected correctly.
[2] Buffer1 data is updated at VSYNC timing.
[3] Buffer2 data is updated at VSYNC+GDLY timing.
[4] Control data (DTYmn) is updated after the delay setting DLYn in the next VSYNC period, DTYmn is reflected to the
LEDCHn current.
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Timing Chart – continued
3. None Overlap Function
None overlap time between PMOSm can be adjustable by the register NOOVLAP1, NOOVLAP2.
NOOVLAP1 is the interval from PMOSm = OFF to PMOS(m+1) = ON. This is set longer than the PMOS off delay not to
cause PMOS = ON simultaneously.
NOOVLAP2 is the interval from PMOS = ON to the beginning of LEDCHn current. This is set longer than the PMOS on
delay.
These register adjustable such as 32 clock, 64 clock, 128 clock, 256 clock by HSYNC.
The necessary clock of HSYNC is changed accordingly. Please refer the section of Description of PWMFREQ[1:0] (Address
0x006).
(Example) NOOVLAP1 = 0, NOOVLAP2 = 0 (DTY101, DTY201 = 0xFFF, DLY1 = 0)
none overlap time (total 64 clock)
1st 2nd 3rd
63th64th 65th
HSYNC
PMOS OFF delay
PGATE1
NOOVLAP1
NOOVLAP2
0
0
0
PGCNT[9:0]
1
30 31 32 33
62 62 63 64 65
(Note 1)
NOOVLAP1 setting
NOOVLAP2 setting
PMOS ON delay
PGATE2
LEDCH1 current
(Note 1) Internal signal for counting PGATE ON timing and LEDCH1 current ON timing.
Figure 28. PGATE1, PGATE2 None Overlap Timing
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Timing Chart – continued
4. PWM Behavior at Close VSYNC Intervals
In this section, PWM dimming behavior is shown if HSYNC is not equal to ideal frequency.
The ideal frequency of HSYNC is 33280 times of VSYNC below example.
(1) HSYNC Frequency less than Ideal Frequency
Example: Delay = 0, Duty = 75 %, PWMFREQ = 0, NOOVLAP1 = NOOVLAP2 = 0, MULSEL = 0
HSYNC = 33280 × VSYNC
HSYNC < 33280 × VSYNC
VSYNC
HSYNC
[1]
[2]
MAIN
COUNTER
PGATE1
PGATE2
・
・
・
・
・
・
PGATE7
PGATE8
PWMn
PGATE8 width is proper
PGATE8 and PWMn width is short
Figure 29. HSYNC Frequency Less than Ideal Frequency
The main counter is reset at the rising edge of VSYNC. The main counter starts counting up by HSYNC and proceed
the line control from PGATE1 to PGATE8.
[1] As HSYNC is equal to the ideal frequency, the main counter reaches the full value 33280. The ON interval of
PGATE8 and PWMn are proper.
[2] As HSYNC is smaller than the ideal frequency, the main counter does not reach the full value. The ON interval of
PGATE8 and PWMn are short.
(2) HSYNC Frequency more than Ideal Frequency
Example: Delay = 0, Duty = 50 %, PWMFREQ = 0, NOOVLAP1 = NOOVLAP2 = 0, MULSEL = 0
HSYNC = 33280 × VSYNC
HSYNC > 33280 × VSYNC
VSYNC
HSYNC
[1]
MAIN
COUNTER
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
PWMn
blank interval
Figure 30. HSYNC Frequency More than Ideal Frequency
[1] As HSYNC is more than the ideal frequency, the main counter continues the full value 33280 without reset. In this
blank interval after PGATE8 = OFF, all LEDs turn off. The ON interval of PGATE8 and PWMn are almost proper,
but all LEDs brightness is LOW.
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Timing Chart – continued
5. ERROR Detection and Release
The following are the internal signals on the timing chart:
PWM_OH[1]
PWM signal for channel 2 control
LOPDET_IL[n-1]
LSHDET_IL[n-1]
VINSWOVP_IL
ISETOCP_IL
ISETOPEN_IL
PGGSH_IL[m-1]
SSEND
R_LOPDET, R_LSHDET, R_VSYNC
ERR_MASKCNTmn
R_SSCNT
LED Open Error signal (HIGH: normal, LOW: error)
LED Short Error signal (HIGH: normal, LOW: error)
VINSW pin Over Voltage Error signal (HIGH: normal, LOW: error)
ISET pin Over Current Error signal (HIGH: normal, LOW: error)
ISET pin OPEN Error signal (HIGH: normal, LOW: error)
PGATEm Comparator signal
Soft start mask signal (HIGH: normal, LOW: mask)
retiming signal
error mask counter for PGATEm
counter for soft start
(m = 1 to 8, n = 1 to 24)
(1) LED Open Detection
LED Open Error is detected after ERRMASK, and LED Open Error is released as shown in Figure 31.
Here ERRMASK[7:0] = 0x03
If PWM_OH[n-1] is shorter than ERR_MSKCNTmn[7:0], the LED OPEN is not detected.
VSYNC
VSYNC
HSYNC
PGATE1
PGATE2
"Low"
HSYNC
PGATE1
"Low"
"High"
"Low"
"High"
PGATE2
・
・
・
・
・
・
・
・
・
・
・
・
"High"
PGATE8
PGATE8
"High"
PWM_OH[1]
PWM_OH[1]
LOPDET_IL[1]
R_LOPDET[1]
SSEND
"High"
"High"
"High"
LOPDET_IL[1]
R_LOPDET[1]
mask
mask
2clock delay
(synchronize)
"High"
SSEND
ERRMASK register
0x03
0x00
0x00
ERRMASK register
0x03
0x00
0x00
ERR_MSKCNT102[7:0]
ERR_MSKCNT102[7:0]
0x01 0x02 0x03 0x00
0x01 0x02 0x03
0x00
ERR_MSKCNT202[7:0]
ERR_MSKCNT202[7:0]
・
・
・
・
・
・
・
・
・
・
・
・
ERR_MSKCNT802[7:0]
ERR_MSKCNT802[7:0]
0x00
0x00
ERLOP1[23:0]
ERLOP2[23:0]
・
・
・
ERLOP1[23:0]
0x000002
0x000000
0x000000
0x000002
0x000000
ERLOP2[23:0]
0x000000
・
・
・
・
・
・
・
・
・
ERLOP8[23:0]
FAILB
ERLOP8[23:0]
0x000000
0x000000
FAILB
Figure 31. LED Open Detection and Release
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(1) LED Open Detection - continued
[Case: LED Open Error signal is LOW width］
While PWM_OH[1] = HIGH and LOPDET_IL[1] = LOW with SSEND = HIGH (Soft Start end), if ERR_MSKCNT does not
counts up until the ERRMASK, FAILB remains HIGH.
In the same condition, if ERR_MSKCNT counts up until the ERRMASK, FAILB asserts LOW.
VSYNC
HSYNC
PGATE1
PGATE2
VSYNC
HSYNC
PGATE1
PGATE2
1st
2nd 3rd
1st
2nd 3rd
4th
1st
2nd 3rd
4th
"Low"
"Low"
"High"
"High"
・
・
・
・
・
・
・
・
・
・
・
・
"High"
"High"
PGATE8
PGATE8
"High"
"High"
PWM_OH[1]
PWM_OH[1]
LOPDET_IL[1]
LOPDET_IL[1]
mask
mask (3 to 4 clock)
R_LOPDET[1]
2clock delay
(synchronize)
R_LOPDET[1]
SSEND
"High"
0x03
0x00
0x00
SSEND
"High"
0x03
0x00
0x00
ERRMASK register
ERR_MSKCNT102[7:0]
ERR_MSKCNT202[7:0]
ERRMASK register
ERR_MSKCNT102[7:0]
ERR_MSKCNT202[7:0]
0x01 0x02 0x03 0x00
0x01 0x02 0x03 0x00 0x01 0x02 0x03
0x00
・
・
・
・
・
・
・
・
・
・
・
・
ERR_MSKCNT802[7:0]
0x00
ERR_MSKCNT802[7:0]
0x00
ERLOP1[23:0]
ERLOP1[23:0]
0x000002
0x000000
0x000000
0x000000
0x000000
ERLOP2[23:0]
ERLOP2[23:0]
0x000000
・
・
・
・
・
・
・
・
・
・
・
・
ERLOP8[23:0]
ERLOP8[23:0]
0x000000
0x000000
FAILB
"High"
FAILB
Figure 32. LED Open Detection (the error signal is LOW width)
(2) LED Short Detection
(Example) ERRMASK[7:0] = 0x03
LED Short Error is detected after ERRMASK, and LED Short Error is released as shown in Figure 33.
If the capacitance of LEDCHn pin CLEDCH is connected, the transient response is affected. Please set the ERRMASK
value considering the time margin of LED short detection.
"High"
"Low"
VSYNC
HSYNC
PGATE1
PGATE2
VSYNC
HSYNC
PGATE1
PGATE2
"Low"
"High"
"Low"
"High"
・
・
・
・
・
・
・
・
・
・
・
・
"High"
"High"
PGATE8
PGATE8
PWM_OH[1]
PWM_OH[1]
"High"
"High"
"High"
0x03
LSHDET_IL[1]
R_LSHDET[1]
SSEND
LSHDET_IL[1]
R_LSHDET[1]
SSEND
mask
mask
2clock delay
(synchronize)
"High"
0x03
0x00
0x00
ERRMASK register
ERR_MSKCNT102[7:0]
ERR_MSKCNT202[7:0]
ERRMASK register
ERR_MSKCNT102[7:0]
ERR_MSKCNT202[7:0]
0x01 0x02 0x03
0x00
0x00
0x01 0x02 0x03
0x00
0x00
・
・
・
・
・
・
・
・
・
・
・
・
0x00
0x00
ERR_MSKCNT802[7:0]
ERLSH1[23:0]
ERR_MSKCNT802[7:0]
ERLSH1[23:0]
0x000000
0x000000
0x000002
0x000002
0x000000
0x000000
ERLSH2[23:0]
ERLSH2[23:0]
・
・
・
・
・
・
・
・
・
・
・
・
0x000000
0x000000
ERLSH8[23:0]
FAILB
ERLSH8[23:0]
FAILB
Figure 33. LED Short Detection and Release
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5. ERROR Detection and Release - continued
(3) VINSW Over Voltage Detection
(Example) VINSWOVPEN = 1, ERRLAT = 0
VINSW Over Voltage is detected after SSEND, and VINSW Over Voltage Error is released as shown in Figure 34.
LEDCHn output is not turned off by VINSW Over Voltage Error.
VSYNC
HSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
PWM_OH[1]
SSEND
"High"
VINSWOVP_IL
ERVINSWOVP
FAILB
Figure 34. VINSW Over Voltage Detection
(4) ISET Over Current Detection
(Example) ERRLAT = 0
ISET Over Current is detected after SSEND, and ISET Over Current Error is released as shown in Figure 35.
LEDCHn output is turned off by ISET Over Current Error.
VSYNC
HSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
PWM_OH[1]
SSEND
"High"
ISETOCP_IL
ERISETOCP
FAILB
Figure 35. ISET Over Current Detection
(5) ISET Open Detection
(Example) ERRLAT = 0
ISET Open is detected after SSEND, and ISET Open Error is released as shown in Figure 36.
LEDCHn output is not turned off by ISET Open Error.
VSYNC
HSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
PWM_OH[1]
SSEND
"High"
ISETOPEN_IL
ERISETOPEN
FAILB
Figure 36. ISET Open Detection
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5. ERROR Detection and Release – continued
(6) Short PGATEm to VINSW Detection
(Example) MULSEL = 0
Short PGATEm to VINSW is detected the timing that PGATEm goes from LOW to HIGH during dimming mode.
Detected PGATEm becomes Hi-z output. Short Error can release by ERRCLR.
VSYNC
HSYNC
PGATE1
PGATE2
short PGATE3 to VINSW
Hi-z
PGATE3
PGATE4
PGATE5
PGATE6
PGATE7
PGATE8
PWM_OH[1]
PGGSH_IL[7:0]
ERPGVINSH[7:0]
FAILB
0xFE
0xFD
0xFB 0xFF
0xF7
0xEF
0x04
0xDF
0xBF
0x7F
0xFE
0xFF
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Figure 37. Short PGATEm to VINSW Detection
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5. ERROR Detection and Release – continued
(7) Short PGATEm to GND Detection
(Example) MULSEL = 0
Short PGATEm to GND is detected the timing that PGATEm goes from HIGH to LOW during dimming mode. Detected
PGATEm becomes Hi-z output. Short Error can release by ERRCLR.
VSYNC
HSYNC
PGATE1
PGATE2
PGATE3
Hi-z
PGATE4
short PGATE4 to GND
PGATE5
PGATE6
PGATE7
PGATE8
PWM_OH[1]
PGGSH_IL[7:0]
ERPGVINSH[7:0]
FAILB
0xFE
0xFD
0xFB 0xF3
0xF7
0xF7
0xE7
0x08
0xD7
0xB7
0x77
0xF5
0xFF
0x00
0xFF
0xF7
0xF7
0xF7
0xF7
0xF7
0xF7
Figure 38. Short PGATEm to GND Detection
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5. ERROR Detection and Release – continued
(8) Short Check Detection of Adjacent LEDCHn
The short check sequence of adjacent the LEDCHn pin is executed at the end of TURNONWAIT interval, if the register
LSHEXE = 1 is written by the end of TURNONWAIT interval, where EXEOK status is HIGH. If LSHEXE = 1 is written
after TURNONWAIT interval, the short check sequence is not executed and the register EXENG = 1.
The short check result can be read from the register ERLED[23:0]. Example both ERLED[5] and ERLED[6] is HIGH,
the LEDCH6 pin and the LEDCH7 pin can be judged as short pin.
internal reset
VSYNC
HSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
PWM_OH[1]
LSHEXE
LSHEXE = 1 is written
by the end of TURNONWAIT
EXEOK
TURNONWAIT
short check
0x000060
dimming
ERLED[23:0]
0x000000
Status
FAILB
OFF
output disable
TURNONWAIT
Figure 39. Short Check Detection of Adjacent LEDCHn
(9) Soft-start Masking Function
LED Open Error cannot be detected during Soft Start (SSEND = LOW). Soft start counter counts up every VSYNC
period until the SSMASK setting (SSEND = HIGH) as shown Figure 40 below. LED Open Error can be detected when
SSEND = HIGH. It is also the same when LED Short Error is detected.
Time of mask = (TURNONWAIT register + SSMASK register) x VSYNC
(Example) SSMASK = 0x3C
internal reset
VSYNC
HSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
output mask
LEDCH1
LOPDET_IL[0]
TURNONWAIT 0x00 0x01 0x02 0x03 0x04 0xFF
0xFF
SSMASK[7:0]
R_SSCNT[7:0]
0x3C
0x00
0x00
0x01 0x02
0x3A 0x3B 0x3C
0xFF
SSEND
FAILB
mask
released "soft start mask"
Figure 40. Setting for Soft Start Mask
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5. ERROR Detection and Release – continued
(10) Error Sequence for the Register AUTOOFF
AUTOOFF set the abnormal LED = OFF automatically.
(Case) the register ERRLAT = 0 and AUTOOFF = 1
VSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
[2]
[5]
LEDCH1(PGATE1) = OFF automatically
AUTOOFF is cleared
LEDCH1
current
LEDCH24
current
[4]
[6]
SPI
Error LEDCH1(PGATE1)
[3]
[1]
External
condition
normal
normal
AUTOOFF(register)
ERRLAT(register)
AUTOCLR(register)
ERRCLR(register)
"High"
"Low"
"Low"
"Low"
ERLSH1(register) 0x000000
LEDEN[23:0](register)
FAILB
0x000001
0xFFFFFF
0x000000
[7]
Enlarged view
Enlarged view
SPI
register Read:
ERLSHmn
ERLOPmn
SPI
register Write:
AUTOCLR
Figure 41. Error Sequence for the register AUTOOFF = 1
[1] If LED Short Error is detected, FAILB asserts LOW.
[2] LEDCH1 output is turned off automatically. (Only target timing (PGATE1))
[3] The external condition turns to normal. The LEDCH1 = OFF continues, and FAILB keeps LOW.
[4] By reading the register ERLSHmn, ERLOPmn, the abnormal LED component can be distinguished.
[5] Once LEDCH1(PGATE1) is off automatically, IC does not judge the LED Short Error status. The LED keeps off.
[6] The register AUTOCLR = 1 is written, The automatical off status is cleared.
[7] IC judges LED Short Error. As the external condition is normal, LED turns on and ERLSH1 = 0x000000 and FAILB
= HIGH.
(Case) the register ERRLAT = 0 and AUTOOFF = 0
[2] When the abnormal is detected, LED does not turn off automatically.
[3] If the abnormal state is released, LED turn on again.
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5. ERROR Detection and Release – continued
(11) Error Sequence for the Register ERRLAT
ERRLAT keeps the abnormal state as latch state, even if that is released.
(Case) the register ERRLAT = 1 and AUTOOFF = 0
VSYNC
PGATE1
PGATE2
・
・
・
・
・
・
PGATE8
LEDCH1
current
[2]
[5]
LEDCH24
current
[4]
[6]
SPI
[1]
[3]
External
condition
normal
normal
Error LEDCH1(PGATE1)
AUTOOFF(register)
ERRLAT(register)
AUTOCLR(register)
ERRCLR(register)
ERLSH1(register)
LEDEN[23:0] (register)
FAILB
"Low"
"High"
"Low"
"Low"
0x000000
0x000001
0xFFFFFF
0x000000
Enlarged view
Enlarged view
SPI
register Read:
ERLOPmn
ERLSHmn
SPI
register Write:
AUTOCLR
Figure 42. Error Sequence for the register ERRLAT = 1
[1] If LED Short Error is detected, FAILB asserts LOW.
[2] LEDCH1 output is still turned on, because AUTOOFF is 0.
[3] The external condition turns to normal. The register ERLSH1 keeps 0x000001 and FAILB asserts LOW.
[4] By reading the register ERLSHmn, ERLOPmn, the abnormal LED component can be distinguished.
[5] LEDCH1 output is still turned on, because AUTOOFF is 0.
[6] The register ERRCLR = 1 is written, The register ERLSH1 is cleared to 0x000000 and FAILB asserts HIGH.
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Condition for Protections
Table 49. Protection Table 1
LED OPEN
LED SHORT
ERRLAT = 0 ERRLAT = 1
ERRLAT = 0
ERRLAT = 1
Pin
LEDCHn in every PGATEm
LEDEN[n-1] = 1 and DTYmn > 0 and
LSHEN = 1 and LEDCHn ON and
LEDEN[n-1] = 1 and DTYmn > 0 and
LOPEN = 1 and LEDCHn ON and
VLEDCHn ≤ 0.15 V
Detection
Condition
Protection
VLEDCHn ≥ VSHDET
Release
Condition
Error Enable
SSMASK
ERRMASK
ERRLAT
AUTOOFF
Error
Register
FAILB(Note 1)
Clear
Condition
AUTOOFF
= 0
LEDEN[n-1] = 0 or LSHEN = 0 or
LEDCHn ON and VLEDCHn < VSHDET
LEDEN[n-1] = 0 or LOPEN = 0 or
LEDCHn ON and VLEDCHn > 0.15 V
LOPEN
LSHEN
O
O
O
O
O
O
O
O
Error
Setting
ERLOP[n-1]
LOW
ERLSH[n-1]
LOW
Error
Flag
Protection released
OFF by LEDEN[n-1] = 0(Note 2)
OFF automatically
ERRCLR = 1
Protection released
ERRCLR = 1
OFF by LEDEN[n-1] = 0(Note 2)
Error
Channel
AUTOOFF
= 1
OFF automatically
‘O’: It has the function.
(Note 1) When the IC detects VCCUVLO or VREG15UVLO or TSD or EN, it cannot detect other protection.
(Note 2) Write LEDEN[n-1] = 0 when the error channel is turned off.
(Note) m = 1 to 8, n = 1 to 24
Table 50. Protection Table 2
ISET OCP
ISET OPEN
ERRLAT = 0 ERRLAT = 1
ERRLAT = 0
ERRLAT = 1
Pin
ISET
Detection
Condition
Release
Condition
Error Enable
SSMASK
ERRMASK
ERRLAT
AUTOOFF
Error
Register
FAILB(Note 1)
Clear
Condition
AUTOOFF
= 0
RISETSP ≤ max 16 kΩ
RISETOPEN ≥ min 340 kΩ
RISETOPEN < min 340 kΩ
Protection
RISETSP > max 16 kΩ
-
O
-
O
-
-
O
-
O
-
Error
Setting
ERISETOCP
LOW
ERISETOPEN
LOW
Error
Flag
Protection released
ERRCLR = 1
Protection released
ERRCLR = 1
-
-
-
Error
Channel
AUTOOFF
= 1
-
‘-’: It does not have the function.
(Note 1) When the IC detects VCCUVLO or VREG15UVLO or TSD or EN, it cannot detect other protection.
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Condition for Protections – continued
Table 51. Protection Table 3
PGATEm to VINSW SHORT
PGATEm to GND SHORT
Pin
PGATEm
Detection
Condition
Release
Condition
Error Enable
SSMASK
ERRMASK
ERRLAT
AUTOOFF
Error
Register
FAILB(Note 1)
Clear
Condition
AUTOOFF
= 0
PGATEm Fall edge and
VPGATEm ≤ VINSW-2.5 V
PGATEm Rise edge and
VPGATEm > VINSW-1.5 V
Protection
ERRCLR = 1
ERRCLR = 1
-
-
-
-
-
-
-
-
-
-
Error
Setting
ERPGVINSH[m-1]
LOW
ERPGGSH[m-1]
LOW
Error
Flag
ERRCLR = 1
ERRCLR = 1
-
-
-
Error
Channel
AUTOOFF
= 1
-
‘-’: It does not have the function.
(Note 1) When the IC detects VCCUVLO or VREG15UVLO or TSD or EN, it cannot detect other protection.
(Note) m = 1 to 8
Table 52. Protection Table 4
VINSW OVP
Short of Adjacent LEDCHn
LEDCHn
ERRLAT = 0
ERRLAT = 1
Pin
VINSW
VVINSW
LSHEXE = 1 before TURNONWAIT time
and
Detection
Condition
Protection
> VVINSWOVPREF
LEDCHn OFF and VLEDCHn < VSHDET during
short check sequence
Release
Condition
Error Enable
SSMASK
ERRMASK
ERRLAT
AUTOOFF
Error
Register
FAILB(Note 1)
Clear
Condition
AUTOOFF
= 0
VVINSW
≤ VVINSWOVPREF × 0.9
VINSWOVPEN
ERRCLR = 1
-
-
-
-
-
O
-
O
-
Error
Setting
ERVINSWOVP
LOW
ERLED[n-1]
LOW
Error
Flag
Protection released
ERRCLR = 1
ERRCLR = 1
-
-
-
Error
Channel
AUTOOFF
= 1
-
‘-’: It does not have the function.
(Note 1) When the IC detects VCCUVLO or VREG15UVLO or TSD or EN, it cannot detect other protection.
(Note) n = 1 to 24
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Condition for Protections – continued
Table 53. Protection Table 5
VCCUVLO
VREG15UVLO
VIOUVLO
VIO
Pin
VCC
VREG15
Detection
Condition
VCC
≤ 2.55 V
VVREG15
≤ 1.3 V
VVIO
≤ 1.41 V
Protection
Release
Condition
VCC
≥ 2.65 V
VVREG15
≥ 1.35 V
VVIO
≥ 1.46 V
Error Enable
SSMASK
ERRMASK
ERRLAT
AUTOOFF
Error Register
FAILB(Note 1)
Clear Condition
AUTOOFF
= 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Error Setting
Error
Flag
-
-
-
-
-
Error Channel
AUTOOFF
= 1
-
‘-’: It does not have the function.
(Note 1) When the IC detects VCCUVLO or VREG15UVLO or TSD or EN, it cannot detect other protection.
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I/O Equivalence Circuit
VCC
FB
EN
VCC
FB
VCC
EN
10k
GND
100k
5k
GND
GND
GND
GND / LGND
VREG15
ISET
VCC
VCC
VCC
GND
VREG15
70k
330k
GND
1k
1k
LGND
ISET
GND
10k
GND
GND
HSYNC / VSYNC / SCSB / SDI / SCLK
VIO
SDO
VIO
VIO
VIO
HSYNC
VSYNC
SCSB
SDI
SDO
1k
SCLK
GND
GND
GND
GND
FAILB
LEDCH1 to LEDCH24
PGATE1 to PGATE8 / VINSW
VINSW
LEDCH1
to
LEDCH24
GND
GND
PGATE1
to
PGATE8
10k
FAILB
1M
LGND
GND GND
LGND
GND
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I/O Equivalence Circuit – continued
SUMFB
TEST1
TEST2
VIO
VCC
VIO
10k
10k
TEST2
1k
TEST1
1k
SUMFB
GND
GND
GND
GND
GND
LSPSET
20k
LSPSET
GND
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
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Operational Notes – continued
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 43. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
14. Functional Safety
“ISO 26262 Process Compliant to Support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in
the datasheet.
“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional Safety Supportive Automotive Products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
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Ordering Information
B D 9
4
1
3
0
x
x
x
-
ME2
Package
Product Rank
MUF: VQFN56FCV080
EFV: HTSSOP-B54
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
HTSSOP-B54 (TOP VIEW)
VQFN56FCV080 (TOP VIEW)
Part Number Marking
LOT Number
Part Number Marking
LOT Number
D 9 4 1 3 0
D 9 4 1 3 0
Pin 1 Mark
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
VQFN56FCV080
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Physical Dimension and Packing Information - continued
Package Name
HTSSOP-B54
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Revision History
Data
Revision
Changes
17.Aug.2022
001
New release
(1) Page 39
Modified description of MSMODE register.
(2) Page 49, 50
Added VINSW pin to the timing chart.
02.Dec.2022
002
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
相关型号：
BD9416FS
BD9416FS是白色LED用高效率驱动器，适用于大屏幕液晶驱动器。BD9416FS内置了可向光源（LED串联连接的阵列）提供适当电压的DCDC转换器。BD9416FS中内置了应对异常状态的几种保护功能。过电压保护(OVP: Over Voltage Protection)、过电流检测(OCP: Over Current Limit Protection of DCDC)、LED 过流保护(LEDOCP: LEDOver Current Protection)、过升压保护(FBMAX: Over Boost Protection)等。因此，可在更宽的输出电压条件及负载条件下使用。
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