BD99954MWV_技术文档

1 to 4-Cell Li-Ion Battery Manager

For Application Processors

BD99954MWV, BD99954GW



General Description



Voltage Measurement for Thermistor.

Bias voltage output for the external thermistor.

BD99954 is a Battery Management LSI for 1-4 cell

Lithium-Ion secondary battery, and available in a 40pin

0.40 mm pitch 5.0 mm x 5.0 mm QFN package and small

41-ball 0.4mm pitch 2.6mm x 3.0mm Wafer-Level CSP

package which is designed to meet high degree demands

for space-constraint equipment such as Low profile

Notebook PC, Tablets and other applications.



SMBus Interface (Clock up friendly I2C) for Host

communication



Embedded OTPROM for initial settings

BD99954 provides a Dual-source Battery Charger, two

port BC1.2 detection and a Battery Monitor with several

alarm(INT#, PROCHOT#) outputs



Packages

Pitch

W

x D

x H

UQFN040V5050

0.4mm 5.0mm x 5.0mm x 1.0mm



Features

UCSP55M3C

6 x 7balls

0.4mm 2.6mm x 3.0mm x 0.62mm



Dual-source Battery Charger



High efficiency Step-Up/Down switching charger for

1-4 cell Li-Ion/Li-poly battery

Two separate input sources for USB-VBUS and DC

adapter.



Two port BC1.2 detectors.

JEITA compliant charging profile

Programmable parameters for Preconditioning, Pre-

charge current, and Fast-charge current

UQFN040V5050

UCSP55M3C



Programmable charging voltage

Programmable charge current

Programmable Switching Frequency: 600kHz to

1.2MHz

 Applications



Ultrabook



Support USB BCS 1.2, ACA, ID pin, OTG

USB-VBUS Over Voltage Protection

Over Voltage Battery Protection

Notebook PC

Ultra-mobile PC

Tablet PC

Battery Short Circuit Detection

Power Path Management with charge pump gate

driver



Structure



Flexibility power path control

Reverse Buck/Boost Option for USB/USB-PD

Bias voltage output for the external thermistor

PMON output

Silicon Monolithic Integrated Circuit



Line up matrix

Parts No.

Package

PROCHOT# output

BD99954MWV

BD99954GW

UQFN040V5050

UCSP55M3C

Support Inhibit / Autonomous Charging

Battery Learn Function

Input Operating Range: 3.8V to 25V

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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Contents

Notation ....................................................................................................................................................................3

Reference .................................................................................................................................................................3

1. INTRODUCTION .................................................................................................................4

2. SIGNAL DESCRIPTION......................................................................................................5

3. PIN CONFIGURATION........................................................................................................6

4. ABSOLUTE MAXIMUM RATING ........................................................................................7

5. THERMAL RESISTANCE ^{(NOTE 1)}........................................................................................7

6. RECOMMENDED OPERATING CONDITION.....................................................................7

7. FUNCTION DESCRIPTIONS...............................................................................................8

7.1.

7.2.

7.3.

7.4.

7.5.

7.6.

7.7.

7.8.

7.9.

Block Diagram ............................................................................................................................................8

External Characteristics for Battery Charger ..........................................................................................9

DC Input & Over Voltage Protection (OVP)............................................................................................10

USB Detection...........................................................................................................................................11

DC/DC Converter ......................................................................................................................................12

Charger......................................................................................................................................................14

Reverse DC/DC Converter.......................................................................................................................16

12-bit ADC .................................................................................................................................................17

Power On...................................................................................................................................................18

8. CONTROL SPECIFICATION.............................................................................................20

8.1.

8.2.

8.3.

8.4.

8.5.

8.6.

SMBus Communication ...........................................................................................................................20

SMBus Protocols......................................................................................................................................20

Command Code........................................................................................................................................22

Battery Charger Commands Description...............................................................................................26

Extended Commands Description..........................................................................................................29

Resister Default Value............................................................................................................................115

9. I/O EQUIVALENT CIRCUIT DIAGRAM .......................................................................... 118

10. ORDERING INFORMATION............................................................................................121

11. MARKING DIAGRAMS ...................................................................................................121

12. PHYSICAL DIMENSION TAPE AND REEL INFORMATION ..........................................122

13. OPERATIONAL NOTES..................................................................................................124

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Notation

Category

Notation

Description

Unit

V

Volt (Unit of voltage)

A

Ampere (Unit of current)

Ohm (Unit of resistance)

Farad (Unit of capacitance)

degree Celsius (Unit of Temperature)

Hertz (Unit of frequency)

second (Unit of time)

minute (Unit of time)

Ω, Ohm

F

deg., degree

Hz

s (lower case)

Min

b, bit

bit (Unit of digital data)

B, byte

1 byte = 8 bits

Unit prefix

M, mega-, mebi-

M, mega-, million-

K, kilo-, kibi-

k, kilo-

2²⁰= 1,048,576 (used with “bit” or “byte”)

10⁶= 1,000,000 (used with “Ω” or “Hz”)

2¹⁰= 1,024 (used with “bit” or “byte”)

10³= 1,000 (used with “Ω” or “Hz”)

10^-3

10^-6

10^-9

10^-12

m, milli-

μ, micro-

n, nano-

p, pico-

xxh, xxH

Numeric value

Hexadecimal number.

“x”: any alphanumeric of 0 to 9 or A to F.

Xxb

Binary number; “b” may be omitted.

“x”: a number, 0 or 1

“_” is used as a nibble (4-bit) delimiter.

(e.g. “0011_0101b” = “35h”)

Address

Data

#xxh

Address in a hexadecimal number.

“x”: any alphanumeric of 0 to 9 or A to F.

bit[n]

n-th single bit in the multi-bit data.

bit[n:m]

“H”, High

“L”, Low

“Z”, “Hi-Z”

Bit range from bit[n] to bit[m].

Signal level

High level (over V_IHor V_OH) of logic signal.

Low level (under V_ILor V_OL) of logic signal.

High impedance state of 3-state signal.

Reference

Name

Reference Document

Release Date

Publisher

I2C-bus

SMBus

“UM10204: I²C-bus specification and user manual Rev. 4”

System Management Bus (SMBus) Specification 3.0

Feb. 13, 2012

Dec. 20, 2014

NXP Semiconductors

SBS-IF

“A Guide to the Safe Use of Secondary Lithium Ion Batteries in

Notebook-type Personal Computers”

JEITA Profile

USB BC

Apr. 10, 2007

Dec. 7, 2010

Dec. 11, 1998

JEITA

“Battery Charging Specification Revision 1.2”

Smart Battery Charger Specification Revision 1.1

USB.org

SBS-IF

Smart Battery

Charger

USB 2.0

USB 3.1

USB PD

Universal Serial Bus Specification Revision 2.0

Universal Serial Bus Revision 3.1 Specification Rev. 1.0

USB Power Delivery Specification Rev. 2.0 V1.0

Jul. 26, 2013

Aug. 11, 2014

Apr. 27, 2000

USB.org

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

1. Introduction

BD99954 is a Battery Manager IC for 1-4Cell Lithium-Ion / Lithium-Ion polymer secondary battery pack used in portable

equipment such as Tablets, Ultra books or others.

BD99954 includes a Battery Charger, two port BC1.2 detection, a Battery Monitor for voltage, current, temperature and

alarm(INT#, PROCHOT#) Controller.

Figure 1-1 shows the Typical Application Circuit.

Q3

Q4

C9

R1

Q1

Q2

C1

C2

VBUS

C8

C14

ACGATE2

ACGATE1

ACP

ACN

USB

C3

BOOT1

HG1

VCC

Q5

L1

USB

VBUS

Q6

R17

REGN

C7

LX1

LG1

System

D+

D-

ID

VBUS_DPI

VBUS_DMI

C5

R18

VBUS_ID

D+

D-

ID

VCC_DPI

VCC_DMI

VCC_ID

C4

BOOT2

LX2

V3P3V

R14

R13

R12

R11

R10

R15

R16

LG2

BD99954

VBUS_DPO

VBUS_DMO

VCC_DPO

VCC_DMO

PROCHOT#

PMON

HG2

SRP

PHY

IMVP

EC

R2

Q7

C11 C12

SRN

IOUT

ACOK

C13

BGATE

SCL

R7

SDA

BATT

VREF

INT#

C15

VREF

R3

R4

C10

Battery

R5

R6

C6

TSENSE

R9

IADP/RESET

C18

GND

C17

Θ

Figure 1-1 Block Diagram

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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2. Signal Description

Table 2-1 Signal Description

Function

No.

Ball

No.

Pin Name

[CSP]

1

2

3

4

5

B2

VBUS

VCC

ACOK

USB Power Supply

DC Power Supply

AC adapter voltage detection open drain output.

Interrupt for I2C

A2

D3

A3

B3

INT#

PROCHOT#

Active low open drain output of “processor hot” indicator. The charger

IC monitors events like adapter current, battery discharge current. Once any

event in PROCHOT# profile is triggered, a minimum 10ms pulse is asserted.

Input current sense resistor negative input.

6

7

8

A4

A5

B4

ACN

ACP

ACGATE1

Input current sense resistor positive input.

Charge pump output to drive adapter input n-channel MOSFET s.

The ACGATE1 voltage is 5V above VBUS during AC adapter insertion.

Charge pump output to drive adapter input n-channel MOSFET s.

The ACGATE2 voltage is 5V above VCC during AC adapter insertion.

Default Input Current Limit Setting pin and System resistor reset pin.

VBUS side USB D- Input / Output

VBUS side USB D+ Input / Output

VBUS side USB D- Output / Input

VBUS side USB D+ Output / Input

VBUS side USB ID pin input

VCC side USB D- Input / Output

VCC side USB D+ Input / Output

VCC side USB D- Output / Input

VCC side USB D+ Output / Input

VCC side USB ID pin input

9

B5

ACGATE2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

A6

B6

C4

C5

C6

D5

D6

D4

E6

F6

G6

E5

F5

G5

IADP/RESET

VBUS_DMI

VBUS_DPI

VBUS_DMO

VBUS_DPO

VBUS_ID

VCC_DMI

VCC_DPI

VCC_DMO

VCC_DPO

VCC_ID

SCL

SDA

PMON

SMBus Clock Input

SMBus Data Input / Output

Buffered total system power current output. Place a resistor between

PMON pin and GND.

24

25

26

F4

G4

E3

IOUT

VREF

TSENSE

Buffered adapter or charge current output selectable with SMBus command.

1.5V LDO Output

Battery temperature monitor pin.

Active low battery present input signal. LOW indicates battery is present,

and HIGH indicates the battery is absent and the charging stop.

Battery Voltage Input

27

28

29

30

31

32

33

34

35

36

37

38

39

40

G3

F3

G2

G1

F2

F1

E2

E1

D2

D1

C1

C2

B1

A1

BATT

BGATE

SRN

SRP

GND

HG2

LX2

BOOT2

LG2

LG1

BOOT1

LX1

Gate Control Output

Charge current sense resistor negative input.

Charge current sense resistor positive input.

Ground

DC/DC Boost side High Side Gate Driver

DC/DC Boost side Inductor Connection

DC/DC Boost side Driver Voltage Output

DC/DC Boost side Low Side Gate Driver

DC/DC Buck side Low Side Gate Driver

DC/DC Buck side Driver Voltage Output

DC/DC Buck side Inductor Connection

DC/DC Buck side High Side Gate Driver

LDO Output

HG1

REGN

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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3. Pin Configuration

21

30

20

VCC_ID

31

GND

HG2

VCC_DPO

VCC_DMO

VCC_DPI

LX2

BOOT2

LG2

VCC_DMI

VBUS_ID

LG1

BOOT1

LX1

VBUS_DPO

VBUS_DMO

VBUS_DPI

HG1

REGN

40

VBUS_DMI

11

1

10

Figure 3-1 Pin Configuration in BD99954MWV (Top View)

G

F

SRP

HG2

SRN

GND

LX2

BATT

BGATE

TSENSE

ACOK

VREF

IOUT

PMON

SDA

VCC_ID

VCC_DPO

VCC_DMO

VCC_DMI

E

BOOT2

LG1

N/C

SCL

D

C

B

A

LG2

VCC_DPI

VBUS_ID

BOOT1

HG1

LX1

VBUS_DPI VBUS_DMO VBUS_DPO

VBUS

PROCHOT# ACGATE1 ACGATE2 VBUS_DMI

IADP/RESET

6

REGN

1

VCC

2

INT#

3

ACN

4

ACP

5

Figure 3-2 Pin Configuration in BD99954GW (Bottom View)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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4. Absolute Maximum Rating

Value

VBUS, VCC, SRN, SRP, ACN, ACP, BATT

LX1, LX2

ACGATE1, ACGATE2, BGATE, BOOT1, BOOT2,

HG1, HG2

-0.3 to 28V

-2 to 28V

-0.3 to 32V

Voltage range

(with respect to GND)

LX1-BOOT1,LX2-BOOT2

ACP-ACN, SRP-SRN

VBUS_DPI, VBUS_DMI, VBUS_ID, VBUS_DPO,

VBUS_DMO, VCC_DPI, VCC_DMI, VCC_ID,

VCC_DPO, VCC_DMO, ACOK, REGN, INT#,

PROCHOT#, IOUT, PMON, SCL, SDA, LG1, LG2

TSENSE, IADP/RESET, VREF

-0.3 to 6V

-0.3 to 0.3 V

-0.3 to 7.0 V

-0.3 to 2.1 V

150℃

-50 to 150℃

Junction temperature

Storage temperature

5. Thermal Resistance ^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 4)}

2s2p^(Note5)

4s5p^(Note7)

UQFN040V5050

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

-

θ_JA

113.6

8

24.5

3

°C/W

Ψ_JT

UCSP55M3C

Power Dissipation^(Note3)

θ_JA

-

W

0.97

(Note 1)Based on JESD51-2A(Still-Air) only BD99954MWV

(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface

of the component package.

(Note 3) Derate by 78.1mW/°C when operating above Ta=25°C (when mounted in ROHM’s standard board)

(Note 4)Using a PCB board based on JESD51-3.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3mm x 76.2mm x 1.57mmt

Top

Copper Pattern

Thickness

70μm

Footprints and Traces

(Note 5)Using a PCB board based on JESD51-5, 7.

Layer Number of

Material

Thermal Via^(Note6)

Board Size

114.3mm x 76.2mm x 1.6mmt

2 Internal Layers

Measurement Board

Pitch

Diameter

4 Layers

FR-4

1.20mm

Φ0.30mm

Top

Bottom

Copper Pattern

Thickness

70μm

Copper Pattern

Thickness

35μm

Copper Pattern

Thickness

70μm

Footprints and Traces

74.2mm x 74.2mm

(Note 6) This thermal via connects with the copper pattern of all layers..

(Note 7)Using a PCB board

Layer Number of

Measurement Board

Material

FR-4

Board Size

63mm x 55mm x 1.6mmt

9 Layers

6. Recommended Operating Condition

MIN

3.8

MAX

25

Unit

V

VBUS

VCC

3.8

25

V

BATT

IIN

0

-

19.2

16

V

A

ISYS

-

16

A

ICHARGE

-

16

A

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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Operating Temperature range

-30

85

℃

7. Function Descriptions

7.1. Block Diagram

VBUS VBUS VBU

VCC_ VCC_ VCC_

DPI DMI ID

_DPI

_DMI

S_ID

VOVP_VCC

VCC

VCC_

DMO

VCC_

DPO

VBUS

_DMO

VBUS

_DPO

VUVLO_VCC

Power

Path

BC1.2 Detector

Control

Logic

VOVP_BUS

VBUS

ACOK

Control Logic

ACN VCC VBUS BATT

BoS

VUVLO_BUS

VOR

VCC

Gate

ACGATE2

VOR

5V

Charge Pump

REGN

VBUS

Gate

LDO

ACGATE1

Charge Pump

REGN

BOOT1

HG1

ACP

ACN

VFB_ADP

xA

VREF_ADP

Buck

DRIVE

R

LX1

LG1

PWM

Control

Logic

VREF_SYS

VFB_CHG

BOOT2

HG2

Slope

Boost

DRIVE

R

SRP

SRN

LX2

Control Logic

xA

LG2

VREF_CHG

VREF_BAT

BATT

BGATE

Charge Pump

VREF_TRC

PROCHOT#

REGN

VREF

1.5V

LDO

VCC

VREF

ADC

VBUS

INT#

VFB_ADP

VFB_CHG

SRN

IADP/RESET

TSENSE

MUX

BATT

PWM Control Logic

Control

Logic

Power Path Control Logic

REGN

IOUT

SCL

SDA

DAC

SMBUS

I/F

PMON

GND

Figure 7-1 Block diagram

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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7.2. External Characteristics for Battery Charger

Adapter=18.0V, Battery=7.4V, LX1=LX2=0.0V, GND=0V, Ta=25℃ (unless otherwise noted.)

Value

Typ.

Item

Symbol

Unit

Condition

Min.

Max.

Adapter Standby Current 1

Adapter Operating Current 2

I_ADP1

I_ADP2

I_BATT1

-

1.0

4.0

1.5

8.0

mA

Charge Pump ON

Not Switching

Battery Standby Current

(VBUS=VCC=0.0V)

BGATE Charge Pump ON

REG0x7Ch[2:0]=5h

50.0

25.0

100.0

50.0

-

μA

BGATE Charge Pump OFF

Deep Sleep mode

Battery Standby Current

(VBUS=VCC=0.0V)

I_BATT2

REG0x7Ch[2:0]=6h

SDA=SCL=0V

BGATE Charge Pump ON

PROCHOT only VSYS [1msec/S]

REG0x7Ch[2:0]=2h

Battery Standby Current

(VBUS=VCC=0.0V)

125

150

200

290

I_BATT3

-

μA

BGATE Charge Pump ON

PROCHOT only VSYS [250μsec/S]

REG0x7Ch[2:0]=1h

Battery Standby Current

(VBUS=VCC=0.0V)

I_BATT4

BGATE Charge Pump ON

with PROCHOT Monitored System

voltage and Battery current

REG0x7Ch[2:0]=0h

Battery Current

700

900

I_BATT5

-

μA

(VBUS=VCC=0.0V)

-

5.2

-

400

5.4

-

kHz

V

SMBus Operation Frequency

REGN Output Voltage

FSMB

V_REGN

V_{REGN_LD}

V_{REGN_UVL}

O

10

5.0

10

mA

REGN External output current

2.5

2.625

200

V

REGN UVLO Voltage

2.375

50

Detecting REGN falling edge

Detecting REGN rising edge

V_{REGN_UVL}

100

mV

REGN UVLO Hysteresis Range

O

1.5

1.55

1.45

V

LDO Output Voltage

V_REF

1.455

1.35

IVREF=1mA

1.40

VREF UVLO release Voltage

V_{REF_UVLO}

V_{REF_UVLO_}

hys

Detecting VREF rising edge

50

100

mV

VREF UVLO Hysteresis Range

25

Detecting VREF falling edge

<PMON>

16

-

μA/W

%

-

REG0x25h[2:0]=6h 6.25W Setting

REG0x25h[2:0]=5h 12.5W Setting

REG0x25h[2:0]=4h 25W Setting

REG0x25h[2:0]=3h 50W Setting

REG0x25h[2:0]=2h 100W Setting

REG0x25h[2:0]=1h 200W Setting

REG0x25h[2:0]=0h 400W Setting

IPMON=50uA

8

4

-

Power Monitor Amplifier Gain

(IPMON)/(VACP×IACP +

VBAT×IBAT )

2

-

G_PMON

-

1

-

0.5

0.25

-

+5

200

I_PMON

-5

-

μA

PMON Maximum Current

I_PMONMAX

<IOUT>

20

-

V/V

mV

V/V

mV

G_IADP

V_IOUT1

V_IOUT2

V_IOUT3

V_IOUT4

V_IOUT5

V_IOUT6

G_IDCHG

V_IDCHG1

V_IDCHG2

V_IDCHG3

V_IDCHG4

-

(VIADP)/(VACP- VACN)

(VACP- VACN)=40.96mV

(VACP- VACN)=20.48mV

(VACP- VACN)=10.24mV

(VACP- VACN)=5.12mV

(VACP- VACN)=2.56mV

(VACP- VACN)=1.28mV

(VIDCHG)/(VSRN- VSRP)

(VSRN- VSRP)=40.96mV

(VSRN- VSRP)=20.48mV

(VSRN- VSRP)=10.24mV

(VSRN- VSRP)=5.12mV

819.2

409.6

204.8

102.4

51.2

835.6

426

235.5

122.9

-

802.8

393.2

174.1

81.92

-

IADP Voltage Accuracy

IDCHG Voltage Accuracy

25.6

-

16

-

655.4

327.7

163.8

81.9

688.2

357.2

204.8

122.9

622.6

298.2

122.9

41

Note: Resister address refer to extended commands

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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7.3. DC Input & Over Voltage Protection (OVP)

7.3.1. Outline



Dual-input for the battery charger source: USB VBUS and VCC

25V over voltage protection.

One of two DC input selection (exclusive)

Effective input is selected by the control registers, VCC as default.

7.3.2. Electrical Characteristics

Adapter=18.0V, Battery=7.4V, LX1=LX2=0.0V, GND=0V, Ta=25℃ (unless otherwise noted.)

Value

Typ.

Item

Symbol

Unit

Condition

Min.

3.8

Max.

25

V

VCC Input Operating Range

VCC UVLO Release Voltage

V_CCRNG

V_{CC_UVLO}

-

3.7

3.8

3.9

VCC rising

VCC falling

V_{CC_UVLO_hy}

mV

VCC UVLO Hysteresis Range

80

130

180

s

V

mV

V

VCC OVP Detection Voltage

VCC OVP Hysteresis Range

USB Input Operating Range

VBUS_UVLO Release Voltage

V_{CC_OVP}

25.0

100

3.8

25.5

150

-

26.0

200

25

VCC rising

VCC falling

V_{CC_OVP_hys}

V_USBRNG

V_{BUS_UVLO}

V_{BUS_UVLO_h}

V

3.7

3.8

3.9

VBUS rising

VBUS falling

VBUS rising

VBUS falling

mV

V

VBUS UVLO Hysteresis Range

VBUS OVP Detection Voltage

VBUS OVP Hysteresis Range

80

130

25.5

150

180

26

ys

V_{BUS_OVP}

V_{BUS_OVP_hy}

25.0

100

mV

200

s

V

VACOK Output “L” Voltage

VACOK Leakage Current

V_{OK_ON}

I_OKL

T_{VBUS_ON}

T_{VBUS_OFF}

-

1.0

1

I(VACOK) =1mA

VACOK = 5V

µA

msec

μsec

VBUS Reverse Output turn-on Time

Voltage Output down-off Time

5

1

10

5

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.4. USB Detection

7.4.1. Outline



USB Charger port detection and USB ID

Supports USB BC 1.2, USB ACA, USB ID pin, USB OTG, and PD plug detection.

Integrated analog switch supports USB HS (480Mbps).

7.4.2. Electrical Characteristics

Table 7-1 Electrical Characteristics for USB Detection

(Ta=25C, BATT=3.6V, VBUS=5.0V)

Specification

Typ.

Item

Symbol

Unit

Condition

Min.

Max.

VDP_SRC voltage

VDP_SRC

VDM_SRC

RCD

0.5

75

0.6

100

-

0.7

125

-

V

Io=0 to 200uA

(output voltage for D+)

VDM_SRC voltage

(output voltage for D-)

RCD resistance

(D+ pull up resistance)

USB port un-detection resistance

(Host D+ pull down resistance)

VDAT_REF voltage

(D+/D- detection voltage)

VLGC voltage

(D+/D- detection voltage)

D+ sink current

D- sink current

kΩ

V

RHDP

100

0.3

1.2

VDAT_RE

F

0.35

1.4

0.4

1.6

HDPR/HDML voltage rising

VLGC

V

IDP_SINK

IDM_SINK

50

85

150

V(HDPR) = 0.6V

V(HDML) = 0.6V

A

RON_US

BSW

IIOFF_U

SB

Switch on-state resistance

-

5

-

10

3

Ω

VIN=3.3V or 0V

VIN=3.3V or 0V VBUS=OPEN

Switch off-state leakage current

-3

μA

Switch capacitance

USB Switch start-up time

CSW

TUPUSB

-

6

-

1

pF

ms

USBSW ON

USBSW OFF→ON

(Ta=25C, VBAT=3.6V, VBUS=5.0V)

Specification

Typ.

Item

Symbol

Unit

Condition

Min.

Max.

RIDopen

RID1

RID2

RID3

RID4

RID5

RID6

RID7

RID8

1000

-

50

kΩ

Ω

USB ID removal detection

-

797

557

440

390

287

200

180

124

102

68

Pull-down detection resistance

RID9

RID10

RID11

RID12

RID13

RID14

47

36.5

1

0

GND level detection

Ratio = 100xV(ID)/VCCIN [%]

ID port voltage rising

COMPH detection voltage ratio

RatioH

85

90

95

%

Note: The pull-down resistance is designed in 5 % accuracy to comply with the standard of MCPC (Mobile Computing Promotion Consortium), except

the 1kΩ resistor for RID_GND. The RID_GND resistance complies with the MHL (Mobile High-definition Link) standard in 20 % accuracy.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.5. DC/DC Converter

7.5.1. - Outline



Input Current Limit value setting: 96 mA to 16352 mA for VBUS and VCC

Charger supply voltage anti-collapse control.

Low power mode support

Include thermal protection and shutdown

7.5.2. Electrical Characteristics

Table 7-2 Electrical Characteristics for DC/DC Converter

Adapter=18.0V, Battery=7.4V, LX1=LX2=0.0V, GND=0V, Ta=25℃ (unless otherwise noted.)

Value

Typ.

Item

Symbol

Unit

Condition

Min.

Max.

USB 500mA Current Accuracy

USB 900mA Current Accuracy

BC1.2 1500mA Current Accuracy

USB-PD 3A Current Accuracy

USB-PD 5A Current Accuracy

Input Current Setting Range

Charge Current Setting LSB

I_USB500

I_USB900

I_USB1500

I_USB3000

I_USB5000

I_ADPRNG

I_ADPLSB

I_ADP1

I_ADP2

I_ADP3

I_ADP4

V_ADPTRNG

398

764

1380

2824

4792

96

448

832

1440

2912

4896

-

500

900

mA

V

REG0x07h/08h=01C0h

REG0x07h/08h=0340h

REG0x07h/08h=05A0h

REG0x07h/08h=0B60h

REG0x07h/08h=1320h

1500

3000

5000

16352

-

+2%

+3%

+5%

+10%

1.4

REG0x07h or REG0x08h

-

32

-2%

-3%

-5%

-10%

0.1

4096

2048

1024

512

-

Input Current Accuracy

(10mΩ current sense resistor)

IADP/RESET pin input Voltage range

IADP/RESET pin Current setting

Range

I_ADPTRNG

128

-

512

-

5120

-

mA

V

IADP/RESET pin Current setting step

I_ADPSTEP

Vreset_d

et

Vreset_re

l

-

RESET Detection Voltage

0.22

IADP/RESET voltage falling

IADP/RESET voltage rising

RESET release Voltage

0.44

100

-

V

RESET Detection duration time

T_RESET

μsec

Minimum System Voltage Setting

Range

V_MSVRNG

2.560

-

19.2

V

VSYSREG_SET=2,560 ~ 19,200mV,

64mV steps.

Minimum System Voltage Setting LSB

V_MSVLSB

V_MSV1

V_MSV2

V_MSV3

V_MSV4

-

64

-

mV

V

-2.0%

-1.0%

-2.0%

3.072

6.144

9.216

12.288

+2.0%

+1.0%

+2.0%

REG0x11h=0C00h

REG0x11h=1800h

REG0x11h=2400h

REG0x11h=3000h

Minimum System

Voltage accuracy

<Anti-Collapse Voltage>

VBUS

Anti-Collapse

Threshold

V_{anti_VBUS}

3.84

-100

3.84

-100

-

25.0

+100

25.0

+100

V

mV

V

REG0x0Dh

REG0x0Eh

Voltage Range

Anti-Collapse

Accuracy

VCC Anti-Collapse Threshold Voltage

Range

Threshold

Voltage V_{anti_VBUS_a}

cc

V_{anti_VCC}

Anti-Collapse

Accuracy

Threshold

Voltage V_{anti_VCC_ac}

mV

c

Switching Frequency 1

Switching Frequency 2

Switching Frequency 3

Switching Frequency 4

FOSC1

FOSC2

FOSC3

FOSC4

510

770

850

600

860

1000

1200

690

950

1150

1380

kHz

REG0x0Ch[3:2]=00b

REG0x0Ch[3:2]=01b

REG0x0Ch[3:2]=10b

REG0x0Ch[3:2]=11b

1020

HRDV1 PMOS RON

HRDV1 NMOS RON

LRDV1 PMOS RON

LRDV1 NMOS RON

HRDV2 PMOS RON

HRDV2 NMOS RON

LRDV2 PMOS RON

LRDV2 NMOS RON

R_HDRV1P

R_HDRV1N

R_LDRV1P

R_LDRV1N

R_HDRV2P

R_HDRV2N

R_LDRV2P

R_LDRV2N

-

6.0

0.7

7.5

0.9

6.0

0.7

7.5

0.9

10.0

1.3

12.0

1.4

10.0

1.3

12.0

1.4

Ω

Note: Resister address refer to extended commands

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.5.3. Detailed IADP input current limit settings



Input Current limit is set by external IADP/RESET pin.

This function is enabled by VM_CTRL_SET.EXTIADPEN bit =1.

Once the charger reset is released when this function is enabled, the corresponding input current value which

depends on the IADP/RESET voltage will be stored to the SEL_ILIM_VAL register. And this is used as the input

current limit. It can be overwritten through SMBus.

Table 7-3 IADP pin Input Current Limit settings

5632

1.37V

5120

4608

4096

3584

3072

2560

512mA/90mV

2048

1536

1024

0.44V

512

RESET

0.56V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

VIADP/RESET (V)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.6. Charger

7.6.1. - Outline



Supports battery insertion and removal detection.

Controls the VSYS output voltage with a deeply discharged battery.

JEITA compliant Battery Charging Profile with thermal control of the charging current and voltage

settings by measuring the temperature from the external thermistor



Supports battery supplement mode

Automatic or manual control of the Watch Dog Timer (via software) while Pre–charging and Fast-charging

7.6.2. Electrical Characteristics

Table 7-4 Electrical Characteristics for Charger

Adapter=18.0V, Battery=7.4V, LX1=LX2=0.0V, GND=0V, Ta=25℃ (unless otherwise noted.)

Value

Typ.

Item

Symbol

Unit

Condition

With Adapter Input

Min.

Max.

Battery Input Operating Range1

V_BATRNG

0.0

2.5

-

19.2

V

Without Adapter Input

Charge Voltage Setting Range

V_CVRNG

V_CVLSB

V_CV1S

2.560

-

19.200

-

V

mV

V

REG0x1A, REG0x1Bh or REG0x1Ch

Charge Voltage Setting LSB

16

-0.5%

2.56

4.192

8.400

12.592

16.800

-

+0.5%

19.2

REG0x1Ah/0x1Bh/0x1Ch=1060h

REG0x1Ah/0x1Bh/0x1Ch=20D0h

REG0x1Ah/0x1Bh/0x1Ch=3130h

REG0x1Ah/0x1Bh/0x1Ch=41A0h

REG0x1Dh

V_CV2S

V

Charge Voltage accuracy

V_CV3S

V

V_CV4S

V

VBAT OVP Detection range

Charge Current Setting Range

Charge Current Setting LSB

V_OVPRNG

V

I_CHGRNG

I_CHGLSB

I_CHG1

0

-

16384

-

mA

REG0x16h

64

-2%

-3%

-5%

-20%

-40%

0

4096

2048

1024

256

128

256

64

+2%

+3%

+5%

+20%

+40%

1024

-

REG0x16h=1000h

REG0x16h=0800h

REG0x16h=0400h

REG0x16h=0100h

REG0x16h=0080h

I_CHG2

Charge Current accuracy

(10mΩ current sense resistor, BATT >

Minimum System Voltage)

I_CHG3

I_CHG4

I_CHG5

Trickle Charge Current Setting Range I_TRCCHGRNG

REG0x14h or REG0x15h

Trickle Charge Current Setting LSB

Maximum Trickle Charge Current

(10mΩ current sense resistor, BATT

< Minimum System Voltage)

I_TRCCHGLSB

-

I_CHG6

-

1024

-

mA

REG0x14h or REG0x15h

Battery Temperature Threshold HOT1

Battery Temperature Threshold HOT2

Battery Temperature Threshold HOT3

Battery Temperature Threshold

COLD1

V_{TH_HOT1}

V_{TH_HOT2}

V_{TH_HOT3}

-

45

50

58

-

°C

OTP Programmable REG0x45h

OTP Programmable REG0x44h

OTP Programmable REG0x43h

V_{TH_COLD1}

V_{TH_COLD2}

Tbat

-

10

2

-

°C

V

OTP Programmable REG0x42h

OTP Programmable REG0x41h

Battery Temperature Threshold

COLD2

Battery Temperature Measurement

Acc

-2

-

+2

-

V_REF*0.9

5

Battery Open Detection Voltage

V_{TH_OPN}

Battery Short Current Detection

Battery Short Current Duration time

I_BATSHORT

T_BATSHORT

0

4

-

25,000

1020

mA

REG0x1Fh

msec REG0x10h[15:8]

Pre Charging Time

T_PRE

T_FAST

13.0

196

108

13

14.5

218

120

15

16

240

132

17

min

Fast Charging Time

High Temperature Protection Time

Charging Termination Delay Time

T_HTPRO

T_TOPOFF

min

sec

Over 58°C

Note: Resister address refer to extended commands

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.6.3. Battery Charging Profile

Figure 7-5 Battery Charging Profile

VBAT

VSYS

IBAT

VBAT x 1.15

VFASTCHG_R

EG_SET1,2,3

ICHG_SET

System Voltage

Charge Current

VSYSREG_SET

Ichg x Rds

VPRECHG_TH

_SET

Battery

Voltage

IPRECH_SET

ITERM_SET

ITRICH_SET

Time

(CC)

(CV)

TRICKLE

CHARGE

PRE

CHARGE

Done

(BGATE OFF)

FAST CHARGE

(BGATE ON)

The charging current is controlled by the battery temperature measured from the external thermistor.

In the low-temperature condition, the charging current is reduced to a half of the setting value (ICHG_SET).

Charging

Current

ICHG_SET

ICHG_SET/2

0

T1 T2

T4

Temperature of Battery Pack

The charging voltage is also reduced by the temperature as set by the control registers, VFASTCHG_REG_SET1/2/3.

Charging

Voltage

VFASTCHG

_REG_SET1

VFASTCHG

_REG_SET2

VFASTCHG

_REG_SET3

0

T1 T2

T3

T4

T5

Temperature of Battery Pack

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.7. Reverse DC/DC Converter

7.7.1. Outline



Charger provides a voltage output (Reverse Buck/Boost) via VBUS or/and VCC when an USB OTG device is connected.

7.7.2. Electrical Characteristics

Table 7-6 Electrical Characteristics for Reverse Buck/Boost

Adapter=18.0V, Battery=7.4V, LX1=LX2=0.0V, GND=0V, Ta=25℃ (unless otherwise noted.)

Value

Typ.

Item

Symbol

Unit Condition

Min.

Max.

Output Current Limit Setting Range

Output Current Limit Setting LSB

I_RADPRNG

I_RADPLSB

I_RADP1

I_RADP2

I_RADP3

0

-

4096

32

4096

2048

1024

512

8128

-

+2%

+3%

+5%

+10%

mA

REG0x09h

-2%

-3%

-5%

-10%

REG0x09h=1000h

Output Current Limit Accuracy

(10mΩ current sense resistor)

REG0x09h=0800h

REG0x09h=0400h

REG0x09h=0200h

I_RADP4

Output Voltage Setting 1

Output Voltage Setting 2

Output Voltage Setting 3

Output Voltage Setting 4

Output Voltage Setting 5

Output Voltage Setting Range

Output Voltage Setting LSB

V_ROUT1

V_ROUT2

V_ROUT3

V_ROUT4

V_ROUT5

4.95

5.15

8.91

11.88

19.8

4.032

-

5.0

5.2

9.0

12.0

20.0

-

5.05

5.25

9.09

12.12

20.2

22.016

-

V

REG0x19h=1380h

REG0x19h=1440h

REG0x19h=2340h

REG0x19h=2F00h

REG0x19h=4E40h

V_ROUTRNG

V_ROUTLSB

V

mV

REG0x19h

64

VBUS_

UVLO

VCC_U

VLO

VBUS Buck/Boost Output Short

Circuit Protection.

V_Rscp

V_Rovp

-

V

V_ROUT

1.1

x

VBUS Buck/Boost OVP Voltage

-

V

VBUS Buck/Boost OVP Detection V_Rovp_hy

Hysteresis Range

V_ROUT

1.05

x

mV

s

Note: Resister address refer to extended commands

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.8. 12-bit ADC

7.8.1. Outline



12-bit Successive Approximation Register A/D Converter

Input Voltage range: 2.0 to 19.2V (BATT)

Input Voltage range: 2.0 to 25V (VBUS, VCC, ACP, SRP)

Input Voltage range: 0.1 to 1.4V (TSENSE)

Input Voltage range: 0.1 to 1.4V (IADP/RESET)

Current monitor range: 0.3 to 16.384A (IACP)

Current monitor range: 0.3 to 25A (IBAT)

7.8.2. Electrical Characteristics

Table 7-7 Electrical Characteristics for 12-bit SAR-ADC

(Unless otherwise specified, Ta=25C, VREF=1.5V)

Specification

Parameter

Symbol

Unit

Condition

Min

Typ

Max

<12-bit SAR ADC>

Resolution

RES

-

12

-

bit

µs

Conversion Period

Gain Error 1

TCONV

20

BATT,VBUS,VCC,ACP,

SRP=5V and 15V

Gerr1

Gerr2

−1.1

-

+1.1

%

TSENSE,IADP/RESET

=0.5V and 1.0V

Gain Error 2

-

Gain Error 3

VOffset error

IOffset error

Gerr3

Voffset

Ioffset

−1.1

-110

+1.1

110

%

IACP,IBAT=1.5A and 8A

mV

mA

-

7.8.3. Functions

SAR-ADC measures the 10 following factors by time sharing. These factors can be disabled by SMBus command.

The actual value and the 2-sample moving average value are read by SMBus command.

#

Factor

Conversion Period

Conversion Interval

1

VBUS or VCC

20us

VBUS 400us

VCC 400us

200us

2

3

4

5

6

7

8

9

IACP

VACP

IBAT(+)

IBAT(-)

VBATT

IACP

VSRP

20us

IADP/RESET or TSENSE

IADP/RESET 200us

TSENSE 1s

200us

10

IBAT(-)

20us

VBUS or VCC

20us

IACP

VACP

20us

IBAT(+)

IBAT(-)

VBATT

IACP

20us

VSRP

IADP/RESET or TSENSE

IBAT(-)

The power calculation of PMON is carried out from IACP, VACP, IBAT, VBATT.

PACP = IACP * VACP

PBAT = IBAT * VBATT

PMON = PACP + PBATT

PMON power change can be observed when the value is stable longer than the “Conversion Interval”, 200us.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.9. Power On

Whenever BD99954 receives power from the adapter or battery, BD99954 wakes up and starts loading data from the OTP. After

OTP loading is completed, BD99954 is in standby position.

7.9.1. VBAT power on and VBUS/VCC plugged-in

At the first VBAT power on, BD99954 starts OTP loading. And when VBUS or VCC is eventually plugged in, BD99954sserts ACOK

and starts the BC1.2 Detection sequence. After the BC1.2 Detection is completed, BD99954 limits the input current, reflects the

BC1.2 setting and starts charging.

7.9.2. VBUS/VCC plugged-off

When VBUS plugged off, BD99954 deasserts AC_OK and limits input current as IADP external pin or minimum setting (it is

programmable). And then VBUS or VCC plugged in again, BD99954sserts AC_OK and starts BC1.2 detection.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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7.9.3. VBUS and VCC plugged in

When VBUS plugged in and then VCC plugged in, BD99954 selects VBUS or VCC with priority setting. If VCC is 1^stpriority

(programmable), BD99954 changes power source from VBUS to VCC. If VBUS is 1^stpriority BD99954 keeps power source VBUS.

Each case AC_OK keeps “H”.

VBAT

VBUS

VCC

VBUS_UVLO

VCC_UVLO

VREF

VREF_UVLO

AC_OK

Keep "H" when VCC pluged in because already VBUS pluged in.

OSC

Stable

OTP Load

Loaded.

Charger Reset

DCDC Control

DCDC start up

VBUS BC1.2 Detection

VCC BC1.2 Detection

Input Current Limit

Deadbattery Comparator

Detected

Initial

Detecting or Waiting

Resistor or Minimum

Change to VCC Input Current Limit

with Peak Control

Detected or Waited

VBUS Input Current Limit

with Peak Control

Deasserted ( VBAT is OK )

BC1.2 Setting

Register Setting

▲EC Write by SMBus.

with Peak Control

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8. Control Specification

BD99954 has several control registers to set configurations or to sense the hardware status for the internal function

operations. Host is able to write to or read from the control registers via SMBus (friendly I2C).

8.1. SMBus Communication

BD99954 operates in slave mode on the SMBus and supports Layer 2 communication protocol.

8.1.1. SMBus Slave Address

Slave Address for the BD99954 is 0001_001.

The register address is set by “Slave Address”. The “Slave Address” is also used as the start address of contiguous

addressing for multiple write or read access.

8.2. SMBus Protocols

The following is a description of the various SMBus protocols. BD99954 supports the protocols defined in this section.

BD99954 does not support all the protocols defined in the SMBus Specification. The results returned by such a device to a

protocol it does not support is undefined.

Below is a key to the protocol diagrams in this section. Not all protocol elements will be presented in every command. For

instance, not all packets are required to include the packet error code.

S

Start Condition

Sr

Repeated Start Condition

Rd Read (bit value of 1)

Wr Write (bit value of 0)

x

Shown under a field indicates that that field is required to have the value of ‘x’

Acknowledge (this bit position may be‘0’ for an ACK)

Acknowledge (this bit position may be‘1’ for a NACK)

Stop Condition

A

N

P

PEC Packet Error Code

Master (SMBus Host) to Slave

Slave (SMBus Device) to Master

BD99954 supports following protocols.



Write Word

Read Word

8.2.1. Write Word

The first byte of a Write Word access is the command code. The next are the high data byte and low data byte to be written.

In this example the master asserts the slave device address followed by the write bit. The device acknowledges and the

master delivers the command code. The slave again acknowledges before the master sends the data bytes. The slave

acknowledges each byte, and the entire transaction is finished with a STOP condition.

BD99954 does not support PEC.

1

S

7

1 1

Slave Address W A

8

1

8

1

A

8

1 1

A P

Command Code

A Data Low Byte

Data High Byte

SMBus Write Word

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.2.2. Read Word

Reading data is slightly more complicated than writing data. First the host must write a command to the slave device. Then it

must follow that command with a repeated START condition to denote a read from that device’s address. The slave then

returns one high and low byte of data.

Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read

transfer. BD99954 does not support PEC.

1

7

1

8

1

S

Slave Address

A

Command Code

A

W

1

7

1

8

1

8

1 1

Sr Slave Address

A

Data Low Byte

A Data High Byte

N P

R

SMBus Read Word

8.2.3. SMBus Communication Timing Waveforms and Timing Specification

Table 8-1 Electrical Characteristics for SMBus Timing Specification

(Unless otherwise specified, Ta=25C, VREF=1.5V)

Specification

Parameter

Symbol

Unit

Condition

Min

Typ

Max

<SMBus>

10

0.0

2.1

250

300

4

-

400

kHz

V

SMBus Frequency

FSMBus

VINL

0.8

SDA/SCL Input Low Voltage

SDA/SCL Input High Voltage

SDA Hold Time from SCL

5.5

V

VINH

-

ns

µs

TH(DAT)

TSU(DAT)

TH(STA)

TSU(STA)

TSU(STOP)

TBUF

SDA Setup Time from SCL

Start Condition Hold Time from SCL

Start Condition Setup Time from SCL

Stop Condition Setup Time from SCL

Bus Free Time

4.7

4

4.7

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.3. Command Code

BD99954 has 3 command maps, "Battery Charger Commands", "Extended Commands" and "Debug Commands". All commands

are addressed within 00h ~ 7Fh address area. And 80h ~ FFh address is a mirror of 00h ~ 7Fh.

"Battery Charger Commands" is a subset of "Smart Battery Charger Specification Revision 1.1."

"Extended Commands" is for charger function enhancement.

"Debug Commands" are used for debug purpose or in production test.

These are selectable by MAP_SET command.

PROTECT_SET : 16'h0000

MAP_SET : 16'h0000

PROTECT_SET : 16'h0000

MAP_SET

: 16'h0001

Battery Charger

Commands

Extended

Commands

Subset of

“Smart Battery Charger Spec. Rev. 1.1”

For charger function enhancement.

- PMON, IOUT

PROTECT_SET : ****

MAP_SET

: ****

- PROCHOT

- Power Path Management

- USB BC1.2 Detection

- Thermal Charging Profile

- etc.

Debug

Commands

For debug and production test.

8.3.1. Battery Charger Commands

Following is a table of "Battery Charger Commands" which BD99954 supports. "Battery Charger Commands" is subset of "Smart

Battery Charger Specification Revision 1.1."

Note: Reserved command should not be accessed. If accessed, operation is not guaranteed.

Code

14h

Command

Protocols Byte

Size

Description

ChargingCurrent Read/Write

Word

2

The Battery, System Host or other master device sends the desired charging

rate (mA).

This command is a mirror of ICHG_SET command of the extended

command.

15h

ChargingVoltage Read/Write

Word

2

The Battery, System Host or other master device sends the desired charging

voltage to the Smart Battery Charger (mV).

This command is a mirror of VFASTCHG_REG_SET1 command of the

extended command.

3Ch

3Dh

3Eh

3Fh

IBUS_LIM_SET

ICC_LIM_SET

Read/Write

Word

2

VBUS Input Current Limit Setting.

This command is a mirror of IBUS_LIM_SET command of the extended

command.

VCC Input Current Limit Setting.

This command is a mirror of ICC_LIM_SET command of the extended

command.

Access Un-protect Setting for Address 3Fh

This command is a mirror of PROTECT_SET command of the extended

command.

Change Command Code Map.

This command is a mirror of MAP_SET command of the extended

command.

Read/Write

Word

PROTECT_SET Read/Write

Word

MAP_SET

Read/Write

Word

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.3.2. Extended Commands

Following is a table of "Extended Commands" which BD99954 supports. "Extended Commands" is for charger function

enhancement.

Note: Reserved command should not be accessed. If accessed, operation is not guaranteed.

Code

Command

Protocols

Byte

Size

2

Description

Charger State Machine Status

VBAT and VSYS Status

VBUS and VCC Status

Charger Operation Status

Charger WDT and Thermal WDT Status

Actual Input Current Limit

Selected Input Current Limit

VBUS Input Current Limit Setting

VCC Input Current Limit Setting

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

CHGSTM_STATUS

VBAT/VSYS_STATUS

VBUS/VCC_STATUS

CHGOP_STATUS

WDT_STATUS

Read Word

CUR_ILIM_VAL

SEL_ILIM_VAL

IBUS_LIM_SET

ICC_LIM_SET

IOTG_LIM_SET

VIN_CTRL_SET

CHGOP_SET1

CHGOP_SET2

Read/Write Word

OTG Output Current Limit Setting

VBUS and VCC Control Setting

Charger Operation Control Setting 1

Charger Operation Control Setting 2

VBUS Collapse Detect Threshold Voltage Setting

VCC Collapse Detect Threshold Voltage Setting

Charger WDT Setting

Battery temperature and Battery short current WDT Setting

VSYS Regulation Setting

VSYS Valid Threshold High Setting (Hysteresis)

VSYS Valid Threshold Low Setting (Hysteresis)

Trickle-charge Current Setting

VBUSCLPS_TH_SET

VCCCLPS_TH_SET

CHGWDT_SET

BATTWDT_SET

VSYSREG_SET

VSYSVAL_THH_SET

VSYSVAL_THL_SET

ITRICH_SET

IPRECH_SET

ICHG_SET

ITERM_SET

Pre-charge Current Setting

Fast-charge Current Setting

Charge Termination Current Setting

Pre-charge Voltage Threshold Setting

Reverse Buck Boost Voltage Setting

Fast Charge Voltage Regulation Setting 1

Fast Charge Voltage Regulation Setting 2 (Hot 1)

Fast Charge Voltage Regulation Setting 3 (Hot 2)

Re-charge Battery Voltage Setting

Battery Over Voltage Protection Setting

Battery Short Current Protection Setting

PROCHOT# pin Control Setting

Peak Input Current Threshold Setting for PROCHOT#

Average Input Current Threshold Setting for PROCHOT#

Dis-charge Current Threshold Setting for PROCHOT#

VSYS Voltage Threshold Setting for PROCHOT#

PMON and IOUT Output Control Setting

PMON DAC Input Value

VPRECHG_TH_SET

VRBOOST_SET

VFASTCHG_REG_SET1

VFASTCHG_REG_SET2

VFASTCHG_REG_SET3

VRECHG_SET

VBATOVP_SET

IBATSHORT_SET

PROCHOT_CTRL_SET

PROCHOT_ICRIT_SET

PROCHOT_INORM_SET Read/Write Word

PROCHOT_IDCHG_SET Read/Write Word

2

PROCHOT_VSYS_SET

PMON_IOUT_CTRL_SET Read/Write Word

Read/Write Word

PMON_DACIN_VAL

IOUT_DACIN_VAL

VCC_UCD_SET

VCC_UCD_STATUS

VCC_IDD_STATUS

VCC_UCD_FCTRL_SET

Read Word

Read/Write Word

Read Word

Read/Write Word

IOUT DAC Input Value

BC1.2 Charger Detector on the VCC side Setting

BC1.2 Charger Detect Status on the VCC side

ID Detect Status on the VCC side

BC1.2 Charger Detector on the VCC side Manual Control

Setting

2

2Ch

VCC_UCD_FCTRL_EN

Read/Write Word

2

BC1.2 Charger Detector on the VCC side Manual Control

Enable

2Dh

2Eh

2Fh

30h

31h

32h

33h

(reserved)

-

2

-

VBUS_UCD_SET

VBUS_UCD_STATUS

VBUS_IDD_STATUS

Read/Write Word

Read Word

BC1.2 Charger Detector on the VBUS side Setting

BC1.2 Charger Detect Status on the VBUS side

ID Detect Status

BC1.2 Charger Detector on the VBUS side Manual Control

Setting

VBUS_UCD_FCTRL_SET Read/Write Word

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Code

34h

Command

Protocols

Byte

Size

2

Description

VBUS_UCD_FCTRL_EN

Read/Write Word

BC1.2 Charger Detector on the VBUS side Manual Control

Enable

35h

36h

37h

38h

39h

3Ah

(reserved)

CHIP_ID

CHIP_REV

IC_SET1

-

2

-

2

-

Read Word

Read/Write Word

Chip ID

Chip Revision

1-Cell mode setting, ACP discharge control and ACOK

control setting.

3Bh

3Ch

3Dh

3Eh

3Fh

IC_SET2

SYSTEM_STATUS

SYSTEM_CTRL_SET

PROTECT_SET

MAP_SET

Read/Write Word

Read Word

Read/Write Word

2

IC Setting Register for debug and production test.

System Power-on Status

Software reset and re-load OTP

Access Un-protect Setting for Address FCh and FEh

Change Command Code Map to Debug Command Code

Map

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

VM_CTRL_SET

Read/Write Word

2

SAR-ADC Measurement Control Setting

JEITA Temperature Window Setting 1

JEITA Temperature Window Setting 2

JEITA Temperature Window Setting 3

JEITA Temperature Window Setting 4

JEITA Temperature Window Setting 5

Battery Current (Charge) Interrupt Threshold Setting

Battery Current (Dis-charge) Interrupt Threshold Setting

Battery Voltage Interrupt Threshold Setting

Battery Temperature Interrupt Threshold Setting

Input Current (between ACP-ACN) Interrupt Threshold

Setting

THERM_WINDOW_SET1 Read/Write Word

THERM_WINDOW_SET2 Read/Write Word

THERM_WINDOW_SET3 Read/Write Word

THERM_WINDOW_SET4 Read/Write Word

THERM_WINDOW_SET5 Read/Write Word

IBATP_TH_SET

IBATM_TH_SET

VBAT_TH_SET

THERM_TH_SET

IACP_TH_SET

Read/Write Word

4Bh

4Ch

4Dh

4Eh

4Fh

VACP_TH_SET

VBUS_TH_SET

VCC_TH_SET

VSYS_TH_SET

EXTIADP_TH_SET

Read/Write Word

2

Input Voltage (ACP) Interrupt Threshold Setting

VBUS Voltage Interrupt Threshold Setting

VCC Voltage Interrupt Threshold Setting

VSYS Voltage Interrupt Threshold Setting

IADP (Input current Limit setting pin) Voltage Interrupt

Threshold Setting

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

IBATP_VAL

IBATP_AVE_VAL

IBATM_VAL

IBATM_AVE_VAL

VBAT_VAL

VBAT_AVE_VAL

THERM_VAL

VTH_VAL

Read Word

Read/Write Word

Read Word

2

Battery Current (Charge) Measurement Value

Battery Current (Charge) Measurement Average Value

Battery Current (Dis-charge) Measurement Value

Battery Current (Dis-charge) Measurement Average Value

Battery Voltage Measurement Value

Battery Voltage Measurement Average Value

Temperature Measurement Value

Thermistor Measurement Voltage Value

Input Current (between ACP-ACN) Measurement Value

Input Current (between ACP-ACN) Measurement Average

Value

IACP_VAL

IACP_AVE_VAL

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

VACP_VAL

VACP_AVE_VAL

VBUS_VAL

VBUS_AVE_VAL

VCC_VAL

VCC_AVE_VAL

VSYS_VAL

VSYS_AVE_VAL

EXTIADP_VAL

Read Word

2

Input Voltage (ACP) Measurement Value

Input Voltage (ACP) Measurement Average Value

VBUS Voltage Measurement Value

VBUS Voltage Measurement Average Value

VCC Voltage Measurement Value

VCC Voltage Measurement Average Value

VSYS Voltage Measurement Value

VSYS Voltage Measurement Average Value

IADP (Input current Limit setting pin) Voltage Measurement

Value

63h

EXTIADP_AVE_VAL

Read Word

2

IADP (Input current Limit setting pin) Voltage Measurement

Average Value

64h

65h

66h

67h

68h

69h

6Ah

VACPCLPS_TH_SET

(reserved)

Read/Write Word

2

-

VACP Collapse Detect Threshold Voltage Setting

-

(reserved)

INT0_SET

INT1_SET

-

Read/Write Word

2

1st Level Interrupt Setting

2nd Level Interrupt Setting 1 (VBUS)

2nd Level Interrupt Setting 2 (VCC)

INT2_SET

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Code

Command

Protocols

Byte

Description

Size

2

-

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

INT3_SET

INT4_SET

INT5_SET

INT6_SET

INT7_SET

INT0_STATUS

INT1_STATUS

INT2_STATUS

INT3_STATUS

INT4_STATUS

INT5_STATUS

INT6_STATUS

INT7_STATUS

REG0

REG1

OTPREG0

OTPREG1

SMBREG

(reserved)

Read/Write Word

-

2nd Level Interrupt Setting 3 (Battery)

2nd Level Interrupt Setting 4 (VSYS)

2nd Level Interrupt Setting 5 (Charger)

2nd Level Interrupt Setting 6 (Charger)

2nd Level Interrupt Setting 7 (SAR-ADC)

1st Level Interrupt Status

2nd Level Interrupt Status 1 (VBUS)

2nd Level Interrupt Status 2 (VCC)

2nd Level Interrupt Status 3 (Battery)

2nd Level Interrupt Status 4 (VSYS)

2nd Level Interrupt Status 5 (Charger)

2nd Level Interrupt Status 6 (Charger)

2nd Level Interrupt Status 7 (SAR-ADC)

Reserved Register 0 (for future use)

Reserved Register 1 (for future use)

Input current limit degradation setting.

Reserved OTP-loaded Register 1 (for future use)

Power Save Mode Setting.

-

2

DEBUG_MODE_SET

Read/Write Word

Debug Mode Setting

8.3.3. Debug Commands

Following is a table of "Debug Commands" which BD99954 supports. "Debug Commands" is used for debug purpose or in

production test.

Note: Reserved command should not be accessed. If accessed, operation is not guaranteed.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.4. Battery Charger Commands Description

Following is a description of " Battery Charger Commands " that are supported by BD99954.

8.4.1. ChargingCurrent

The Battery, System Host or other master device sends the desired charging rate (mA).

Command Code:

Bus Protocol:

Bit

14h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

ICHG_SET[13]

ICHG_SET[12]

ICHG_SET[11]

ICHG_SET[10]

ICHG_SET[9]

ICHG_SET[8]

ICHG_SET[7]

ICHG_SET[6]

reserved

Charging current setting.

0 to 16,320mA, 64mA steps.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.4.2. ChargingVoltage

The Battery, System Host or other master device sends the desired charging voltage to the Smart Battery Charger (mV).

Command Code:

Bus Protocol:

Bit

15h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VFASTCHG_REG_SET1[14]

VFASTCHG_REG_SET1[13]

VFASTCHG_REG_SET1[12]

VFASTCHG_REG_SET1[11]

VFASTCHG_REG_SET1[10]

VFASTCHG_REG_SET1[9]

VFASTCHG_REG_SET1[8]

VFASTCHG_REG_SET1[7]

VFASTCHG_REG_SET1[6]

VFASTCHG_REG_SET1[5]

VFASTCHG_REG_SET1[4]

reserved

Charging Regulation Voltage.

3,072 to 19,200mV, 16mV steps.

The register range : 0 to 32,752mV.

But the actual range : 3,072 to 19,200mV.

4

3

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.4.3. IBUS_LIM_SET

VBUS Input Current Limit Setting

Command Code:

Bus Protocol:

3Ch

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

IBUS_LIM_SET1[13]

IBUS_LIM_SET1[12]

IBUS_LIM_SET1[11]

IBUS_LIM_SET1[10]

IBUS_LIM_SET1[9]

IBUS_LIM_SET1[8]

IBUS_LIM_SET1[7]

IBUS_LIM_SET1[6]

IBUS_LIM_SET1[5]

reserved

VBUS input current limitation.

0 to 16,352mA, 32mA steps.

4

3

reserved

2

reserved

1

reserved

0

reserved

8.4.4. ICC_LIM_SET

VCC Input Current Limit Setting

Command Code:

Bus Protocol:

3Dh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

ICC_LIM_SET1[13]

ICC_LIM_SET1[12]

ICC_LIM_SET1[11]

ICC_LIM_SET1[10]

ICC_LIM_SET1[9]

ICC_LIM_SET1[8]

ICC_LIM_SET1[7]

ICC_LIM_SET1[6]

ICC_LIM_SET1[5]

reserved

VCC input current limitation.

0 to 16,352mA, 32mA steps.

4

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.4.5. PROTECT_SET

Access Un-protect Setting for the “debug command map” (debug and production test only)

Command Code:

Bus Protocol:

Bit

3Eh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

PROTECT_SET[15]

PROTECT_SET[14]

Access Un-protect Setting for the “debug command map”

(debug and production test only)

PROTECT_SET[13]

PROTECT_SET[12]

PROTECT_SET[11]

PROTECT_SET[10]

PROTECT_SET[9]

PROTECT_SET[8]

PROTECT_SET[7]

PROTECT_SET[6]

PROTECT_SET[5]

PROTECT_SET[4]

PROTECT_SET[3]

PROTECT_SET[2]

PROTECT_SET[1]

PROTECT_SET[0]

4

3

2

1

0

8.4.6. MAP_SET

Change Command Code Map

Command Code:

Bus Protocol:

3Fh

Read/Write Word

Description

Change Command Code Map

Bit

15

14

13

12

11

10

9

Symbol

MAP_SET [15]

MAP_SET [14]

MAP_SET[13]

MAP_SET[12]

MAP_SET[11]

MAP_SET[10]

MAP_SET[9]

MAP_SET[8]

MAP_SET[7]

MAP_SET[6]

MAP_SET[5]

MAP_SET[4]

MAP_SET[3]

MAP_SET[2]

MAP_SET[1]

MAP_SET[0]

8

7

6

5

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5. Extended Commands Description

Following is a description of "Extended Commands" that are supported by BD99954.

8.5.1. CHGSTM_STATUS

Charger State Machine Status

Command Code:

Bus Protocol:

Bit

00h

Read Word

Symbol

Description

15

14

13

12

11

10

9

reserved

PREV_CHGSTM_STATE[6]

PREV_CHGSTM_STATE[5]

PREV_CHGSTM_STATE[4]

PREV_CHGSTM_STATE[3]

PREV_CHGSTM_STATE[2]

PREV_CHGSTM_STATE[1]

PREV_CHGSTM_STATE[0]

reserved

The previous state of the charger state-machine.

8

7

6

CHGSTM_STATE[6]

The current state of the charger state-machine.

5

CHGSTM_STATE[5]

4

CHGSTM_STATE[4]

3

CHGSTM_STATE[3]

2

CHGSTM_STATE[2]

1

CHGSTM_STATE[1]

0

CHGSTM_STATE[0]

State definition.

CHGSTM_STATE

State Name

Description

PREV_CHGSTM_STATE

00h

01h

02h

03h

04h

05h

08h

09h

10h

11h

12h

13h

14h

15h

18h

20h

21h

22h

23h

24h

25h

28h

40h

Suspend

Trickle-Charge

Pre-Charge

Fast-Charge

Top-off

Done

OTG

OTG Done

Suspend charging

Trickle-charging

Pre-charging

Fast Charging

Reached to Termination Current

Charging finished

USB On The Go (Reverse Buck Boost Operation)

OTG Done

Temperature Error 1

Temperature Error 2

Temperature Error 3

Temperature Error 4

Temperature Error 5

Temperature Error 6

Temperature Error 7

Thermal Shut Down 1

Thermal Shut Down 2

Thermal Shut Down 3

Thermal Shut Down 4

Thermal Shut Down 5

Thermal Shut Down 6

Thermal Shut Down 7

Battery Error

Out of standard temperature while Suspend State

Out of standard temperature while Trickle-Charge State

Out of standard temperature while Pre-Charge State

Out of standard temperature while Fast-Charge State

Out of standard temperature while Top-off State

Out of standard temperature while after Top-off State (DONE)

Out of standard temperature while OTG State

Thermal Shut Down while Suspend State

Thermal Shut Down while Trickle-Charge State

Thermal Shut Down while Pre-Charge State

Thermal Shut Down while Fast-Charge State

Thermal Shut Down while Top-off State

Thermal Shut Down after Top-off State (DONE)

Thermal Shut Down while OTG State

Battery Error

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Battery Error

(40h)

(0)

(13)

(10)

(12)

Suspend

(00h)

Thermal Shut Down 1

(20h)

(11)

Temperature Error 1

(10h)

(1)

(12)

Trickle-Charge

(01h)

Thermal Shut Down 2

(21h)

Temperature Error 2

(11h)

(12)

(2)

(12)

Pre-Charge

(02h)

Thermal Shut Down 3

(22h)

Temperature Error 3

(12h)

(3)

(4)

(5)

(12)

Fast-Charge

(03h)

Thermal Shut Down 4

(23h)

Temperature Error 4

(13h)

(7)

(10)

(12)

Top-off

(04h)

Thermal Shut Down 5

(24h)

(11)

Temperature Error 5

(14h)

(12)

(6)

(10)

(12)

Done

(05h)

Thermal Shut Down 6

(25h)

Temperature Error 6

(15h)

(12)

(10)

(12)

OTG

(08h)

Thermal Shut Down 7

(28h)

(8)

Temperature Error 7

(18h)

OTG Done

(09h)

(9)

(12)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Arc Condition

#

to next state

back to previous state

(0)

CHG_EN is 0, disabled or USB_SUS is 1, suspended.

-----

or VBUS and VCC and VACP are undetected or disabled.

or Thermistor is open.

or Power Path is changed.

or Anti-collapse is occurred.

or VSYS SCP timer is expired (20ms).

VBUS or VCC or VACP detected.

and SDP_CHG_TRIG bit set if SDP_CHG_TRIG_EN=1 and

SDP port detected.

(1)

-----

and Charge enable.

and DCDC Soft-started.

and State Transition Timer expired (25ms).

and No anti-collapse occurred.

and No Vsys short occurred.

(2)

(3)

VBAT > VPRECHG_TH_SET

and State Transition Timer expired (25ms).

-

VBAT <= VPRECHG_TH_SET

and State Transition Timer expired (25ms).

VBAT > VSYSREG_SET

VBAT <= VSYSREG_SET

and AUTO_FST=1

and State Transition Timer expired (25ms).

ITERM comparotor deasserted or VBAT <=

Re-charge Battery Voltage

(4)

ITERM comparotor asserted.

and AUTO_TOF=1

and State Transition Timer expired (25ms).

and VBAT > Re-charge Battery Voltage

and State Transition Timer expired (25ms).

Charging Termination Timer expired (15s).

(5)

(6)

(7)

-----

VBAT <= Re-charge Battery Voltage

and State Transition Timer expired (25ms).

-----

OTG Device is detected or VRBOOST_EN is enabled.

and VRBOOST_TRIG=1

and VBUS and VCC and VACP is undetected.

and Power Path with OTG Device is enabled,

VBUS_EN/VCC_EN=1

and State Transition Timer expired (25ms).

OTG Device is undetected or VRBOOST_EN is disabled -----

or VRBOOST_TRIG=0.

(8)

and State Transition Timer expired (25ms).

(9)

State Transition Timer expired (25ms).

and Reverse Buck Boost Voltage is under UVLO level.

TSD comparator asserted.

-----

(10)

(11)

(12)

TSD comparator de-asserted.

and State Transition Timer expired (25ms).

Thermal range isn't HOT3 and COLD2.

and State Transition Timer expired (25ms).

Thermal range is HOT3 or COLD2.

and State Transition Timer expired (25ms).

Charger WDT is expired or Thermal WDT is expired

or VBAT >= Battery Over voltage

-----

(13) <Charging>

VBAT < Battery Over voltage

-----

and Charge is disabled or suspended.

Or VBUS and VCC and VACP are undetected or disabled.

Or Thermistor is open.

Or Power Path is changed.

<OTG>

OTG Device is undetected or RBOOST_EN is disabled.

or USB_SUS=1, suspended.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.2. VBAT/VSYS_STATUS

VBAT and VSYS Status

Command Code:

Bus Protocol:

01h

Read Word

Bit

Symbol

Description

VSYS over-voltage status.

“1”: VSYS > VSYS_OVP / “0”: VSYS < VSYS_OVP

15

VSYS_OV

DCDC Soft-Start completion status.

“1”: Soft-Start finished / “0”: Not finished.

VSYS short-circuit detection status.

“1”: VSYS SCP timer expired. / “0”: Normal operation.

VSYS UVLO detection status.

14

13

12

VSYS_SSD

VSYS_SCP

VSYS_UVN

“1”: Low voltage. / “0”: Normal voltage.

11

10

9

8

7

reserved

Battery short-circuits detection status.

“1”: Battery Short Current Detected / “0”: Normal operation

6

IBAT_SHORT

5

4

reserved

VBAT over-voltage Status.

“1”: VBAT > VBAT_OVP / “0”: VBAT < VBAT_OVP with Hysteresis

3

VBAT_OV

2

1

reserved

Dead Battery status.

0

DEAD_BAT

“1”: Dead Battery, VBAT < VSYSREG_SET, Detected / “0”: Normal

operation, VBAT >= VSYSREG_SET.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.3. VBUS/VCC_STATUS

VBUS and VCC Status

Command Code:

Bus Protocol:

02h

Read Word

Bit

15

14

13

Symbol

Description

reserved

VACP_detection status.

“1”: VACP detected (over UVLO level) / “0”: not detected or low level.

12

VACP_DET

VCC/VACP over-voltage status.

"1":VCC > VCC_OVP / "0":Normal voltage. (When VCC_EN = 1)

"1":VACP > VCC_OVP / "0":Normal voltage.

(When VCC_EN = VBUS_EN = 0)

11

VCC_OVP

VCC/VACP input current limit control status.

“1”: VCC input current limit controlled. / “0”: No. (When VCC_EN = 1)

“1”: VACP input current limit controlled. / “0”: No.

(When VCC_EN = VBUS_EN = 0)

10

ILIM_VCC_MOD

VCC/VACP anti-collapse status.

“1”: VCC Anti-collapse / “0”: normal operation. (When VCC_EN = 1)

“1”: VACP Anti-collapse / “0”: normal operation.

(When VCC_EN = VBUS_EN = 0)

VCC detection status.

“1”: VCC detected (over UVLO level) / “0”: not detected or low level.

9

8

VCC_CLPS

VCC_DET

7

6

5

4

reserved

VBUS over -voltage status.

3

2

1

0

VBUS_OVP

“1”: VBUS > VBUS_OVP / “0”: Normal voltage.

VBUS current limit control statusStatus.

“1”: Limit controlled. / “0”: No.

VBUS anti-collapse status.

“1”: Anti-collapse / “0”: normal operation.

ILIM_VBUS_MOD

VBUS_CLPS

VBUS_DET

VBUS detection status.

“1”: VBUS detected (over UVLO level) / “0”: not detected or low level.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.4. CHGOP_STATUS

Charger Operation Status

Command Code:

Bus Protocol:

03h

Read Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

BATTEMP[2]

BATTEMP[1]

BATTEMP[0]

reserved

Battery temperature range and the thermistor status.

Please see next table.

8

7

Re-charge voltage detection status.

“1”: VBAT < VRECHG_SET / “0”: VBAT keeps enough voltage.

6

VRECHG_DET

5

4

3

2

reserved

Reverse Buck Boost UVLO detection status.

“1”: Normal voltage. / “0”: Low voltage.

Reverse Buck Boost status.

1

0

RBOOST_UV

RBOOSTS

“1”: Boosting / “0”: Not boosting.

BAT_TEMP

Temperature Range

Room Temp

HOT1

HOT2

HOT3

COLD1

COLD2

Temp. Disable

Battery Open

Description

T2 < Tbat < T3

T3 < Tbat < T5

T5 < Tbat < T4

T4 < Tbat

0h

1h

2h

3h

4h

5h

6h

7h

T1 < Tbat < T2

Tbat < T1

Disable thermal control (No Thermistor)

TSENSE_BAT port is open.

Register Name

Description

Default Value

C6h ( 2 deg.)

C3h ( 5 deg.)

BEh (10 deg.)

BBh (13 deg.)

9Eh (42 deg.)

9Bh (45 deg.)

91h (55 deg.)

8Eh (58 deg.)

9Dh (47 deg.)

96h (50 deg.)

Note

T1 in JEITA profile

T2 in JEITA profile

T3 in JEITA profile

T4 in JEITA profile

Between T3 and T4

TMPTHR1A[7:0]

TMPTHR1B[7:0]

TMPTHR2A[7:0]

TMPTHR2B[7:0]

TMPTHR3A[7:0]

TMPTHR3B[7:0]

TMPTHR4A[7:0]

TMPTHR4B[7:0]

TMPTHR5A[7:0]

TMPTHR5B[7:0]

Lower threshold of T1

Upper threshold of T1

Lower threshold of T2

Upper threshold of T2

Lower threshold of T3

Upper threshold of T3

Lower threshold of T4

Upper threshold of T4

Lower threshold of T5

Upper threshold of T5

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.5. WDT_STATUS

Charger WDT and Battery Temperature WDT Status

Command Code:

Bus Protocol:

Bit

04h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

THERMWDT_VAL[7]

THERMWDT_VAL[6]

THERMWDT_VAL[5]

THERMWDT_VAL[4]

THERMWDT_VAL[3]

THERMWDT_VAL[2]

THERMWDT_VAL[1]

THERMWDT_VAL[0]

CHGWDT_VAL[7]

CHGWDT_VAL[6]

CHGWDT_VAL[5]

CHGWDT_VAL[4]

CHGWDT_VAL[3]

CHGWDT_VAL[2]

CHGWDT_VAL[1]

CHGWDT_VAL[0]

Current Battery Temperature Watch-dog Timer Count Value

0 to 255 minutes, 1-minute steps.

Current Charge Watch-dog Timer Count Value

For pre-charging, 0 to 255 minutes, 1-minute steps.

For fast-charging, 0 to 1020 minutes, 4-minutes steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.6. CUR_ILIM_VAL

Actual Input Current Limit

Command Code:

Bus Protocol:

05h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

CUR_ILIM_VAL[13]

CUR_ILIM_VAL[12]

CUR_ILIM_VAL[11]

CUR_ILIM_VAL[10]

CUR_ILIM_VAL[9]

CUR_ILIM_VAL[8]

CUR_ILIM_VAL[7]

CUR_ILIM_VAL[6]

CUR_ILIM_VAL[5]

CUR_ILIM_VAL[4]

CUR_ILIM_VAL[3]

CUR_ILIM_VAL[2]

CUR_ILIM_VAL[1]

CUR_ILIM_VAL[0]

Current Input Current Limit Value

0 to 16,383mA, 1mA steps.

4

3

2

1

0

Input current limit functions.

Input current limit

selector

Input current limit control

and soft start

Peak power

control

+1

A

A>B

IADP pin Input current limit

Input Current Limit

A=B

A<B

200%~100%

100%~50%

High

Low

IBUS_LIM_SET

ICC_LIM_SET

-n

B

A

1/2

20ms Timer

Compare

BC1.2 Port Detection

Or 100ms-timer expired

Anti-Collapse

SEL_ILIM_VAL

CUR_ILIM_VAL

Input current limit selector:

The “Input current limit selector” block selects an original input current limit from the register setting or detected BC1.2,

DCP/CDP/SDP, result.

Input current limit control and soft start:

The “Input current limit control and soft start” block controls the input current limit slope 1mA/10us for soft start. And this block

modifies the input current limit, -N or 1/2, when the anti-collapse occurs.

Peak power control:

The “Peak power control” block controls the peak of the input current limit. It is defined by VIN_CTRL_SET.PPC_CAP[1:0] and

PPC_SUB_CAP[1:0] registers.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Sample case timing chart: Input current limit with peak control.

a) After setting the input current limit, the anti-collapse occurred.

VBUS

VBUS Plugged.

BC1.2 Detector

BC1.2 Detecting or 100ms Waiting

100ms~312ms typ.

BC1.2 Detected or 100ms Waited

3,000mA for example.

The anti-collapse occurred,

after setting the input current limit.

Initial = 100mA

3,000mA

SEL_ILIM_VAL

CUR_ILIM_VAL

1/2 step back,

because of the anti-collapse.

Step-up, 1mA/10us

3,750mA

1,500mA

20ms

1,875mA

2,250mA

1,125mA

Input Current Limit

The peak power is controlled on the basis of a value of

the CUR_ILIM_VAL.

For example, the duty is 125%/10ms and 75%/10ms.

b) During setting the input current limit, the anti-collapse occurred.

VBUS

VBUS Plugged.

BC1.2 Detector

BC1.2 Detecting or 100ms Waiting

100ms~312ms typ.

BC1.2 Detected or 100ms Waited

3,000mA for example.

The anti-collapse occurred,

during setting the input current limit.

SEL_ILIM_VAL

CUR_ILIM_VAL

Initial = 100mA

-N step back, because of the anti-collapse.

2,000mA

Step-up, 1mA/10us

20ms

2,500mA

1,500mA

Input Current Limit

The peak power is controlled on the basis of a value of

the CUR_ILIM_VAL.

For example, the duty is 125%/10ms and 75%/10ms.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Peak input current control operation is defined by VIN_CTRL_SET.PPC_CAP[1:0] and PPC_SUB_CAP[1:0]

belowdemonstrates.

as

PPC_CAP=01b

PPC_SUB_CAP=00b

PPC_SUB_CAP=01b

PPC_SUB_CAP=10b

150.0%

125.0%

2ms

110.0%

97.0%

90.0%

20ms

10ms

1ms

PPC_CAP=01b

PPC_SUB_CAP=00b

PPC_SUB_CAP=01b

PPC_SUB_CAP=10b

200.0%

150.0%

125.0%

95.0%

94.0%

75.0%

PPC_CAP=11b

PPC_SUB_CAP=00b

PPC_SUB_CAP=01b

PPC_SUB_CAP=10b

200.0%

175%

150.0%

95.0%

92.0%

50.0%

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.7. SEL_ILIM_VAL

Selected Input Current Limit

Command Code:

Bus Protocol:

06h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

SEL_ILIM_VAL[13]

SEL_ILIM_VAL[12]

SEL_ILIM_VAL[11]

SEL_ILIM_VAL[10]

SEL_ILIM_VAL[9]

SEL_ILIM_VAL[8]

SEL_ILIM_VAL[7]

SEL_ILIM_VAL[6]

SEL_ILIM_VAL[5]

SEL_ILIM_VAL[4]

SEL_ILIM_VAL[3]

SEL_ILIM_VAL[2]

SEL_ILIM_VAL[1]

SEL_ILIM_VAL[0]

Selected Input Current Limit Setting

0 to 16,383mA, 1mA steps.

4

3

2

1

0

8.5.8. IBUS_LIM_SET

VBUS Input Current Limit Setting

Command Code:

Bus Protocol:

07h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

IBUS_LIM_SET[13]

IBUS_LIM_SET[12]

IBUS_LIM_SET[11]

IBUS_LIM_SET[10]

IBUS_LIM_SET[9]

IBUS_LIM_SET[8]

IBUS_LIM_SET[7]

IBUS_LIM_SET[6]

IBUS_LIM_SET[5]

reserved

VBUS input current limitation.

0 to 16,352mA, 32mA steps.

4

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.9. ICC_LIM_SET

VCC/VACP Input Current Limit Setting

Command Code:

Bus Protocol:

08h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

ICC_LIM_SET[13]

ICC_LIM_SET[12]

ICC_LIM_SET[11]

ICC_LIM_SET[10]

ICC_LIM_SET[9]

ICC_LIM_SET[8]

ICC_LIM_SET[7]

ICC_LIM_SET[6]

ICC_LIM_SET[5]

reserved

VCC input current limitation. (When VCC_EN=1)

VACP input current limitation. (When VCC_EN=VBUS_EN=0)

0 to 16,352mA, 32mA steps.

4

3

reserved

2

reserved

1

reserved

0

reserved

8.5.10. IOTG_LIM_SET

OTG Output Current Limit Setting

Command Code:

Bus Protocol:

09h

Read/Write Word

Description

Bit

15

14

13

12

11

10

9

Symbol

reserved

IOTG_LIM_SET[13]

IOTG_LIM_SET[12]

IOTG_LIM_SET[11]

IOTG_LIM_SET[10]

IOTG_LIM_SET[9]

IOTG_LIM_SET[8]

IOTG_LIM_SET[7]

IOTG_LIM_SET[6]

IOTG_LIM_SET[5]

reserved

VBUS/VCC output current limit when OTG.

0 to 16,352mA, 32mA steps.

8

7

6

5

4

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.11. VIN_CTRL_SET

VBUS and VCC Control Setting

Command Code:

Bus Protocol:

0Ah

Read/Write Word

Bit

Symbol

Description

"Enabling OTG reverse buck boost output to VBUS and VCC both.

“1”: Enable / “0”: Disable."

15

OTG_BOTH_EN

When OTG_BOTH_EN=1 and VBUS_EN=VCC_EN=1, OTG reverse buck

boost output same voltage at VBUS and VCC,

VBUS=VCC=VRBOOST_SEL[14:6].

Reverse buck Boost operation Trigger.

“1”: Trigger/ “0”; No trigger

Enabling VCC Reverse buck Boost operation.

“1”: Enable / “0”: Disable.

Enabling VBUS Reverse buck Boost operation.

“1”: Enable / “0”: Disable.

14

13

12

VRBOOST_TRIG

VRBOOST_EN[1]

VRBOOST_EN[0]

"Enabling output to VBUS and VCC both.

“1”: Enable / “0”: Disable."

11

PP_BOTH_THRU

When PP_BOTH_THRU=1 and VBUS_EN=VCC_EN=1,

VIN_ORD=0 : Power path output same voltage from VCC to VBUS,

VIN_ORD=1 : Power path output same voltage from VBUS to VCC.

10

9

8

reserved

VBUS / VCC input priority.

“1”: VBUS prior / “0”: VCC prior.

Enabling VBUS input.

“1”: Enable / “0”: Disable.

Enabling VCC input.

“1”: Enable / “0”: Disable.

7

6

5

VIN_ORD

VBUS_EN

VCC_EN

Disabling the input current limit for avoiding VSYS drop when VBAT is the

dead-battery, VBAT is < VSYSREG_SET.

“1”: Disable the input current limit / “0”: Enable the input current limit.

Power source peak current sub-capability

4

VSYS_PRIORITY

3

2

1

0

PPC_SUB_CAP[1]

PPC_SUB_CAP[0]

PPC_CAP[1]

Power source peak current capability

PPC_CAP[0]

PPC_CAP PPC_SUB_CAP Overload Capabilities Description

00b

01b

*b

00b

Peak current equals (IBUS_LIM_SET or ICC_LIM_SET) .

Peak current equals 150.0% (IBUS_LIM_SET or ICC_LIM_SET) for 1ms.

Low current equals 97.0% (IBUS_LIM_SET or ICC_LIM_SET) for 19ms.

Peak current equals 125.0% (IBUS_LIM_SET or ICC_LIM_SET) for 2ms.

Low current equals 97.0% (IBUS_LIM_SET or ICC_LIM_SET) for 18ms.

Peak current equals 110.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

Low current equals 90.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

Peak current equals 200.0% (IBUS_LIM_SET or ICC_LIM_SET) for 1ms.

Low current equals 95.0% (IBUS_LIM_SET or ICC_LIM_SET) for 19ms.

Peak current equals 150.0% (IBUS_LIM_SET or ICC_LIM_SET) for 2ms.

Low current equals 94.0% (IBUS_LIM_SET or ICC_LIM_SET) for 18ms.

Peak current equals 125.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

Low current equals 75.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

Peak current equals 200.0% (IBUS_LIM_SET or ICC_LIM_SET) for 1ms.

Low current equals 95.0% (IBUS_LIM_SET or ICC_LIM_SET) for 19ms.

Peak current equals 175.0% (IBUS_LIM_SET or ICC_LIM_SET) for 2ms.

Low current equals 92.0% (IBUS_LIM_SET or ICC_LIM_SET) for 18ms.

Peak current equals 150.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

Low current equals 50.0% (IBUS_LIM_SET or ICC_LIM_SET) for 10ms.

01b

10b

00b

01b

10b

00b

01b

10b

11b

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Power Path Controll Flow chart

Path through mode : ON



Power supply from VCC to VBUS

Charger

EC

PDIC

VBUS/VCC pluged-in

ACOK flag

Change Command Map into Extended Command Map

SMBus Write MAP_SET(Address 3Fh) = 01h

Negotiation

Command Map is Extended Command Map

Check Input port Status to Charger

SMBus Read VBUS/VCC_STATUS(Address 02h)

Return Data

Check Status to PDIC

VCC side PD type

VBUS side PD type

Return Data

Address 02h : VBUS/VCC_STATUS = [xxx00xx1xxxx0xx0]

Bit12 : VACP_DET = 0

Bit11 : VCC_OVP = 0

Bit9 : VCC_DET = 1

Bit3 : VBUS_OVP = 0

Bit0 : VBUS_DET = 0

VCC side PD type < VBUS side PD type

Enter Path through from VCC to VBUS mode

SMBus write VIN_CTRL_SET(Address 0Ah) =

[00001000011xxxxx]

Bit11 : PP_BOTH_THRU = 1

Bit7 : VIN_ORD = 0 (VCC prior)

Bit6,5 : VBUS_EN=VCC_EN=1

Enter Path Through Mode



Power supply from VBUS to VCC

Charger

EC

PDIC

VBUS/VCC pluged-in

ACOK flag

Change Command Map into Extended Command Map

SMBus Write MAP_SET(Address 3Fh) = 01h

Negotiation

Command Map is Extended Command Map

Check Input port Status to Charger

SMBus Read VBUS/VCC_STATUS(Address 02h)

Return Data

Check Status to PDIC

VCC side PD type

VBUS side PD type

Return Data

Address 02h : VBUS/VCC_STATUS = [xxx00xx0xxxx0xx1]

Bit12 : VACP_DET = 0

Bit11 : VCC_OVP = 0

Bit9 : VCC_DET = 0

Bit3 : VBUS_OVP = 0

Bit0 : VBUS_DET = 1

VCC side PD type >= VBUS side PD type

Enter Path through from VCC to VBUS mode

SMBus write VIN_CTRL_SET(Address 0Ah) =

[00001000111xxxxx]

Bit11 : PP_BOTH_THRU = 1

Bit7 : VIN_ORD = 1 (VBUS prior)

Bit6,5 : VBUS_EN=VCC_EN=1

Enter Path Through Mode

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Path through mode : OFF

Charger

EC

PDIC

VBUS or VCC plugged-out

Recognized Disconnect

Change Command Map into Extended Command Map

SMBus Write MAP_SET(Address 3Fh) = 01h

Command Map is Extended Command Map

Exit Path through mode

SMBus write VIN_CTRL_SET(Address 0Ah) =

[00000000x11xxxxx]

Bit11 : PP_BOTH_THRU = 1

Bit7 : VIN_ORD = previous value

Bit6,5 : VBUS_EN=VCC_EN=1

Exit Path Through Mode

Interrupt from INT#

Charger detect under voltage output port

Check Status to Charger

SMBus Read INT1_STATUS(Address 71h) and

INT2_STATUS(Address 72h) and INT7_STATUS(Address

77h).

Return Data

Clear Status resister to Charger

SMBus Write INT0_STATUS(Address 70h) = 0000h

Clear status resister



Timing Chart

Path Through mode after VBUS input

VBUS plugged-out

VBUS

Red Italic；Power

VBUS UVLO release

Blue Italic : Analog Signal

Black ； Internal Digital Signal

Green ； Resister settings

VBUS_UVLO_A

VBUS_UVLO_D

DCDC_STB

DCDC stop after UVLO detect.

Start BC1.2 detection or Timer 100ms

BC1.2 Detecting/Waiting

DCDC Stand-by

Default

(VBUS UCD) Default

DCDC_CTRL

Detected/Waited

Finish detection and dcdc start.

DCDC_CTRL is "H” after ACP_UVLO is “H”

VBUS_PowerPath

VBUS_PP=ON

CTRL

VCC_PowerPath

CTRL

VCC_PP=OFF

Need discharge for Co

VCC UVLO

VCC

VCC_UVLO_A

VCC_UVLO_D

(VCC UCD)

ILIM

VCC UVLO release

VCC UVLO disable when through operation

VCC UVLO disable during discharge

Default

SET (VBUS)

Default

VBUS_LOAD

VCC_LOAD

Both port set discharge signal during

20ms after path through mode finish.

Both port is discharged during

20ms

ACP

ACP_UVLO

Finished path through mode

Start path through

mode

PP_BOTH_THRU

PATH_THRU_EN

VIN_ORD

VIN_ORD have to fix input port side

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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VBUS path through mode after resister setting

Red Italic；Power

VBUS plugged-out

VBUS

VBUS UVLO release

VBUS_UVLO_A

Blue Italic : Analog Signal

Black ； Internal Digital Signal

Green ； Resister settings

VBUS_UVLO_D

DCDC_STB

DCDC stop after UVLO detect.

DCDC_STB

Start BC1.2 detection or Timer 100ms

DCDC Stand-by

Default

BC1.2 Detecting/Waiting

(VBUS UCD)

DCDC_CTRL

Default

Detected/Waited

Finish detection and dcdc start.

DCDC_CTRL is "H” after ACP_UVLO is “H”

VBUS_PPCTRL

VCC_PPCTRL

VCC

VBUS_PP=ON

VCC_PP=ON

Need discharge from capacitor.

VCC_UVLO_A

VCC_UVLO_D

(VCC UCD)

ILIM

VCC UVLO release

VCC UVLO

VCC UVLO disable when through operation

VCC UVLO disable during discharge

Default

SET (VBUS)

Default

VBUS_LOAD

VCC_LOAD

ACP

Both port set discharge signal during

20ms after path through mode finish.

Both port is discharged

during 20ms

ACP_UVLO

PP_BOTH_THRU

PATH_THRU_EN

VIN_ORD

Finished path through mode

Resister reset when power path turn off.

If path through mode goes again, resister is setting again.

Start path through mode

VIN_ORD have to fix input port side

Detect OVP at Output port

Red Italic；Power

VBUS

Blue Italic : Analog Signal

VBUS UVLO release

VBUS_UVLO_A

Black ； Internal Digital Signal

Green ； Resister settings

VBUS_UVLO_D

DCDC_STB

Start BC1.2 detection or Timer 100ms

BC1.2 Detecting/Waiting

(VBUS UCD)

DCDC_CTRL

Default

Detected/Waited

Finish detection and dcdc start.

DCDC doesn't stop until detect output port OVP

DCDC_CTRL is "H” after ACP_UVLO is “H”

VBUS_PPCTRL

VCC_PPCTRL

VCC

VBUS_PP=ON

VCC_PP=OFF

VCC power path turn off and discharge

VCC UVLO disable during discharge

VCC_UVLO_A

VCC_UVLO_D

(VCC UCD)

ILIM

VCC UVLO release

VCC UVLO

VCC UVLO disable when through operation

Default

SET (VBUS)

Both port is discharged during

20ms

VBUS_LOAD

VCC_LOAD

ACP

Both port set discharge signal during

20ms after path through mode finish.

ACP_UVLO

PP_BOTH_THRU

PATH_THRU_EN

VBUS_OVP

VCC_OVP

Exit path through mode until release OVP

condition.

Set path through mode

Finished path through mode

Resister reset when OVP detection

VIN_ORD

VIN_ORD have to fix input port side

Detect OVP at Input port

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Red Italic；Power

VBUS

VBUS UVLO release

VBUS_UVLO_A

Blue Italic : Analog Signal

Black ； Internal Digital Signal

Green ； Resister settings

VBUS_UVLO_D

DCDC_STB

Start BC1.2 detection or Timer 100ms

DCDC Stand-by

BC1.2 Detecting/Waiting

(VBUS UCD)

DCDC_CTRL

Default

Detected/Waited

Finish detection and dcdc start.

DCDC stop and VBUS power

path turn off.

DCDC_CTRL is "H” after ACP_UVLO is “H”

VBUS_PPCTRL

VCC_PPCTRL

VCC

VBUS_PP=ON

VCC_PP OFF

VCC power path turn off and discharge

VCC_UVLO_A

VCC_UVLO_D

(VCC UCD)

ILIM

VCC UVLO release

VCC UVLO disable when through operation

VCC UVLO

VCC UVLO disable during discharge

Finish detection and dcdc start.

Default

SET (VBUS)

Default

Both port is discharged

during 20ms

VBUS_LOAD

VCC_LOAD

ACP

Both port set discharge signal during

20ms after path through mode finish.

ACP_UVLO

PP_BOTH_THRU

PATH_THRU_EN

VBUS_OVP

VCC_OVP

Finished path through mode

Exit path through mode until release OVP

Set path through mode

Resister reset when detect OVP

VIN_ORD

VIN_ORD have to fix input port side

Role swap from VBUS to VCC when path through mode

Red Italic；Power

Blue Italic : Analog Signal

Black ； Internal Digital Signal

Green ； Resister settings

Path through mode turn off when role swapping.

Occur role swap

VBUS

VBUS UVLO release

VBUS_UVLO_A

VBUS_UVLO_D

DCDC_STB

VCC UVLO disable when through operation

VCC UVLO disable during discharge

DCDC_STB

Start BC1.2 detection or Timer 100ms

BC1.2 Detecting/Waiting

DCDC Stand-by

Default

(VBUS UCD) Default

DCDC_CTRL

Default

DCDC stop due to

VBUS plugged-out.

Finish detection and dcdc start.

DCDC start up after ACPUVLO

release and 100msec min.

DCDC_CTRL is "H” after ACP_UVLO is “H”

VBUS_PPCTRL

VCC_PPCTRL

VCC

VBUS_PP=ON

VCC_PP=OFF

Plugged-out VCC

VCC_UVLO_A

VCC_UVLO_D

(VCC UCD)

ILIM

VCC UVLO release

VCC UVLO disable when through

operation

VCC UVLO

BC1.2 Detecting/Waiting

Default

Detected/Waited

Input Current limit set default value of VCC

SET (VCC) Default

Default

SET (VBUS)

Default

VBUS_LOAD

VCC_LOAD

ACP

Both port is discharged

during 20ms

Power path become through condition

due to PP_BOTH_THRU signal.

ACP_UVLO

PP_BOTH_THRU

PATH_THRU_EN

VIN_ORD

Set path through mode

Set path

through mode

Finished path

through mode

VIN_ORD need change when input

and output change.

VIN_ORD have to fix input port side

VIN_ORD fixed Input port side when path through use after input

voltage under UVLO

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.12. CHGOP_SET1

Charger Operation Control Setting 1

Command Code:

Bus Protocol:

0Bh

Read/Write Word

Bit

15

14

Symbol

DCP_2500_SEL

SDP_500_SEL

ILIM_AUTO_DISEN

reserved

Description

Select current limitation when DCP charger attached.

Select current limitation when SDP charger attached.

Disable automatic limitation of the input current.

“1”: Disable / “0”: Enable.

13

12

Disable charging trigger by BC1.2 detection.

If this bit is "1: disable", after 100ms when VBUS/VCC plugged in,

BD99954 starts charging without BC1.2 detection.

“1”: Disable / “0”: Enable.

11

VCC_BC_DISEN

Disable charging trigger by BC1.2 detection.

If this bit is "1: disable", after 100ms when VBUS/VCC plugged in,

BD99954 starts charging without BC1.2 detection.

“1”: Disable / “0”: Enable.

Enable the charging trigger after SDP charger attached.

“1”: Enable SDP_CHG_TRIG bit as charging trigger / “0”: Disable

SDP_CHG_TRIG bit as charging trigger.

10

9

VBUS_BC_DISEN

SDP_CHG_TRIG_EN

Charging trigger after SDP charger attached.

“1”: Start charging / “0”: Not start charging.

8

7

SDP_CHG_TRIG

reserved

Top-off transition mode.

This bit is trigger to move to the top-off charge state.

This bit is only effective when the charging state transitions from fast-

charge to top-off charge.

“1”: Auto control / “0”: Manual control.

Fast charging transition mode.

6

AUTO_TOF

AUTO_FST

This bit is only effective when the charging state transitions from pre-

charge to fast-charge.

5

“1”: Auto control / “0”: Manual control.

4

3

reserved

Automatic re-charging mode.

“1”: Auto control / “0”: Manual control.

AUTO_RECH

2

1

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.13. CHGOP_SET2

Charger Operation Control Setting 2

Command Code:

Bus Protocol:

0Ch

Read/Write Word

Bit

Symbol

Description

15

reserved

Enabling the input current limit re-setting when starting fast charge.

“1”: Enable. / “0”: Disable.

14

ILIM_RESET_EN

13

12

11

DCDC_1MS_SEL[1]

DCDC_1MS_SEL[0]

reserved

Select ILIM re-setting step period.

00b: 10us/ 01b: 50us/ 10b: 100us/ 11b: 1ms

Select ILIM drop width when Anti-collapse. or VBAT<VIN comparator

asserted.

“1”: The input current limit drop into 1/4. / “0”: 1/2.

10

9

SEL_ILIM_DIV

reserved

Enabling Battery Learning operation, suspend charging and DC/DC

convertor.

8

BATT_LEARN

This bit is cleared automatically when VBAT is the dead battery, VBAT <

VSYSREG_SET.

“1”: Enable / “0”: Disable.

Enabling Charger operation.

“1”: Enable / “0”: Disable.

Suspend USB charging and DC/DC convertor.

“1”: Suspend / “0”: Active.

7

6

CHG_EN

USB_SUS

Initialization value for CHOP_SS (Chopper Mode during DCDC soft start.)

"1": Chopper Mode during DCDC soft start / "0": Synchronized Mode.

This register is "Read-Only" and is loaded from OTP.

Initialization value for CHOP_ALL (Continuous Chopper Mode.)

"1": Always in Chopper Mode / "0": Synchronized Mode.

This register is "Read-Only" and is loaded from OTP.

DCDC Clock Select.

00b: 600kHz (H:L=1:1)/ 01b: 857kHz (H:L=3:4)/

10b: 1000kHz (H:L=1:2)/ 11b: 1200kHz (H:L=2:3)

Enable operation in Chopper Mode during DCDC soft start.

"1": Chopper Mode during DCDC soft start / "0": Synchronized Mode.

Initial value is loaded from CHOP_SS_INIT during DCDC standby.

Force continuous Chopper Mode operation.

5

4

CHOP_SS_INIT

CHOP_ALL_INIT

3

2

DCDC_CLK_SEL[1]

DCDC_CLK_SEL[0]

1

0

CHOP_SS

CHOP_ALL

"1": Continuous Chopper Mode / "0" Synchronized Mode.

Initial value is loaded from CHOP_ALL_INIT during DCDC standby.

8.5.14. VBUSCLPS_TH_SET

VBUS Collapse Detect Threshold Voltage Setting

Command Code:

Bus Protocol:

0Dh

Read/Write Word

Description

Bit

15

14

13

12

11

10

9

Symbol

reserved

VBUSCLPS_TH_SET[14]

VBUSCLPS_TH_SET[13]

VBUSCLPS_TH_SET[12]

VBUSCLPS_TH_SET[11]

VBUSCLPS_TH_SET[10]

VBUSCLPS_TH_SET[9]

VBUSCLPS_TH_SET[8]

VBUSCLPS_TH_SET[7]

reserved

VBUS Anti-collapse entry voltage threshold.

3,840 to 32,640mV, 128mV steps.

The register range : 0 to 32,640mV.

But the actual range : 3,840 to 25,088mV.

“00h”setting disables VBUS collapse detection.

8

7

6

5

reserved

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.15. VCCCLPS_TH_SET

VCC Collapse Detect Threshold Voltage Setting

Command Code:

Bus Protocol:

0Eh

Read/Write Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

VCCCLPS_TH_SET[14]

VCCCLPS_TH_SET[13]

VCCCLPS_TH_SET[12]

VCCCLPS_TH_SET[11]

VCCCLPS_TH_SET[10]

VCCCLPS_TH_SET[9]

VCCCLPS_TH_SET[8]

VCCCLPS_TH_SET[7]

reserved

VCC Anti-collapse entry voltage threshold

3,840 to 32,640mV, 128mV steps.

The register range : 0 to 32,640mV.

But the actual range : 3,840 to 25,088mV.

“00h”setting disables VCC collapse detection.

8

7

6

5

reserved

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.5.16. CHGWDT_SET

Charger WDT Setting

Command Code:

Bus Protocol:

0Fh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

WDT_FST[7]

WDT_FST[6]

WDT_FST[5]

WDT_FST[4]

WDT_FST[3]

WDT_FST[2]

WDT_FST[1]

WDT_FST[0]

WDT_PRE[7]

WDT_PRE[6]

WDT_PRE[5]

WDT_PRE[4]

WDT_PRE[3]

WDT_PRE[2]

WDT_PRE[1]

WDT_PRE[0]

Watch Dog Timer setting for Fast Charging.

4 to 1020 minutes range, 4-minute steps.

“00h”setting stops this timer.

Watch Dog Timer setting for Pre-charging.

1 to 255 minutes range, 1-minute steps.

“00h”setting stops this timer.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.17. BATTWDT_SET

Battery Temperature and Battery short current WDT Setting

Command Code:

Bus Protocol:

Bit

10h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

WDT_IBAT_SHORT[7]

WDT_IBAT_SHORT[6]

WDT_IBAT_SHORT[5]

WDT_IBAT_SHORT[4]

WDT_IBAT_SHORT[3]

WDT_IBAT_SHORT[2]

WDT_IBAT_SHORT[1]

WDT_IBAT_SHORT[0]

WDT_THERM[7]

Watch Dog Timer setting for Battery Short Current.

4 to 1020 ms range, 4ms steps.

“00h”setting stops this timer.

Watch Dog Timer setting for Battery Temperature.

1 to 255 minutes range, 1-minute steps.

“00h”setting stops this timer.

WDT_THERM[6]

WDT_THERM[5]

4

WDT_THERM[4]

3

WDT_THERM[3]

2

WDT_THERM[2]

1

WDT_THERM[1]

0

WDT_THERM[0]

8.5.18. VSYSREG_SET

VSYS Regulation Setting

Command Code:

Bus Protocol:

11h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VSYSREG_SET[14]

VSYSREG_SET[13]

VSYSREG_SET[12]

VSYSREG_SET[11]

VSYSREG_SET[10]

VSYSREG_SET[9]

VSYSREG_SET[8]

VSYSREG_SET[7]

VSYSREG_SET[6]

reserved

VSYS regulation voltage setting and

threshold voltage from Pre-charging to Fast-charging.

2,560 to 19,200mV, 64mV steps.

The register range : 0 to 32,704mV.

But the actual range : 2,560 to 19,200mV.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.19. VSYSVAL_THH_SET

VSYS Valid Threshold High Setting (Hysteresis)

Command Code:

Bus Protocol:

Bit

12h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VSYSVAL_THH_SET[14]

VSYSVAL_THH_SET[13]

VSYSVAL_THH_SET[12]

VSYSVAL_THH_SET[11]

VSYSVAL_THH_SET[10]

VSYSVAL_THH_SET[9]

VSYSVAL_THH_SET[8]

VSYSVAL_THH_SET[7]

VSYSVAL_THH_SET[6]

reserved

VSYS voltage rising detection threshold with hysteresis.

2,560 to 19,200mV, 64mV steps.

The register range : 0 to 32,704mV.

But the actual range : 2,560 to 19,200mV.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.5.20. VSYSVAL_THL_SET

VSYS Valid Threshold Low Setting (Hysteresis)

Command Code:

Bus Protocol:

Bit

13h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VSYSVAL_THL_SET[14]

VSYSVAL_THL_SET[13]

VSYSVAL_THL_SET[12]

VSYSVAL_THL_SET[11]

VSYSVAL_THL_SET[10]

VSYSVAL_THL_SET[9]

VSYSVAL_THL_SET[8]

VSYSVAL_THL_SET[7]

VSYSVAL_THL_SET[6]

reserved

VSYS voltage falling detection threshold with hysteresis.

2,560 to 19,200mV, 64mV steps.

The register range : 0 to 32,704mV.

But the actual range : 2,560 to 19,200mV.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.21. ITRICH_SET

Trickle-charge Current Setting

Command Code:

Bus Protocol:

14h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

ITRICH_SET[10]

ITRICH_SET[9]

ITRICH_SET[8]

ITRICH_SET[7]

ITRICH_SET[6]

reserved

Trickle-charging current setting.

0 to 1,024mA, 64mA steps.

The register range : 0 to 1,984mA.

But the actual range : 0 to 1,024mA.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.5.22. IPRECH_SET

Pre-charge Current Setting

Command Code:

Bus Protocol:

15h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

IPRECH_SET[10]

IPRECH_SET[9]

IPRECH_SET[8]

IPRECH_SET[7]

IPRECH_SET[6]

reserved

Pre-charging current setting.

0 to 1,024mA, 64mA steps.

The register range : 0 to 1,984mA.

But the actual range : 0 to 1,024mA.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

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8.5.23. ICHG_SET

Fast-charge Current Setting

Command Code:

Bus Protocol:

16h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

ICHG_SET[13]

ICHG_SET[12]

ICHG_SET[11]

ICHG_SET[10]

ICHG_SET[9]

ICHG_SET[8]

ICHG_SET[7]

ICHG_SET[6]

reserved

Fast-charging current setting.

0 to 16,320mA, 64mA steps.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.5.24. ITERM_SET

Charge Termination Current Setting

Command Code:

Bus Protocol:

17h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

ITERM_SET[10]

ITERM_SET[9]

ITERM_SET[8]

ITERM_SET[7]

ITERM_SET[6]

reserved

Charging Termination Current.

0 to 1,024mA, 64mA steps.

The register range : 0 to 1,984mA.

But the actual range : 0 to 1,024mA.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.25. VPRECHG_TH_SET

Pre-charge Voltage Threshold Setting

Command Code:

Bus Protocol:

18h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VPRECHG_TH_SET[14]

VPRECHG_TH_SET[13]

VPRECHG_TH_SET[12]

VPRECHG_TH_SET[11]

VPRECHG_TH_SET[10]

VPRECHG_TH_SET[9]

VPRECHG_TH_SET[8]

VPRECHG_TH_SET[7]

VPRECHG_TH_SET[6]

reserved

Threshold voltage from Trickle-charging to Pre-charging

2,048 to 19,200mV, 64mV steps.

The register range : 0 to 32,704mV.

But the actual range : 2,048 to 19,200mV.

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

8.5.26. VRBOOST_SET

Reverse buck boost voltage Setting

Command Code:

Bus Protocol:

19h

Read/Write Word

Description

Bit

15

14

13

12

11

10

9

Symbol

reserved

VRBOOST_SET[14]

VRBOOST_SET[13]

VRBOOST_SET[12]

VRBOOST_SET[11]

VRBOOST_SET[10]

VRBOOST_SET[9]

VRBOOST_SET[8]

VRBOOST_SET[7]

VRBOOST_SET[6]

reserved

Reverse buck boost voltage setting.

4,032 to 22,016mV, 64mV steps.

The register range : 0 to 32,704mV.

But the actual range : 4,032 to 22,016mV.

8

7

6

5

4

reserved

3

reserved

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.27. VFASTCHG_REG_SET1

Fast Charge Voltage Regulation Setting 1

Command Code:

Bus Protocol:

1Ah

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VFASTCHG_REG_SET1[14]

VFASTCHG_REG_SET1[13]

VFASTCHG_REG_SET1[12]

VFASTCHG_REG_SET1[11]

VFASTCHG_REG_SET1[10]

VFASTCHG_REG_SET1[9]

VFASTCHG_REG_SET1[8]

VFASTCHG_REG_SET1[7]

VFASTCHG_REG_SET1[6]

VFASTCHG_REG_SET1[5]

VFASTCHG_REG_SET1[4]

reserved

Fast Charging Regulation Voltage.

2,560 to 19,200mV, 16mV steps.

The register range : 0 to 32,752mV.

But the actual range : 2,560 to 19,200mV.

4

3

2

reserved

1

reserved

0

reserved

8.5.28. VFASTCHG_REG_SET2

Fast Charge Voltage Regulation Setting 2 (Hot 1)

Command Code:

Bus Protocol:

Bit

1Bh

Read/Write Word

Symbol

Description

15 reserved

14 VFASTCHG_REG_SET2[14] Fast Charging Regulation Voltage for the JEITA temperature range T3-T5.

13 VFASTCHG_REG_SET2[13] 2,560 to 19,200mV, 16mV steps.

12 VFASTCHG_REG_SET2[12] The register range : 0 to 32,752mV.

11 VFASTCHG_REG_SET2[11] But the actual range : 2,560 to 19,200mV.

10 VFASTCHG_REG_SET2[10]

9

8

7

6

5

4

3

2

1

0

VFASTCHG_REG_SET2[9]

VFASTCHG_REG_SET2[8]

VFASTCHG_REG_SET2[7]

VFASTCHG_REG_SET2[6]

VFASTCHG_REG_SET2[5]

VFASTCHG_REG_SET2[4]

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.29. VFASTCHG_REG_SET3

Fast Charge Voltage Regulation Setting 3 (Hot 2)

Command Code:

Bus Protocol:

1Ch

Read/Write Word

Bit

15

14

Symbol

Description

reserved

VFASTCHG_REG_SET3[14]

Fast Charging Regulation Voltage for the JEITA temperature

range T5-T4 and T1-T2.

2,560 to 19,200mV, 16mV steps.

13

VFASTCHG_REG_SET3[13]

12

11

10

9

8

7

6

5

4

3

VFASTCHG_REG_SET3[12]

VFASTCHG_REG_SET3[11]

VFASTCHG_REG_SET3[10]

VFASTCHG_REG_SET3[9]

VFASTCHG_REG_SET3[8]

VFASTCHG_REG_SET3[7]

VFASTCHG_REG_SET3[6]

VFASTCHG_REG_SET3[5]

VFASTCHG_REG_SET3[4]

reserved

The register range : 0 to 32,752mV.

But the actual range : 2,560 to 19,200mV.

2

reserved

1

reserved

0

reserved

8.5.30. VRECHG_SET

Re-charge Battery Voltage Setting

Command Code:

Bus Protocol:

1Dh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VRECHG_SET[14]

VRECHG_SET[13]

VRECHG_SET[12]

VRECHG_SET[11]

VRECHG_SET[10]

VRECHG_SET[9]

VRECHG_SET[8]

VRECHG_SET[7]

VRECHG_SET[6]

VRECHG_SET[5]

VRECHG_SET[4]

reserved

Re-charge Battery Voltage.

2,560 to 19,200mV, 16mV steps.

The register range : 0 to 32,752mV.

But the actual range : 2,560 to 19,200mV.

4

3

2

reserved

1

reserved

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.31. VBATOVP_SET

Battery Over Voltage Protection Setting

Command Code:

Bus Protocol:

1Eh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VBATOVP_SET[14]

VBATOVP_SET[13]

VBATOVP_SET[12]

VBATOVP_SET[11]

VBATOVP_SET[10]

VBATOVP_SET[9]

VBATOVP_SET[8]

VBATOVP_SET[7]

VBATOVP_SET[6]

VBATOVP_SET[5]

VBATOVP_SET[4]

reserved

Battery over-voltage detection threshold.

2,560 to 19,200mV, 16mV steps.

The register range : 0 to 32,752mV.

But the actual range : 2,560 to 19,200mV.

4

3

2

reserved

1

reserved

0

reserved

8.5.32. IBATSHORT_SET

Battery Short Current Protection Setting

Command Code:

Bus Protocol:

1Fh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

IBATM_SHORT_SET[14]

IBATM_SHORT_SET[13]

IBATM_SHORT_SET[12]

IBATM_SHORT_SET[11]

IBATM_SHORT_SET[10]

IBATM_SHORT_SET[9]

IBATM_SHORT_SET[8]

IBATM_SHORT_SET[7]

IBATM_SHORT_SET[6]

IBATM_SHORT_SET[5]

IBATM_SHORT_SET[4]

IBATM_SHORT_SET[3]

IBATM_SHORT_SET[2]

IBATM_SHORT_SET[1]

IBATM_SHORT_SET[0]

Battery Short Current Protection Threshold

0 to 25,000mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 25,000mA.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.33. PROCHOT_CTRL_SET

PROCHOT# pin Control Setting

Command Code:

Bus Protocol:

20h

Read/Write Word

Bit

15

14

13

12

11

10

9

Symbol

PROCHOT_DG_SET[1]

PROCHOT_DG_SET[0]

reserved

Description

PROCHOT# de-glitch period (VSYS, INORM) setting.

00b: 200us/ 01b: 500us/ 10b:1ms/ 11b:50ms

reserved

PROCHOT_ICRIT_DG_SET[1]

PROCHOT_ICRIT_DG_SET[0]

PROCHOT_IDCHG_DG_SET[1]

PROCHOT_IDCHG_DG_SET[0]

reserved

PROCHOT# de-glitch period (ICRIT) setting.

00b: 100us/ 01b: 200us/ 10b: 500us/ 11b:1ms

PROCHOT# de-glitch period (IDCHG) setting.

00b: 200us/ 01b: 500us/ 10b:1ms/ 11b:5ms

8

7

6

reserved

5

reserved

4

3

2

1

PROCHOT_EN[4]

PROCHOT_EN[3]

PROCHOT_EN[2]

PROCHOT_EN[1]

PROCHOT_EN[0]

PROCHOT# 2nd level enable (VSYS)

PROCHOT# 2nd level enable (IDCHG)

PROCHOT# 2nd level enable (INORM)

PROCHOT# 2nd level enable (ICRIT)

PROCHOT# 1st level enable

0

PROCHOT_EN[4]&

PROCHOT_EN[0]

VSYS_AVE_VAL,

VSYS Voltage Measurement

Average Value

+

EN

-

PROCHOT_VSYS_SET,

VSYS Voltage Threshold

PROCHOT_DG_SET[1:0]

De-glitch period setting for VSYS and INORM

200us/500us/1ms/50ms

PROCHOT_EN[3]&

PROCHOT_EN[0]

IBATM_AVE_VAL,

Battery Dis-charge Current

Measurement Average Value

+

-

EN

PROCHOT_IDCHG_SET,

Dis-charge Current Threshold

PROCHOT_IDCHG_DG_SET[1:0]

De-glitch period setting for IDGHG

200us/500us/1ms/5ms

PROCHOT#

10ms Debounce

(>=10ms width)

PROCHOT_EN[2]&

PROCHOT_EN[0]

IACP_AVE_VAL,

Input Current Measurement

Average Value

+

EN

-

PROCHOT_INORM_SET,

Average Input Current Threshold

PROCHOT_DG_SET[1:0]

De-glitch period setting for VSYS and INORM

200us/500us/1ms/50ms

PROCHOT_EN[1]&

PROCHOT_EN[0]

IACP_VAL,

Input Current Measurement Value

+

EN

-

PROCHOT_ICRIT_SET,

Peak Input Current Threshold

PROCHOT_ICRIT_DG_SET[1:0]

De-glitch period setting for ICRIT

100us/200us/500us/1ms

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.34. PROCHOT_ICRIT_SET

Peak Input Current Threshold Setting for PROCHOT#

Command Code:

Bus Protocol:

Bit

21h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

PROCHOT_ICRIT_SET[14]

PROCHOT_ICRIT_SET[13]

PROCHOT_ICRIT_SET[12]

PROCHOT_ICRIT_SET[11]

PROCHOT_ICRIT_SET[10]

PROCHOT_ICRIT_SET[9]

PROCHOT_ICRIT_SET[8]

PROCHOT_ICRIT_SET[7]

PROCHOT_ICRIT_SET[6]

PROCHOT_ICRIT_SET[5]

PROCHOT_ICRIT_SET[4]

PROCHOT_ICRIT_SET[3]

PROCHOT_ICRIT_SET[2]

PROCHOT_ICRIT_SET[1]

PROCHOT_ICRIT_SET[0]

Peak Input Current Threshold for PROCHOT#

0 to 16,384mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 16,383mA.

4

3

2

1

0

8.5.35. PROCHOT_INORM_SET

Average Input Current Threshold Setting for PROCHOT#

Command Code:

Bus Protocol:

Bit

22h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

PROCHOT_INORM_SET[14]

PROCHOT_INORM_SET[13]

PROCHOT_INORM_SET[12]

PROCHOT_INORM_SET[11]

PROCHOT_INORM_SET[10]

PROCHOT_INORM_SET[9]

PROCHOT_INORM_SET[8]

PROCHOT_INORM_SET[7]

PROCHOT_INORM_SET[6]

PROCHOT_INORM_SET[5]

PROCHOT_INORM_SET[4]

PROCHOT_INORM_SET[3]

PROCHOT_INORM_SET[2]

PROCHOT_INORM_SET[1]

PROCHOT_INORM_SET[0]

Average Input Current Threshold for PROCHOT#

0 to 16,384mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 16,383mA.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.36. PROCHOT_IDCHG_SET

Dis-charge Current Threshold Setting for PROCHOT#

Command Code:

Bus Protocol:

Bit

23h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

PROCHOT_IDCHG_SET[13]

PROCHOT_IDCHG_SET[14]

PROCHOT_IDCHG_SET[12]

PROCHOT_IDCHG_SET[11]

PROCHOT_IDCHG_SET[10]

PROCHOT_IDCHG_SET[9]

PROCHOT_IDCHG_SET[8]

PROCHOT_IDCHG_SET[7]

PROCHOT_IDCHG_SET[6]

PROCHOT_IDCHG_SET[5]

PROCHOT_IDCHG_SET[4]

PROCHOT_IDCHG_SET[3]

PROCHOT_IDCHG_SET[2]

PROCHOT_IDCHG_SET[1]

PROCHOT_IDCHG_SET[0]

Dis-charge Current Threshold for PROCHOT#

0 to 25,000mA, 1mA steps.

The register range: 0 to 32,752mA.

But the actual range: 0 to 25,000mA.

4

3

2

1

0

8.5.37. PROCHOT_VSYS_SET

VSYS Voltage Threshold Setting for PROCHOT#

Command Code:

Bus Protocol:

Bit

24h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

PROCHOT_VSYS_SET[14]

PROCHOT_VSYS_SET[13]

PROCHOT_VSYS_SET[12]

PROCHOT_VSYS_SET[11]

PROCHOT_VSYS_SET[10]

PROCHOT_VSYS_SET[9]

PROCHOT_VSYS_SET[8]

PROCHOT_VSYS_SET[7]

PROCHOT_VSYS_SET[6]

PROCHOT_VSYS_SET[5]

PROCHOT_VSYS_SET[4]

PROCHOT_VSYS_SET[3]

PROCHOT_VSYS_SET[2]

PROCHOT_VSYS_SET[1]

PROCHOT_VSYS_SET[0]

VSYS Voltage Threshold for PROCHOT#

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,752mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.38. PMON_IOUT_CTRL_SET

PMON and IOUT Output Control Setting

Command Code:

Bus Protocol:

Bit

25h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

reserved

IOUT Input source select.

0b: Measurement Average Value/ 1b: Measurement Value

PMON Input source select.

0b: Measurement Average Value/ 1b: Measurement Value

IOUT enable.

“1”: Enable / “0”: Disable.

IOUT source select.

“1”: Input Current / “0”: Battery Dis-charge Current.

9

8

7

6

IMON_INSEL

PMON_INSEL

IOUT_OUT_EN

IOUT_SOURCE_SEL

5

4

IOUT_GAIN_SET[1]

IOUT_GAIN_SET[0]

IOUT gain select.

00b: 5V/V / 01b: 10V/V / 10b: 20V/V/ 11b: 40V/V

PMON Enable.

3

PMON_OUT_EN

“1”: Enable / “0”: Disable.

2

1

0

PMON_GAIN_SET[2]

PMON_GAIN_SET[1]

PMON_GAIN_SET[0]

PMON gain select.

0h: x1/ 1h: x2/ 2h: x4/ 3h: x8/ 4h: x16/ 5h: x32/ 6h: x64

8.5.39. PMON_DACIN_VAL

PMON DAC Input Value (for debug and production test)

Command Code:

Bus Protocol:

Bit

26h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

PMON_DACIN_VAL[9]

PMON_DACIN_VAL[8]

PMON_DACIN_VAL[7]

PMON_DACIN_VAL[6]

PMON_DACIN_VAL[5]

PMON_DACIN_VAL[4]

PMON_DACIN_VAL[3]

PMON_DACIN_VAL[2]

PMON_DACIN_VAL[1]

PMON_DACIN_VAL[0]

PMON DAC Input Value

(for debug and production test)

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.40. IOUT_DACIN_VAL

IOUT DAC Input Value (for debug and production test)

Command Code:

Bus Protocol:

Bit

27h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IOUT_DACIN_VAL[11]

IOUT_DACIN_VAL[10]

IOUT_DACIN_VAL[9]

IOUT_DACIN_VAL[8]

IOUT_DACIN_VAL[7]

IOUT_DACIN_VAL[6]

IOUT_DACIN_VAL[5]

IOUT_DACIN_VAL[4]

IOUT_DACIN_VAL[3]

IOUT_DACIN_VAL[2]

IOUT_DACIN_VAL[1]

IOUT_DACIN_VAL[0]

IOUT DAC Input Value

(for debug and production test)

4

3

2

1

0

8.5.41. VCC_UCD_SET

BC1.2 Charger Detector on the VCC side Setting

Command Code:

Bus Protocol:

Bit

28h

Read/Write Word

Symbol

Description

15

14

13

reserved

Trigger for re-trial of the USB Charger Port detection.

“1”: Start detection / “0”: Release the operation.

12

BCSRETRY

11

10

9

reserved

Trigger for re-trial of USB ID Resistor detection.

“1”: Start detection / “0”: Release the operation.

Enabling USB Charger port detection.

“1”: Enable / “0”: Disable.

Enabling USB ID Resistor detection.

“1”: Enable / “0”: Disable.

Setting USB Enumeration to Ready.

“1”: Skip Secondary Detection / “0”: Normal operation.

USB ID input polling enable.

8

7

6

5

4

ADCRTRY

USBDETEN

IDRDETEN

ENUMRDY

ADCPOLEN

“1”: Enable (always detection) / “0”: Disable.

DCD timeout period setting.

“1”: 1280 ms / “0”: 640 ms.

3

2

1

DCDMODE

reserved

Enabling automatic USB-Switch control.

“1”: Enable (auto) / “0”: Disable (manual).

USB Switch manual control.

USB_SW_EN

0

USB_SW

“1”: Switch ON / “0”: Switch OFF.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.42. VCC_UCD_STATUS

BC1.2 Charger Detect Status on the VCC side

Command Code:

Bus Protocol:

29h

Read Word

Bit

Symbol

Description

DCD (USB Data Contact Detection) failed (timeout) status.

“1”: Failed / “0”: Succeeded.

15

DCDFAIL

reserved

CHGPORT[1]

CHGPORT[0]

14

13

12

USB Charger Port Detection result.

00b: No charger port/ 01b: SDP/ 10b: CDP/ 11b: DCP

Pull-up detected at Primary Detection after DCDFAIL.

“1”: Detected / “0”: Not detected.

11

PUPDET

10

9

8

reserved

USB VBUS valid voltage detection status.

“1”: Valid / “0”: Not valid.

USB Charger Port detection status.

“1”: Detected / “0”: Not detected.

7

6

VBUS_VLD

CHGDET

5

4

reserved

USB OTG Device detection status.

“1”: Detected / “0”: Not detected.

3

OTGDET

2

1

0

reserved

CHGDET

PUPDET

DCDFAIL

CHGPORT[1]

CHGPORT[0]

VBUS Open

SDP

CDP

0

1

0

1

0

1

0

1

0

1

0

1

DCP

Pull-up Port

Open Port

Unstable Port

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.43. VCC_IDD_STATUS

ID Detect Status on the VCC side

Command Code:

Bus Protocol:

2Ah

Read Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

7

VBUS voltage status while ID detection.

“1”: Normal voltage / “0”: Abnormal voltage.

Check MHL ID (1k Ohm) detection support.

“1”: Supported / “0”: Not supported.

USB ID Resistor contact detection status.

“1”: Detected (contacted) / “0”: Not detected (removed).

USB ID detection result.

6

5

4

VBINOP

EXTID

IDRDET

3

2

1

0

INDO[3]

INDO[2]

INDO[1]

INDO[0]

INDO

0h

ID Resistance

0 - 10Ω

36.5kΩ

47kΩ

Detected Port/Device

RID_GND (OTG)

1h

RID_C (ACA_C, SDP)

2h

-

3h

68kΩ

RID_B (ACA_B, DCP)

4h

102kΩ

124kΩ

180kΩ

200kΩ

287kΩ

390kΩ

440kΩ

557kΩ

797kΩ

>1MΩ

-

5h

RID_A (ACA_A, CDP)

6h

-

7h

RID_FLOAT

8h

-

9h

-

Ah

Bh

Ch

Dh

Eh

Fh

-

1KΩ

(MHL)

Illegal ID

Unknown

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.44. VCC_UCD_FCTRL_SET

BC1.2 Charger Detector on the VCC side Manual Control Setting

Command Code:

Bus Protocol:

2Bh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

UCDSWEN

RREF_EN

DPPU_EN

DPREF_EN

DMREF_EN

DPDET_EN

DMDET_EN

DPSINK_EN

DMSINK_EN

DP_BUFF_EN

DM_BUFF_EN

In normal operation, please don’t set these registers.

4

3

2

1

0

8.5.45. VCC_UCD_FCTRL_EN

BC1.2 Charger Detector on the VCC side Manual Control Enable

Command Code:

Bus Protocol:

Bit

2Ch

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

EXTCLKENBL

PLSTESTEN

reserved

UCDSWEN_TSTENB

RREF_EN_TSTENB

DPPU_EN_TSTENB

DPREF_EN_TSTENB

DMREF_EN_TSTENB

DPDET_EN_TSTENB

DMDET_EN_TSTENB

DPSINK_EN_TSTENB

DMSINK_EN_TSTENB

DP_BUFF_EN_TSTENB

DM_BUFF_EN_TSTENB

In normal operation, please don’t set these registers.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.46. VBUS_UCD_SET

BC1.2 Charger Detector on the VBUS side Setting

Command Code:

Bus Protocol:

Bit

30h

Read/Write Word

Symbol

Description

15

14

13

reserved

Trigger for re-trial of the USB Charger Port detection.

“1”: Start detection / “0”: Release the operation.

12

BCSRETRY

11

10

9

reserved

Trigger for re-trial of USB ID Resistor detection.

“1”: Start detection / “0”: Release the operation.

Enabling USB Charger port detection.

“1”: Enable / “0”: Disable.

Enabling USB ID Resistor detection.

“1”: Enable / “0”: Disable.

Setting USB Enumeration to Ready.

“1”: Skip Secondary Detection / “0”: Normal operation.

USB ID input polling enable.

8

7

6

5

4

ADCRTRY

USBDETEN

IDRDETEN

ENUMRDY

ADCPOLEN

“1”: Enable (always detection) / “0”: Disable.

DCD timeout period setting.

“1”: 1280 ms / “0”: 640 ms.

3

2

1

DCDMODE

reserved

Enabling automatic USB-Switch control.

“1”: Enable (auto) / “0”: Disable (manual).

USB Switch manual control.

USB_SW_EN

0

USB_SW

“1”: Switch ON / “0”: Switch OFF.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.47. VBUS_UCD_STATUS

BC1.2 Charger Detect Status on the VBUS side

Command Code:

Bus Protocol:

Bit

31h

Read Word

Symbol

Description

DCD (USB Data Contact Detection) failed (timeout) status.

“1”: Failed / “0”: Succeeded.

15

DCDFAIL

reserved

CHGPORT[1]

CHGPORT[0]

14

13

12

USB Charger Port Detection result.

00b: No charger port/ 01b: SDP/ 10b: CDP/ 11b: DCP

Pull-up detected at Primary Detection after DCDFAIL.

“1”: Detected / “0”: Not detected.

11

PUPDET

10

9

8

reserved

USB VBUS valid voltage detection status.

“1”: Valid / “0”: Not valid.

USB Charger Port detection status.

“1”: Detected / “0”: Not detected.

7

6

VBUS_VLD

CHGDET

5

4

reserved

USB OTG Device detection status.

“1”: Detected / “0”: Not detected.

3

OTGDET

2

1

0

reserved

CHGDET

PUPDET

DCDFAIL

CHGPORT[1] CHGPORT[0]

VBUS Open

SDP

CDP

0

1

0

1

0

1

0

1

0

1

0

1

DCP

Pull-up Port

Open Port

Unstable Port

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.48. VBUS_IDD_STATUS

ID Detect Status on the VBUS side

Command Code:

Bus Protocol:

32h

Read Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

7

VBUS voltage status while ID detection.

“1”: Normal voltage / “0”: Abnormal voltage.

Check MHL ID (1k Ohm) detection support.

“1”: Supported / “0”: Not supported.

USB ID Resistor contact detection status.

“1”: Detected (contacted) / “0”: Not detected (removed).

USB ID detection result.

6

5

4

VBINOP

EXTID

IDRDET

3

2

1

0

INDO[3]

INDO[2]

INDO[1]

INDO[0]

INDO

0h

1h

ID Resistance

0 - 10Ω

36.5kΩ

47kΩ

Detected Port/Device

RID_GND (OTG)

RID_C (ACA_C, SDP)

-

2h

3h

68kΩ

RID_B (ACA_B, DCP)

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

102kΩ

124kΩ

180kΩ

200kΩ

287kΩ

390kΩ

440kΩ

557kΩ

797kΩ

>1MΩ

-

RID_A (ACA_A, CDP)

-

RID_FLOAT

-

1KΩ

Illegal ID

(MHL)

Unknown

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.49. VBUS_UCD_FCTRL_SET

BC1.2 Charger Detector on the VBUS side Manual Control Setting

Command Code:

Bus Protocol:

33h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

UCDSWEN

RREF_EN

DPPU_EN

DPREF_EN

DMREF_EN

DPDET_EN

DMDET_EN

DPSINK_EN

DMSINK_EN

DP_BUFF_EN

DM_BUFF_EN

In normal operation, please don’t set these registers.

4

3

2

1

0

8.5.50. VBUS_UCD_FCTRL_EN

BC1.2 Charger Detector on the VBUS side Manual Control Enable

Command Code:

Bus Protocol:

Bit

34h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

EXTCLKENBL

PLSTESTEN

reserved

UCDSWEN_TSTENB

RREF_EN_TSTENB

DPPU_EN_TSTENB

DPREF_EN_TSTENB

DMREF_EN_TSTENB

DPDET_EN_TSTENB

DMDET_EN_TSTENB

DPSINK_EN_TSTENB

DMSINK_EN_TSTENB

DP_BUFF_EN_TSTENB

DM_BUFF_EN_TSTENB

In normal operation, please don’t set these registers.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.51. CHIP_ID

Chip ID

Command Code:

Bus Protocol:

38h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

CHIP_ID[15]

CHIP_ID[14]

CHIP_ID[13]

CHIP_ID[12]

CHIP_ID[11]

CHIP_ID[10]

CHIP_ID[9]

CHIP_ID[8]

CHIP_ID[7]

CHIP_ID[6]

CHIP_ID[5]

CHIP_ID[4]

CHIP_ID[3]

CHIP_ID[2]

CHIP_ID[1]

CHIP_ID[0]

Chip ID

4

3

2

1

0

8.5.52. CHIP_REV

Chip Revision

Command Code:

Bus Protocol:

Bit

39h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

CHIP_REV[15]

CHIP_REV[14]

Chip Revision

CHIP_REV[13]

CHIP_REV[12]

CHIP_REV[11]

CHIP_REV[10]

CHIP_REV[9]

CHIP_REV[8]

CHIP_REV[7]

CHIP_REV[6]

CHIP_REV[5]

CHIP_REV[4]

CHIP_REV[3]

CHIP_REV[2]

CHIP_REV[1]

CHIP_REV[0]

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.53. IC_SET1

ACP discharge control and ACOK control setting.

Command Code:

Bus Protocol:

Bit

3Ah

Read/Write Word

Symbol

Description

15

14

13

12

reserved

1 cell battery mode.

“1”: 1 cell battery mode/ “0”: 2~4 cells battery mode

11

ONE_CELL_MODE

“1”:VFASTCHG_REG_SET1, 2, 3 set less than 4.6V and

VSYSREG_SET set less than 5.0V

“0”:VSYSREG_SET set more than 5.0V

10

9

reserved

VACP Auto Discharge control is enable when the Power path is changed.

“1”: VACP Auto discharge control is enabled./ “0”: Disabled.

VACP Discharge control when the VACP power path is plugged off.

“1”: VACP load on and discharged./ “0”: VACP load off.

VACP_AUTO_DISCHG

8

VACP_LOAD

7

6

5

4

3

2

reserved

ACOK open drain output polarity control.

1

0

ACOK_POL

“1”: ACOK polarity is inverted, L=Asserted, Hi-z=Deasserted. / “0”: ACOK

polarity is normal, L=Deasserted, Hi-z=Asserted.

ACOK open drain output disable.

ACOK_DISEN

“1”: Disable, ACOK is Hi-z. / “0”: Enable.

8.5.54. IC_SET2

Debug Setting Register (for debug and production test)

Command Code:

Bus Protocol:

Bit

3Bh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

reserved

8

7

6

5

4

3

DEBUG_SET[8]

DEBUG_SET[7]

DEBUG_SET[6]

DEBUG_SET[5]

DEBUG_SET[4]

reserved

Debug Setting (for debug and production test)

2

reserved

1

reserved

0

DEBUG_SET[0]

Debug Setting (for debug and production test)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.55. SYSTEM_STATUS

System Power-on Status

Command Code:

Bus Protocol:

3Ch

Read Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

7

Reset status for MONRST.

“1”: Reset asserted / “0”: Reset released.

Reset status for ALMRST.

“1”: Reset asserted / “0”: Reset released.

Reset status for CHGRST.

6

5

4

MONRST_STATE

ALMRST_STATE

CHGRST_STATE

“1”: Reset asserted / “0”: Reset released.

3

2

reserved

OTPROM loading status.

“1” shows the OTPROM loading is finished./ “0”: not finished.

Reset status for ALLRST.

“1”: Reset asserted / “0”: Reset released.

1

0

OTPLD_STATE

ALLRST_STATE

8.5.56. SYSTEM_CTRL_SET

Software reset and reload OTP

Command Code:

Bus Protocol:

3Dh

Read/Write Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

7

Writing “1” resets Voltage Meter block and the status registers. But the setting

registers are not initialized.

Writing “0” releases reset operation.

Writing “1” resets Interrupt block and the status registers. But the setting

registers are not initialized.

Writing “0” releases reset operation.

Writing “1” resets Battery Charger block and USB Detector block and the

status registers. But the setting registers are not initialized.

Writing “0” releases reset operation.

6

5

4

MONRST

ALMRST

CHGRST

3

2

reserved

Writing “1” starts to load the OTPROM data into the internal registers.

OTPROM data is loaded automatically for power-on sequence. But if

necessary, user is able to reload the OTPROM data by writing this bit “1”.

Writing “1” resets Voltage Meter block, Interrupt block, Battery Charger block

and USB Detector blocks and the status registers. But the setting registers are

not initialized.

1

OTPLD

0

ALLRST

Writing “0” release reset operation.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.57. PROTECT_SET

Access Un-protect Setting for Address 3Fh

Command Code:

Bus Protocol:

Bit

3Eh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

PROTECT_SET[15]

PROTECT_SET[14]

PROTECT_SET[13]

PROTECT_SET[12]

PROTECT_SET[11]

PROTECT_SET[10]

PROTECT_SET[9]

PROTECT_SET[8]

PROTECT_SET[7]

PROTECT_SET[6]

PROTECT_SET[5]

PROTECT_SET[4]

PROTECT_SET[3]

PROTECT_SET[2]

PROTECT_SET[1]

PROTECT_SET[0]

Access Un-protect Setting for the “debug command map”

(debug and production test only)

4

3

2

1

0

8.5.58. MAP_SET

Change Command Code Map

Command Code:

Bus Protocol:

3Fh

Read/Write Word

Description

Change Command Code Map

Bit

15

14

13

12

11

10

9

Symbol

MAP_SET[15]

MAP_SET[14]

MAP_SET[13]

MAP_SET[12]

MAP_SET[11]

MAP_SET[10]

MAP_SET[9]

MAP_SET[8]

MAP_SET[7]

MAP_SET[6]

MAP_SET[5]

MAP_SET[4]

MAP_SET[3]

MAP_SET[2]

MAP_SET[1]

MAP_SET[0]

8

7

6

5

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.59. VM_CTRL_SET

SAR-ADC Measurement Control Setting

Command Code:

Bus Protocol:

Bit

40h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

ADCINTERVAL[1]

ADCINTERVAL[0]

ADCMOD[1]

ADCMOD[0]

ADCTMOD[1]

ADCTMOD[0]

SAR-ADC Operating Interval Setting.

00b: No Interval/ 01b: 1ms/ 10b: 10ms/ 11b: 100msec

Operation Mode Setting

00b: Power Down/ 01b: Normal Operation

Test Mode Setting

00b: Normal Operation/ 01b: Test Mode

IADP (Input current Limit setting pin) voltage measurement.

“1”: Enable / “0”: Disable.

VSYS voltage measurement.

“1”: Enable / “0”: Disable.

VCC voltage measurement.

“1”: Enable / “0”: Disable.

VBUS voltage measurement.

“1”: Enable / “0”: Disable.

VACP voltage measurement.

“1”: Enable / “0”: Disable.

IACP voltage measurement.

“1”: Enable / “0”: Disable.

TSENSE voltage measurement.

“1”: Enable / “0”: Disable.

VBAT voltage measurement.

“1”: Enable / “0”: Disable.

IBATM current (discharge) measurement.

“1”: Enable / “0”: Disable.

IBATP current (current) measurement.

“1”: Enable / “0”: Disable.

9

8

7

6

5

4

3

2

1

0

EXTIADPEN

VSYSENB

VCCENB

VBUSENB

VACPENB

IACPENB

THERMENB

VBATENB

IBATMENB

IBATPENB

8.5.60. THERM_WINDOW_SET1

JEITA Battery Temperature Window Setting 1

Command Code:

Bus Protocol:

Bit

41h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

TMPTHR1B[7]

TMPTHR1B[6]

Upper threshold of T1, JEITA profile.

(200-THERM1B [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

TMPTHR1B[5]

TMPTHR1B[4]

TMPTHR1B[3]

TMPTHR1B[2]

TMPTHR1B[1]

TMPTHR1B[0]

TMPTHR1A[7]

TMPTHR1A[6]

TMPTHR1A[5]

TMPTHR1A[4]

TMPTHR1A[3]

TMPTHR1A[2]

TMPTHR1A[1]

TMPTHR1A[0]

Lower threshold of T1, JEITA profile.

(200-THERM1A [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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8.5.61. THERM_WINDOW_SET2

JEITA Battery Temperature Window Setting 2

Command Code:

Bus Protocol:

Bit

42h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

TMPTHR2B[7]

TMPTHR2B[6]

Upper threshold of T2, JEITA profile.

(200-THERM2B [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

TMPTHR2B[5]

TMPTHR2B[4]

TMPTHR2B[3]

TMPTHR2B[2]

TMPTHR2B[1]

TMPTHR2B[0]

TMPTHR2A[7]

TMPTHR2A[6]

TMPTHR2A[5]

TMPTHR2A[4]

TMPTHR2A[3]

TMPTHR2A[2]

TMPTHR2A[1]

TMPTHR2A[0]

Lower threshold of T2, JEITA profile.

(200-THERM2A [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

4

3

2

1

0

8.5.62. THERM_WINDOW_SET3

JEITA Battery Temperature Window Setting 3

Command Code:

Bus Protocol:

Bit

43h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

TMPTHR3B[7]

TMPTHR3B[6]

Upper threshold of T3, JEITA profile.

(200-THERM3B [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

TMPTHR3B[5]

TMPTHR3B[4]

TMPTHR3B[3]

TMPTHR3B[2]

TMPTHR3B[1]

TMPTHR3B[0]

TMPTHR3A[7]

TMPTHR3A[6]

TMPTHR3A[5]

TMPTHR3A[4]

TMPTHR3A[3]

TMPTHR3A[2]

TMPTHR3A[1]

TMPTHR3A[0]

Lower threshold of T3, JEITA profile.

(200-THERM3A [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.63. THERM_WINDOW_SET4

JEITA Battery Temperature Window Setting 4

Command Code:

Bus Protocol:

Bit

44h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

TMPTHR4B[7]

TMPTHR4B[6]

Upper threshold of T4, JEITA profile.

(200-THERM4B [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

TMPTHR4B[5]

TMPTHR4B[4]

TMPTHR4B[3]

TMPTHR4B[2]

TMPTHR4B[1]

TMPTHR4B[0]

TMPTHR4A[7]

TMPTHR4A[6]

TMPTHR4A[5]

TMPTHR4A[4]

TMPTHR4A[3]

TMPTHR4A[2]

TMPTHR4A[1]

TMPTHR4A[0]

Lower threshold of T4, JEITA profile.

(200-THERM4A [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

4

3

2

1

0

8.5.64. THERM_WINDOW_SET5

JEITA Battery Temperature Window Setting 5

Command Code:

Bus Protocol:

Bit

45h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

TMPTHR5B[7]

TMPTHR5B[6]

Upper threshold of T5, between T3 and T4.

(200-THERM5B [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

TMPTHR5B[5]

TMPTHR5B[4]

TMPTHR5B[3]

TMPTHR5B[2]

TMPTHR5B[1]

TMPTHR5B[0]

TMPTHR5A[7]

TMPTHR5A[6]

TMPTHR5A[5]

TMPTHR5A[4]

TMPTHR5A[3]

TMPTHR5A[2]

TMPTHR5A[1]

TMPTHR5A[0]

Lower threshold of T5, between T3 and T4.

(200-THERM5A [7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

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TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.65. IBATP_TH_SET

Battery Current (Charge) Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

46h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATP_TH_SET[14]

IBATP_TH_SET[13]

IBATP_TH_SET[12]

IBATP_TH_SET[11]

IBATP_TH_SET[10]

IBATP_TH_SET[9]

IBATP_TH_SET[8]

IBATP_TH_SET[7]

IBATP_TH_SET[6]

IBATP_TH_SET[5]

IBATP_TH_SET[4]

IBATP_TH_SET[3]

IBATP_TH_SET[2]

IBATP_TH_SET[1]

IBATP_TH_SET[0]

Battery Current (Charge) Interrupt Threshold.

0 to 25,000mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 25,000mA.

4

3

2

1

0

8.5.66. IBATM_TH_SET

Battery Current (Dis-charge) Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

47h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATM_TH_SET[14]

IBATM_TH_SET[13]

IBATM_TH_SET[12]

IBATM_TH_SET[11]

IBATM_TH_SET[10]

IBATM_TH_SET[9]

IBATM_TH_SET[8]

IBATM_TH_SET[7]

IBATM_TH_SET[6]

IBATM_TH_SET[5]

IBATM_TH_SET[4]

IBATM_TH_SET[3]

IBATM_TH_SET[2]

IBATM_TH_SET[1]

IBATM_TH_SET[0]

Battery Current (Dis-charge) Interrupt Threshold.

0 to 25,000mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 25,000mA.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

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TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.67. VBAT_TH_SET

Battery Voltage Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

48h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VBAT_TH_SET[14]

VBAT_TH_SET[13]

VBAT_TH_SET[12]

VBAT_TH_SET[11]

VBAT_TH_SET[10]

VBAT_TH_SET[9]

VBAT_TH_SET[8]

VBAT_TH_SET[7]

VBAT_TH_SET[6]

VBAT_TH_SET[5]

VBAT_TH_SET[4]

VBAT_TH_SET[3]

VBAT_TH_SET[2]

VBAT_TH_SET[1]

VBAT_TH_SET[0]

Battery Voltage Interrupt Threshold.

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

8.5.68. THERM_TH_SET

Battery Temperature Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

49h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

reserved

8

7

6

5

4

3

2

1

0

THERM_TH_SET[7]

THERM_TH_SET[6]

THERM_TH_SET[5]

THERM_TH_SET[4]

THERM_TH_SET[3]

THERM_TH_SET[2]

THERM_TH_SET[1]

THERM_TH_SET[0]

Battery Temperature Interrupt Threshold Setting

(200-THERM_TH_SET[7:0]) deg-C.

-55 to 200 deg-C range, 1 deg-C steps.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

8.5.69. IACP_TH_SET

Input Current (between ACP-ACN) Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

4Ah

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IACP_TH_SET[14]

IACP_TH_SET[13]

IACP_TH_SET[12]

IACP_TH_SET[11]

IACP_TH_SET[10]

IACP_TH_SET[9]

IACP_TH_SET[8]

IACP_TH_SET[7]

IACP_TH_SET[6]

IACP_TH_SET[5]

IACP_TH_SET[4]

IACP_TH_SET[3]

IACP_TH_SET[2]

IACP_TH_SET[1]

IACP_TH_SET[0]

Input Current (between ACP-ACN) Interrupt Threshold.

0 to 16,384mA, 1mA steps.

The register range : 0 to 32,752mA.

But the actual range : 0 to 16,383mA.

4

3

2

1

0

8.5.70. VACP_TH_SET

Input Voltage (ACP) Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

4Bh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VACP_TH_SET[14]

VACP_TH_SET[13]

VACP_TH_SET[12]

VACP_TH_SET[11]

VACP_TH_SET[10]

VACP_TH_SET[9]

VACP_TH_SET[8]

VACP_TH_SET[7]

VACP_TH_SET[6]

VACP_TH_SET[5]

VACP_TH_SET[4]

VACP_TH_SET[3]

VACP_TH_SET[2]

VACP_TH_SET[1]

VACP_TH_SET[0]

Input Voltage (ACP) Interrupt Threshold.

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

http://www.rohm.com/

TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.71. VBUS_TH_SET

VBUS Voltage Interrupt Threshold Setting

Command Code:

Bus Protocol:

4Ch

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VBUS_TH_SET[14]

VBUS_TH_SET[13]

VBUS_TH_SET[12]

VBUS_TH_SET[11]

VBUS_TH_SET[10]

VBUS_TH_SET[9]

VBUS_TH_SET[8]

VBUS_TH_SET[7]

VBUS_TH_SET[6]

VBUS_TH_SET[5]

VBUS_TH_SET[4]

VBUS_TH_SET[3]

VBUS_TH_SET[2]

VBUS_TH_SET[1]

VBUS_TH_SET[0]

VBUS Voltage Interrupt Threshold.

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

8.5.72. VCC_TH_SET

VCC Voltage Interrupt Threshold Setting

Command Code:

Bus Protocol:

4Dh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VCC_TH_SET[14]

VCC_TH_SET[13]

VCC_TH_SET[12]

VCC_TH_SET[11]

VCC_TH_SET[10]

VCC_TH_SET[9]

VCC_TH_SET[8]

VCC_TH_SET[7]

VCC_TH_SET[6]

VCC_TH_SET[5]

VCC_TH_SET[4]

VCC_TH_SET[3]

VCC_TH_SET[2]

VCC_TH_SET[1]

VCC_TH_SET[0]

VCC Voltage Interrupt Threshold.

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

http://www.rohm.com/

TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.73. VSYS_TH_SET

VSYS Voltage Interrupt Threshold Setting

Command Code:

Bus Protocol:

4Eh

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VSYS_TH_SET[14]

VSYS_TH_SET[13]

VSYS_TH_SET[12]

VSYS_TH_SET[11]

VSYS_TH_SET[10]

VSYS_TH_SET[9]

VSYS_TH_SET[8]

VSYS_TH_SET[7]

VSYS_TH_SET[6]

VSYS_TH_SET[5]

VSYS_TH_SET[4]

VSYS_TH_SET[3]

VSYS_TH_SET[2]

VSYS_TH_SET[1]

VSYS_TH_SET[0]

VSYS Voltage Interrupt

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,752mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

8.5.74. EXTIADP_TH_SET

IADP (Input current Limit setting pin) Voltage Interrupt Threshold Setting

Command Code:

Bus Protocol:

Bit

4Fh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

EXTIADP_TH_SET[11]

EXTIADP_TH_SET[10]

EXTIADP_TH_SET[9]

EXTIADP_TH_SET[8]

EXTIADP_TH_SET[7]

EXTIADP_TH_SET[6]

EXTIADP_TH_SET[5]

EXTIADP_TH_SET[4]

EXTIADP_TH_SET[3]

EXTIADP_TH_SET[2]

EXTIADP_TH_SET[1]

EXTIADP_TH_SET[0]

IADP (Input current Limit setting pin) voltage Interrupt

(for Debug use)

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

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Datasheet

BD99954MWV, BD99954GW

8.5.75. IBATP_VAL

Battery Current (Charge) Measurement Value

Command Code:

Bus Protocol:

Bit

50h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATP_VAL[14]

IBATP_VAL[13]

IBATP_VAL[12]

IBATP_VAL[11]

IBATP_VAL[10]

IBATP_VAL[9]

IBATP_VAL[8]

IBATP_VAL[7]

IBATP_VAL[6]

IBATP_VAL[5]

IBATP_VAL[4]

IBATP_VAL[3]

IBATP_VAL[2]

IBATP_VAL[1]

IBATP_VAL[0]

Battery Current (Charge) Measurement Value

0 to 25,000mA, 1mA steps.

4

3

2

1

0

8.5.76. IBATP_AVE_VAL

Battery Current (Charge) Measurement Average Value

Command Code:

Bus Protocol:

Bit

51h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATP_AVE_VAL[14]

IBATP_AVE_VAL[13]

IBATP_AVE_VAL[12]

IBATP_AVE_VAL[11]

IBATP_AVE_VAL[10]

IBATP_AVE_VAL[9]

IBATP_AVE_VAL[8]

IBATP_AVE_VAL[7]

IBATP_AVE_VAL[6]

IBATP_AVE_VAL[5]

IBATP_AVE_VAL[4]

IBATP_AVE_VAL[3]

IBATP_AVE_VAL[2]

IBATP_AVE_VAL[1]

IBATP_AVE_VAL[0]

Battery Current (Charge) Measurement Average Value

0 to 25,000mA, 1mA steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

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TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.77. IBATM_VAL

Battery Current (Dis-charge) Measurement Value

Command Code:

Bus Protocol:

Bit

52h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATM_VAL[14]

IBATM_VAL[13]

IBATM_VAL[12]

IBATM_VAL[11]

IBATM_VAL[10]

IBATM_VAL[9]

IBATM_VAL[8]

IBATM_VAL[7]

IBATM_VAL[6]

IBATM_VAL[5]

IBATM_VAL[4]

IBATM_VAL[3]

IBATM_VAL[2]

IBATM_VAL[1]

IBATM_VAL[0]

Battery Current (Dis-charge) Measurement Value

0 to 25,000mA, 1mA steps.

4

3

2

1

0

8.5.78. IBATM_AVE_VAL

Battery Current (Dis-charge) Measurement Average Value

Command Code:

Bus Protocol:

Bit

53h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

IBATM_AVE_VAL[14]

IBATM_AVE_VAL[13]

IBATM_AVE_VAL[12]

IBATM_AVE_VAL[11]

IBATM_AVE_VAL[10]

IBATM_AVE_VAL[9]

IBATM_AVE_VAL[8]

IBATM_AVE_VAL[7]

IBATM_AVE_VAL[6]

IBATM_AVE_VAL[5]

IBATM_AVE_VAL[4]

IBATM_AVE_VAL[3]

IBATM_AVE_VAL[2]

IBATM_AVE_VAL[1]

IBATM_AVE_VAL[0]

Battery Current (Dis-charge) Measurement Average Value

0 to 25,000mA, 1mA steps.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

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TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.79. VBAT_VAL

Battery Voltage Measurement Value

Command Code:

Bus Protocol:

54h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VBAT_VAL[14]

VBAT_VAL[13]

VBAT_VAL[12]

VBAT_VAL[11]

VBAT_VAL[10]

VBAT_VAL[9]

VBAT_VAL[8]

VBAT_VAL[7]

VBAT_VAL[6]

VBAT_VAL[5]

VBAT_VAL[4]

VBAT_VAL[3]

VBAT_VAL[2]

VBAT_VAL[1]

VBAT_VAL[0]

Battery Voltage Measurement Value

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

8.5.80. VBAT_AVE_VAL

Battery Voltage Measurement Average Value

Command Code:

Bus Protocol:

Bit

55h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VBAT_AVE_VAL[14]

VBAT_AVE_VAL[13]

VBAT_AVE_VAL[12]

VBAT_AVE_VAL[11]

VBAT_AVE_VAL[10]

VBAT_AVE_VAL[9]

VBAT_AVE_VAL[8]

VBAT_AVE_VAL[7]

VBAT_AVE_VAL[6]

VBAT_AVE_VAL[5]

VBAT_AVE_VAL[4]

VBAT_AVE_VAL[3]

VBAT_AVE_VAL[2]

VBAT_AVE_VAL[1]

VBAT_AVE_VAL[0]

Battery Voltage Measurement Average Value

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

http://www.rohm.com/

TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.81. THERM_VAL

Thermistor Temperature Measurement Value

Command Code:

Bus Protocol:

Bit

56h

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

reserved

8

7

6

5

4

3

2

1

0

THERM_VAL[7]

THERM_VAL[6]

THERM_VAL[5]

THERM_VAL[4]

THERM_VAL[3]

THERM_VAL[2]

THERM_VAL[1]

THERM_VAL[0]

Temperature Measurement Value

(200-THERM_VAL[7:0]) deg-C.

-55 to 200 deg-C, 1 deg-C steps.

Write Word access is available when VM_CTRL_SET.THERMENB bit = 0.

8.5.82. VTH_VAL

Thermistor Measurement Voltage Value

Command Code:

Bus Protocol:

Bit

57h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VTH_VAL[11]

VTH_VAL[10]

VTH_VAL[9]

VTH_VAL[8]

VTH_VAL[7]

VTH_VAL[6]

VTH_VAL[5]

VTH_VAL[4]

VTH_VAL[3]

VTH_VAL[2]

VTH_VAL[1]

VTH_VAL[0]

Thermistor Measurement Voltage Value

(for Debug use)

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

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TSZ22111-14-001

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Datasheet

BD99954MWV, BD99954GW

8.5.83. IACP_VAL

Input Current (between ACP-ACN) Measurement Value

Command Code:

Bus Protocol:

58h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

IACP_VAL[14]

IACP_VAL[13]

IACP_VAL[12]

IACP_VAL[11]

IACP_VAL[10]

IACP_VAL[9]

IACP_VAL[8]

IACP_VAL[7]

IACP_VAL[6]

IACP_VAL[5]

IACP_VAL[4]

IACP_VAL[3]

IACP_VAL[2]

IACP_VAL[1]

IACP_VAL[0]

Input Current (between ACP-ACN) Measurement Value

0 to 16,384mA, 1mA steps.

4

3

2

1

0

8.5.84. IACP_AVE_VAL

Input Current (between ACP-ACN) Measurement Average Value

Command Code:

Bus Protocol:

Bit

59h

Read Word

Symbol

Description

15 reserved

14 IACP_AVE_VAL[14]

13 IACP_AVE_VAL[13]

12 IACP_AVE_VAL[12]

11 IACP_AVE_VAL[11]

10 IACP_AVE_VAL[10]

Input Current (between ACP-ACN) Measurement Average Value

0 to 16,384mA, 1mA steps.

9

8

7

6

5

4

3

2

1

0

IACP_AVE_VAL[9]

IACP_AVE_VAL[8]

IACP_AVE_VAL[7]

IACP_AVE_VAL[6]

IACP_AVE_VAL[5]

IACP_AVE_VAL[4]

IACP_AVE_VAL[3]

IACP_AVE_VAL[2]

IACP_AVE_VAL[1]

IACP_AVE_VAL[0]

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

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Datasheet

BD99954MWV, BD99954GW

8.5.85. VACP_VAL

Input Voltage (ACP) Measurement Value

Command Code:

Bus Protocol:

Bit

5Ah

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VACP_VAL[14]

VACP_VAL[13]

VACP_VAL[12]

VACP_VAL[11]

VACP_VAL[10]

VACP_VAL[9]

VACP_VAL[8]

VACP_VAL[7]

VACP_VAL[6]

VACP_VAL[5]

VACP_VAL[4]

VACP_VAL[3]

VACP_VAL[2]

VACP_VAL[1]

VACP_VAL[0]

Input Voltage (ACP) Measurement Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

8.5.86. VACP_AVE_VAL

Input Voltage (ACP) Measurement Average Value

Command Code:

Bus Protocol:

Bit

5Bh

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VACP_AVE_VAL[14]

VACP_AVE_VAL[13]

VACP_AVE_VAL[12]

VACP_AVE_VAL[11]

VACP_AVE_VAL[10]

VACP_AVE_VAL[9]

VACP_AVE_VAL[8]

VACP_AVE_VAL[7]

VACP_AVE_VAL[6]

VACP_AVE_VAL[5]

VACP_AVE_VAL[4]

VACP_AVE_VAL[3]

VACP_AVE_VAL[2]

VACP_AVE_VAL[1]

VACP_AVE_VAL[0]

Input Voltage (ACP) Measurement Average Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

TSZ02201-0B4B0A700040-1-2

18. Jul. 2017, Rev.001

http://www.rohm.com/

TSZ22111-14-001

86/127

Datasheet

BD99954MWV, BD99954GW

8.5.87. VBUS_VAL

VBUS Voltage Measurement Value

Command Code:

Bus Protocol:

5Ch

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VBUS_VAL[14]

VBUS_VAL[13]

VBUS_VAL[12]

VBUS_VAL[11]

VBUS_VAL[10]

VBUS_VAL[9]

VBUS_VAL[8]

VBUS_VAL[7]

VBUS_VAL[6]

VBUS_VAL[5]

VBUS_VAL[4]

VBUS_VAL[3]

VBUS_VAL[2]

VBUS_VAL[1]

VBUS_VAL[0]

VBUS Voltage Measurement Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

8.5.88. VBUS_AVE_VAL

VBUS Voltage Measurement Average Value

Command Code:

Bus Protocol:

Bit

5Dh

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VBUS_AVE_VAL[14]

VBUS_AVE_VAL[13]

VBUS_AVE_VAL[12]

VBUS_AVE_VAL[11]

VBUS_AVE_VAL[10]

VBUS_AVE_VAL[9]

VBUS_AVE_VAL[8]

VBUS_AVE_VAL[7]

VBUS_AVE_VAL[6]

VBUS_AVE_VAL[5]

VBUS_AVE_VAL[4]

VBUS_AVE_VAL[3]

VBUS_AVE_VAL[2]

VBUS_AVE_VAL[1]

VBUS_AVE_VAL[0]

VBUS Voltage Measurement Average Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.89. VCC_VAL

VCC Voltage Measurement Value

Command Code:

Bus Protocol:

5Eh

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VCC_VAL[14]

VCC_VAL[13]

VCC_VAL[12]

VCC_VAL[11]

VCC_VAL[10]

VCC_VAL[9]

VCC_VAL[8]

VCC_VAL[7]

VCC_VAL[6]

VCC_VAL[5]

VCC_VAL[4]

VCC_VAL[3]

VCC_VAL[2]

VCC_VAL[1]

VCC_VAL[0]

VCC Voltage Measurement Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

8.5.90. VCC_AVE_VAL

VCC Voltage Measurement Average Value

Command Code:

Bus Protocol:

Bit

5Fh

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VCC_AVE_VAL[14]

VCC_AVE_VAL[13]

VCC_AVE_VAL[12]

VCC_AVE_VAL[11]

VCC_AVE_VAL[10]

VCC_AVE_VAL[9]

VCC_AVE_VAL[8]

VCC_AVE_VAL[7]

VCC_AVE_VAL[6]

VCC_AVE_VAL[5]

VCC_AVE_VAL[4]

VCC_AVE_VAL[3]

VCC_AVE_VAL[2]

VCC_AVE_VAL[1]

VCC_AVE_VAL[0]

VCC Voltage Measurement Average Value

0 to 25,600mV, 1mV steps.

The register range : 0 to 32,767mV.

But the actual range : 0 to 25,600mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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8.5.91. VSYS_VAL

VSYS Voltage Measurement Value

Command Code:

Bus Protocol:

60h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

VSYS_VAL[14]

VSYS_VAL[13]

VSYS_VAL[12]

VSYS_VAL[11]

VSYS_VAL[10]

VSYS_VAL[9]

VSYS_VAL[8]

VSYS_VAL[7]

VSYS_VAL[6]

VSYS_VAL[5]

VSYS_VAL[4]

VSYS_VAL[3]

VSYS_VAL[2]

VSYS_VAL[1]

VSYS_VAL[0]

VSYS Voltage Measurement Value

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,752mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

8.5.92. VSYS_AVE_VAL

VSYS Voltage Measurement Average Value

Command Code:

Bus Protocol:

Bit

61h

Read Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

reserved

VSYS_AVE_VAL[14]

VSYS_AVE_VAL[13]

VSYS_AVE_VAL[12]

VSYS_AVE_VAL[11]

VSYS_AVE_VAL[10]

VSYS_AVE_VAL[9]

VSYS_AVE_VAL[8]

VSYS_AVE_VAL[7]

VSYS_AVE_VAL[6]

VSYS_AVE_VAL[5]

VSYS_AVE_VAL[4]

VSYS_AVE_VAL[3]

VSYS_AVE_VAL[2]

VSYS_AVE_VAL[1]

VSYS_AVE_VAL[0]

VSYS Voltage Measurement Average Value

0 to 19,200mV, 1mV steps.

The register range : 0 to 32,752mV.

But the actual range : 0 to 19,200mV.

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.93. EXTIADP_VAL

IADP (Input current Limit setting pin) Voltage Measurement Value

Command Code:

Bus Protocol:

62h

Read Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

Description

reserved

EXTIADP_VAL[11]

EXTIADP_VAL[10]

EXTIADP_VAL[9]

EXTIADP_VAL[8]

EXTIADP_VAL[7]

EXTIADP_VAL[6]

EXTIADP_VAL[5]

EXTIADP_VAL[4]

EXTIADP_VAL[3]

EXTIADP_VAL[2]

EXTIADP_VAL[1]

EXTIADP_VAL[0]

IADP (Input current Limit setting pin) voltage Measurement Value

(for Debug use)

4

3

2

1

0

8.5.94. EXTIADP_AVE_VAL

IADP (Input current Limit setting pin) Voltage Measurement Average Value

Command Code:

Bus Protocol:

63h

Read Word

Bit

Symbol

Description

15 reserved

14 reserved

13 reserved

12 reserved

11 EXTIADP_AVE_VAL[11]

10 EXTIADP_AVE_VAL[10]

IADP (Input current Limit setting pin) voltage Measurement Average Value

(for Debug use)

9

8

7

6

5

4

3

2

1

0

EXTIADP_AVE_VAL[9]

EXTIADP_AVE_VAL[8]

EXTIADP_AVE_VAL[7]

EXTIADP_AVE_VAL[6]

EXTIADP_AVE_VAL[5]

EXTIADP_AVE_VAL[4]

EXTIADP_AVE_VAL[3]

EXTIADP_AVE_VAL[2]

EXTIADP_AVE_VAL[1]

EXTIADP_AVE_VAL[0]

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.95. VACPCLPS_TH_SET

VACP Collapse Detect Threshold Voltage Setting

Command Code:

Bus Protocol:

64h

Read/Write Word

Bit

Symbol

Description

15 reserved

14 VACPCLPS_TH_SET[14]

13 VACPCLPS_TH_SET[13]

12 VACPCLPS_TH_SET[12]

11 VACPCLPS_TH_SET[11]

10 VACPCLPS_TH_SET[10]

VACP Anti-collapse entry voltage threshold.

3,840 to 32,640mV, 128mV steps.

The register range: 0 to 32,640mV.

But the actual range: 3,840 to 25,088mV.

“00h”setting disables VACP collapse detection.

9

8

7

6

5

4

3

2

1

0

VACPCLPS_TH_SET[9]

VACPCLPS_TH_SET[8]

VACPCLPS_TH_SET[7]

reserved

8.5.96. INT0_SET

1st Level Interrupt Setting

Command Code:

Bus Protocol:

68h

Read/Write Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

2nd Level Interrupt 7 (SAR-ADC) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 6 (Charger) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 5 (Charger) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 4 (VSYS) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 3 (Battery) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 2 (VCC) Enable.

“1”: Enable / “0”: Disable.

2nd Level Interrupt 1 (VBUS) Enable.

“1”: Enable / “0”: Disable.

1st Level Interrupt Enable.

7

6

5

4

3

2

1

0

INT7_EN

INT6_EN

INT5_EN

INT4_EN

INT3_EN

INT2_EN

INT1_EN

INT0_EN

“1”: Enable / “0”: Disable.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.97. INT1_SET

2nd Level Interrupt Setting 1 (VBUS)

Command Code:

Bus Protocol:

69h

Read/Write Word

Bit

Symbol

Description

Enabling interrupt of entering to VBUS reverse buck boost voltage low.

“1”: Enable / “0”: Disable.

15

VBUS_RBUV_DET

Enabling interrupt of exit from VBUS reverse buck boost voltage low.

“1”: Enable / “0”: Disable.

14

VBUS_RBUV_RES

13

12

11

10

reserved

Enabling interrupt VBUS Voltage > VBUS_TH_SET.

“1”: Enable / “0”: Disable.

9

VBUS_TH_DET

Enabling interrupt VBUS Voltage <= VBUS_TH_SET.

“1”: Enable / “0”: Disable.

8

7

6

VBUS_TH_RES

reserved

Enabling interrupt of VBUS input current-limit modified.

“1”: Enable / “0”: Disable.

VBUS_IIN_MOD

Enabling interrupt of VBUS over voltage detected.

“1”: Enable / “0”: Disable.

Enabling interrupt of VBUS over voltage resumed

“1”: Enable / “0”: Disable.

Enabling interrupt of entering to VBUS Anti-collapse operation.

“1”: Enable / “0”: Disable.

Enabling interrupt of exit from VBUS Anti-collapse operation.

“1”: Enable / “0”: Disable.

Enabling interrupt of VBUS detect.

“1”: Enable / “0”: Disable.

Enabling interrupt of VBUS removal.

“1”: Enable / “0”: Disable.

5

4

3

2

1

0

VBUS_OV_DET

VBUS_OV_RES

VBUS_CLPS_DET

VBUS_CLPS RES

VBUS_DET

VBUS_RES

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.98. INT2_SET

2nd Level Interrupt Setting 2 (VCC)

Command Code:

Bus Protocol:

6Ah

Read/Write Word

Bit

Symbol

Description

Enabling interrupt of entering to VCC reverse buck boost voltage low.

“1”: Enable / “0”: Disable.

15

VCC_RBUV_DET

Enabling interrupt of exit from VCC reverse buck boost voltage low.

“1”: Enable / “0”: Disable.

14

VCC_RBUV_RES

13

12

11

10

reserved

Interrupt VCC Voltage > VCC_TH_SET.

“1”: Enable / “0”: Disable.

9

VCC_TH_DET

Interrupt VCC Voltage <= VCC_TH_SET.

“1”: Enable / “0”: Disable.

8

7

VCC_TH_RES

reserved

Interrupt of VCC/VACP input current-limit modified.

“1”: Enable / “0”: Disable.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

6

VCC_IIN_MOD

Interrupt of VCC over voltage detected.

“1”: Enable / “0”: Disable.

Interrupt of VCC over voltage resumed

“1”: Enable / “0”: Disable.

5

4

VCC_OVP_DET

VCC_OVP_RES

Interrupt of entering to VCC/VACP Anti-collapse operation.

“1”: Enable / “0”: Disable.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

Interrupt of exit from VCC/VACP Anti-collapse operation.

“1”: Enable / “0”: Disable.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

3

2

VCC_CLPS_DET

VCC_CLPS_RES

Interrupt of VCC detect.

1

0

VCC_DET

VCC_RES

“1”: Enable / “0”: Disable.

Interrupt of VCC removal.

“1”: Enable / “0”: Disable.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.99. INT3_SET

2nd Level Interrupt Setting 3 (Battery)

Command Code:

Bus Protocol:

6Bh

Read/Write Word

Bit

Symbol

Description

Interrupt of the thermistor detected.

“1”: Enable / “0”: Disable.

Interrupt of the thermistor removal.

“1”: Enable / “0”: Disable.

15

TH_DET

TH_RMV

14

13

12

reserved

Interrupt of the thermistor out of the charging range.

“1”: Enable / “0”: Disable.

Interrupt of the thermistor in to the charging range.

“1”: Enable / “0”: Disable.

Interrupt VBAT Voltage > VBAT_TH_SET.

“1”: Enable / “0”: Disable.

11

10

9

TMP_OUT_DET

TMP_OUT_RES

VBAT_TH_DET

Interrupt VBAT Voltage <= VBAT_TH_SET.

“1”: Enable / “0”: Disable.

8

VBAT_TH_RES

Interrupt of Battery over current detected.

“1”: Enable / “0”: Disable.

Interrupt of Battery over current resumed.

“1”: Enable / “0”: Disable.

Interrupt of VBAT over voltage detected.

“1”: Enable / “0”: Disable.

Interrupt of VBAT over voltage resumed.

“1”: Enable / “0”: Disable.

Interrupt of Entering to Battery-assist mode.

“1”: Enable / “0”: Disable.

Interrupt of Exiting from Battery-assist mode.

“1”: Enable / “0”: Disable.

7

IBAT_SHORT_DET

IBAT_SHORT_RES

VBAT_OV_DET

VBAT_OV_RES

BAT_ASSIST_DET

BAT_ASSIST_RES

6

5

4

3

2

1

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.100.

INT4_SET

2nd Level Interrupt Setting 4 (VSYS)

Command Code:

Bus Protocol:

6Ch

Read/Write Word

Bit

15

14

13

12

11

10

Symbol

Description

reserved

Interrupt VSYS Voltage > VSYS_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt VSYS Voltage <= VSYS_TH_SET.

“1”: Enable / “0”: Disable.

9

8

VSYS_TH_DET

VSYS_TH_RES

7

6

reserved

Interrupt of VSYS over voltage detected.

“1”: Enable / “0”: Disable.

Interrupt of VSYS over voltage resumed.

“1”: Enable / “0”: Disable.

Interrupt of VSYS short circuit detected.

“1”: Enable / “0”: Disable.

Interrupt of VSYS short circuit resumed.

“1”: Enable / “0”: Disable.

Interrupt of VSYS under voltage detected.

“1”: Enable / “0”: Disable.

Interrupt of VSYS under voltage resumed.

“1”: Enable / “0”: Disable.

5

4

3

2

1

0

VSYS_OV_DET

VSYS_OV_RES

VSYS_SHT_DET

VSYS_SHT_RES

VSYS_UV_DET

VSYS_UV_RES

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.101.

INT5_SET

2nd Level Interrupt Setting 5 (Charger)

Command Code:

Bus Protocol:

6Dh

Read/Write Word

Bit

15

14

Symbol

Description

reserved

Interrupt of OTP load done.

“1”: Enable / “0”: Disable.

Interrupt of Power-on.

13

12

OTP_LOAD_DONE

PWR_ON

“1”: Enable / “0”: Disable.

Interrupt IADP voltage range transition.

“1”: Enable / “0”: Disable.

11

10

EXTIADP_TRNS

reserved

Interrupt IADP (Input current Limit setting pin) voltage >

EXTIADP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt IADP (Input current Limit setting pin) voltage <=

EXTIADP_TH_SET.

9

8

EXTIADP_TH_DET

EXIADP_TH_RES

“1”: Enable / “0”: Disable.

Interrupt of entering to Battery Maintenance charging.

“1”: Enable / “0”: Disable.

Interrupt of exit from Battery Maintenance charging.

“1”: Enable / “0”: Disable.

Interrupt of the TSD detected.

“1”: Enable / “0”: Disable.

Interrupt of the TSD resumed.

“1”: Enable / “0”: Disable.

Interrupt of Charger Watchdog Timer expired.

“1”: Enable / “0”: Disable.

Interrupt of Battery Temperature Watchdog Timer expired.

“1”: Enable / “0”: Disable.

7

6

5

4

3

2

1

0

BAT_MNT_DET

BAT_MNT_RES

TSD_DET

TSD_RES

CHGWDT_EXP

THERMWDT_EXP

TMP_TRNS

Interrupt of the Battery Temperature range transition.

“1”: Enable / “0”: Disable.

Interrupt of Charger-State transition.

“1”: Enable / “0”: Disable.

CHG_TRNS

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.102.

INT6_SET

2nd Level Interrupt Setting 6 (Charger)

Command Code:

Bus Protocol:

6Eh

Read/Write Word

Bit

15

14

Symbol

Description

reserved

Interrupt of USB Port contact detected on the VBUS side.

“1”: Enable / “0”: Disable.

Interrupt of USB Charger detected on the VBUS side.

“1”: Enable / “0”: Disable.

Interrupt of USB ID contact removed on the VBUS side.

“1”: Enable / “0”: Disable.

13

12

11

VBUS_UCD_PORT_DET

VBUS_UCD_UCHG_DET

VBUS_UCD_URID_RMV

Interrupt of USB OTG device detected on the VBUS side.

“1”: Enable / “0”: Disable.

10

9

VBUS_UCD_OTG_DET

reserved

Interrupt of USB ID resistance change on the VBUS side.

“1”: Enable / “0”: Disable.

8

VBUS_UCD_URID_MOD

7

6

reserved

Interrupt of USB Port contact detected on the VCC side.

“1”: Enable / “0”: Disable.

Interrupt of USB Charger detected on the VCC side.

“1”: Enable / “0”: Disable.

Interrupt of USB ID contact removed on the VCC side.

“1”: Enable / “0”: Disable.

5

4

3

VCC_UCD_PORT_DET

VCC_UCD_UCHG_DET

VCC_UCD_URID_RMV

Interrupt of USB OTG device detected on the VCC side.

“1”: Enable / “0”: Disable.

2

1

0

VCC_UCD_OTG_DET

reserved

Interrupt of USB ID resistance change on the VCC side.

“1”: Enable / “0”: Disable.

VCC_UCD_URID_MOD

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.103.

INT7_SET

2nd Level Interrupt Setting 7 (SAR-ADC)

Command Code:

Bus Protocol:

6Fh

Read/Write Word

Bit

Symbol

Description

Interrupt of PROCHOT# asserted.

“1”: Enable / “0”: Disable.

15

PROCHOT_DET

Interrupt of PROCHOT# de-asserted.

“1”: Enable / “0”: Disable.

14

PROCHOT_RES

13

12

reserved

Interrupt of VACP detect.

“1”: Enable / “0”: Disable.

11

10

VACP_DET

VACP_RES

Interrupt of VACP removal.

“1”: Enable / “0”: Disable.

Interrupt Input Voltage (ACP) Voltage > VACP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Input Voltage (ACP) Voltage <= VACP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Input Current (between ACP-ACN) > IACP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Input Current (between ACP-ACN) <= IACP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt TSENSE Voltage > THERM_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt TSENSE Voltage <= THERM_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Battery Current (Dis-charge) > IBATM_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Battery Current (Dis-charge) <= IBATM_TH_SET.

“1”: Enable / “0”: Disable.

9

8

7

6

5

4

3

2

1

0

VACP_TH_DET

VACP_TH_RES

IACP_TH_DET

IACP_THE_RES

THERM_TH_DET

THERM_TH_RES

IBATM_TH_DET

IBATM_TH_RES

IBATP_TH_DET

IBATP_TH_RES

Interrupt Battery Current (Charge) > IBATP_TH_SET.

“1”: Enable / “0”: Disable.

Interrupt Battery Current (Charge) <= IBATP_TH_SET.

“1”: Enable / “0”: Disable.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.104.

INT0_STATUS

1st Level Interrupt Status

Command Code:

Bus Protocol:

70h

Read/Write Word

Bit

15

14

13

12

11

10

9

Symbol

Description

reserved

8

2nd Level Interrupt 7 (SAR-ADC) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 6 (Charger) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 5 (Charger) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 4 (VSYS) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 3 (Battery) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 2 (VCC) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2nd Level Interrupt 1 (VBUS) Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

7

6

5

4

3

2

1

0

INT7_STATUS

INT6_STATUS

INT5_STATUS

INT4_STATUS

INT3_STATUS

INT2_STATUS

INT1_STATUS

INT0_STATUS

1st Level Interrupt Status.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.105.

INT1_STATUS

2nd Level Interrupt Status 1 (VBUS)

Command Code:

Bus Protocol:

71h

Read/Write Word

Bit

Symbol

Description

Interrupt status of entering to VBUS reverse buck boost voltage low.

“1”: Event occurred / “0”: No event.

15

VBUS_RBUV_DET

“1-Write”: Status clear.

Interrupt status of exit from VBUS reverse buck boost voltage low.

“1”: Event occurred / “0”: No event.

14

VBUS_RBUV_RES

“1-Write”: Status clear.

13

12

11

10

reserved

Interrupt status VBUS Voltage > VBUS_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

9

VBUS_TH_DET

Interrupt status VBUS Voltage <= VBUS_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

8

7

6

VBUS_TH_RES

reserved

Interrupt status of VBUS input current-limit modified.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

VBUS_IIN_MOD

Interrupt status of VBUS over voltage detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VBUS over voltage resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of entering to VBUS Anti-collapse operation.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of exit from VBUS Anti-collapse operation.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VBUS detect.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VBUS removal.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

5

4

3

2

1

0

VBUS_OV_DET

VBUS_OV_RES

VBUS_CLPS_DET

VBUS_CLPS RES

VBUS_DET

VBUS_RES

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.106.

INT2_STATUS

2nd Level Interrupt Status 2 (VCC)

Command Code:

Bus Protocol:

72h

Read/Write Word

Bit

Symbol

Description

Interrupt status of entering to VCC reverse buck boost voltage low.

“1”: Event occurred / “0”: No event.

15

VCC_RBUV_DET

“1-Write”: Status clear.

Interrupt status of exit from VCC reverse buck boost voltage low.

“1”: Event occurred / “0”: No event.

14

VCC_RBUV_RES

“1-Write”: Status clear.

13

12

11

10

reserved

Interrupt status VCC Voltage > VCC_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

9

VCC_TH_DET

Interrupt status VCC Voltage <= VCC_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

8

7

VCC_TH_RES

reserved

Interrupt status of VCC/VACP input current-limit modified.

“1”: Event occurred / “0”: No event.

6

VCC_IIN_MOD

“1-Write”: Status clear.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

Interrupt status of VCC over voltage detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VCC over voltage resumed.

“1”: Event occurred / “0”: No event.

5

4

VCC_OVP_DET

VCC_OVP_RES

“1-Write”: Status clear.

Interrupt status of entering to VCC/VACP Anti-collapse operation.

“1”: Event occurred / “0”: No event.

3

2

VCC_CLPS_DET

VCC_CLPS_RES

“1-Write”: Status clear.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

Interrupt status of exit from VCC/VACP Anti-collapse operation.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

(VACP-input is enabled when VCC_EN=VBUS_EN=0/ VCC-input is

enabled when VCC_EN=1)

Interrupt status of VCC detect.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

1

0

VCC_DET

VCC_RES

Interrupt status of VCC removal.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.107.

INT3_STATUS

2nd Level Interrupt Status 3 (Battery)

Command Code:

Bus Protocol:

73h

Read/Write Word

Bit

Symbol

Description

Interrupt status of the thermistor detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of the thermistor removal.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

15

TH_DET

TH_RMV

14

13

12

reserved

Interrupt status of the thermistor out of the charging range.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of the thermistor in to the charging range.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status VBAT Voltage > VBAT_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

11

10

9

TMP_OUT_DET

TMP_OUT_RES

VBAT_TH_DET

Interrupt status VBAT Voltage <= VBAT_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

8

VBAT_TH_RES

Interrupt status of Battery over current detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Battery over current resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VBAT over voltage detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VBAT over voltage resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Entering to Battery-assist mode.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Exiting from Battery-assist mode.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

7

IBAT_SHORT_DET

IBAT_SHORT_RES

VBAT_OV_DET

VBAT_OV_RES

BAT_ASSIST_DET

BAT_ASSIST_RES

6

5

4

3

2

1

0

reserved

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.108.

INT4_STATUS

2nd Level Interrupt Status 4 (VSYS)

Command Code:

Bus Protocol:

74h

Read/Write Word

Bit

15

14

13

12

11

10

Symbol

Description

reserved

Interrupt status VSYS Voltage > VSYS_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status VSYS Voltage <= VSYS_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

9

8

VSYS_TH_DET

VSYS_TH_RES

7

6

reserved

Interrupt status of VSYS over voltage detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VSYS over voltage resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VSYS short circuit detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VSYS short circuit resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VSYS under voltage detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of VSYS under voltage resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

5

4

3

2

1

0

VSYS_OV_DET

VSYS_OV_RES

VSYS_SHT_DET

VSYS_SHT_RES

VSYS_UV_DET

VSYS_UV_RES

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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INT5_STATUS

2nd Level Interrupt Status 5 (Charger)

Command Code:

Bus Protocol:

75h

Read/Write Word

Bit

15

14

Symbol

Description

reserved

Interrupt status of OTP load done.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Power-on.

“1”: Event occurred / “0”: No event.

13

12

OTP_LOAD_DONE

PWR_ON

“1-Write”: Status clear.

Interrupt status of IADP voltage range transition.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

11

10

EXTIADP_TRNS

reserved

Interrupt status of IADP (Input current Limit setting pin) voltage >

EXTIADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of IADP (Input current Limit setting pin) voltage <=

EXTIADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

9

8

EXTIADP_TH_DET

EXIADP_TH_RES

Interrupt status of entering to Battery Maintenance charging.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of exit from Battery Maintenance charging.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of the TSD detected.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of the TSD resumed.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Charger Watchdog Timer expired.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Battery Temperature Watchdog Timer expired.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Temperature range transition.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of Charger-State transition.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

7

6

5

4

3

2

1

0

BAT_MNT_DET

BAT_MNT_RES

TSD_DET

TSD_RES

CHGWDT_EXP

THERMWDT_EXP

TMP_TRNS

CHG_TRNS

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.110.

INT6_STATUS

2nd Level Interrupt Status 6 (Charger)

Command Code:

Bus Protocol:

76h

Read/Write Word

Bit

15

14

Symbol

Description

reserved

Interrupt status of USB Port contact detected on the VBUS side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of USB Charger detected on the VBUS side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

13

12

11

VBUS_UCD_PORT_DET

VBUS_UCD_UCHG_DET

VBUS_UCD_URID_RMV

Interrupt status of USB ID contact removed on the VBUS side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of USB OTG device detected on the VBUS side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

10

9

VBUS_UCD_OTG_DET

reserved

Interrupt status of USB ID resistance change on the VBUS side.

“1”: Event occurred / “0”: No event.

8

VBUS_UCD_URID_MOD

“1-Write”: Status clear.

7

6

reserved

Interrupt status of USB Port contact detected on the VCC side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of USB Charger detected on the VCC side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

5

4

3

VCC_UCD_PORT_DET

VCC_UCD_UCHG_DET

VCC_UCD_URID_RMV

Interrupt status of USB ID contact removed on the VCC side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status of USB OTG device detected on the VCC side.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

2

1

0

VCC_UCD_OTG_DET

reserved

Interrupt status of USB ID resistance change on the VCC side.

“1”: Event occurred / “0”: No event.

VCC_UCD_URID_MOD

“1-Write”: Status clear.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.111.

INT7_STATUS

2nd Level Interrupt Status 7 (SAR-ADC)

Command Code:

Bus Protocol:

77h

Read/Write Word

Bit

Symbol

Description

Interrupt status of PROCHOT# asserted.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

15

PROCHOT_DET

Interrupt status of PROCHOT# de-asserted.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

14

PROCHOT_RES

13

12

reserved

Interrupt status of VACP detect.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

11

10

VACP_DET

VACP_RES

Interrupt status of VACP removal.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Input Voltage (ACP) Voltage > VADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Input Voltage (ACP) Voltage <= VADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Input Current (between ACP-ACN) > IADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Input Current (between ACP-ACN) <= IADP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status TSENSE Voltage > THERM_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status TSENSE Voltage <= THERM_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Battery Current (Dis-charge) > IBATM_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Battery Current (Dis-charge) <= IBATM_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

9

8

7

6

5

4

3

2

1

0

VACP_TH_DET

VACP_TH_RES

IACP_TH_DET

IACP_THE_RES

THERM_TH_DET

THERM_TH_RES

IBATM_TH_DET

IBATM_TH_RES

IBATP_TH_DET

IBATP_TH_RES

Interrupt status Battery Current (Charge) > IBATP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

Interrupt status Battery Current (Charge) <= IBATP_TH_SET.

“1”: Event occurred / “0”: No event.

“1-Write”: Status clear.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.112.

REG0

Reserved Register 0 (for future use)

Command Code:

Bus Protocol:

78h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

RESERVE_REG0[15]

RESERVE_REG0[14]

RESERVE_REG0[13]

RESERVE_REG0[12]

RESERVE_REG0 [11]

RESERVE_REG0 [10]

RESERVE_REG0 [9]

RESERVE_REG0 [8]

RESERVE_REG0 [7]

RESERVE_REG0 [6]

RESERVE_REG0 [5]

RESERVE_REG0 [4]

RESERVE_REG0 [3]

RESERVE_REG0 [2]

RESERVE_REG0 [1]

RESERVE_REG0 [0]

Description

Reserved Register 0 (for future use)

4

3

2

1

0

8.5.113.

REG1

Reserved Register 1 (for future use)

Command Code:

Bus Protocol:

79h

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

RESERVE_REG1[15]

RESERVE_REG1[14]

RESERVE_REG1[13]

RESERVE_REG1[12]

RESERVE_REG1[11]

RESERVE_REG1[10]

RESERVE_REG1[9]

RESERVE_REG1[8]

RESERVE_REG1[7]

RESERVE_REG1[6]

RESERVE_REG1[5]

RESERVE_REG1[4]

RESERVE_REG1[3]

RESERVE_REG1[2]

RESERVE_REG1[1]

RESERVE_REG1[0]

Description

Reserved Register 1 (for future use)

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.114.

OTPREG0

Input current limit degradation setting. For ditails, please see 8.5.6. CUR_ILIM_VAL.

Command Code:

Bus Protocol:

Bit

7Ah

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

RESERVE_OTPREG0[15]

RESERVE_OTPREG0[14]

RESERVE_OTPREG0[13]

RESERVE_OTPREG0[12]

ILIM_DECREASE[11]

ILIM_DECREASE[10]

ILIM_DECREASE[9]

ILIM_DECREASE[8]

ILIM_DECREASE[7]

ILIM_DECREASE[6]

ILIM_DECREASE[5]

ILIM_DECREASE[4]

ILIM_DECREASE[3]

ILIM_DECREASE[2]

ILIM_DECREASE[1]

ILIM_DECREASE[0]

Reserved OTP-loaded Register 0 (for future use)

Input current limit degradation setting when anti-collapse occurs.

4

3

2

1

0

8.5.115.

OTPREG1

Reserved OTP-loaded Register 1 (for future use)

Command Code:

Bus Protocol:

Bit

7Bh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

RESERVE_OTPREG1[15]

RESERVE_OTPREG1[14]

RESERVE_OTPREG1[13]

RESERVE_OTPREG1[12]

RESERVE_OTPREG1[11]

RESERVE_OTPREG1[10]

RESERVE_OTPREG1[9]

RESERVE_OTPREG1[8]

RESERVE_OTPREG1[7]

RESERVE_OTPREG1[6]

RESERVE_OTPREG1[5]

RESERVE_OTPREG1[4]

RESERVE_OTPREG1[3]

RESERVE_OTPREG1[2]

RESERVE_OTPREG1[1]

RESERVE_OTPREG1[0]

Reserved OTP-loaded Register 1 (for future use)

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.116.

SMBREG

Power Save Mode Setting.

Command Code:

Bus Protocol:

7Ch

Read/Write Word

Bit

15

14

13

12

11

10

9

8

7

6

5

Symbol

SMBREG[15]

Description

Reserved SMBus Clock Domain Register (for future use)

SMBREG[14]

SMBREG[13]

SMBREG[12]

SMBREG[11]

SMBREG[10]

SMBREG[9]

SMBREG[8]

SMBREG[7]

SMBREG[6]

SMBREG[5]

SMBREG[4]

SMBREG[3]

4

3

Power Save Mode Setting.

0h: Normal Operation

1h: BGATE ON with PROCHOT# Monitored only System voltage/

2

POWER_SAVE_MODE[2]

2h: BGATE ON with PROCHOT# Monitored only System voltage (1ms)/

5h: BGATE ON without PROCHOT#//

6h: BGATE OFF/

Other: reserved.

1

0

POWER_SAVE_MODE[1]

POWER_SAVE_MODE[0]

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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BD99954 enters into 4 power modes by SMBus writing RESERVE_SMBREG0SMBREG.POWER_SAVE_MODE[2:0] register.

And BD99954 exits from a power mode by SMBus clearing RESERVE_SMBREG0SMBREG.POWER_SAVE_MODE[2:0]

register.

If BD99954 is in a power mode, BD99954 exits from power mode automatically by VBUS/VCC plugged-in and goes back to

power mode automatically by VBUS/VCC plugged-off.

POWER_SAVE_MODE[2:0]=1h: (BGATE ON with PROCHOT# Monitored only System voltage) sample operation flow.

BD99954

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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POWER_SAVE_MODE[2:0] =2h: BGATE ON with PROCHOT# Monitored only System voltage (1ms interval) sample operation

flow.

BD99954

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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POWER_SAVE_MODE[2:0]=5h: BGATE ON without PROCHOT# sample operation flow.

BD99954

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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POWER_SAVE_MODE[2:0]=6h: BGATE OFF sample operation flow.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.5.117.

DEBUG_MODE_SET

Debug Mode Setting

Command Code:

Bus Protocol:

Bit

7Fh

Read/Write Word

Symbol

Description

15

14

13

12

11

10

9

8

7

6

5

DEBUG_MODE_SET[15]

DEBUG_MODE_SET[14]

DEBUG_MODE_SET[13]

DEBUG_MODE_SET[12]

DEBUG_MODE_SET[11]

DEBUG_MODE_SET[10]

DEBUG_MODE_SET[9]

DEBUG_MODE_SET[8]

DEBUG_MODE_SET[7]

DEBUG_MODE_SET[6]

DEBUG_MODE_SET[5]

DEBUG_MODE_SET[4]

DEBUG_MODE_SET[3]

DEBUG_MODE_SET[2]

DEBUG_MODE_SET[1]

DEBUG_MODE_SET[0]

Debug Mode Setting

4

3

2

1

0

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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8.6. Resister Default Value

Register

Read/

Bit

OTP/POR

Value(HEX) Value(DEC) [V,mA,min]

OTP/POR

Unit

Address Name

OTP

Write

Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

15 14 13 12 11 10

9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

7

0

1

0

1

0

1

0

1

0

1

0

1

0

6

0

1

0

1

0

1

0

1

0

1

0

1

0

5

0

1

0

1

0

1

0

1

0

4

0

1

0

1

0

1

0

1

0

3

0

1

0

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

CHGSTM_STATUS

VBAT/VSYS_STATUS

VBUS/VCC_STATUS

CHGOP_STATUS

WDT_STATUS

R

No

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0000

05C0

05E0

00E0

6C68

002E

0000

3010

0630

2300

1580

1340

0100

0A00

0000

0800

13C0

20D0

1FB0

22D0

4000

4519

2710

1388

4000

1340

00AC

0000

00D0

0000

-

HEX

mA

HEX

V

-

CUR_ILIM_VAL

SEL_ILIM_VAL

-

1472

1504

-

IBUS_LIM_SET

ICC_LIM_SET

R/W Yes

IOTG_LIM_SET

VIN_CTRL_SET

CHGOP_SET1

-

CHGOP_SET2

-

VBUSCLPS_TH_SET

VCCCLPS_TH_SET

CHGWDT_SET

BATTWDT_SET

VSYSREG_SET

VSYSVAL_THH_SET

VSYSVAL_THL_SET

ITRICH_SET

0

V

192,16

24,48

8.96

5.504

4.928

256

2560

0

min

V

mA

V

IPRECH_SET

ICHG_SET

ITERM_SET

VPRECHG_TH_SET

VRBOOST_SET

2.048

5.056

8.4

8.112

8.912

16384

-

V

VFASTCHG_REG_SET1 R/W Yes

VFASTCHG_REG_SET2 R/W Yes

VFASTCHG_REG_SET3 R/W Yes

V

VRECHG_SET

VBATOVP_SET

R/W Yes

V

IBATSHORT_SET

mA

HEX

mA

V

PROCHOT_CTRL_SET

PROCHOT_ICRIT_SET

10000

5000

16384

4.928

-

PROCHOT_INORM_SET R/W Yes

PROCHOT_IDCHG_SET R/W Yes

PROCHOT_VSYS_SET

R/W Yes

PMON_IOUT_CTRL_SET R/W Yes

HEX

PMON_DACIN_VAL

IOUT_DACIN_VAL

R

No

-

VCC_UCD_SET

R/W Yes

-

VCC_UCD_STATUS

VCC_IDD_STATUS

VCC_UCD_FCTRL_SET

VCC_UCD_FCTRL_EN

R

No

-

R

-

R/W

-

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Register

Read/

Bit

OTP/POR

Value(HEX) Value(DEC) [V,mA,min]

OTP/POR

Unit

Address Name

OTP

Write

Address

30h

15 14 13 12 11 10

9

0

1

0

1

8

7

1

0

6

1

0

1

0

5

0

4

1

0

3

0

1

0

2

0

1

0

1

0

1

0

1

0

VBUS_UCD_SET

VBUS_UCD_STATUS

VBUS_IDD_STATUS

R/W Yes

0

1

0

00D0

0000

0346

0009

0200

0000

13FF

-

HEX

31h

R

No

32h

33h

VBUS_UCD_FCTRL_SET R/W

No

34h

VBUS_UCD_FCTRL_EN

CHIP_ID

R/W

R

No

38h

Yes

39h

CHIP_REV

R

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

IC_SET1

R/W Yes

Yes

IC_SET2

SYSTEM_STATUS

SYSTEM_CTRL_SET

PROTECT_SET

MAP_SET

R

No

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

VM_CTRL_SET

THERM_WINDOW_SET1

R/W Yes

41h

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C3C6

BBBE

9B9E

8E91

5,2

℃

42h

43h

THERM_WINDOW_SET2

THERM_WINDOW_SET3

13,10

45,42

58,55

44h

45h

46h

47h

48h

49h

THERM_WINDOW_SET4

THERM_WINDOW_SET5

IBATP_TH_SET

R/W Yes

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

9699

1656

4000

1800

0032

1388

0ED8

0000

0777

0000

50,47

℃

mA

V

5718

IBATM_TH_SET

16384

VBAT_TH_SET

6.144

THERM_TH_SET

150

℃

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

IACP_TH_SET

VACP_TH_SET

VBUS_TH_SET

VCC_TH_SET

VSYS_TH_SET

EXTIADP_TH_SET

IBATP_VAL

5000

mA

V

3.8

V

3.8

V

0

V

1.911

V

R

No

-

HEX

IBATP_AVE_VAL

IBATM_VAL

R

IBATM_AVE_VAL

VBAT_VAL

R

VBAT_AVE_VAL

THERM_VAL

VTH_VAL

R

R/W

R

IACP_VAL

R

IACP_AVE_VAL

VACP_VAL

R

VACP_AVE_VAL

VBUS_VAL

R

VBUS_AVE_VAL

VCC_VAL

R

VCC_AVE_VAL

VSYS_VAL

R

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Register

Read/

Bit

OTP/POR

Value(HEX) Value(DEC) [V,mA,min]

OTP/POR

Unit

Address Name

OTP

Write

Address

61h

62h

63h

64h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

15 14 13 12 11 10

9

0

8

7

0

1

0

6

0

1

0

5

0

1

0

4

0

1

0

3

0

1

0

2

0

1

0

1

0

1

0

1

0

VSYS_AVE_VAL

EXTIADP_VAL

EXTIADP_AVE_VAL

VACPCLPS_TH_SET

INT0_SET

R

No

0

0000

00FF

0000

-

0

-

0

-

HEX

V

R/W Yes

HEX

mA

INT1_SET

INT2_SET

INT3_SET

INT4_SET

INT5_SET

INT6_SET

INT7_SET

INT0_STATUS

INT1_STATUS

INT2_STATUS

INT3_STATUS

INT4_STATUS

INT5_STATUS

INT6_STATUS

INT7_STATUS

RESERVE_REG0

RESERVE_REG1

OTPREG0

R/W

No

R/W Yes

OTPREG1

R/W

R

No

HEX

RESERVE_SMBREG0

(reserved)

R

DEBUG_MODE_SET

R/W

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

9. I/O Equivalent circuit diagram

VCC_ID, VBUS_ID

IADP/RESET

REGN

○

93Ω

○

1.26M 200k

4K

30k

10k

IADP/RESET

VCC_ID

VBUS_ID

○

10k

○

10k

30k

○

VCC_DPI, VCC_DMI, VBUS_DPI, VBUS_DMI

VCC_DPO, VCC_DMO, VBUS_DPO, VBUS_DMO

VCC_DPO

VCC_DMO

VBUS_DPO

VBUS_DMO

10k

VCC_DPI

VCC_DMI

VBUS_DPI

VBUS_DMI

10k

10.64k

SCL

SDA

VREF

250k

15k

SDA

SCL

(Next Page)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

VREF

TSENSE

REGN

○

10k

VREF

TSENSE

423k

704k

○

IOUT

PMON

REGN

100Ω

IOUT

100Ω

PMON

100Ω

REGN

ACP

REGN

1.33M

600k

100k

70k

1450k

(Next Page)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

ACN, SRP, SRN

INT#, PROCHOT#, ACOK

ACN

SRP

SRN

INT#

PROCHOT#

ACOK

20Ω

BGATE, BATT

ACGATE1, ACGATE2, VBUS, VCC

9.2k

ACGATE1

ACGATE2

BGATE

BATT

VBUS

VCC

LG1, LG2

BOOT1, BOOT2, HG1, HG2, LX1, LX2

REGN

BOOT1,2

LG1,2

GND

HG1,2

143k

1M

LX1,2

GND

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

10. Ordering Information

B D 9

9

5

4

M W V

-

E 2

Part Number

Package

Packaging and forming specification

MWV: UQFN040V5050 E2: Embossed tape and reel

GW : UCSP55M3C

11. Marking Diagrams

UQFN040V5050 (TOP VIEW)

Part Number Marking

B D 9 9 9 5

4 A

LOT Number

1PIN MARK

USCP55M3 (TOP VIEW)

1PIN MARK

Part Number Marking

LOT Number

954

A

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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12. Physical Dimension Tape and Reel Information

Package Name

UQFN040V5050

Package Name

UCSP55M3C

Figure 12-1 Package Dimensions in QFN

Figure 12-2 Package Dimensions in WL-CSP

Figure 12-3 Tape and Reel Information in QFN

Figure 12-4 Tape and Reel Information in WL-CSP

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

(BLANK PAGE)

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

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13. Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

OR

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground

due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below

ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions

such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Thermal Consideration

Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in

deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size

and copper area to prevent exceeding the Pd rating.

6. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.

The electrical characteristics are guaranteed under the conditions of each parameter.

7. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

8. Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

9. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

11. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Operational Notes – continued

12. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure xx. Example of monolithic IC structure

13. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

14. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe

Operation (ASO).

15. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction

temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below

the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat

damage.

16. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

17. Disturbance light (only BD99954GW)

In a device where a portion of silicon is exposed to light such as in a WL-CSP, IC characteristics may be affected due

to photoelectric effect. For this reason, it is recommended to come up with countermeasures that will prevent the chip

from being exposed to light.

18. Thermal Pad (only BD99954MWV)

Thermal pad connect GND terminal or open.

19. Power Path Sequece

This product is capable of turning both VCC and VBUS power paths ON simultaneously.

Please immediately turn the simultaneous power path ON if one of the VCC or VBUS port has been disconnected and

simultaneous ON is not needed.

If the simultaneous power path is not turned off immediately, and a new device is connected to the disconnected port,

there is a possibility that this device gets damaged.

In that case, ROHM cannot assume responsibility for the damage.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Operational Notes – continued

20. VBUS overshoot

There is possibility of voltage overshoot on VCC or VBUS inputs depending on settings and conditions for the following

parameters: input voltage (VBUS and VCC), input voltage for IADP (set by external voltage divider), total system

capacitance and respective ESR.

Please refer carefully to this datasheet and the separate application notes when making selection of those parameters

and register settings to properly match your design.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Datasheet

BD99954MWV, BD99954GW

Revision History

Revision Number

001

Description

Revision Date

12. Jul. 2017

Initial release.

* Product structure: Silicon monolithic integrated circuit. ** This product is not designed to protect against radioactive rays.

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.003


型号：	BD99954MWV
厂家：	ROHM
描述：	BD99954MWV is a Battery Management LSI for 1-4 cell Lithium-Ion secondary battery, and available in a 40pin 0.40 mm pitch 5.0 mm x 5.0 mm QFN package and small 41-ball 0.4mm pitch 2.6mm x 3.0mm Wafer-Level CSP package which is designed to meet high degree demands for space-constraint equipment such as Low profile Notebook PC, Tablets and other applications. It provides a Dual-source Battery Charger, two port BC1.2 detection and a Battery Monitor with several alarm(INT#, PROCHOT#) outputs.Read more about Battery Charge ICs... 电池 PC
文件：	总130页 (文件大小：3157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD99954MWV [ROHM]

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