BH6172GU-E2 [ROHM]
High-efficiency Power Management IC; 高效率的电源管理IC
| 型号： | BH6172GU-E2 |
| 厂家： | 
ROHM |
| 描述： | High-efficiency Power Management IC |
| 文件： | 总17页 (文件大小：917K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
Power Management IC Series for Mobile Phones
High-efficiency
Power Management IC
BH6172GU
●
Descriptions
BH6172GU incorporates 1 DCDC+ 5 Linear LDO regulators.
It is integrated in a small 2.6mm×2.6mm size package, with 16 steps adjustable Vo’s for every channel,
low voltage output (0.8V~) to support almost any kind of mobile application now available.
●
Features
1) 1ch 500mA, high efficiency Step-down Converter. (16 steps adjustable VO by I2C)
2) 5-channel CMOS-type LDOs. (16 steps adjustable VO by I2C, 150mA×3, 300mA×2)
3) Power ON/OFF control enabled by I2C interface or external pin
4) I2C compatible Interface. (Device address is “1001111”)
5) Wafer Level CSP package(2.6mm×2.6mm) for space-constrained applications
6) Discharge resistance selectable for power-down sequence ramp speed control
7) Over-current protection in all LDO regulators
8) Over-current protection in Step-down Converter
9) Over-voltage protection in Step-down Converter
10) Thermal shutdown protection
●
●
Applications
Mobile phones, Portable game systems, Portable mp3 players, Portable DVD players, Portable TV, Portable GPS,
PDA, Portable electronic dictionaries, etc.
Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Rating
Unit
Maximum Supply Voltage (VBAT)
Maximum Supply Voltage (PBAT)
Maximum Supply Voltage (VUSB)
VBATMAX
VPBATMAX
VUSBMAX
DVDDMAX
6.0
6.0
6.0
4.5
V
V
V
V
Maximum Supply Voltage (DVDD)
Maximum Input Voltage 1
(LX, FB, OUT1, OUT2, OUT3, OUT4,
OUT5, EN_LD1, EN_LD2, EN_LD3,
EN_LD4)
VINMAX1
VBAT + 0.3
V
Maximum Input Voltage 2
(NRST, CLK, DATA)
VINMAX2
DVDD + 0.3
V
Power Dissipation
Pd
900*1
mW
℃
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-35 ～ +85
-55 ～ +125
℃
* This is an allowable loss of the ROHM evaluation glass epoxy board(60mm×60mm×16mm).
To use at temperature higher than 25C , derate 9.0mW per 1C.
** Must not exceed Pd or ASO.
Sep. 2008
●
Recommended Operating Conditions (Ta=25C)
Parameter
Symbol
Range
Unit
2
2
VBAT Voltage
PBAT Voltage
VUSB Voltage
DVDD Voltage
VBAT
VPBAT
VUSB
*
2.20 ～ 5.50
2.20 ～ 5.50
V
V
V
V
*
*2*3 2.20 ～ 5.50
4
VDVDD
*
1.70 ～ 4.20
*2 Whenever the VBAT or PBAT or VUSB voltage is under the LDO, SWREG output voltage,
or else under certain levels, the LDO and SWREG output is not guaranteed to meet its published specifications.
*3 VUSB Power Supply can be externally connected to the VBAT, PBAT Power Supply when necessary.
*4 The DVDD Voltage must be under the Battery Voltage VBAT, PBAT at any times.
●
Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PBAT =3.6V, VUSB=5.0V)
Parameter
Circuit Current
Symbol
Min.
Typ.
Max.
Unit
Condition
VBAT
Circuit Current 1
(OFF)
VUSB
Circuit Current 1
(OFF)
IQVB1
-
-
0.4
0
1
1
μA
μA
LDO1～5=OFF
SWREG1=OFF
NRST=L
IQUSB1
DVDD=0V
LDO1～5=OFF
SWREG1=OFF
VBAT
Circuit Current 2
(OFF)
IQVB2
-
0.4
1
μA
NRST=L
DVDD=0V
VUSB=VBAT external connection
VBAT
Circuit Current 3
(STANDBY)
VUSB
Circuit Current 2
(STANDBY)
IQVB3
-
-
0.7
0
1.4
1
μA
μA
LDO1～5=OFF
SWREG1=OFF
NRST=H
IQUSB2
DVDD=2.6V
LDO1～5=OFF
SWREG1=OFF
NRST=H
DVDD=2.6V
VBAT
Circuit Current 4
(STANDBY)
IQVB4
-
0.7
1.4
μA
VUSB=VBAT external connection
VBAT
Circuit Current 5
(Active)
VUSB
Circuit Current 3
(Active)
IQVB5
-
-
170
35
300
70
μA
μA
LDO1～5=ON(no load, initial voltage)
SWREG1=ON(no load, initial voltage)
NRST=H
IQUSB3
DVDD=2.6V
LDO1～5=ON(no load, initial voltage)
SWREG1=ON(no load, initial voltage)
NRST=H
VBAT
Circuit Current 6
(Active)
IQVB6
-
200
350
μA
DVDD=2.6V
VUSB=VBAT external connection
◎This product is not especially designed to be protected from radioactivity.
2/16
●
Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PBAT =3.6V, VUSB=5.0V, DVDD=2.6V)
Logic pin character
0.7×
DVDD
DVDD+
0.3
0.3×
Input “H” level
Input “L” level
VIH1
VIL1
IIC1
-
-
V
V
Pin voltage: DVDD
Pin voltage: 0 V
NRST
(CMOS input)
-0.3
0
DVDD
Input leak
current
0.3
1
μA
EN_LD1,
EN_LD2,
EN_LD3,
Input “H” level
Input “L” level
VIH2
VIL2
1.44
-
-
-
-
V
V
0.4
EN_LD4
(NMOS input)
Input leak
current
IIC2
-1
0
1
μA
Digital characteristics (Digital pins: CLK and DATA )
DVDD
+
0.3
0.2×
DVDD
0.8×
DVDD
Input "H" level
VIH3
VIL3
-
-
V
V
Input "L" level
Input leak
-0.3
IIC3
VOL
-1
-
0
-
1
μA
Pin voltage: DVDD
IOL=6mA
current
DATA output "L" level voltage
0.4
V
●
Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PBAT =3.6V, VUSB=5.0V)
Parameter
SWREG
Symbol
Min.
Typ.
Max.
Unit
Condition
initial value
Output Voltage
VOSW
0.94
1.00
1.06
V
Io=100mA
Vo=1.00V
Output current
Efficiency
IOSW
ηSW
fOSC
-
-
-
-
500
mA
%
90
1.7
-
-
Io=100mA, Vo=2.40V, VBAT=3.2V
Vo=1.00V
Oscillating Frequency
MHz
Output Inductance
Short circuit current
LSWREG
ISHTSW
1.5
-
2.2
-
-
μH
Ta= -30～75C
Ta= -30～75C
500
mA
Ta= -30～75C
with SWREG's DC bias
Output Capacitance
CSWREG
3.3
4.7
-
μF
3/16
●
Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PBAT =3.6V, VUSB=5.0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
LDO1
initial value
Output Voltage
VOM1
0.970
1.000
1.030
V
Io=1mA@VBAT=4.5V
Io=150mA@VBAT=3.4V
Output current
VOM1C
-
-
-
150
-
mA
V
Vo=1.0V
Io=50mA
Dropout Voltage
VOM1DP
0.1
VBAT=3.4～4.5V, Io=50mA
Vo=1.0V
Io=50μA～150mA, VBAT=3.6V
Input Voltage Stability
Load Stability
⊿VIM1
⊿VLM1
-
-
2
-
-
mV
mV
20
Vo=1.0V
VR=-20dBV
fR=120Hz
Io=50mA, Vo=2.6V
Ripple rejection ratio
RRM1
-
60
-
dB
BW=20Hz～20kHz
Short circuit current
Output Capacitor
ISHTM3
COUT1
-
-
180
1.0
-
-
mA
Vo=0V
Ta= -30～75C
with LDO's DC bias
μF
LDO2
initial value
Output Voltage
VOM2
2.522
2.600
2.678
V
Io=1mA@VBAT=4.5V
Io=150mA@VBAT=3.4V
Output current
VOM2C
-
-
-
150
-
mA
V
Vo=2.6V
Io=50mA
Dropout Voltage
VOM2DP
0.1
VBAT=3.4～4.5V, Io=50mA
Vo=2.6V
Io=50μA～150mA, VBAT=3.6V
Input Voltage Stability
Load Stability
⊿VIM2
⊿VLM2
-
-
2
-
-
mV
mV
20
Vo=2.6V
VR=-20dBV
fR=120Hz
Io=50mA, Vo=2.6V
Ripple rejection ratio
RRM2
-
60
-
dB
BW=20Hz～20kHz
Short circuit current
Output Capacitor
ISHTM3
COUT2
-
-
180
1.0
-
-
mA
Vo=0V
Ta= -30～75C
with LDO's DC bias
μF
LDO3
initial value
Output Voltage
VOM3
2.716
2.800
2.884
V
Io=1mA@VBAT=4.5V
Io=150mA@VBAT=3.4V
Output current
VOM3C
-
-
-
300
-
mA
V
Vo=2.8V
Io=50mA
Dropout Voltage
VOM3DP
0.1
VBAT=3.4～4.5V, Io=50mA
Vo=2.8V
Io=50μA～300mA, VBAT=3.6V
Input Voltage Stability
Load Stability
⊿VIM3
⊿VLM3
-
-
2
-
-
mV
mV
20
Vo=2.8V
VR=-20dBV
fR=120Hz
Io=50mA, Vo=2.6V
Ripple rejection ratio
RRM3
-
60
-
dB
BW=20Hz～20kHz
Short circuit current
Output Capacitor
ISHTM3
COUT3
-
-
180
1.0
-
-
mA
Vo=0V
Ta= -30～75C
with LDO's DC bias
μF
4/16
●
Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PBAT =3.6V, VUSB=5.0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
LDO4
initial value
Output Voltage
VOM4
1.746
1.800
1.854
V
Io=1mA@VBAT=4.5V
Io=300mA@VBAT=3.4V
Output current
VOM4C
-
-
-
300
-
mA
V
Vo=1.8V
Io=50mA
Dropout Voltage
VOM4DP
0.1
VBAT=3.4～4.5V, Io=50mA
Vo=1.8V
Io=50μA～300mA, VBAT=3.6V
Input Voltage Stability
Load Stability
⊿VIM4
⊿VLM4
-
-
2
-
-
mV
mV
30
Vo=1.8V
VR=-20dBV
fR=120Hz
Io=50mA, Vo=2.6V
Ripple rejection ratio
RRM4
-
60
-
dB
BW=20Hz～20kHz
Short circuit current
Output Capacitor
ISHTM4
COUT4
-
-
340
1.0
-
-
mA
Vo=0V
Ta= -30～75C
with LDO's DC bias
μF
LDO5
initial value
Output Voltage
VOM5
3.201
3.300
3.399
V
Io=1mA@VUSB=5.5V
Io=150mA@VUSB=4.4V
Output current
VOM5C
-
-
-
150
-
mA
V
Vo=3.3V
Io=50mA
Dropout Voltage
VOM5DP
0.1
VUSB=4.4～5.5V, Io=50mA
Vo=3.3V
Io=50μA～150mA, VUSB=5.5V
Input Voltage Stability
Load Stability
⊿VIM5
⊿VLM5
-
-
2
-
-
mV
mV
20
Vo=3.3V
VR=-20dBV
fR=120Hz
Io=50mA, Vo=2.6V
Ripple rejection ratio
RRM5
-
60
-
dB
BW=20Hz～20kHz
Short circuit current
Output Capacitor
ISHTM5
COUT5
-
-
180
1.0
-
-
mA
Vo=0V
Ta= -30～75C
with LDO's DC bias
μF
5/16
●
SWREG & LDOs Output Voltage table
Usage
Power Supply Initial Output Voltage
Load max
Adjustable range
example
SWREG
CORE
CORE
I/O1
VBAT/PBAT
VBAT
1.00V
1.00V
2.60V
2.80V
1.80V
3.30V
500mA
150mA
150mA
300mA
300mA
150mA
0.80-2.40V
1.00-3.30V
1.00-3.30V
1.20-3.30V
1.20-3.30V
1.20-3.30V
LDO1
LDO2
LDO3
LDO4
LDO5
VBAT
MEMORY
I/O2
VBAT
VBAT
USB
VBAT/VUSB
SWREG
0.80V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.365V
1.40V
1.50V
1.65V
1.80V
1.85V
2.40V
LDO1
LDO2
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.85V
2.60V
2.70V
2.80V
2.85V
3.00V
3.30V
LDO3
LDO4
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.85V
1.90V
2.00V
2.60V
2.70V
2.80V
2.85V
3.00V
3.30V
LDO5
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.85V
1.90V
2.00V
2.60V
2.70V
2.80V
2.85V
3.00V
3.30V
1.00V
1.10V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.85V
2.60V
2.70V
2.80V
2.85V
3.00V
3.30V
1.20V
1.30V
1.40V
1.50V
1.60V
1.70V
1.80V
1.85V
1.90V
2.00V
2.60V
2.70V
2.80V
2.85V
3.00V
3.30V
Programmable
Output Voltages
6/16
●
Block diagram, Ball matrix
4.7uF
init 1.00V
150mA
OUT1
LDO1
1.00-3.30V
0.1V step
DVDD
DATA
1uF
1uF
1uF
1uF
EN_LD1
I2C IF
VBAT1
OUT2
GND
TEST2
EN_LD2
EN_LD1
VBAT2
NRST
CLK
OUT4
EN_LD3
EN_LD4
OUT3
OUT1
DVDD
FB
CLK
E
D
C
B
A
init 2.60V
150mA
OUT2
LDO2
1.00-3.30V
0.1V step
NRST
EN_LD2
PBAT
init 2.80V
300mA
OUT3
LDO3
1.20-3.30V
0.1V step
4.7uF
LX
2.2uH
SWREG
0.8-2.40V
4.7uF
EN_LD3
PGND
FB
500mA
init 1.00V
init 1.80V
300mA
OUT4
LDO4
1.20-3.30V
0.1V step
REFC
TEST
DATA
EN_LD4
(OPEN) TEST
(OPEN) TEST2
VUSB
OUT5
VUSB
PGND
LX
PBAT
1uF
1uF
REFC
init 3.30V
150mA
REF
OUT5
LDO5
1.20-3.30V
0.1V step
0.1uF
1
2
3
4
5
Fig.1 Block diagram
Fig.2 Ball matrix
●
Pin description
Ball No.
B4
C4
E1
E4
A5
A4
A3
B5
D4
D5
D1
E5
E3
A1
B1
C2
D2
D3
C3
A2
C5
C1
B3
E2
PIN Name
DATA
CLK
VBAT1
VBAT2
PBAT
LX
Function
Data input/output for I2C
CLK input for I2C
Power Supply 1
Power Supply 2
Power Supply for SWREG
Inductor Connect pin for SWREG
Ground for SWREG
Voltage Feed back pin for SWREG
RESET Input Pin (Low Active)
LDO1 Output
PGND
FB
NRST
OUT1
OUT2
OUT3
OUT4
OUT5
REFC
LDO2 Output
LDO3 Output
LDO4 Output
LDO5 Output
Reference Voltage Output
EN_LD1 LDO1 Enable Pin
EN_LD2 LDO2 Enable Pin
EN_LD3 LDO3 Enable Pin
EN_LD4 LDO4 Enable Pin
VUSB
DVDD
GND
*1 USBVBUS Power Supply
Digital Power Supply
Analog Ground
TEST
TEST2
TEST PIN (Always keep OPEN at normal use)
TEST PIN (Always keep OPEN at normal use)
*TEST, TEST2 pin is used during our company shipment test.
Please keep TEST pin and TEST2 pin “OPEN” at all times.
*1 VUSB Power Supply can be externally connected to the VBAT Power Supply when necessary.
7/16
●
I2C Bus INTERFACE
The I2C compatible synchronous serial interface provides access to programmable functions and register on the device.
This protocol uses a two-wire interface for bi-directional communications between the LSI’s connected to the bus.
The two interface lines are the Serial Data Line(DATA), and the Serial Clock Line(CLK). These lines should be connected to
the power supply DVDD by a pull-up resistor, and remain high even when the bus is idle.
1.Start and Stop Conditions
When CLK is high, pulling DATA low produces a start condition and pulling DATA high produces a stop condition.
Every instruction is started when a start condition occurs and terminated when a stop condition occurs.
During read, a stop condition causes the read to terminate and the chip enters the standby state.
During write, a stop condition causes the fetching of write data to terminate, after which writing starts automatically.
Upon the completion of writing, the chip enters the standby state. Two or more start conditions cannot be entered
consecutively.
tSU.STA tHD.STA
tSU.STO
CLK
DATA
Start
condition
Stop condition
Fig.3 I2C Start, Stop condition
2.Data transmission
Data on the DATA input can be modified while CLK is low. When CLK is high, modifying the DATA input means a start or
stop condition.
tSU.DAT
tHD.DAT
CLK
DATA
Modify data
Modify data
Fig.4 I2C Data Transmission Timing
All other acknowledge, write, and read timings all conform to the I2C standard.
3.Device addressing
The device address for this device is “1001111”.
Read/write instruction
Device address
code
1
0
0
1
1
1
1
R/W
MSB
LSB
Fig.5 I2C device address
8/16
●
I2C Bus AC specification
Characteristics
CLK clock frequency
CLK clock “low” time
CLK clock “high” time
Bus free time
Start condition hold time
Start condition setup time
Symbol
fCLK
tLOW
tHIGH
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tSU.STO
Min
0
Max
400
Unit
kHz
μs
μs
μs
μs
μs
ns
1.3
0.6
1.3
0.6
0.6
0
-
-
-
-
-
-
-
-
Data input hold time
Data input setup time
Stop condition setup time
100
0.6
ns
μs
tF
tHIGH
tLOW
tR
CLK
tSU.STO
tSU.STA
tHD.DAT tSU.DAT
tHD.STA
DATA
(INPUT)
tBUF
Fig.6 Bus timing 1
CLK
DATA
(INPUT)
DO
tWR
Write data
input
Acknowledge
output
Start
condition
Stop
condition
Fig.7 Bus timing 2
9/16
●
I2C Register information
○REGCNT(SWREGON, LDO*ON)
Control each SWREG, LDO.
0
1
ON
OFF
○SWADJ(SWREGADJ[3:0])
Change SWREG output voltage by 16 steps.
“0000”
～
0.80V
～
“1111”
2.40V
○LDOADJ*(LDO*ADJ[3:0])
Change LDO1～5 output voltage by 16 steps.
“0000”
～
1.00V(LDO1, 2), 1.20V(LDO3, 4, 5)
～
“1111”
3.30V
○PDSEL(SWPDSEL, LDO*PDSEL)
Change the discharge resistance of SWREG, LDO.
0
1
1kΩ
10kΩ
○PDCNT(SWPD, LDO*PD)
Enable/disable the discharge resistance of SWREG, LDO.
0
1
Discharge disable
Discharge enable
○EN_SEL(ENLD*_EN)
Select either an enable pin or I2C register for LDO1～4 ON/OFF control.
0
1
External enable pin selected
I2C register selected
10/16
●
Reference data(ICC)
ICC(OFF) VUSB=5.0V
ICC(OFF) VBAT=VUSB short
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VBAT [V]
VBAT [V]
ICC(ACTIVE) VBAT=VUSB short
ICC(STBY) VBAT=VUSB short
1
10
9
8
7
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
3.2
3.7
4.2
4.7
5.2
5.7
VBAT [V]
VBAT [V]
●
Reference data(SWREG)
SWREG Load Regulation VO=1.0V
SWREG Line Regulation VO=1.0V
2
1.9
6
5.5
5
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VBAT
4.5
4
3.5
3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
50
100
150
200
250
IO [mA]
300
350
400
450
500
VBAT [V]
SWREG Efficiency vs Io (Vo=1.365V)
VBAT=3.6V
100
90
80
70
60
50
40
30
20
10
0
0
50
100
150
200
250
300
350
400
450
500
IO[mA]
11/16
●
Reference data(Output stability)
4
3.5
3
4
4
3.5
3
LDO3 Load Regulation 3.0V
LDO2 Load Regulation 2.60V
LDO1 Load Regulation 1.20V
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0.5
0
0.5
0
0.5
0
0
50
100
150
200
0
50
100
150
200
250
300
0
50
100
150
200
IO [mA]
IO [mA]
IO [mA]
4
3.5
3
4
LDO4 Load Regulation 1.80V
LDO5 Load Regulation 3.30V
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
100
200
300
400
0
50
100
150
200
IO [mA]
IO [mA]
●
Reference data(Input stability)
6
6
6
LDO1 Line Regulation 1.20V
5.5
LDO2 Line Regulation 2.60V
LDO3 Line Regulation 3.0V
5.5
5
5.5
5
5
4.5
4
VBAT
VBAT
VBAT
4.5
4
4.5
4
3.5
3
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0.5
0
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VBAT [V]
VBAT [V]
VBAT [V]
6
5.5
5
6
5.5
5
LDO4 Line Regulation 1.80V
LDO5 Line Regulation 3.30V
VBAT
4.5
4
4.5
4
VUSB
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VBAT [V]
VUSB [V]
12/16
●
Reference data(Load transient response)
LDO1
LDO2
IO
IO
IO
IO
LDO2
LDO1
LDO1
LDO2
LDO3
LDO4
IO
IO
IO
IO
LDO3
LDO3
LDO4
LDO4
LDO5
IO
IO
LDO5
LDO5
●
Reference data(Rise time)
LDO1
LDO2
EN_LD1
LDO1
EN_LD2
LDO2
LDO3
LDO4
EN_LD3
EN_LD4
LDO3
LDO4
13/16
●
Reference data(VBAT line transient response)
LDO1
LDO2
LDO3
VBAT
VBAT
VBAT
LDO1
LDO3
LDO2
LDO4
LDO5
VBAT
VUSB
LDO5
LDO4
14/16
●
Use-related Cautions
(1) Absolute maximum ratings
If applied voltage (VBAT, VADP, VUSB), operating temperature range (Topr), or other absolute maximum ratings are
exceeded, there is a risk of damage. Since it is not possible to identify short, open, or other damage modes, if special modes
in which absolute maximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures.
(2) Recommended operating range
This is the range within which it is possible to obtain roughly the expected characteristics. For electrical characteristics, it is
those that are guaranteed under the conditions for each parameter. Even when these are within the recommended operating
range, voltage and temperature characteristics are indicated.
(3) Reverse connection of power supply connector
There is a risk of damaging the LSI by reverse connection of the power supply connector. For protection from reverse
connection, take measures such as externally placing a diode between the power supply and the power supply pin of the
LSI.
(4) Power supply lines
In the design of the board pattern, make power supply and GND line wiring low impedance.
When doing so, although the digital power supply and analog power supply are the same potential, separate the digital
power supply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to
the common impedance of the wiring patterns. Similarly take pattern design into account for GND lines as well.
Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND
pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at
low temperatures is not a problem for various characteristics of the capacitors used.
(5) GND voltage
Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm
that there are no pins for which the potential becomes less than a GND by actually including transition phenomena.
(6) Shorts between pins and misinstallation
When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is
installed erroneously, there is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance
getting between pins or between a pin and a power supply or GND.
(7) Operation in strong magnetic fields
Be careful when using the LSI in a strong magnetic field, since it may malfunction.
(8) Inspection in set board
When inspecting the LSI in the set board, since there is a risk of stress to the LSI when capacitors are connected to low
impedance LSI pins, be sure to discharge for each process. Moreover, when getting it on and off of a jig in the inspection
process, always connect it after turning off the power supply, perform the inspection, and remove it after turning off the
power supply. Furthermore, as countermeasures against static electricity, use grounding in the assembly process and take
appropriate care in transport and storage.
(9) Input pins
Parasitic elements inevitably are formed on an LSI structure due to potential relationships. Because parasitic elements
operate, they give rise to interference with circuit operation and may be the cause of malfunctions as well as damage.
Accordingly, take care not to apply a lower voltage than GND to an input pin or use the LSI in other ways such that parasitic
elements operate. Moreover, do not apply a voltage to an input pin when the power supply voltage is not being applied to
the LSI. Furthermore, when the power supply voltage is being applied, make each input pin a voltage less than the power
supply voltage as well as within the guaranteed values of electrical characteristics.
(10) Ground wiring pattern
When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND
pattern and small signal GND pattern and provide single point grounding at the reference point of the set so that voltage
variation due to resistance components of the pattern wiring and large currents do not cause the small signal GND voltage
to change. Take care that the GND wiring pattern of externally attached components also does not change.
(11) Externally attached capacitors
When using ceramic capacitors for externally attached capacitors, determine constants upon taking into account a
lowering of the rated capacitance due to DC bias and capacitance change due to factors such as temperature.
(12) Thermal shutdown circuit (TSD)
When the junction temperature becomes higher than a certain specific value, the thermal shutdown circuit operates and
turns the switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as
possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit
operating or use the LSI assuming its operation.
(13) Thermal design
Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in
actual states of use.
(14) Rush Current
Extra care must be taken on power coupling, power, ground line impedance, and PCB design while excess amount of rush
current might instantly flow through the power line when powering-up a LSI which is equipped with several power supplies,
depending on on/off sequence, and ramp delays.
15/16
●
Selecting a Model Name When Ordering
B
H
6
1
7
2
G
U
－
E
2
Part number
6172 :
DCDC 1ch + LDO 5 ch
Package type
GU : VCSP85H2 (BH6172)
Taping type
ROHM model name
E2 : Reel-wound embossed taping
VCSP85H2 (BH6172GU)
< Tape and Reel information >
< Dimension >
1PIN MARK
Lot. No.
Embossed carrier tape(with dry pack)
Tape
BH6172
3000pcs
E2
Quantity
Direction
of feed
2.60±0.05
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
S
0.06
S
A
24-φ0.3±0.05
0.05
A
B
E
1234
1234
1234
1234
1234
1234
D
C
B
A
B
(φ0.15) INDEX POST
Direction of feed
reel
1pin
1
2
3
4
5
0.3±0.05
P=0.5×4
※When you order , please order in times the amount of package quantity.
(Unit:mm)
Catalog No.08T305A '08.9 ROHM ©
Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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© 2009 ROHM Co., Ltd. All rights reserved.
R0039
A
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