BM67221FV-C [ROHM]
High Speed Digital Isolator;型号: | BM67221FV-C |
厂家: | ROHM |
描述: | High Speed Digital Isolator |
文件: | 总28页 (文件大小:3023K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
High Speed Digital Isolator
2500 Vrms 2ch
BM67221FV-C
General Description
Key Specification
The BM67221FV-C is a high-speed isolator IC used in
electric vehicles and hybrid vehicles. This IC features
dielectric strength of 2500 Vrms between I/O. Maximum
propagation delay time is 45 ns.
Supply Voltage Range:
Propagation Delay:
Stand-by Current:
4.5V to 5.5V
45ns (Max)
0μA (Typ)
-40°C to +125°C
Operating Temperature Range:
Features
Package
W(Typ) x D(Typ) x H(Max)
1. Dielectric strength of 2500 Vrms between I/O
2. Maximum propagation delay time of 45 ns
3. Built-in 2ch bi-directional propagation
4. AEC-Q100 Qualified
5. UL1577 Recognized:File No. E356010
Applications
Propagation of logic signal within electric and hybrid
vehicles
SSOP-B20W
6.50mm x 8.10mm x 2.01mm
Typical Application Circuit
EN1
7
EN2
14
17
13
VCC1
VCC2
4
8
UVLO
UVLO
TEN1
OUT2
TEN2
LVG.
HVG.
IN2
pulse
5
16
Q
S
R
generator
pulse
*
*
generator
IN1
OUT1
pulse
S
R
Q
15
6
generator
pulse
generator
11
20
2
9
GND1
GND2
LVG.
HVG.
* Please connect bypass capacitor directly to the IC pin.
Figure 1. BM67221FV-C Application Example
○Products structure: Silicon hybrid integrated circuit ○This product has no designed protection against radioactive rays.
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BM67221FV-C
Pin Configuration
N.C.
GND1
N.C.
GND2
N.C.
N.C.
VCC1
OUT2
IN1
VCC2
IN2
OUT1
EN2
EN1
TEN1
GND1
N.C.
TEN2
N.C.
GND2
Figure 2. BM67221FV-C Package (SSOP-B20W)
Pin Description
No.
1
Pin Name
NC
Function
No Connection
No.
20
19
18
17
16
15
14
13
12
11
Pin Name
GND2
NC
Function
Ground 2
2
GND1
NC
Ground 1
No Connection
No Connection
Power supply 2
Input 2
3
No Connection
Power supply 1
Output 2
NC
4
VCC1
OUT2
IN1
VCC2
IN2
5
6
Input 1
Output 1
OUT1
EN2
7
EN1
Enable input 1
Test mode input 1
Ground 1
Enable input 2
Test mode input 2
No Connection
Ground 2
8
TEN1
GND1
NC
TEN2
NC
9
10
No Connection
GND2
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BM67221FV-C
Description of Operation
1. Input/Output logic
The input/output logic levels for the BM67221FV-C are as shown in the table below.
No.
1
2
3
4
5
6
7
8
EN1
L
EN2
L
IN1
X
L
IN2
X
L
H
L
H
L
H
L
H
L
H
L
OUT1
OUT2
L
L
L
*
L
L
L
L
L
L
*
L
*
L
H
L
H
L
L
H
H
H
L
H
H
L
*
L
L
L
L
L
L
H
H
L
H
H
L
L
H
H
9
10
11
12
13
H
H
* Retains its previous state
In case EN1 and EN2 pins are "L" as in no. 1, the logic of OUT1 pin and OUT2 pin becomes "L".
The logic of OUT2 pin becomes "L" in case EN1 pin is "L" and EN2 pin is "H" as in no. 2 ~ 5. The output logic of OUT1
pin retains its previous state when IN1 pin is “H”.
The logic of OUT1 pin becomes "L" in case EN2 pin is "L" and EN1 pin is "H" as in no. 6 ~ 9.
The output logic of OUT1 (OUT2) changes according to the input logic of IN1 (IN2) in case EN1 and EN2 pins are in
"H" as in no. 10 ~ 13.
Likewise, since pull up/pull down resistor has not been connected to IN1, IN2, EN1 and EN2 pins, it is necessary to
connect external resistor in case you would like to fix the input logic of IN1, IN2, EN1 and EN2 pins.
2. TEN pins
The TEN pins serve as a test enable pin, respectively.
Please connect to GND to avoid the possibility of chip malfunction.
3. Output pin voltage
Logic levels for output pins are indicated in the truth table in Sections 1, 6, and 7. However, it may be assumed that
such logic levels disable the output circuit to fully turn ON at a low voltage when turning ON or OFF the power supply,
thus putting the output pin into the high impedance state.
4. Under Voltage Lock Out (UVLO) function
This IC has a built-in UVLO function to prevent the IC from malfunctioning whenever the power supply voltage drops.
It triggers the UVLO state when VCC1 pin and VCC2 pin are changed to 3.8V (Typ) or less and becomes in operational
state when changed to 4.0V (Typ) or more.
(1) VCC1 pin voltage drops at 4V (Typ) or more for VCC2 and in case VCC2 was changed to 3.8V (Typ) or below, the
output logic of OUT2 pin becomes "L" and output logic of OUT1 pin changes to hold state.
(2) VCC2 pin voltage drops at 4V Typ. or more for VCC1 and in case it changed to 3.8V (Typ), the output logic of
OUT1 pin becomes "L" and the output logic of OUT2 pin changes to hold state.
(3) In case VCC2 pin voltage was changed from 3.8V (Typ) or less to 4.0V (Typ) or more in 4.0V (Typ) or more for
VCC1 pin voltage, the output logic of OUT2 pin changes according to the input logic of input IN2 pin. The output
logic of OUT1 pin becomes "L".
(4) In case the VCC1 pin voltage was changed from 3.8V (Typ) or less to 4.0V (Typ) or more at 4.0V (Typ) or more for
VCC2 pin voltage, the output logic of OUT1 pin changes according to the input logic of IN1 pin.
5. Under Voltage Lock Out (UVLO) function masking time
This IC provides masking time for the UVLO function. The masking time is set to 10 µsec (Typ).
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BM67221FV-C
6. Input/Output logic levels with power supply turned OFF
The following table shows the output logic levels according to the order in which the power supply turns OFF.
Power
Supply
No.
IN1
IN2
OUT1
OUT2
1
2
3
4
5
6
7
8
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
H
VCC1
VCC2
In case VCC1 is turned OFF as in No. 1 ~ 4, the output logic of OUT2 pin becomes "L" and the output logic of OUT1
pin is retained.
In case VCC2 is turned OFF as in no. 5 ~ 8, the output logic of OUT1 pin becomes "L" and the logic output of OUT2 is
retained.
7. Output logic levels with power supply turned ON
The following table shows the output logic levels according to the order in which the power supply turns ON.
Turning-ON Turning-ON
No.
IN1
IN2
OUT1
OUT2
Order1
Order2
1
2
3
4
5
6
7
8
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L*
L*
L
L
H
H
L
H
L
H
L
L*
L
L*
VCC1
VCC2
VCC2
VCC1
*Different input and output logic
In case VCC1 is turned ON first as in no. 1 ~ 4, a signal from VCC1 side to the circuit of VCC2 side cannot be
received because of the cancellation by the signal before the circuit of VCC2 side starts-up. For that reason, the
output logic of OUT1 pin becomes "L" and the output logic does not match with the input logic as in no. 3, 4*.
In case VCC2 is turned ON first as in no. 5 ~ 8, the signal from VCC2 side to the circuit of VCC1 side cannot be
received because of the cancellation by the signal before the circuit of VCC1 side starts-up. For that reason, the
output logic of OUT2 pin becomes "L" and the output logic does not match with the input logic as in no. 6 and 8*.
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BM67221FV-C
Timing Chart
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
OUT1
OUT2
Figure 3. VCC1 to VCC2 (IN1=L, IN2=L)
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
Mask time
Mask time
(typ.10µs)
(typ.10µs)
OUT1
Mask time
Mask time
(typ.10µs)
(typ.10µs)
OUT2
Figure 4. VCC1 to VCC2 (N1=H, IN2=H)
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Timing Chart - continued
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
Mask time
Mask time
Mask time
(typ.10µs)
(typ.10µs)
(typ.10µs)
OUT1
Mask time
(typ.10µs)
OUT2
Figure 5. VCC1 to VCC2 (IN1=L to H, IN2=L to H)
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
OUT1
Mask time
(typ.10µs)
OUT2
Figure 6. VCC1 to VCC2 (IN1=H to L, IN2=H to L)
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BM67221FV-C
Timing Chart - continued
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
OUT1
OUT2
Figure 7. VCC2 to VCC1 (IN1=L, IN2=L)
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
Mask time
(typ.10µs)
Mask time
(typ.10µs)
OUT1
OUT2
Mask time
(typ.10µs)
Mask time
(typ.10µs)
Figure 8. VCC2→ VCC1(IN1=H, IN2=H)
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Timing Chart - continued
UVLO OFF
UVLO ON
VCC1
VCC2
EN1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN2
IN1
IN2
Mask time
(typ.10µs)
OUT1
Mask time
(typ.10µs)
Mask time
(typ.10µs)
Mask time
(typ.10µs)
OUT2
Figure 9. VCC2 to VCC1(IN1=L to H, IN2=L to H)
UVLO OFF
UVLO ON
VCC1
UVLO OFF
UVLO ON
Input inhibition area(max.500µs)
Input inhibition area(max.500µs)
EN1
EN2
IN1
IN2
Mask time
µs
OUT1
OUT2
typ.10
)
(
Figure 10. VCC2 to VCC1 (IN1=H to L, IN2=H to L)
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BM67221FV-C
Absolute Maximum Ratings
Rating
BM67221FV-C
7.0(Note 1)
Parameter
Symbol
Unit
Power Supply Voltage 1
Power Supply Voltage 2
IN1 Pin Voltage
VCC1
VCC2
V
V
7.0(Note 2)
VIN1
-0.3 to +7.0(Note 1)
-0.3 to +7.0(Note 2)
-0.3 to +7.0(Note 2)
-0.3 to +7.0(Note 1)
±10(Note 3)
V
IN2 Pin Voltage
VIN2
V
OUT1 Pin Voltage
VOUT1
VOUT2
IOMAX(OUT)
VGND
Topr
V
OUT2 Pin Voltage
V
Output Current
mA
Vrms
°C
°C
W
GND1-GND2 Ground Potential
Operating Temperature Range
Storage Temperature Range
2500
-40 to +125
-55 to +150
1.19(Note 4)
Tstg
Power Dissipation
Maximum Junction
Temperature
Pd
Tjmax
150
°C
(Note 1) Reference to GND1.
(Note 2) Reference to GND2.
(Note 3) Should not exceed Pd and ASO.
(Note 4) Derate by 9.52mW/°C when operating above Ta=25°C, when mounted on a glass epoxy board measuring 70 mm 70 mm 1.6 mm (including a
copper foil area of 3% or less).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as
short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a
special mode exceeding the absolute maximum ratings
Recommended Operating Conditions
Parameter
Symbol
VCC1
BM67221FV-C
4.5 to 5.5(Note 5)
4.5 to 5.5(Note 6)
Unit
V
Power Supply Voltage 1
Power Supply Voltage 2
VCC2
V
(Note 5) Relative to GND1
(Note 6) Relative to GND2
Insulation Related Characteristics
Parameter
Symbol
RS
Characteristic
>109
Unit
Ω
Insulation Resistance(VIO=500V)
Insulation Withstand Voltage/1Min
Insulation Test Voltage/1s
VISO
2500
Vrms
Vrms
VISO
3000
UL1577 Ratings Table
Following values are described in UL Report.
Parameter
Side 1 Circuit Current
Values
0.21
0.21
1.05
1.05
2500
125
Units
Conditions
mA
mA
mW
mW
Vrms
℃
VCC1=5V
VCC2=5V
VCC1=5V
VCC2=5V
Side 2 Circuit Current
Side 1 Consumption Power
Side 2 Consumption Power
Isolation Voltage
Maximum Operating (Ambient) Temperature
Maximum Junction Temperature
Maximum Strage Temperature
Maximum Data Transmission Rate
℃
150
℃
150
MHz
20
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BM67221FV-C
Electrical Characteristics (All values at Ta-40C to125C and VCC4.5V to 5.5V, unless otherwise specified)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
<Whole>
VCC1 Power Supply Current, Quiescent
VCC2 Power Supply Current, Quiescent
VCC1 Power Supply Current, DC
VCC2 Power Supply Current, DC
VCC1 Power Supply Current, 10kbps
VCC2 Power Supply Current, 10kbps
VCC1 Power Supply Current, 1Mbps
VCC2 Power Supply Current, 1Mbps
IN1,IN2 Input Inhibition Area
ICC1STBY
ICC2STBY
ICC1Q
-
-
-
-
-
-
-
-
-
0
10
10
µA
µA
EN1 = 0
0
EN2 = 0
0.21
0.21
0.22
0.22
0.86
0.86
-
0.42
mA
mA
mA
mA
mA
mA
µs
VIN = 0 or VCC
VIN = 0 or VCC
fIN : 5kHz
ICC2Q
0.42
ICC10k1
ICC10k2
ICC1M1
ICC1M2
tIN
0.44
0.44
fIN : 5kHz
2.00
fIN : 500kHz
fIN : 500kHz
2.00
500(Note 7)
<Output pin: OUT1 and OUT2>
High-level Output Voltage
VOH
VOL
VCC-0.5
0
VCC-0.3
0.2
VCC
0.4
V
V
IO=-4mA
IO=4mA
Low-level Output Voltage
(Note 7) Please do not switch the input signal IN1 and IN2 between tIN sections. Output may not match the logic input.
VCC1
VCC2
tIN
EN1
EN2
Figure 11. IN1, IN2 Input Inhibition Area
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BM67221FV-C
Electrical Characteristics – continued
(All values at Ta-40C to 125C and VCC4.5Vto5.5V, unless otherwise specified)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
<Input pin: IN1 and IN2>
Input Current
IIN
-
VCC×0.7
0
0
-
10
VCC
µA
V
VIN=VCC
High-level Input Threshold
Low-level Input Threshold
<Enable pin: EN1 and EN2>
Input Current
VINH
VINL
-
VCC×0.3
V
IEN
-
VCC×0.7
0
0
-
10
VCC
µA
V
VEN=VCC
High-level Input Threshold
Low-level Input Threshold
<Test pin: T_EN1 and T_EN2>
Input Current
VENH
VENL
-
VCC×0.3
V
ITEN
30
VCC×0.7
0
50
-
70
VCC
µA
V
VT_EN=VCC
High-level Input Threshold
Low-level Input Threshold
<Switching Characteristics>
Propagation Delay (Low to High)
Propagation Delay (High to Low)
Propagation Distortion
Rise Time
VTENH
VTENL
-
VCC×0.3
V
tPLH
10
10
-
20
20
0
45
45
8
ns
ns
tPHL
|tPLH - tPHL
|
ns
tr
tf
-
2.5
2.5
35
-
ns
Fall Time
-
-
ns
design assurance
Common-Mode Transient Immunity
CML
-
-
kV/µs
Input/Output Timing
50%
50%
IN1, IN2
tPHL
T
tPHL
90%
90%
50%
50%
OUT1, OUT2
10%
10%
tf
tr
Figure 12. Input/Output Timing Chart
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BM67221FV-C
Typical Performance Curve
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0.0
125°C
125°C
25°C
25°C
-40°C
-40°C
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage: VCC [V]
Supply Voltage: VCC [V]
Figure 13. Circuit Current vs Supply Voltage
(VCC1 Power Supply Current)
Figure 14. Circuit Current vs Supply Voltage
(VCC2 Power Supply Current, DC)
10
8
6.0
125°C
25°C
-40°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
125°C -40°C 25°C
6
4
125°C
25°C
-40°C
2
0
-2
0
1
2
3
4
5
0
1
2
3
4
5
Input Voltage : V [V]
IN
Input Voltage : VIN [V]
Figure 15. Input Current vs Input Voltage
(Input Current at Input Pin)
Figure 16. Output Voltage vs Input Voltage
(High-/Low-level Input Threshold, VCC1, VCC2=4.5V)
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BM67221FV-C
Typical Performance Curve - continued
6.0
5.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
125°C 25°C -40°C
125°C 25°C -40°C
5.0
125°C
25°C
-40°C
125°C
25°C
-40°C
4.5
0
5
0
5
0
5
0
5
0.0
-0.5
0
1
2
3
4
5
0
1
2
3
4
5
Input Voltage : VIN[V]
Input Voltage : V [V]
IN
Figure 17. Output Voltage vs Input Voltage
(High-/Low-level Input Threshold, VCC1, VCC2=5.0V)
Figure 18. Output Voltage vs Input voltage
(High-/Low-level Input Threshold, VCC1, VCC2=5.5V)
4.5
5.0
4.8
4.6
4.4
4.2
4.0
4.3
4.1
3.9
3.7
3.5
-40°C
-40°C
25°C
25°C
125°C
125°C
0
2
4
6
8
10
0
2
4
6
8
10
Output Current : lO [mA]
Output Current : lO [mA]
Figure 19. Output Voltage vs Output Current
Figure 20. output Voltage vs Output Current
(High-level Output Voltage,VCC1,VCC2=4.5V)
(High-level Output Voltage,VCC1,VCC2=5.0V)
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BM67221FV-C
Typical Performance Curve - continued
5.5
5.3
1.0
0.8
0.6
0.4
0.2
0.0
-40°C
125°C
5.1
4.9
4.7
4.5
25°C
25°C
125°C
-40°C
0
2
4
6
8
10
0
2
4
6
8
10
Output Current : lO [mA]
Output Current : lO [mA]
Figure 21. Output Voltage vs Output Current
Figure 22. Output Voltage vs Output Current
(High-level Output Voltage, VCC1,VCC2=5.5V)
(Low-level Output Voltage VCC1, VCC2=4.5V)
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
125°C
125°C
25°C
25°C
-40°C
-40°C
0
2
4
6
8
10
0
2
4
6
8
10
Output Current : lO [mA]
Output Current: IO [mA]
Figure 23. Output Voltage vs Output Current
Figure 24. Output Voltage vs Output Current
(Low-level Output Voltage, VCC1, VCC2=5.0V)
(Low-level Output Voltage, VCC1, VCC2=5.5V)
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Typical Performance Curve - continued
26
25
24
23
22
21
20
19
18
17
16
26
25
24
23
tPHL
22
tPHL
21
20
tPLH
19
tPLH
18
17
16
-50 -25
0
25
50 75 100 125 150
-50 -25
0
25
50 75 100 125 150
Temperature: [°C]
Temperature: [°C]
Figure 25. Propagation Delay vs Temperature
(VCC1, VCC2 = 4.5V)
Figure 26. Propagation Delay vs Temperature
(VCC1, VCC2 = 5.0V)
26
25
24
23
22
21
20
19
18
17
16
2.0
1.5
1.0
0.5
0.0
tPHL
125°C
tPLH
25°C
-40°C
0.2
0.0
0.4
0.6
0.8
1.0
-50 -25
0
25 50 75 100 125 150
Temperature:[°C]
Input Frequency : [Mbps]
Figure 27. Propagation Delay vs Temperature
(VCC1, VCC2 = 5.5V)
Figure 28. Circuit Current vs Input Frequency
(VCC1 Power Supply Current, VCC1, VCC2 = 4.5V)
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Typical Performance Curve – continued
2.0
1.5
1.0
2.0
1.5
1.0
0.5
0.0
125°C
0.5
125°C
-40°C
25°C
25°C
-40°C
0.0
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
Input Frequency : [Mbps]
Input Frequency :[Mbps]
Figure 29. Circuit Current vs Input Frequency
(VCC1 Power Supply Current , VCC1, VCC2 = 5.0V)
Figure 30. Circuit Current vs Input Frequency
(VCC1 Power Supply Current VCC1, VCC2 = 5.5V)
2.0
1.5
1.0
0.5
0.0
2.0
1.5
1.0
0.5
0.0
125°C
125°C
25°C
25°C
-40°C
-40°C
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
Input Frequency : [Mbps]
Input Frequency: [Mbps]
Figure 31. Circuit Current vs Input Frequency
(VCC2 Power Supply Current, VCC1, VCC2 = 4.5V)
Figure 32. Circuit Current vs Input Frequency
(VCC2 Power Supply Current, VCC1, VCC2 = 5.0V)
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Typical Performance Curve - continued
2.0
1.5
1.0
125°C
0.5
25°C
-40°C
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Input Frequency: [Mbps]
Figure 33. Circuit Current vs Input Frequency
(VCC2 Power Supply Current, VCC1, VCC2 =5.5V)
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I/O Equivalent Circuit
VCC1
VCC2
VCC2
VCC1
OUT1
OUT2
IN1
IN2
GND
Figure 34. IN1, IN2
Figure 35. OUT1, OUT2
VCC1
VCC2
VCC1
VCC2
TEN1
TEN2
EN1
EN2
100k
Figure 36. TEN1, TEN2
Figure 37. EN1, EN2
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Power Dissipation Reduction Characteristics
Measuring equipment: TH156 (Kuwano Electric)
Measuring condition: Mounted on the ROHM’s board
Board size: 70 70 1.6 mm3
1.5
Single-layer board: ja 105.3C/W
1.19W
1.0
0.5
0
0
25
50
75
100
Ambient Temperature: [°C]
125
150
Figure 38. SSOP-B20W Power Dissipation Reduction Curve
Thermal Dissipation
In consideration of the power consumption (P), package power dissipation (Pd), and ambient temperature (Tj) of this IC,
ensure that the operating temperature of the chip will not exceed 150C. If Tj is beyond 150C, parasitic elements may
malfunction and may cause leakage current to increase. Constantly using the IC under the said conditions may deteriorate
the IC and further lead to its breakdown. Strictly keep Tjmax at 150C under any circumstances.
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the Pd rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Appendix: Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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Ordering Information
B M 6
7
2
2
1
F
V -
CE 2
Package
FV : SSOP-B20W
Packaging and forming specification
E2: Embossed tape and reel
Part Number
Marking Diagram
SSOP-B20W
TOP VIEW
Product Name.
BM67221
LOT No.
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
SSOP-B20W
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Revision History
Date
Revision
001
Changes
25.Jun.2012
28.Aug.2012
New Release
002
Fix typo about Figure 7. VCC2→ VCC1(IN1=L,IN2=L)
P.3 Add a description about 4) Under voltage lock out.
P.10 Fix typo about Electrical Characteristics about IN1, IN2 Input inhibition area.
P.5~P.8 Fix typo about input inhibition about area.
P.11 Add minimum propagation delay.
26.Oct.2012
20.Dec.2012
003
004
P.21 Delete description.
P.1 Add a description 4) AEC-Q100 Qualified at Features
Applied new style and improved understandability.
P.1 Add a description 5) UL1577 Recognized at Features
P.9 Add UL1577 Ratings Table
05.Mar.2014
25.Dec.2015
005
006
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
Datasheet
Buy
BM67221FV-C - Web Page
Distribution Inventory
Part Number
Package
Unit Quantity
BM67221FV-C
SSOP-B20W
2000
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
2000
Taping
inquiry
Yes
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