BU1523KV_技术文档

Image Correction ICs

Image Correction IC

for Panel

BU1523KV

No.11060EAT05

●Description

BU1523KV is an image quality adjustment IC for in-vehicle displays. It can control brightness, contrast, hue, intensity,

sharpness, etc. It is equipped with both RGB and YCbCr as input/output interfaces. It also incorporates LVDS output

capability with an embedded LVDS transmitter.

●Features

1) RGB input data format

Width of data bus 24bit

Vertical/horizontal synchronizing and data enable signal

2) RGB output data format

It is the same as the entry format

3) YCbCr input data format

ITU-R BT.656-4 or synchronization signal YCbCr

Width of data bus 8bit

Vertical/horizontal synchronizing and data field signal

Date range conform ITU-R BT.601 or full range

4) YCbCr output data format

The same as the entry format

Capable of processing BT.656 input to generate and output

synchronization signal from SAV/EAV

5) RGB IF Image quality adjustment

Contrast, Brightness, Hue, Chroma and Sharpness

Independent RGB gamma correction

6) YCbCr Image quality adjustment

Contrast, Brightness, Hue, Chroma and Sharpness

7) LVDS Transmitter

Built-in LVDS transmitter

Converts RGB24 bit, vertical/horizontal synchronization signal

and data enable inputs into 4ch LVDS data streams

8) 2-line serial interface slave function

The register in BU1523KV can be set

9) Package

VQFP100

●Applications

In-vehicle display etc.

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2011.02 - Rev.A

1/22

Technical Note

BU1523KV

●Absolute maximum ratings

[Table 1]

Parameter

Supply voltage 1

Symbol

VDDIO

VDDI2C

PVDD

LVDD

VDD

Ratings

-0.3～+4.0

Unit

V

Supply voltage 2

-0.3～+4.0

V

Supply voltage 3

-0.3～+4.0

V

Supply voltage 4

-0.3～+4.0

V

Supply voltage 5

-0.3～+2.1

V

Input voltage range

Storage temperature range

VIN

-0.3～IO_LVL+0.3 ^*1

-40～+125

V

Tstg

℃

mW

Power dissipation

PD

1000 ^*2, 1499 ^*3

*1 IO_LVL is a generic name of VDDIO, VDDI2C

*2 IC only. In the case exceeding 25℃, 10mW should be reduced at the rating 1℃.

*3 When packaging a glass epoxy board of 70x70x1.6mm. If exceeding 25℃, 14.99mW should be reduced at the rating 1℃

*

Has not been designed to withstand radiation.

Operation is not guaranteed at absolute maximum ratings.

●Operating conditions

[Table 2]

Ratings

Typ.

Parameter

Symbol

Unit

Min.

3.0

Max.

3.6

Supply voltage1(IO)

Supply voltage2(IO)

Supply voltage3(PLL)

Supply voltage4(LVDS)

Supply voltage5(CORE)

Input voltage range

VDDIO

VDDI2C

PVDD

LVDD

VDD

3.3

1.8

-

V

3.0

3.6

V

3.0

3.6

V

1.65

0.0

1.95

V

VIN

IO_LVL^*1

+85

V

Operating temperature range

Topr

-40

-

℃

*1 IO_LVL is a generic name of VDDIO, VDDI2C.

*

Please supply power source in order of VDD→ (VDDIO, VDDI2C, PVDD,LVDD).

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2011.02 - Rev.A

2/22

Technical Note

BU1523KV

●Block Diagram

LPDNB

RGBMUTE

MIR_EN

TAP/TAN

TBP/TBN

TCP/TCN

TDP/TDN

CbCr

Y

YCbCr/

RGB

Convert

Output

Data

Convert

RDI0~RDI7

GDI0~GDI7

BDI0~BDI7

Hue

Adjust

Chroma

Adjust

RGB

Gamma

LVDS

Transmitter

RGB/

YCbCr

Convert

RGB

RGBCKI

RGBHSI

RGBVSI

RGBDEI

Contrast

Adjust

Brightness

Adjust

Sharpnes

Adjust

TCKP/TCKN

PLL

RGB IF Image quality adjustment part

YDI0~YDI7

YDO0~YDO7

Output

Data

Convert

SAV/EAV

Detect

CbCr

Y

YCKI

YHSI

YVSI

Hue

Adjust

Chroma

Adjust

YCKO

YHSO

YVSO

YFLDO

YFLDI

Contrast

Adjust

Brightness

Adjust

Sharpnes

Adjust

YCbCr IF Image quality adjustment part

SCL

SDA

I2C IF

(slave)

Register

I2CDEV

RESETB

TEST0

TEST1

The LVDS data output mode

LPDNB

RGBMUTE

MIR_EN

TAP/TAN

TBP/TBN

TCP/TCN

TDP/TDN

CbCr

Y

RDI0~RDI7

GDI0~GDI7

BDI0~BDI7

Output

Data

Convert

YCbCr/

RGB

Convert

Chroma

Adjust

Hue

Adjust

RGB

Gamma

LVDS

Transmitter

RGB/

YCbCr

conversion

RGBCKI

RGBHSI

RGBVSI

RGBDEI

RGB

Brightness

Adjust

Contrast

Adjust

Sharpnes

Adjust

TCKP/TCKN

PLL

RDO0~RDO7

GDO0~GDO7

BDO0~BDO7

RGBCKO

RGB IF Image quality adjustment part

SCL

SDA

RGBHSO

RGBVSO

RGBDEO

I2C IF

(slave)

Register

I2CDEV

RESETB

TEST0

TEST1

The RGB data output mode (YCbCr interface cannot be used.)

Terminal selection from register

*Change their modes with register setting.

Fig. 1 Block diagram

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2011.02 - Rev.A

3/22

Technical Note

BU1523KV

●Terminal Functions・Equivalent circuit diagram

[Table 3 Terminal Functions (1/4)]

PowerSupply

No.

Name

In/Out

(*1)

Init

(*2)

I/O

Type

Function Description

System

(*4)

BDI4

BDI5

BDI6

BDI7

RGB B Data [4] input

1

2

I

-

a

A

-

RGB B Data [5] input

-

RGB B Data [6] input

3

I

-

a

RGB B Data [7] input

4

I

-

a

RGBHSI

RGB H Sync input

5

I

-

a

RGBVSI

RGB V Sync input

6

I

-

a

RGBDEI

RGB Data Enable input

7

I

-

a

GND

Ground

8

G

I

a,b

a

RGBCKI

RGB Clock input

9

-

B

-

VDDIO

IO power source

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P

I/O

I

-

a

I2CVDD

2-line serial interface IO power source

2-line serial interface data input / output ^(*6)

2-line serial interface clock input

Ground

-

b

-

SDA

In

b

G

H

-

SCL

-

b

GND

G

P

O

-

a,b

a

VDDIO

IO power source

-

VDD

CORE power source

-

YDO7/RGBDEO

YDO6/RGBVSO

YDO5/RGBHSO

YDO4/BDO7

YDO3/BDO6

YDO2/BDO5

YDO1/BDO4

YDO0/BDO3

YFLDO/BDO2

BT601 YcbCr data [7] / RGB data output

BT601 YcbCr data [6] / RGB V Sync output

BT601 YcbCr data [5] / RGB H Sync output

BT601 YcbCr data [4] / RGB B data [7] output

BT601 YcbCr data [3] / RGB B data [6] output

BT601 YcbCr data [2] / RGB B data [5] output

BT601 YcbCr data [1] / RGB B data [4] output

BT601 YcbCr data [0] / RGB B data [3] output

BT601 Field output / RGB B data [2] output

Low

a

D

a

*

Fix an unused input pin to GND or VDDIO (Fix SDA and SCL to I2CVDD. TEST0 and TEST1 are excluded.) .

*1) “I” shows the input, “O” shows the output, “I/O” shows the bidirection, “P” shows the power supply, and “G” shows GND.

*2) “PD” shows the pull-down, “In” shows the input mode, and “Low” shows the Low level output.

*4) "a" in the column in the power supply system shows VDDIO, "b" shows I2CVDD, "c" shows LVDD, and "d" shows PVDD.

*6) “SDA” is output at "L" level when usually using it or is in the state of high impedance, and "H" level is not output.

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2011.02 - Rev.A

4/22

Technical Note

BU1523KV

[Table 3 Terminal Functions (2/4) ]

Power Supply

No.

Name

In/Out

(*1)

Init

(*2)

I/O

Type

Function Description

System

(*4)

YVSO/BDO1

YHSO/BDO0

GND

BT601 YcbCr data [1] / RGB V Sync output

BT601 YcbCr data [0] / RGB H Sync output

Ground

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

O

Low

-

a

D

-

G

a,b

a

YCKO/RGBCKO

VDDIO

BT601 Clock output / RGB Clock output

IO power source

O

Low

-

D

-

P

a

GDO7

RGB G data [7] output

O

Low

-

a

D

-

GDO6

RGB G data [6] output

O

a

GDO5

RGB G data [5] output

O

a

GDO4

RGB G data [4] output

O

a

VDDIO

IO power source

P

a

(*5)

YCKI/GDO3

GND

BT656 Clock input / RGB G data [3] output

Ground

I/O

G

In

a

F

-

a,b

a

YHSI/GDO2

YVSI/GDO1

YFLDI/GDO0

VDD

BT656 H Sync input / RGB G data [2] output ^(*5)

BT656 V Sync input / RGB G data [1] output ^(*5)

BT601 Field input / RGB G data [0] output

CORE power source

I/O

P

In

E

-

In

a

In

a

-

YDI0/RDO7

YDI1/RDO6

YDI2/RDO5

VDDIO

BT656 Y data [0] input / RGB R data [7] output ^(*5)

BT656 Y data [1] input / RGB R data [6] output ^(*5)

BT656 Y data [2] input / RGB R data [5] output ^(*5)

IO power source

I/O

P

In

a

E

-

In

a

In

a

-

a

YDI3/RDO4

YDI4/RDO3

YDI5/RDO2

YDI6/RDO1

YDI7/RDO0

BT656 Y data [3] input / RGB R data [4] output ^(*5)

BT656 Y data [4] input / RGB R data [3] output ^(*5)

BT656 Y data [5] input / RGB R data [2] output ^(*5)

BT656 Y data [6] input / RGB R data [7] output ^(*5)

BT656 Y data [7] input / RGB R data [0] output ^(*5)

I/O

In

a

E

In

a

In

a

In

a

In

a

*

Fix an unused input pin to GND or VDDIO (Fix SDA and SCL to I2CVDD. TEST0 and TEST1 are excluded.) .

*1) “I” shows the input, “O” shows the output, “I/O” shows the bidirection, “P” shows the power supply, and “G” shows GND.

*2) “PD” shows the pull-down, “In” shows the input mode, and “Low” shows the Low level output.

*4) "a" in the column in the power supply system shows VDDIO, "b" shows I2CVDD, "c" shows LVDD, and "d" shows PVDD.

*5) 36-50 pins direction depends on the modes.

the RGB data output mode: output

the LVDS data output mode: input

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2011.02 - Rev.A

5/22

Technical Note

BU1523KV

[Table 3 Terminal Functions (3/4) ]

Power Supply

No.

Name

In/Out

(*1)

Init

(*2)

I/O

Type

Function Description

System

(*4)

GND

Ground

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

G

I

-

a,b

a

d

c

-

A

B

A

C

B

-

I2CDEV

RGBMUTE

MIR_EN

TEST0

TEST1

RESETB

LPDNB

VDDIO

PGND

PVDD

LGND

TDP

I²C device address setting

MUTE signal : High active

LVDS data mirror enable : High active

Test pin 0 ^(*3)(Connect to GND)

Test pin 1 ^(*3)(Connect to GND)

Logic reset signal: Low active

LVDS reset signal: Low active

IO power source

-

I

-

I

-

I

PD

I

PD

-

I

-

P

G

P

G

O

G

P

O

G

-

PLL ground

-

PLL ground

-

LVDS ground

-

LVDS data output D ch P

LVDS data output D ch N

LVDS clock output P

-

c

I

TDN

-

c

I

TCKP

TCKN

TCP

-

c

I

LVDS clock output N

-

c

I

LVDS data output C ch P

LVDS data output C ch N

LVDS ground

-

c

I

TCN

-

c

I

LGND

LVDD

TBP

-

c

-

LVDS power source

-

c

-

LVDS data output B ch P

LVDS data output B ch N

LVDS data output A ch P

LVDS data output A ch N

LVDS ground

-

c

I

TBN

-

c

I

TAP

-

c

I

TAN

-

c

I

LGND

-

c

-

*

Fix an unused input pin to GND or VDDIO (Fix SDA and SCL to I2CVDD. TEST0 and TEST1 are excluded.) .

*1) “I” shows the input, “O” shows the output, “I/O” shows the bidirection, “P” shows the power supply, and “G” shows GND.

*2) “PD” shows the pull-down, “In” shows the input mode, and “Low” shows the Low level output.

*3) Fix TEST0 and TEST1 to GND (The opening is a prohibition of use)

*4) "a" in the column in the power supply system shows VDDIO, "b" shows I2CVDD, "c" shows LVDD, and "d" shows PVDD.

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2011.02 - Rev.A

6/22

Technical Note

BU1523KV

[Table 3 Terminal Functions (4/4) ]

Power Supply

No.

Name

In/Out

(*1)

Init

(*2)

I/O

Type

Function Description

System

(*4)

GND

RDI0

RDI1

RDI2

RDI3

RDI4

RDI5

RDI6

RDI7

Ground

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

G

I

-

a,b

a

-

RGB R data [0] input

RGB R data [1] input

RGB R data [2] input

RGB R data [3] input

RGB R data [4] input

RGB R data [5] input

RGB R data [6] input

RGB R data [7] input

IO power source

A

-

I

a

I

a

I

a

I

a

I

a

I

a

I

a

VDDIO

GDI0

GDI1

GND

GDI2

GDI3

GDI4

GDI5

GDI6

GDI7

VDD

P

I

a

RGB G data [0] input

RGB G data [1] input

GND

a

A

-

I

a

G

I

a,b

a

RGB G data [2] input

RGB G data [3] input

RGB G data [4] input

RGB G data [5] input

RGB G data [6] input

RGB G data [7] input

CORE power source

RGB B data [0] input

RGB B data [1] input

RGB B data [2] input

RGB B data [3] input

IO power source

A

-

I

a

I

a

I

a

I

a

I

a

P

I

-

BDI0

BDI1

BDI2

BDI3

VDDIO

a

A

-

I

a

I

a

I

a

P

a

*

Fix an unused input pin to GND or VDDIO (Fix SDA and SCL to I2CVDD. TEST0 and TEST1 are excluded.) .

*1) “I” shows the input, “O” shows the output, “I/O” shows the bidirection, “P” shows the power supply, and “G” shows GND.

*2) “PD” shows the pull-down, “In” shows the input mode, and “Low” shows the Low level output.

*4) "a" in the column in the power supply system shows VDDIO, "b" shows I2CVDD, "c" shows LVDD, and "d" shows PVDD.

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2011.02 - Rev.A

7/22

Technical Note

BU1523KV

[Table 4 (1/2)]

Type

Equivalent circuit configuration

Type

Equivalent circuit configuration

VDDIO

To internal

A

B

To internal

GND

Input terminal

Input terminal with schmitt

VDDIO

Internal signal

To internal

Internal signal

C

D

GND

Input terminal with pull down

Output terminal

VDDIO

To internal

Internal signal

To internal

GND

Internal signal

E

F

Internal signal

GND

Internal signal

GND

Input/Output terminal

Input/Output terminal with schmitt

I2CVDD

To internal

GND

Internal signal

To internal

G

H

Internal signal

GND

Input/Output terminal

(2-line serial I/F)

Input terminal with schmitt

(2-line serial I/F)

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2011.02 - Rev.A

8/22

Technical Note

BU1523KV

[Table 4 (2/2)]

Type

Equivalent circuit configuration

LVDD

Internal signal

T*P

T*N

I

Internal signal

GND

Output terminal (LVDS)

●Pin configurations

GND [76]

[50] YDI7/RDO0

RDI0 [77]

RDI1 [78]

RDI2 [79]

RDI3 [80]

RDI4 [81]

RDI5 [82]

RDI6 [83]

RDI7 [84]

VDDIO [85]

GDI0 V [86]

GDI1 [87]

GND [88]

GDI2 [89]

GDI3 [90]

GDI4 [91]

GDI5 [92]

GDI6 [93]

GDI7 [94]

VDD [95]

BDI0 [96]

BDI1 [97]

BDI2 [98]

BDI3 [99]

VDDIO [100]

[49] YDI6/RDO1

[48] YDI5/RDO2

[47] YDI4/RDO3

[46] YDI3/RDO4

[45] YDDIO

[44] YDI2/RDO5

[43] YDI1/RDO6

[42] YDI0/RDO7

[41] YDD

[40] YFLDI/GDO0

[39] YVSI/GDO1

[38] YHSI/GDO2

[37] GND

[36] YCKI/GDO3

[35] YDDIO

[34] GDO4

[33] GDO5

[32] GDO6

[31] GDO7

[30] VDDIO

[29] YCKO/RGBCKO

[28] GND

1PIN MARK

[27] YHSO/BDO0

[26] YVSO/BDO1

[Pin No.] Pin Name

Fig.2 Pin configurations

9/22

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2011.02 - Rev.A

Technical Note

BU1523KV

●Electrical characteristics (DC)

[Table 5]

Unless otherwise specified, VDD=1.80V, VDDIO=3.3V, I2CVDD=3.3V, PVDD=3.3V, LVDD=3.3V, GND=0.0V, Ta=25℃, fIN=36MHz

Limits

Parameter

Symbol

Unit

Condition

Min.

8.0

Typ.

-

Max.

36.0

Input frequency 1

Input frequency 2

Input clock duty

FIN1

FIN2

DCKI

IDD1

ILVDD1

ILVDD2

IDDst1

IIH

MHz RGBCKI

MHz YCKI

8.0

45

-

50

16

55

38

-

55.0

55

-

%

mA

μA

V

RGBCKI, YCKI

36MHz (VDD)

Operational current

LVDS supply current

Leakage current

Input ”H” current

Input ”L” current

36MHz, LVDS_RS = 1 (LVDD, PVDD)

Input toggle pattern (Fig.4)

-

36MHz, LVDS_RS = 0 (LVDD, PVDD)

Input toggle pattern (Fig.4)

-

Release reset , input pin =GND

(VDD)

-

50

10

100

-10

25

-

VIH=IO_LVL

VIL=GND

IIL

-

Pull-down current

Input ”H” voltage 1

Input ”L” voltage 1

Input ”H” voltage 2

Input ”L” voltage 2

Output ”H” voltage

IPD

50

-

VIH=IO_LVL

IO_LVL

x0.8

IO_LVL

+0.3

Normal input

VIH1

VIL1

(Including input mode of I/O terminal)

IO_LVL

x 0.2

Normal input

-0.3

-

V

(Including input mode of I/O terminal)

IO_LVL

x0.85

IO_LVL

+0.3

Hysteresis input

(RESETB, RGBCKI, YCKI, LPDNB, SCL, RGBMUTE)

VIH2

VIL2

-

V

IO_LVL

x 0.15

Hysteresis input

(RESETB, RGBCKI, YCKI, LPDNB, SCL, RGBMUTE)

-0.3

-

V

IO_LVL

-0.4

IOH=-1.0mA(DC)

(including output mode of I/O terminal)

VOH

VOL

-

IO_LVL

0.4

V

IOL=1.0mA(DC)

(including output mode of I/O terminal)

Output ”L” voltage

LVDS Transmitter

0.0

-

V

Normal Swing

250

350

450

300

35

mV

V

LVDS_RS^(*1)= 1

RL=100Ω

Differential output voltage

VOD

Reduced Swing

120

200

LVDS_RS^(*1)= 0

Change in VOD between

complementary output states

ΔVOD

VOC

ΔVOC

IOS

-

Common mode voltage

1.125

1.25

1.375

35

RL=100Ω

Change in VOC between

complementary output states

-

mV

mA

μA

Output short circuit current

Output TRI-STATE current

-24

VOUT^(*2)=0V, RL=100Ω

LPDNB=GND

IOZ

±10

VOUT^(*2)=GND to LVDD

*

IO_LVL is a generic name of VDDIO, VDDI2C.

(*1) LVDS_RS is a register name controlled with 2-line serial interface.

(*2) VOUT=TAN/P, TBN/P, TCN/P, TDN/P, TCKN/P

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2011.02 - Rev.A

10/22

Technical Note

BU1523KV

RL

Fig.3 LVDS Transmitter characteristic diagram

CLKIN

Tx0

Tx1

Tx2

Tx3

Tx4

Tx5

Tx6

X=A,B,C,D

※Input waveform to the LVDS transmitter block

※Tx0-7 are the data before being serialized by the LVDS transmitter.

Refer to Fig.8 for the serialized data sequence.

Fig.4 Input toggle pattern

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2011.02 - Rev.A

11/22

Technical Note

BU1523KV

●Electric Characteristics (AC)

1. Image quality adjustment data input interface timing

RGB(Y)VSI / RGB(Y)HSI

RGBDEI / YFLDI

R(G,B,Y)DI[7:0]

ｔ_CKI

RGB(Y)CKI

(RGB(Y)CK_POL=1)

RGB(Y)CKI

(RGB(Y)CK_POL=0)

ｔ_CMSｔ_CMH

Fig.5 Data input interface timing

[Table 6]

Unless otherwise specified, VDD=1.80V, VDDIO=3.3V, I2CVDD=3.3V, PVDD=3.3V, LVDD=3.3V, GND=0.0V, Ta=25℃

Description

Min.

27.7

18.1

45

Typ.

Max.

125

55

-

Unit

ns

%

Symbol

t_CKI1

RGBCKI Clock Cycle

YCKI Clock Cycle

-

t_CKI2

d_CKI

t_CMS

t_CMH

RGB(Y)CKI Clock Duty

50

-

RGB(Y)CKI Rise / Fall set-up Time

RGB(Y)CKI Rise / Fall Hold Time

6

ns

5

-

* RGB(Y)CK_POL is an internal register of BU1523KV to determine the polarity of RGB(Y)CKI.

* Ensure to make the total number of 1 line input pixels to YCbCr interface to be even (multiple of 4, in case of cycles).

2. Image quality adjustment data output interface timing

ｔ_CKO

RGB(Y)CKO

(R(Y) CK_POL=1)

ｔ_OHH

ｔ_OHL

RGB(Y)VSO

/ RGB(Y)HSO

RENO / YFLDO

ｔ_ODV

R(G,B,Y)DO

Fig.6 Data output interface timing

[Table 7]

Unless otherwise specified, VDD=1.80V, VDDIO=I2CVDD=PVDD=LVDD=3.3V, GND=0.0V, Ta=25℃

Symbol

t_CKO1

Description

Min.

27.7

18.1

40

Typ.

Max.

125

60

Unit

ns

%

RGBCKO Clock Cycle

YCKO Clock Cycle

-

t_CKO2

d_CKO1

d_CKO2

t_ODV

RGBCKO Clock Duty

YCKO Clock Duty

50

-

35

65

%

Output delay R(G, B,Y)DO

-

5

ns

t_OHL,t_OHHOutput delay RGB(Y)VSO, RGB(Y)HSO, RENO/YFLDO

-

5

* The above figure shows the waveform when RGB(Y)CK_POL= “1” is set. When RGB(Y)CK_POL= “0” is set, RGB(Y)VSO, RGB(Y)HSO and

RGB(Y)DO are output at the falling edge of RGB(Y)CKO.

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2011.02 - Rev.A

12/22

Technical Note

BU1523KV

3. LVDS transmitter switching characteristic

[Table 8]

Unless otherwise specified, VDD=1.80V, VDDIO=I2CVDD=PVDD=LVDD=3.3V, GND=0.0V, Ta=25℃, fIN=36MHz

Symbol

Description

MIN

TYP

MAX

Unit

tLVT

LDVS Transition Time

ns

-

0.6

1.5

tTOP1

tTOP0

tTOP6

tTOP5

tTOP4

tTOP3

tTOP2

tPLL

Output Data Position 0

Output Data Position 1

Output Data Position 2

Output Data Position 3

Output Data Position 4

Output Data Position 5

Output Data Position 6

Phase Locked Loop Set Time

ns

ms

-1.2

0.0

+1.2

^tCKI-1.2

7

^tCKI+1.2

7

tCKI

7

tCKI

2

3

4

5

6

^tCKI-1.2

7

2

3

4

5

6

^tCKI+1.2

7

^tCKI-1.2

7

3

4

5

6

^tCKI+1.2

7

tCKI

7

^tCKI-1.2

7

^tCKI+1.2

7

tCKI

7

^tCKI-1.2

7

^tCKI+1.2

7

tCKI

7

^tCKI-1.2

7

^tCKI+1.2

7

tCKI

7

-

10.0

LVDS Output

Vdiff=(TxP)-(TxN)

80%

20%

80%

20%

TxP

V_diff

CL

RL

TxN

t_LVT

LVDS Output Load

Fig.7 LVDS Output AC Timing diagram 1

www.rohm.com

2011.02 - Rev.A

13/22

Technical Note

BU1523KV

TCKP/N OUT

(Differential)

TA2

TB2

TA1

TB1

TC1

TD1

TA0

TB0

TC0

TD0

TA6

TB6

TC6

TD6

TA5

TB5

TA4

TB4

TA3

TB3

TAP/N

TBP/N

TC5

TD5

TC4

TD4

TC3 TC2

TD3 TD2

TCP/N

TDP/N

Next Cycle

Previous Cycle

t_TOP1

t_TOP0

t_TOP6

t_TOP5

t_TOP4

t_TOP3

t_TOP2

Fig.8 LVDS Output AC Timing diagram 2

LPDNB

POWER

CLKIN

t_PLL

TCKP/N

* POWER shows VDDIO, I2CVDD, VDD, LVDD, PVDD

* CLKIN is a clock input to the LVDS transmitter.

Fig.9 LVDS Phase Locked Loop Set Time

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2011.02 - Rev.A

14/22

Technical Note

BU1523KV

4. 2-line serial interface timing

SDA

SCL

t_SU;DAT

t_LOW

t_BUF

t_HD;ST

A

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_HIGH

Fig.10 2-line serial interface timing

[Table 9]

Unless otherwise specified, VDD=1.80V, VDDIO=3.3V, I2CVDD=3.3V, PVDD=3.3V, LVDD=3.3V, GND=0.0V, Ta=25℃

Symbol

f_SCL

Description

MIN

0

TYP

MAX

Unit

kHz

µs

SDL clock frequency

-

400

Holding time(Repetition) ”START” Condition

After this period, the first clock pulse is generated.

t_HD;STA

0.6

1.3

0.6

0

-

t_LOW

Low period of SDL clock

µs

t_HIGH

High period of SDL clock

µs

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

Setup time of repetition ”START” condition

Data hold time

µs

Data setup time

100

0.6

1.3

-

ns

Setup time of 'STOP' condition

'Bus free time between STOP' condition and 'START' condition

µs

www.rohm.com

2011.02 - Rev.A

15/22

Technical Note

BU1523KV

●Operation explanation of each block

1. Image quality adjustment of RGB interface

It adjusts image quality input through 24-bit RGB interface.

The supported I/O interface consists of 24-bit data, vertical synchronization signal, horizontal synchronization signal and

data enable signal. It converts 24-bit RGB into YCbCr444 and makes adjustment on the contrast, brightness, sharpness,

hue and intensity in the YCbCr space. The contrast, brightness and sharpness are adjusted against the luminance (Y)

component and the hue and intensity are adjusted against the color difference (CbCr) component. In addition to the

image quality adjustment in the YCbCr space, it is also equipped with the RGB independent gamma correction capability

in the RGB space. Converting YCbCr444 to 24-bit RGB, gamma correction is made to each of the RGB components.

16 gamma curve points can be set and the intervals between those set points are linearly interpolated. When the

RGBMUTE terminal is set to “High” level, the RGB output data will be all “0” from the next frame.

2. Image quality adjustment of YUV

It adjusts image quality input through YCbCr422 interface.

The supported I/O interfaces are ITU-R BT.656-4 and YCbCr with synchronization signal (complied with ITU-R BT.601).

When the input is ITU-R BT.656-4, the output can be selected from ITU-R BT.656-4 and YCbCr with synchronization

signal. However, when the input is YCbCr with synchronization signal, the output can only be YCbCr with synchronization

signal. It makes adjustment on the contrast, brightness, sharpness, hue and intensity in the YCbCr space. The contrast,

brightness and sharpness are adjusted against the luminance (Y) component and the hue and intensity are adjusted

against the color difference (CbCr) component.

3. LVDS transmitter

It outputs high-speed serial data for image quality adjustment of RGB interface in LVDS format. The data mapping to be

output in the LVDS format can be changed by the register setting. When the LPDNB terminal is set to “Low” level, the

LVDS transmitter part will go into power down mode. The LVDS output will become Hi-Z status.

4. 2-line serial interface

2-line serial interface slave function is embedded. The registers are accessed through this interface. The slave address is

46h (in 7-bit notation) when I2CDEV=0 and 47h (in 7-bit notation) when I2CDEV=1. The sub address is automatically

incremented when consecutively accessed twice or more in read or write operation. * Slave address of 46h and 47h are in

hexadecimal. * Fig.11 depicts the status when I2CDEV=0.

SDA

SCL

S

1-7

8

9

1-7

8

9

1-7

8

9

P

START

condition address

Slave

STOP

condition

R/W

ACK

Sub address

ACK

Data

ACK

Data sending and receiving waveform

Write

Slave address

W

(0)

A(S)/

A(S)

S

A(S) Sub address A(S) Write data A(S) Write data A(S)

Write data

P

(46h)

sequence

Read

Slave address

(46h)

W

(0)

Slave address

(46h)

R

(1)

A(M)/

P

A(M)

A(S) Sub address A(S)

S

A(S) Read data A(M)

Read data

sequence

S = START condition

P = STOP condition

A(S) = acknowledge by slave

A(M) = acknowledge by master

A(S) = not acknowledge by slave

A(M) = not acknowledge by master

Fig.11 2-line serial interface format

www.rohm.com

2011.02 - Rev.A

16/22

Technical Note

BU1523KV

●Example of application circuit

V_DD

F.Bead*1

(3.3V System)

(1.8V System)

(3.3V System)

VDDIO

VDD

LVDD

LGND

0.1uF

0.01uF

LVDD

LGND

GND

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

I2CVDD

CLKOUT

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RE0

RE1

RE2

RE3

RE4

RE5

RE6

CLKOUT

R4

0.1uF

0.01uF

R5

R6

R7

R8

R9

G4

G5

G6

G7

G8

G9

B4

B5

B6

B7

B8

B9

VDD

GND

PVDD

PGND

PVDD

PGND

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

Main CPU

(Graphic LSI)

[RGB Data]

TAN

TAP

TBN

TBP

RA-

RGBCKI, RGBVSI,

RGBHSI, RGBDEI,

RDI0～7, GDI0～7, BDI0～7

RA+

RB-

RB+

[BT.601 Data]

YCKO,YFLDO,

YVSO, YHSO,

YDO0～7

RC-

TC4

TC5

TC6

TD0

TD1

TD2

TD3

TD4

TD5

TCN

TCP

RC+

BU1523KV

BU16002KVT

TCLK

TDN

RCLK-

RCLK+

RD-

V_DD

(3.3V System)

SDA

SCL

OPEN

TDP

RD+

R0

R1

G0

G1

B0

B1

LPDB

open

RCKO

BDO4

BDO3

BDO2

RMUTE

open

OPEN

[BT.656 Data]

YCKI,YFLDI,

YVSI, YHSI,

YDI0～7

DVD,

Digital TV Encoder,

Camera etc.

PD

OE

100Otwist

Pair Cable

or

PCB trace

DK

R/F

Reset IC

RESETB

I2CDEV

TEST0,1,2

PCB(Transmitter)

PCB(Receiver)

*1: Recommended Parts: F.Bead: BLM18A-Series (Murata Manufacturing)

*2: If LVDS_RS is tied to “1”, LVDS swing is 350m V. If LVDS_RS is tied to “0”, LVDS swing is 200m V.

Fig.12 BU1523KV System connection Diagram

The above figure is an example of system connection for reference only and not intended to guarantee operation.

www.rohm.com

2011.02 - Rev.A

17/22

Technical Note

BU1523KV

●Procedure for turning on power supply

Follow the power-on sequence of VDD→(VDDIO, I2CVDD, PVDD, LVDD) as depicted in Fig.13. The timing for power-on

sequence is shown in Table 10 however, it is recommended to make the intervals of t^PWUV2, tPWUV and tPWUVL as short as

possible. Until after voltage is applied to all the power sources, the levels of all the input pins are fixed and the low level is

input onto RESETB, the internal status and pins remain unstable. Remove the reset after inputting the clock (RGBCKI,

YCKI). When the clock (RGBCKI, YCKI) is to be temporarily halted during the operation, apply the reset after the clock

(RGBCKI, YCKI) stopped to fix the operation, then follow the power-on sequence and remove the reset after inputting the

clock (RGBCKI, YCKI). 2-line serial interface is enabled for communication after the reset (RESETB) is removed. However,

racing may be caused if the rising edge of the reset (RESETB) signal and the signal change of 2-line serial interface occur

at the same time. Ensure not to allow the rising edge of the reset (RESETB) signal and the signal change of 2-line serial

interface to occur at the same time. Design the system to avoid racing and system malfunction when the internal status and

pins are unstable.

* The reset is also possible by the software reset (SRST_R_IP, SRST_Y_IP, SRST_LVDS).

Min Level Voltage

VDD

Min Level Voltage

I2CVDD

VDDIO

t_PWUV2

Min Level Voltage

t_PWUV

PVDD

LVDD

t_PWUVL

Clock Input

Clock Stop

Clock Input

Use PVDD and LVDD together.

※

RGBCKI

YCKI

Reset after the clock stops.

t_CR

RESETB

LPDNB

Release reset after inputting the clock.

I2CVDD

All input

terminals of

group

t_UNCV2

Regulations from start of I2CVDD

VDDIO

All input

terminals of

group

t_UNCV

t_RR

Regulations from start of I2CVDD

Reset State

The state of the terminal is invalid.

Reset State

Fig.13 Power supply input procedure (Min level is power-supply voltage lower bound of recommended range.)

[Table 10 Recommended value at time to turn on power supply]

Item

t_PWUV2

t_PWUV

t_PWUVL

t_UNCV2

t_UNCV

t_RR

Min.

0

Max.

50

1

Unit

ms

0

1

-

t_CR

0.1

-

www.rohm.com

2011.02 - Rev.A

18/22

Technical Note

BU1523KV

The power-off sequence is reverse of the power-on sequence, in the order of (VDDIO, I2CVDD, PVDD, LVDD)→VDD as

depicted in Fig.14. The timing for power-off sequence is shown in Table 11, however, it is recommended to make the

intervals of t^PWDV2m, tPWDV and tPWDVL as short as possible.

Note that turning off from the VDD (Power to the internal CORE) makes the internal status and pin status unstable.

Min Level Voltage

VDD

Min Level Voltage

I2CVDD

t_PWDV

Min Level Voltage

VDDIO

t_PWD

Min Level Voltage

PVDD

LVDD

Use PVDD and LVDD together.

※

t_PWDV

Operation Stop

Operation S

tate

Fig.14 Power-off procedure (Min level is power-supply voltage lower bound of recommended range of motion.)

[Table 11 Power-off time recommended value]

Item

t_PWDV2

t_PWDV

t_PWDVL

Min.

0

Max.

50

Unit

ms

0

50

0

50

www.rohm.com

2011.02 - Rev.A

19/22

Technical Note

BU1523KV

●PCB Design Guideline for LVDS

・Interconnecting media between Transmitter and Receiver ( i.e.PCB trace, connector, and cable) should be well balanced.

(Keep all these differential impedance and the length of media as same as possible.).

・Locate by –pass capacitors adjacent to the device pins as close as possible.

・Minimize the distance between traces of a pair. (S1) to maximize common mode rejection.

See following figure.

・Place adjacent LVDS trace pair at least twice (>2 x S1) as far away.

・Avoid 90 degree bends.

・Minimize the number of VIA on LVDS traces.

・Match impedance of PCB trace, connector, media (cable) and termination to minimize reflections (emissions)

for cabled applications (typically 100Ω Differential mode characteristic impedance).

GND

+Signal

-Signal

GND

S1

>2 x S1

+

⁺Receiver

Driver

+Receiver

Receiver

Driver

100Ω

Receiver

-

+

-

Receiver

-

+

Point-to-point configuration

Good

Multi-drop configuration

No Good

Monitor Pad

Stub

Layer1

Layer2

GND

Signal Via

GND Via

Fig.15 PCB Design Guideline for LVDS

www.rohm.com

2011.02 - Rev.A

20/22

Technical Note

BU1523KV

●Notes for use

(1) Absolute Maximum Ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can

break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any

special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety

measures including the use of fuses, etc.

(2) Recommended Operating conditions

These conditions represent a range within which characteristics can be provided approximately as expected.

The electrical characteristics are guaranteed under the conditions of each parameter.

(3) Reverse connection of power supply connector

The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown

due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply

terminal.

(4) Power supply line

Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard,

for the digital block power supply and the analog block power supply, even though these power supplies has the same

level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing

the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns.

For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply

terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an

electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem

including the occurrence of capacity dropout at a low temperature, thus determining the constant.

(5) GND voltage

Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.

Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric

transient.

(6) Short circuit between terminals and erroneous mounting

In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can

break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between

the terminal and the power supply or the GND terminal, the ICs can break down.

(7) Operation in strong electromagnetic field

Be noted that using ICs in the strong electromagnetic field can malfunction them.

(8) Inspection with set PCB

On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.

Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set

PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the

jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In

addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to

the transportation and the storage of the set PCB.

(9) Input terminals

In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the

parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the

input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals

a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage

to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is

applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of

electrical characteristics.

(10) Ground wiring pattern

If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND

pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that

resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the

small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.

(11) External capacitor

In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a

degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.

(12) Rush current

For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal

powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width

of GND wiring, and routing of wiring.

www.rohm.com

2011.02 - Rev.A

21/22

Technical Note

BU1523KV

●Ordering part number

B

U

1

5

2

3

K

V

-

E

2

Part No.

Package

KV:VQFP100

Packaging and forming specification

E2: Embossed tape and reel

VQFP100

16.0 0.2

14.0 0.1

Tape

Embossed carrier tape (with dry pack)

75

51

Quantity

500pcs

E2

50

76

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

100

1.0

26

1

25

+0.05

1PIN MARK

0.145

-

0.03

+

−

6°

4°

0.08

S

+0.05

0.2

-

0.04

M

0.08

Direction of feed

1pin

0.5 0.1

Reel

Order quantity needs to be multiple of the minimum quantity.

(Unit : mm)

∗

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2011.02 - Rev.A

22/22

Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-

controller or other safety device). ROHM shall bear no responsibility in any way for use of any

of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R1120

A


型号：	BU1523KV
厂家：	ROHM
描述：	Image Correction IC for Panel 图像校正IC，适用于面板
文件：	总23页 (文件大小：400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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