BU3058FV-E2 [ROHM]
Clock Generator, PDSO16,;
| 型号： | BU3058FV-E2 |
| 厂家： | 
ROHM |
| 描述： | Clock Generator, PDSO16, 光电二极管 |
| 文件： | 总5页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Structure
Product
Silicon monolithic Integrated circuit
Clock Generator With Built-in VCXO
Type
BU3058FV
Feature
To generate clocks for the Digital-TV.
Clock signals are generated by connecting crystal oscillator.
Built-in VCXO has the variable width of Typ±105ppm.
○Absolute Maximum Ratings
(Ta=25℃)
Parameter
Symbol
VDD
VIN
Ratings
-0.3 ～4.0
Unit
Supply voltage
Input Voltage
Storage Temperature range
V
V
℃
-0.3～VDD+0.3
-55～125
Tstg
450※
1
Power dissipation
PD
mW
※
1
A measure value at mounting on 70x70x1.6mm glass epoxy substrate.
In the case of exceeding Ta=25°C, 4.5mW should be reduced per 1°C.
The radiation-resistance design is not carried out.
※
※
Operation is not guaranteed.
○Operating Conditions
Parameter
Symbol
Ratings
Unit
3.135 ～ 3.465
0.8VDD ～ VDD
0.0 ～ 0.2VDD
Supply voltage
Input ”H” Voltage
Input ”L” Voltage
Operating
Temperature
VDD
VIH
VIL
V
V
V
-10 ～ 75
℃
topr
Vc
Frequency
Control Voltage
0.0 ～ VDD
V
REV. A
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○
（
Electrical Characteristics
VDD=3.3V, Ta=25°C, Crystal Frequency=27.000000MHz, at No Load, unless otherwise specified
）
Limit
Parameter
Symbol
Unit
Conditions
Min.
VDD-0.4
－
Typ.
－
Max.
－
VOH
VOL
V
V
IOH=4.0mA
IOL=4.0mA
Output H voltage
Output L voltage
－
0.4
Operating
circuit current
－
IDD
40.0
52.0
mA
Output No Load
Input H current 1
Input H current 2
Input H current 3
Input L current 1
Input L current 2
Input L current 3
Crystal Pullability
IupH
IdnH
IdirH
IupL
IdnL
IdirL
fp
-1.5
19.0
-1.5
－
69.0
－
1.5
136.5
1.5
μA
μA
μA
μA
μA
μA
PDB Terminal,VIH=VDD
TEST Terminal,VIH=VDD
VCTRL, SEL1, SEL2 Terminal,VIH=VDD
PDB Terminal,VIL=0.0V
-126.0
-1.5
-53.0
－
-17.0
1.5
TEST Terminal,VIL=0.0V
-1.5
－
1.5
VCTRL, SEL1, SEL2 Terminal,VIL=0.0V
※
0≦VCTRL≦VDD
±80
±105
±130
ppm
※
This is a guarantee with only IC.
The arrangement with a crystal maker is required separately about crystal variation.
○Block diagram
Output
11:CLK54M
14:CLKOUT
PLL1
PLL2
7:SEL1
8:SEL2
Select
Control
10:TEST
TEST Terminal,With pull-down
15:PDB
Power-down control terminal
With pull-up
4:VCTRL
1:XIN
9:CLK27M
VCXO
16:XOUT
○Table of Output Frequency（Crystal Frequency=27.000000MHz）
14pin
11pin
9pin
mode No.
SEL1
SEL2
CLKOUT
CLK54M
CLK27M
①
②
③
④
L
L
L
H
L
66.000000MHz
74.250000MHz
77.000000MHz
82.000000MHz
54.000000MHz
54.000000MHz
54.000000MHz
54.000000MHz
27.000000MHz
27.000000MHz
27.000000MHz
27.000000MHz
H
H
H
REV. A
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○Package Outline, Appearance of Marker
Lot No.
3058F
SSOP-B16
○Pin Function
PIN No.
PIN Name
XIN
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Crystal Input terminal
Power supply for VCXO
GND for VCXO
AVDD1
AVSS1
VCTRL
AVDD2
AVSS2
SEL1
SEL2
CLK27M
TEST
CLK54M
VSS
VDD
CLKOUT
PDB
XOUT
VCXO control input terminal
Power supply for PLL-Analog
GND for PLL-Analog
CLKOUT output control terminal1
CLKOUT output control terminal2
27.000000MHz Output
Test terminal with pull-down
54.000000MHz Output
GND for PLL-Digital
Power supply for PLL-Digital
66.000000MHz / 74.250000MHz / 77.000000MHz / 82.000000MHz Output
Power-down control terminal,with pull-up
Crystal Output terminal
●Cautions on use（BU3058FV）
Basically, mount ICs to the printed circuit board for use. (If the ICs are not mounted to the printed circuit board,
the characteristics of ICs may not be fully demonstrated.)
Mount 0.1µF capacitors in the vicinity of the IC PINs between 2PIN (AVDD1), 3PIN (AVSS1), and 5PIN(AVDD2),
6PIN(AVSS2), and 12PIN (VSS), 13PIN (VDD) respectively.
To obtain accurate frequency, capacitance (pF) need to be placed between 3PIN (AVSS1) and 1PIN (XIN),
3PIN (AVSS1) and 16PIN(XOUT).
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the
power supply and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU3058FV from the
printed circuit board or to insert a capacitor (of 1 or less), which bypasses high frequency desired, between the
power supply and the GND terminal.
For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the
internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power
wiring, width of GND wiring, and routing of wiring.
REV. A
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●Cautions on use （common）
（１）Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down
devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the
absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
（２）Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics
are guaranteed under the conditions of each parameter.
（３）Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the
reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal.
（４）Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block
power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power
supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power
supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar
manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in
order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem
including the occurrence of capacity dropout at a low temperature, thus determining the constant.
（５）GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to
be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.
（６）Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the
ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply
or the GND terminal, the ICs can break down.
（７）Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
（８）Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure
to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection
process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn
OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the
assembly process and pay thorough attention to the transportation and the storage of the set PCB.
（９）Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough
attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any
parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC.
In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within
the guaranteed value of electrical characteristics.
（１０）Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the
small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and
voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause
fluctuations in the GND wiring pattern of external parts as well.
（１１）External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation
in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
REV. A
Notice
N o t e s
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illustrate the standard usage and operations of the Products. The peripheral conditions must
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However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
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