ML5239_技术文档

FEDL5239-05

Created on: December 1,2020

ML5239

Analog Front-End IC for 16-Serial-Cell Lithium-Ion Secondary Battery Protection

◼ General Description

ML5239 is a power voltage monitoring IC for 5 to 16-cell lithium-ion secondary battery pack. It can be

connected in multi-stage series to monitor the voltage of more than 17-cell lithium-ion battery.

It also has a pin for driving an external cell balance FET, enabling to control the balance for each battery cell.

◼ Features

⚫ 5 to 16 cell voltage measurement function

Built-in 12-bit successive approximation type ADC

Cell voltage measurement precision: ±10mV at 25°C, cell voltage 3.6V

⚫ Cell voltage measurement time:1ms (typ)/cell

⚫ Open/short detection function of cell voltage measurement pin

⚫ Multi-stage series IC-IC communication function

MCU interface: SPI serial interface

CRC communication error detection

⚫ SPI communication speed = 500kHz (max) at four-stage configuration

Multi-stage connection ICs: 16 (max)

⚫ Cell balance FET driving pin

⚫ Temperature sensor input: 4 channels

⚫ Current consumption

Cell voltage measurement state: 1.2mA (typ), 2.4mA (max)

Power-down state: 0.1µA (typ), 1µA (max)

⚫ Power supply voltages: 10 to 72V

⚫ Operational temperature: -40 to 85°C

⚫ Package: 64-pin plastic TQFP

Note)

This product cannot be used for in-vehicle use and for any equipment, device, or system that requires

a specific quality and high level of reliability (e.g., medical equipment, transportation equipment,

aerospace machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not

sure whether your purpose of use applies to the above special purpose, please contact a ROHM sales

representative before purchasing.

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ML5239

◼ Block Diagram

HV

VREG

GNDU

VREGU

CCH

VREF

CCL

/CSO

Charge

Pump

SCKO

Voltage

Regulator

SPI I/F

SDOI

/INTI

VDD

V16

CB16

V15

Vref

Generator

Level

Shifter

CB15

V14

ID

Cell Voltage

Level Shifter

CB14

V13

GPOUT

/CS

12bit

A/D

Converter

SPI I/F

SCK

SDI

Control

Logic

V3

CB3

V2

SDO

/INTO

Clock

Generator

TEST1

TEST2

CB2

V1

CB1

GND

PUPI

Thermistor

Input

Thermistor

Driver

/PUPI

PUPO

/PUPO

Powerup

Control

◼ Pin Configuration (Top View)

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CB13

V12

CB12

V11

CB11

V10

CB10

V9

TEST2

TEST1

VREGU

/CSO

SCKO

SDOI

3

4

5

6

7

/INTI

8

GNDU

VREF

9

CB9

V8

10

11

12

13

14

15

16

VREG

CB8

V7

TEMP4

TEMP3

TEMP2

TEMP1

TDRV

GPOUT

CB7

V6

CB6

V5

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◼ Pin Description

Pin No.

Pin name

I/O

O

Description

1

CB13

V12

CB12

V11

CB11

V10

CB10

V9

Battery cell 13 cell balance control output pin.

Battery cell 13 low voltage input and Battery cell 12 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 11, input the

same potential as the highest V pin (V5 to V11) of the battery connected to

the IC.

2

3

I

O

I

Battery cell 12 cell balance control output pin.

Battery cell 12 low voltage input and Battery cell 11 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 10, input the

same potential as the highest V pin (V5 to V10) of the battery connected to

the IC.

4

5

O

I

Battery cell 11 cell balance control output pin.

Battery cell 11 low voltage input and Battery cell 10 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 9, input the

same potential as the highest V pin (V5 to V9) of the battery connected to the

IC.

6

7

O

I

Battery cell 10 cell balance control output pin.

Battery cell 10 low voltage input and Battery cell 9 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 8, input the

same potential as the highest V pin (V5 to V8) of the battery connected to the

IC.

8

9

CB9

V8

O

I

Battery cell 9 cell balance control output pin.

Battery cell 9 low voltage input and Battery cell 8 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 7, input the

same potential as the highest V pin (V5 to V7) of the battery connected to the

IC.

10

11

12

CB8

V7

O

I

Battery cell 8 cell balance control output pin.

Battery cell 8 low voltage input and Battery cell 7 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 6, input the

same potential as the highest V pin (V5 to V6) of the battery connected to the

IC.

13

14

CB7

V6

O

I

Battery cell 7 cell balance control output pin.

Battery cell 7 low voltage input and Battery cell 6 high voltage input pin.

If the number of connected battery cells is in the range of 5, input the same

potential as the highest V pin (V5) of the battery connected to the IC.

Battery cell 6 cell balance control output pin.

15

16

17

18

19

20

21

22

23

24

25

26

CB6

V5

O

I

Battery cell 6 low voltage input and Battery cell 5 high voltage input pins.

Battery cell 5 cell balance control output pin.

CB5

V4

O

I

Battery cell 5 low voltage input and Battery cell 4 high voltage input pins.

Battery cell 4 cell balance control output pin.

CB4

V3

O

I

Battery cell 4 low voltage input and Battery cell 3 high voltage input pins.

Battery cell 3 cell balance control output pin.

CB3

V2

O

I

Battery cell 3 low voltage input and Battery cell 2 high voltage input pins.

Battery cell 2 cell balance control output pin.

CB2

V1

O

I

Battery cell 2 low voltage input and Battery cell 1 high voltage input pins.

Battery cell 1 cell balance control output pin.

CB1

GND

O

—

These are ground pins.

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Pin No.

27

Pin name

/CS

I/O

I

Description

SPI interface chip select pin. The SPI interface is active if the input is "L"

level. Be sure to input "H" level when completing one data write/read

operation.

SPI interface clock input pin. Capture the SDI input into the LSI at the rising

edge of the SCK clock. Output the data from the SDO pin or SDI pin at the

falling edge of the SCK.

28

SCK

I

SPI interface data input pin.

29

30

31

SDI

SDO

/INTO

IO

O

It is data I/O pin for upper IC in multi-stage connection.

SPI interface data output pin. If /CS input is in "H" level, output of this pin is

Hi-Z state.

Interrupt signal output to an external MCU. This pin is an NMOS open drain

output pin and outputs "L" level if interrupted.

O

ID identification pin at multi-stage connection. Set it to the GND level without

multi-stage connection or for the lowest IC connected with the external MCU.

Set it to the VREG level of the IC at multi-stage connection for ICs other than

the lowest one.

32

ID

I

33

34

GPOUT

TDRV

O

General output pin. This pin has an NMOS open drain output.

Ground pin for thermistor. Set this to 0V output during temperature

measurement or to be the Hi-Z state otherwise. This pin has an NMOS open

drain output.

35

36

37

38

TEMP1

TEMP2

TEMP3

TEMP4

IO

Temperature measurement thermistor connection pin. Connect an NTC

thermistor between this pin and the TDRV pin and a resistor between this pin

and the VREG pin.

This can be switched to general output by the register setting.

Built-in 5.3V regulator output pin. Connect a 1F capacitor between this pin

and GND. Power supply for IC internal circuit.

39

40

VREG

VREF

O

Reference voltage output pin for the built-in ADC. Connect a 1F capacitor

between this pin and GND.

GND pin for the communication circuit with a higher IC at multi-stage

connection. Connect to the GND pin of the higher IC via a resistor. Connect

to the VDD pin without a higher IC.

41

42

GNDU

/INTI

—

Interrupt signal input pin from a higher IC at multi-stage connection. Connect

to the /INTO pin of the higher IC via a resistor. It has a built-in 100k pull-up

resistor between this pin and the VREGU pin. Set this to the open state

without a higher IC.

I

Data I/O pin of the SPI interface with a higher IC at multi-stage connection.

Connect to the SDI pin of the higher IC via a resistor. Set this to the open

state without a higher IC.

43

44

45

SDOI

SCKO

/CSO

IO

O

Serial clock output pin of the SPI interface with a higher IC at multi-stage

connection. Connect to the SCK pin of the higher IC via a resistor. Set this to

the open state without a higher IC.

Chip select output pin of the SPI interface with a higher IC at multi-stage

connection. Connect to the /CS pin of the higher IC via a resistor. Set this to

the open state without a higher IC.

O

Power supply pin for the communication circuit with a higher IC at multi-stage

connection. Connect to the VREG pin of the higher IC via a resistor. Connect

to the VDD pin without a higher IC.

46

47

VREGU

TEST1

—

I

LSI test input pin. Fix to GND level.

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Pin No.

48

Pin name

TEST2

I/O

I

Description

It has a built-in 1M (typ) pull-down resistor in the LSI.

Connection pin of capacitor for the internal voltage multiplier circuit. Connect

a capacitor of 0.22F between this pin and the CCH pin of this IC.

Connection pin of capacitor for the internal voltage multiplier circuit. Connect

a capacitor of 0.22F between this pin and the CCL pin of this IC.

Pin for smoothing multiplied voltage. Connect a capacitor of 0.22F between

this pin and the VDD pin of this IC.

49

50

51

CCL

CCH

HV

O

Power-up trigger signal input pin (reverse phase). The "L" pulse input moves

the state from power-down to power-up. Set it to the GND level without

multi-stage connection or for the lowest IC connected with the external MCU.

Power-up trigger signal input pin (normal phase). The "H" pulse input moves

the state from power-down to power-up.

52

/PUPI

I

53

54

PUPI

GND

I

—

These are ground pins.

Power-up trigger signal output pin (normal phase). Connect to the PUPI pin

of a higher IC via a resistor at multi-phase connection. Set this to the open

state without a higher IC.

55

PUPO

O

Power-up trigger signal output pin (reverse phase). Connect to the /PUPI pin

of a higher IC via a resistor at multi-phase connection. Set this to the open

state without a higher IC.

56

57

/PUPO

VDD

O

Power supply input pin.

—

Connect an external CR filter for noise rejection.

Battery cell 16 high voltage input pin.

If the number of connected battery cells is in the range of 5 to 15, input the

same potential as the highest V pin (V5 to V15) of the battery connected to

the IC.

58

59

60

61

62

63

64

V16

CB16

V15

I

O

I

Battery cell 16 cell balance control output pin.

Battery cell 16 low voltage input and Battery cell 15 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 14, input the

same potential as the highest V pin (V5 to V14) of the battery connected to

the IC.

CB15

V14

O

I

Battery cell 15 cell balance control output pin.

Battery cell 15 low voltage input and Battery cell 14 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 13, input the

same potential as the highest V pin (V5 to V13) of the battery connected to

the IC.

CB14

V13

O

I

Battery cell 14 cell balance control output pin.

Battery cell 14 low voltage input and Battery cell 13 high voltage input pins.

If the number of connected battery cells is in the range of 5 to 12, input the

same potential as the highest V pin (V5 to V12) of the battery connected to

the IC.

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◼ Absolute Maximum Ratings

(GND= 0V, Ta = 25°C)

Unit

Item

Symbol

V_DD

Condition

Rating

Potential difference between

VDD, VREGU, GNDU, and HV

-0.3 to +86.5

V

Supply voltage

Potential difference between

V_REG

-0.3 to +6.5

V

V_REGU

Applied to V1 to V16, TEST1,

and TEST2 pins

V_IN1

-0.3 to V_DD+0.3

-0.3 to V_REG+0.3

V

Applied to /CS, SCK, SDI,

TEMP1 to TEMP4, and ID pins

V_IN2

Input voltage

Potential difference between

SDOI and /INTI pins and GNDU

V_IN3

-0.3 to V_REGU+0.3

-0.5 to V_DD+0.3

V

V_IN4

Applied to PUPI and /PUPI pins

VDD=50V,

Applied to VREG, VREF, SDI,

SDO, /INTO, GPOUT, PUPO,

/PUPO, SDOI, /CSO, SCKO,

TDRV, and TEMP1 to TEMP4

pins

Short-circuit

output current

I_OS

20

mA

Power dissipation

Storage

P_D

Ta=25°C

3.6

W

T_STG

—

-50 to +150

°C

◼ Recommended Operating Conditions

(GND= 0V)

Item

Symbol

V_DD

Condition

Applied to VDD pin

Range

Unit

V

10 to 72

Supply voltage

Potential difference between VREGU

and GNDU pins

V_REGU

Ta

5.1 to 5.5

-40 to +85

V

Operational

temperature

No VREG output load

°C

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◼ Electrical Characteristics

⚫ DC Characteristics

V_DD= 10 to 72V, VREGU-GNDU = 5.1 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load

Item

Symbol

V_IH

Condition

Min.

Typ.

—

Max.

V_REG

Unit

V

Digital "H" input voltage (Note 1)

Digital "L" input voltage (Note 1)

Digital "H" input voltage (Note 2)

Digital "L" input voltage (Note 2)

PUPI and /PUPI pins "H" input

voltage

—

0.8×V_REG

V_IL

—

0

0.8×V_REGU

0

—

0.2×V_REG

V_REGU

V

V_IHU

V_ILU

GNDU pin reference

—

V

—

0.2×V_REGU

V

V_IHP

V_ILP

—

3.6

0

—

VDD

0.7

V

PUPI and /PUPI pins "L" input

voltage

Digital "H" input current (Note 1)

Digital "L" input current (Note 1)

Digital "H" input current (Note 2)

SDOI pin "L" input current

I_IH

I_IL

V_IH= V_REG

V_IL= GND

—

–2

—

–2

—

2

—

2

µA

I_IHU

I_ILU

V_IH= V_REGU

V_IL= GNDU

V_REGU=5.3V, V_IL=

GNDU

—

/INTI pin "L" input current

I_ILU

I_IHP

I_ILP

–106

—

-53

—

-26

2

µA

PUPI and /PUPI pins "H" input

current

V_IH= 5V

PUPI and /PUPI pins "L" input

current

V_IL= GND

–2

—

Digital "H" output voltage (Note 3)

Digital "L" output voltage (Note 4)

V_OH

V_OL

I_OH=-100A

I_OL=1mA

V_REG-0.2

0

—

V_REG

0.2

V

I_OH=-100A

GNDU pin reference

Digital "H" output voltage (Note 5)

Digital "L" output voltage (Note 5)

V_OHU

V_OLU

V_OHP

V_OLP

I_OLK

V_REGU-0.2

—

V_REGU

0.4

V_HV

0.4

2

V

I_OL=1mA

GNDU pin reference

I_OH=-50A

0

V_HV-0.2

0

PUPO and /PUPO pins "H" output

V

voltage

PUPO and /PUPO pins "L" output

voltage

VDD pin reference

I_OL=50A

VDD pin reference

V

Digital output leakage current

(*6)

V_OH=V_REG

V_OL=0V

,

–2

µA

10V < V_DDpin voltage <

72V

VREG output voltage

V_REG

5.1

5.3

4.7

5.5

V

Output load current <

1.5mA

Output load current <

VREF output voltage

V_REF1

4.68

4.72

0.1A

HV pin output voltage range

CB pin output resistor

V_HV

R_CB

VDD pin reference

3.3

50

—

5.5

V

—

100

220

k

Applied to CBn pin

CB pin output voltage

V_CB

Vn-1

—

Vn

V

n=1 to 16

VREG dropping detection voltage

VREG return detection voltage

V_RGD

V_RGR

—

4.0

4.3

4.7

4.6

5.1

V

Note 1: Applied to /CS, SCK, SDI, and ID pins.

Note 2: Applied to SDOI and /INTI pins.

Note 3: Applied to SDO, SDI, and TEMP1 to TEMP4 pins.

Note 4: Applied to SDO, /INTO, GPOUT, SDI, and TEMP1 to TEMP4 pins.

Note 5: Applied to /CSO, SCKO, and SDOI pins.

Note 6: Applied to SDO, /INTO, and GPOUT pins.

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⚫ Supply Current Characteristics

V_DD= 10 to 72V, GND = 0V, Ta = -40 to +85°C, no VREG and VREF output load.

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Cell voltage measuring

state

supply current (Note 1)

Power-down

supply current (Note 1)

VREGU power supply

current

Scan measurement

VREGU=GNDU=VDD

I_DD1

—

1.2

2.4

mA

I_DDS

VREGU=GNDU=VDD

—

0.1

1.0

µA

At multi-stage connection

VREGU-GNDU=5.3V

I_REGU

250

500

(Note 1) This is defined by total current flowing into the VDD and VREGU pins without multi-stage connection.

⚫ Cell Voltage Measurement Characteristics

V_DD= 10 to 72V, GND = 0V, Ta = -40 to +85°C, no VREG output load.

Item

Symbol

I_INVC

Condition

Cell voltage being

measured

Min.

Typ.

Max.

Unit

Cell monitoring pin

input current

-1

—

1

µA

Cell monitoring pin

input leakage current

Cell voltage not

being measured

Each cell voltage =

3.6V

I_ILVC

-1

—

1

µA

V_CERT

-10

10

mV

Ta= 25°C

Cell voltage

measurement error

Each cell voltage = 1

to 4.3V

V_CER

-25

—

25

mV

Ta=-10 to 60°C

—

Measurement resolution

V_LSB

t_SCAN

t_SEL

—

5000/4095

—

10.0

1.2

mV

ms

16-cell scan

measurement

Select measurement

7.0

0.8

8.3

1

Cell voltage

measurement time

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⚫ Temperature Sensor Input Measurement Characteristics

V_DD= 10 to 72V, GND = 0V, Ta = -40 to +85°C, no VREG output load.

Item

Symbol

I_TEMP

Condition

TEMP input = 0.4 to

4.5V

Min.

Typ.

Max.

Unit

TEMP1 - TEMP4 pins

input current

-2

—

2

µA

TDRV pin

"L" output voltage

TDRV bit = "0"

I_OL=1mA

V_OLT

0

—

0.1

2

V

TDRV bit = "1"

TDRV pin voltage=0

to 3V

TDRV pin

output leakage current

I_TDRV

-2

µA

TEMP pin

input voltage

TEMP input = 0.4 to

4.5V

V_TER

-20

—

20

mV

measurement error

Measurement resolution

Ta=-10 to 60°C

—

V_LSB

t_SCAN

t_SEL

—

4700/4095

—

mV

ms

4 temperature scan

measurement

Select measurement

1.9

0.8

2.3

1

2.7

1.2

Temperature

measurement time

⚫ AC Characteristics

V_DD= 10 to 72V, VREGU-GNDU = 5.1 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load

Item

Symbol

Condition

operating at 4 or

less-stage

Min.

Typ.

Max.

Unit

SPI communication speed

fck

100

—

500

kHz

configuration(Note1)

operating at 2 to 16

stage

SPI communication speed

(ID Automatic Setting)

fckid

500

—

650

kHz

configuration(Note1)

/CS-SCK setup time

SCK-/CS hold time

SCK "H" pulse width

SCK "L" pulse width

SCK-SDI setup time

SCK-SDI hold time

SCK-SDO output delay

time

t_CSS

t_CSH

t_WH

t_WL

1000

950

—

ns

950

t_DIS

t_DIH

200

t_DOD

t_CS

—

2

—

700

—

ns

µs

ns

/CS "H" pulse width

/CS-/CSO output delay

time

operating at 4 or

less-stage

t_PDCS

—

100

configuration(Note1)

SCK-SCKO output delay

time

t_PDCK

—

0

—

100

115

15

ns

SDI-SDOI output delay

time

t_PDDI

/CSO and SCKO output

delay time difference

SCKO and SDOI output

delay time difference

SDOI-SDO output delay

time

|t_PDCS-t_P

|

DCK

|t_PDDI-t_P

10

—

35

|

DCK

t_PDDO

115

Note1: This product is recommended to communicate on the same board for multi-stage series

connection. IC-IC transmission delay time is assumed to be less than 10ns.

RSPI=100Ω to 330Ω, RVREGU=100Ω to 330Ω, RGNDU=100Ω to 330Ω, CREGU=10nF to 1.0uF

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Timing diagram at data write

tCSS

tCS

/CS

tWH tWL

tCSH

SCK

tDIH

tDIS

SDI

SDO

/CSO

tDOD

Hi-Z

tPDCS

tPDCK

SCKO

SDOI

tPDDI

Timing diagram at multi-stage connection

/CS

SCKO

SDOI

SDOI=output mode

SDOI=Input mode

tPDDO

SDOI=output mode

Hi-Z

SDO

tPDDO

SDI

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V_DD= 10 to 72V, VREGU-GNDU = 5.1 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load.

Item

Symbol

t_PUP

Condition

Min.

6.0

Typ.

Max.

Unit

PUPI "H" pulse width

PUPI-PUPO

output delay time

Power-up waiting time

/INTI- /INTO

—

s

t_PDPO

t_PUW

—

20

—

5

10

—

1

ms

s

—

t_PDINT

output delay time

Power-up operation timing diagram

V_IHP(For the lowest IC. For upper ICs, PUPO of the lower IC is input)

PUPI

t_PUP

t_PDPO

/PUPO

PUPO

5.3V

VREG

0V

4.7V

VREF

0V

t_PUW

State

Waiting power-up stabilization

Power-down

Interrupt output timing diagram

/INTI

t_PDINT

/INTO

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◼ Functional Description

⚫ MCU Interface

The ML5239 is equipped with the SPI interface.

The SPI interface is enabled by setting the /CS pin to the "L" level. It imports the SDI pin data into the LSI

in synchronization with the SCK pin clock rise. It outputs the read data to the SDO pin in synchronization

with the SCK pin clock fall. The SPI interface is disabled by setting the /CS pin to the "H" level to return to

the initial state. Always set the /CS pin to the "H" level every time one data write/read operation completes.

/CS

SCK

SDI

Hi-Z

SDO

The communication format consists of the control register address, access mode/ID data, write data/read

data, and CRC code, all in 8 bits (1 byte) with MSB first.

Data write operation is performed in one byte.

One data read operation can read data from successive addresses.

Communication format at data write

Register

address

Access

mode

Write data CRC code

(8 bit) (8 bit)

Communication format at data read

CRC code

(8 bit)

Register

address

Access

mode

Number of Read data 1 Read data 2

data bytes

(8 bit)

Access mode/ID data

The following table shows the configuration.

7

6

5

4

3

2

1

0

Bit

name

RD/WR WR_ALL

—

ID3

ID2

ID1

ID0

The ID address of an IC in multi-stage connection is specified by ID0 to ID3 bits. Each ID at 16-stages

connection is shown in the following table.

Multi-stage

connection order

ID3 ID2 ID1 ID0

0

1

0

1

0

Lowest IC

2nd lowest IC

3rd lowest IC

:

1

0

1

0

1

14th lowest IC

15th lowest IC

16th lowest IC

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A data write operation can be performed for all the ICs in multi-stage connection using WR_ALL bit.

At read operation, the WR_ALL bit is ignored, and data is read from the specified IC.

WR_ALL

Accessed IC

0

1

IC specified using the ID0 to ID3 bits

All ICs in multi-stage connection

The access mode of read/write is selected using the RD/WR bit.

RD/WR

Access mode

Write

0

1

Read

Number of data bytes

The following table shows the configuration.

7

6

5

4

3

2

1

0

Bit

name

—

DB4

DB3

DB2

DB1

DB0

The number of bytes of read data is specified using the DB0 to DB4 bits. "Number of read data bytes - 1"

should be set. If only one byte is read, "0" should be specified. Up to 32 bytes can be read successively.

CRC calculation

This IC is equipped with the 8-bit CRC calculation circuit to detect any communication error, and it

appends a CRC (Cycle Redundancy Code) generated using a polynomial X⁸+X²+X+1 to each

communication data. It is calculated from all of the address to write/read data, and the result is generated in

MSB first. (It includes the empty bits 4 and 5 of the access mode/ID data and 5 to 7 of the number of data

bytes.) When the /CS pin is set to "H" level, the CRC calculation is initialized, and the initial value is set to

FF [h].

The data write operation is performed on the specified register only when the CRC computation result

matches the received CRC code. Otherwise, the data write operation is not performed. When a CRC error is

detected, the CRC error flag is set, allowing the interrupt signal to the external MCU to be output to the

/INTO pin. For details, refer to the INT_EN and INT_REQ registers of the control register.

The CRC computation is also performed for each transmit/receive data during data read operation to output

the result at the end of the read data. The external MCU can detect any communication error by comparing

the CRC computation result and the received CRC code.

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⚫ Control Register

The control register map is shown below.

* Note: The initial value of the INT_REQ register is value after software reset.

Initial

value

Address

Register name

R/W

Description

00H

01H

02H

03H

04H

05H

NOOP

RSTREQ

INT_EN

INT_REQ

PDACP

R/W

W

R/W

W

55H

00H

80H

00H *

00H

Register for user

Software reset request register

Interrupt enable register

Interrupt request register

Power-down code acceptor

Power-down control register

Cell voltage measurement control

register

POWER

R/W

00H

06H

07H

08H

MEAS_VCELL

MEAS_TEMP

MEAS_VREG

R/W

00H

Temperature sensor measurement

control register

VREG voltage measurement

control register

Open/short detection measurement

control register

Status register

Cell voltage measurement status

(lower eight cells)

09H

0AH

0BH

MEAS_VOPSH

STATUS

R/W

R

00H

STAT_VML

R

Cell voltage measurement status

(higher eight cells)

Temperature sensor measurement

status

0CH

0DH

0EH

0FH

STAT_VMH

STAT_TM

CBALL

R

00H

R

Cell balancing control register

(lower eight cells)

Cell balancing control register

(higher eight cells)

R/W

CBALH

10H

11H

12H

13H

14H

IDSEL

IDACP

IDREG

WDTACP

SETWDT

SELOUT

SETOUT

RSVD

R

W

R/W

W

R/W

R

00H

09H

00H

ID storing register

ID automatic setting code acceptor

ID automatic setting register

WDT setting acceptor

WDT setting register

15H

16H

Pin switch register

Pin output setting register

Reserved register

17H to 1FH

Cell 1 measurement result register

(lower byte)

Cell 1 measurement result register

(higher byte)

Cell 2 measurement result register

(lower byte)

Cell 2 measurement result register

(higher byte)

Cell 3 measurement result register

(lower byte)

Cell 3 measurement result register

(higher byte)

Cell 4 measurement result register

(lower byte)

Cell 4 measurement result register

(higher byte)

20H

21H

22H

23H

24H

25H

26H

27H

28H

VCELL1L

VCELL1H

VCELL2L

VCELL2H

VCELL3L

VCELL3H

VCELL4L

VCELL4H

VCELL5L

R

00H

Cell 5 measurement result register

(lower byte)

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Cell 5 measurement result register

(higher byte)

29H

Address

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

40H

41H

42H

43H

44H

VCELL5H

Register name

VCELL6L

VCELL6H

VCELL7L

VCELL7H

VCELL8L

VCELL8H

VCELL9L

VCELL9H

VCELL10L

VCELL10H

VCELL11L

VCELL11H

VCELL12L

VCELL12H

VCELL13L

VCELL13H

VCELL14L

VCELL14H

VCELL15L

VCELL15H

VCELL16L

VCELL16H

TEMP1L

R

R/W

R

00H

Initial

value

Description

Cell 6 measurement result register

(lower byte)

Cell 6 measurement result register

(higher byte)

Cell 7 measurement result register

(lower byte)

Cell 7 measurement result register

(higher byte)

Cell 8 measurement result register

(lower byte)

Cell 8 measurement result register

(higher byte)

Cell 9 measurement result register

(lower byte)

Cell 9 measurement result register

(higher byte)

00H

Cell 10 measurement result

register (lower byte)

Cell 10 measurement result

register (higher byte)

Cell 11 measurement result

register (lower byte)

Cell 11 measurement result

register (higher byte)

Cell 12 measurement result

register (lower byte)

Cell 12 measurement result

register (higher byte)

Cell 13 measurement result

register (lower byte)

Cell 13 measurement result

register (higher byte)

Cell 14 measurement result

register (lower byte)

Cell 14 measurement result

register (higher byte)

Cell 15 measurement result

register (lower byte)

Cell 15 measurement result

register (higher byte)

Cell 16 measurement result

register (lower byte)

Cell 16 measurement result

register (higher byte)

TEMP1 measurement result

register (lower byte)

TEMP1 measurement result

register (higher byte)

TEMP1H

TEMP2 measurement result

register (lower byte)

TEMP2 measurement result

register (higher byte)

TEMP3 measurement result

register (lower byte)

TEMP2L

TEMP2H

TEMP3L

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TEMP3 measurement result

45H

Address

46H

TEMP3H

Register name

TEMP4L

TEMP4H

VREGL

R

R/W

R

00H

register (higher byte)

Initial

value

Description

TEMP4 measurement result

register (lower byte)

TEMP4 measurement result

register (higher byte)

00H

47H

R

VREG voltage measurement result

register (lower byte)

VREG voltage measurement result

register (higher byte)

For test (Do not use. Operation is

not guaranteed if it is used.)

48H

R

49H

VREGH

R

Others

TEST

R/W

1. NOOP Register (Adrs = 00H)

7

6

5

4

3

2

1

0

Bit

name

R/W

Initial

value

NO7

R/W

0

NO6

R/W

1

NO5

NO4

NO3

R/W

0

NO2

R/W

1

NO1

R/W

0

NO0

R/W

1

R/W

0

R/W

1

No function is assigned to the NOOP register. Read/write access to this register does not change the

LSI state. The written data can be read as it is.

2. RSTREQ Register (Adrs = 01H)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

—

R

0

RST

W

Bit

name

R/W

Initial

value

0

The RSTREQ register requests a software reset.

Setting the RST bit to "1" generates a reset by software request.

All the registers other than IDREG are initialized by the software reset execution.

This is a write-only register. If you read it, 00H is read.

RST

0

1

Software reset

Reset is not performed (initial value)

Reset is performed

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3. INT_EN Register (Adrs = 02H)

7

6

5

4

3

2

EMVR

R/W

0

1

0

EMVC

R/W

0

Bit

name

R/W

Initial

value

EWDOV EVRGR EVRGD ECRC

EID

R/W

0

EMT

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

The INT_EN register sets whether or not to enable the interrupt signal output to the /INTO pin.

The EMVC bit sets whether or not to enable an interrupt on completion of cell voltage measurement.

Cell voltage measurement

EMVC

completion interrupt

0

1

Disabled (initial value)

Enabled

The EMT bit sets whether or not to enable an interrupt on completion of temperature sensor

measurement.

Temperature sensor

measurement completion interrupt

EMT

0

1

Disabled (initial value)

Enabled

The EMVR bit sets whether or not to enable an interrupt on completion of VREG voltage

measurement.

VREG voltage measurement

EMVR

completion interrupt

0

1

Disabled (initial value)

Enabled

The EID bit sets whether or not to enable an interrupt on completion of ID automatic setting.

ID automatic setting completion

EID

interrupt

0

1

Disabled (initial value)

Enabled

The ECRC bit sets whether or not to enable an interrupt when a CRC error is detected.

ECRC

CRC error interrupt

Disabled (initial value)

Enabled

0

1

The EVRGD bit sets whether or not to enable an interrupt when a VREG output voltage dropping is

detected.

VREG dropping

detection interrupt

EVRGD

0

1

Disabled (initial value)

Enabled

The EVRGR bit sets whether or not to enable an interrupt when a VREG output voltage return is

detected.

VREG return detection

EVRGR

interrupt

0

1

Disabled (initial value)

Enabled

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The EWDOV bit sets whether or not to enable an interrupt when WDT overflows.

EWDOV

WDT overflow interrupt

Prohibited

Enabled (initial value)

0

1

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4. INT_REQ Register (Adrs = 03H)

7

6

5

4

3

2

QMVR

R/W

0

1

0

QMVC

R/W

0

Bit

name

R/W

Initial

value

QWDOV QVRGR QVRGD QCRC

QID

R/W

0

QMT

R/W

0

R

0

R/W

0 *

R/W

0 *

R/W

0

The INT_REQ register contains interrupt request flags. Each request flag is set to "1" when an

interrupt is generated, regardless of the setting of INT_EN register. Only when an interrupt enabled by

the INT_EN register is generated, the "L" level is output to the /INTO pin.

An interrupt can be cleared by writing data "0". Writing data "1" is ignored. If you want to clear only

one interrupt, write "1" to the other bits. When all enabled interrupt request flags are cleared to "0", the

output to /INTO pin is set to the "Hi-Z" level.

* Note: The initial values of the QVRGR bit and the QVRGD bit are values after software reset.

Please initialize before use.

The QMVC bit indicates whether a cell voltage measurement completion interrupt has been generated.

Cell voltage measurement

QMVC

completion interrupt

0

1

Without interrupt (initial value)

An interrupt is generated

The QMT bit indicates whether a temperature sensor measurement completion interrupt has been

generated.

Temperature sensor

measurement completion interrupt

QMT

0

1

Without interrupt (initial value)

An interrupt is generated

The QMVR bit indicates whether a VREG voltage measurement completion interrupt has been

generated.

VREG voltage measurement

QMVR

completion interrupt

0

1

Without interrupt (initial value)

An interrupt is generated

The QID bit indicates whether an ID automatic setting completion interrupt has been generated.

ID automatic setting completion

QID

interrupt

0

1

Without interrupt (initial value)

An interrupt is generated

The QCRC bit indicates whether an interrupt has been generated when a CRC error is detected.

QCRC

CRC error interrupt

Without interrupt (initial value)

An interrupt is generated

0

1

The QVRGD bit indicates whether an interrupt has been generated when a VREG output voltage

dropping is detected.

If a dropping is detected during the VREG output voltage return state, an interrupt occurs, and it is

cleared during the VREG output voltage dropping detection state, then an interrupt does not occur

even in the dropping detection state.

VREG dropping detection

QVRGD

interrupt

0

1

Without interrupt (initial value *)

An interrupt is generated

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The QVRGR bit indicates whether an interrupt has been generated when a VREG output voltage return

is detected.

If a return from VREG output voltage dropping detection state is detected, an interrupt occurs.

QVRGR

VREG return detection interrupt

Without interrupt (initial value *)

An interrupt is generated

0

1

The QWDOV bit indicates whether an interrupt occurs when WDT overflows.

QWDOV

WDT overflow interrupt

Without interrupt (initial value)

An interrupt is generated

0

1

5. PDACP Register (Adrs = 04H)

7

6

5

4

3

2

1

0

Bit

name

R/W

Initial

value

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

The PDACP register enables writing to PDWN of the POWER register to avoid entering the

power-down mode accidentally. Writing 0x55 and 0xAA successively to this register enables setting

PDWN of POWER register to "1".

6. POWER Register (Adrs = 05H)

7

—

R

0

6

—

R

0

5

—

R

0

4

PDWN

W

3

—

R

0

2

—

R

0

1

—

R

0

—

R

0

Bit

name

R/W

Initial

value

0

The POWER register controls the power-down.

The PDWN bit is used to enable the power-down state.

PDWN

Power-down

Normal state (initial

value)

0

1

Power-down

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7. MEAS_VCELL Register (Adrs = 06H)

7

6

—

R

0

5

—

R

0

4

3

C3

R/W

0

2

C2

R/W

0

1

0

C0

R/W

0

Bit

name

R/W

Initial

value

MVC

R/W

0

SCV

R/W

0

C1

R/W

0

The MEAS_VCELL register controls the cell voltage measurement.

Use the SCV bit and the C0 to C3 bits to select the measurement mode and the battery cell(s) to be

measured.

SCV C3

C2

0

1

0

1

0

1

0

1

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Cell voltage measurement

Only cell 1 is measured

Only cell 2 is measured

Only cell 3 is measured

Only cell 4 is measured

Only cell 5 is measured

Only cell 6 is measured

Only cell 7 is measured

Only cell 8 is measured

Only cell 9 is measured

Only cell 10 is measured

Only cell 11 is measured

Only cell 12 is measured

Only cell 13 is measured

Only cell 14 is measured

Only cell 15 is measured

Only cell 16 is measured

0

1

0

1

0

1

Only cell 1 is measured

Cell 1 to cell 2 are measured in the scan mode

Cell 1 to cell 3 are measured in the scan mode

Cell 1 to cell 4 are measured in the scan mode

Cell 1 to cell 5 are measured in the scan mode

Cell 1 to cell 6 are measured in the scan mode

Cell 1 to cell 7 are measured in the scan mode

Cell 1 to cell 8 are measured in the scan mode

Cell 1 to cell 9 are measured in the scan mode

Cell 1 to cell 10 are measured in the scan mode

Cell 1 to cell 11 are measured in the scan mode

Cell 1 to cell 12 are measured in the scan mode

Cell 1 to cell 13 are measured in the scan mode

Cell 1 to cell 14 are measured in the scan mode

Cell 1 to cell 15 are measured in the scan mode

Cell 1 to cell 16 are measured in the scan mode

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The MVC bit is used to control the start/stop of cell voltage measurement and to verify the cell voltage

measurement completion status. The cell voltage measurement results are stored in the VCELLnL and

VCELLnH registers (20H to 3FH).

Read

Write

Cell voltage

measurement

Stop (initial value)

Start

Cell voltage

MVC

measurement

Completed/stopped

(initial value)

0

1

0

1

Measuring

It is possible to stop the cell voltage measurement by writing "0" to the MVC bit while measuring the

cell voltage. In that case, the measurement stops after the cell voltage measurement in progress is

completed. The read value of MVC bit remains "1" until the measurement stops, and it is reset to "0"

after the measurement stops.

Any change in the settings of the SCV bit and C3 to C0 bits is ignored during the measurement (while

the read value of MVC bit is "1").

Also, setting the MVC bit to "1" is ignored while measuring temperature sensor, VREG voltage, and

open/short detection.

8. MEAS_TEMP Register (Adrs = 07H)

7

MT

R/W

0

6

—

R

0

5

—

R

0

4

3

—

R

0

2

—

R

0

1

T1

R/W

0

T0

R/W

0

Bit

name

R/W

Initial

value

SCT

R/W

0

The MEAS_TEMP register controls the measurement of the temperature sensors (TEMP1 to TEMP4

pins input voltage).

The SCT, T0, and T1 bits select the temperature sensor measurement mode.

SCT

T1

T0

Temperature sensor measurement mode

TEMP1 pin input voltage measurement only

(initial value)

0

1

0

1

0

1

0

1

0

TEMP2 pin input voltage measurement only

TEMP3 pin input voltage measurement only

TEMP4 pin input voltage measurement only

TEMP1 pin input voltage measurement only

TEMP1 to TEMP2 pins input voltage scan

measurement

TEMP1 to TEMP3 pins input voltage scan

measurement

TEMP1 to TEMP4 pins input voltage scan

measurement

1

0

1

0

1

The MT bit is used to control the start/stop of temperature sensor measurement and to verify the

temperature sensor measurement completion status. The temperature sensor measurement results are

stored in the TEMPnL and TEMPnH registers (40H to 47H).

Write

Read

TEMP pin voltage

measurement

TEMP pin voltage

measurement

Completed/stopped

(initial value)

Measuring

MT

0

1

Stop (initial value)

Start

0

1

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It is possible to stop the temperature sensor measurement by writing "0" to the MT bit while measuring

the temperature sensor. In that case, the measurement stops after the temperature sensor measurement

in progress is completed. The read value of MT bit remains "1" until the measurement stops, and it is

reset to "0" after the measurement stops.

Any change in the settings of the SCT, T0, T1 bits is ignored during the measurement (while the read

value of the MT bit is "1").

Also, setting the MT bit to "1" is ignored while measuring cell voltage, VREG voltage, and open/short

detection.

9. MEAS_VREG Register (Adrs = 08H)

7

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

—

R

0

—

R

0

Bit

name

R/W

Initial

value

MVR

R/W

0

The MEAS_VREG register controls the VREG voltage measurement.

The voltage actually measured by this register is VREG×1/2 instead of VREG itself.

The MVR bit is used to control the start/stop of VREG voltage measurement and to verify the VREG

voltage measurement completion status. The VREG voltage measurement result is stored in the

VREGL and VREGH registers (48H to 49H).

Read

Write

VREG voltage

measurement

VREG voltage

measurement

Completed/stopped

(initial value)

Measuring

MVR

0

1

Disabled (initial value)

Start

0

1

Writing "0" to the MVR bit cannot stop the VREG voltage measurement while measuring the VREG

voltage.

Also, setting the MVR bit to "1" is ignored while measuring cell voltage, temperature sensor, and

open/short detection.

10. MEAS_VOPSH Register (Adrs = 09H)

7

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

—

R

0

—

R

0

Bit

name

R/W

Initial

value

MOS

R/W

0

The MEAS_VOPSH register controls measuring the open/short detection of the cell voltage

measurement pin.

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The MOS bit is used to control the open/short detection measurement start/stop of cell voltage

measurement pin and to verify the cell voltage measurement completion status. The cell voltage

measurement results are stored in the VCELLnL and VCELLnH registers (20H to 3FH).

Read

Write

Open/short detection

measurement

Open/short detection

measurement

Completed/stopped (initial

value)

MOS

0

1

Stop (initial value)

Start

0

1

Measuring

It is possible to stop the detection measurement by writing "0" to the MOS bit while measuring

open/short detection of cell voltage measurement pin. In that case, the measurement stops after the cell

voltage measurement in progress is completed. The read value of MOS bit remains "1" until the

measurement stops, and it is reset to "0" after the measurement stops.

Setting the MOS bit to "1" is ignored during the cell voltage measurement, temperature sensor

measurement, and VREG voltage measurement.

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11. STATUS Register (Adrs = 0AH)

7

—

R

0

6

5

4

3

MOS

R

2

MVR

R

1

0

MVC

R

Bit

name

R/W

Initial

value

VRGD CBALH CBALL

MT

R

0

R

0

R

0

The STATUS register indicates various status information. Writing to this register is ignored.

The MVC bit indicates the cell voltage measurement state. This is the same as the MVC bit of the

MEAS_VCELL register.

Cell voltage measuring

MVC

state

Measuring completed

0

(initial value)

1

Measuring

The MT bit indicates the temperature sensor measurement state. This is the same as the MT bit of the

MEAS_TEMP register.

Temperature sensor

MT

measurement

Measuring completed

0

(initial value)

1

Measuring

The MVR bit indicates the VREG voltage measurement state. This is the same as the MVR bit of the

MEAS_VREG register.

MVR

VREG measurement

Measuring completed

(initial value)

0

1

Measuring

The MOS bit indicates the open/short detection measurement state of the cell voltage measurement pin.

This is the same as the MOS bit of the MEAS_VOPSH register.

Open/short detection

measurement state

MOS

Measuring completed (initial

0

value)

1

Measuring

The CBALL bit indicates the CB pin output status of the lower eight cells.

CBALL

CB1 to CB8 pin status

All outputs at Vn-1 pin (initial value)

Any outputs at Vn pin

0

1

The CBALH bit indicates the CB pin output status of the higher eight cells.

CBALH

CB9 to CB16 pin status

All outputs at Vn-1 pin (initial value)

Any outputs at Vn pin

0

1

The VRGD bit indicates the VREG output voltage dropping detection state.

VREG output voltage dropping

VRGD

detection state

0

1

Not detecting dropping (initial value)

Detecting dropping

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12. STAT_VML Register (Adrs = 0BH)

7

VC8

R

6

VC7

R

5

VC6

R

4

VC5

R

3

VC4

R

2

VC3

R

1

0

VC1

R

Bit

name

R/W

VC2

R

Initial

value

0

The STAT_VML register indicates the cell voltage measurement state and the open/short detection

measurement state of the lower eight cells.

If the cell voltage measurement is started with the MVC bit of the MEAS_VCELL register set to "1",

the VC1 to VC8 bits are reset to "0", and the bits corresponding to measured cells are reset to "1". The

progress of the cell voltage measurement can be checked by reading this register.

If open/short detection measurement of cell voltage measurement pin is started with the MOS bit of the

MEAS_VOPSH register set to "1", the VC1 to VC8 bits are reset to "0", and the bits corresponding to

measured cells are reset to "1". The progress of the open/short detection measurement can be checked

by reading this register.

The VC1 to VC8 bits indicate the cell voltage measurement completion state.

VCn

Cell voltage measuring state

During measurement or not to be measured

(initial value)

0

1

Measurement completed

13. STAT_VMH Register (Adrs = 0CH)

7

VC16

R

6

VC15

R

5

VC14

R

4

VC13

R

3

VC12

R

2

VC11

R

1

VC10

R

0

VC9

R

Bit

name

R/W

Initial

value

0

The STAT_VMH register indicates the cell voltage measurement state and the open/short detection

measurement state of the higher eight cells.

If the cell voltage measurement is started with the MVC bit of the MEAS_VCELL register set to "1",

the VC9 to VC16 bits are reset to "0", and the bits corresponding to measured cells are reset to "1".

The progress of the cell voltage measurement can be checked by reading this register.

If open/short detection measurement of cell voltage measurement pin is started with the MOS bit of the

MEAS_VOPSH register set to "1", the VC9 to VC16 bits are reset to "0", and the bits corresponding to

measured cells are reset to "1". The progress of the open/short detection measurement can be checked

by reading this register.

The VC9 to VC16 bits indicate the cell voltage measurement completion state.

VCn

Cell voltage measuring state

During measurement or not to be measured

(initial value)

0

1

Measurement completed

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14. STAT_TM Register (Adrs = 0DH)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

TM4

R

2

TM3

R

1

0

TM1

R

Bit

name

R/W

Initial

value

TM2

R

0

The STAT_TM register indicates the temperature sensor measurement state.

If the temperature sensor measurement is started with the MT bit of the MEAS_TEMP register set to

"1", the TM1 to TM4 bits are reset to "0", and the bits corresponding to measured pins are reset to "1".

The progress of the temperature sensor measurement can be checked by reading this register.

The TM1 to TM4 bits indicate the temperature sensor measurement completion state.

TMn

Temperature sensor measurement

During measurement or not to be measured

(initial value)

0

1

Measurement completed

15. CBALL Register (Adrs = 0EH)

7

6

5

4

3

2

1

0

Bit

name

R/W

Initial

value

SW8

R/W

0

SW7

R/W

0

SW6

R/W

0

SW5

R/W

0

SW4

R/W

0

SW3

R/W

0

SW2

R/W

0

SW1

R/W

0

The CBALL register sets the CBn pin output of the lower eight cells.

Use the SW1 to SW8 bits to set each CBn pin output. Multiple bits can be set to "1".

SW8

0

SW7

0

SW6

0

SW5

0

SW4

0

SW3

0

SW2

0

SW1

0

CB1 to CB8 pin status

CBn = Vn-1 (initial value)

CB1 pin = V1 pin

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Other CBn pin = Vn-1

CB2 pin = V2 pin

Other CBn pin = Vn-1

CB3 pin = V3 pin

Other CBn pin = Vn-1

CB4 pin = V4 pin

Other CBn pin = Vn-1

CB5 pin = V5 pin

Other CBn pin = Vn-1

CB6 pin = V6 pin

Other CBn pin = Vn-1

CB7 pin = V7 pin

Other CBn pin = Vn-1

CB8 pin = V8 pin

Other CBn pin = Vn-1

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16. CBALH Register (Adrs = 0FH)

7

SW16

R/W

0

6

SW15

R/W

0

5

SW14

R/W

0

4

SW13

R/W

0

3

SW12

R/W

0

2

SW11

R/W

0

1

0

Bit

name

R/W

Initial

value

SW10

R/W

0

SW9

R/W

0

The CBALH register sets the CBn pin output of the higher eight cells.

Use the SW9 to SW16 bits to set each CBn pin output. Multiple bits can be set to "1".

SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9 CB9 to CB16 pin status

0

CBn = Vn-1 (initial value)

CB9 pin = V9 pin

0

1

Other CBn pin = Vn-1

CB10 pin = V10 pin

Other CBn pin = Vn-1

CB11 pin = V11 pin

Other CBn pin = Vn-1

CB12 pin = V12 pin

Other CBn pin = Vn-1

CB13 pin = V13 pin

Other CBn pin = Vn-1

CB14 pin = V14 pin

Other CBn pin = Vn-1

CB15 pin = V15 pin

Other CBn pin = Vn-1

CB16 pin = V16 pin

Other CBn pin = Vn-1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

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17. IDSEL Register (Adrs = 10H)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

0

Bit

name

R/W

Initial

value

—

R

0

ID

R

status

The IDSEL register stores the state (input level) of the ID pin.

18. IDACP Register (Adrs = 11H)

7

6

5

4

3

2

1

0

Bit

name

R/W

Initial

value

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

The IDACP register allows writing to IDREG in order to prevent IDREG from being accidentally

written. Writing 0x5A to this register enables the writing operation to IDREG.

19. IDREG Register (Adrs = 12H)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

ID3

R/W

0

2

ID2

R/W

0

1

ID1

R/W

0

ID0

R/W

0

Bit

name

R/W

Initial

value

The IDREG register stores the ID assignment of each IC in multi-stage connection.

The IDs which are automatically set are as follows. For instructions on configuring automatic setting,

refer to "ID Automatic Setting Function".

Multi-stage

ID3 ID2 ID1 ID0

connection

order

0

1

0

1

0

Lowest IC

2nd lowest IC

3rd lowest IC

:

1

0

1

0

1

14th lowest IC

15th lowest IC

16th lowest IC

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20. WDTACP Register (Adrs = 13H)

7

6

5

4

3

2

1

0

Bit

name

R/W

Initial

value

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

—

W

0

The WDTACP register allows writing to SETWDT in order to prevent SETWDT from being

accidentally written. Writing 0xA5 to this register enables the writing operation to SETWDT.

21. SETWDT Register (Adrs = 14H)

7

ENWD

R/W

0

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

WDT1

R/W

0

WDT0

R/W

0

Bit

name

R/W

Initial

value

The SETWDT register sets the watchdog timer run/stop and the overflow period.

The WDT0 and WDT1 bits set the overflow period.

WDT1

WDT0

Overflow period (Typ)

1 second (initial value)

2 seconds

0

1

0

1

0

1

4 seconds

8 seconds

The ENWD bit controls the run/stop of the watchdog timer.

ENWD WDT operation state

0

1

Run (initial value)

Stop

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22. SELOUT Register (Adrs = 15H)

7

STO4

R/W

0

6

STO3

R/W

0

5

STO2

R/W

0

4

STO1

R/W

0

3

—

R

0

2

—

R

0

1

0

—

R

0

Bit

name

R/W

Initial

value

—

R

0

The SELOUT register switches the thermistor connection pin for temperature measurement to the

general-purpose output.

The STO1 to STO4 bits set the TEMPn pin status.

STOn

TEMPn pin status

Input for temperature sensor measurement

(initial value)

0

1

General-purpose output

23. SETOUT Register (Adrs = 16H)

7

6

5

4

3

2

—

R

0

1

—

R

0

TDRV

R/W

1

Bit

name

R/W

Initial

value

TO4

R/W

0

TO3

R/W

0

TO2

R/W

0

TO1

R/W

0

GPO

R/W

1

The SETOUT register sets the output level of the output pin.

The TDRV bit sets the TDRV pin output status.

TDRV

TDRV pin output status

L output

0

1

HiZ (initial value)

The GPO bit sets the GPOUT pin output status.

GPO

0

1

GPOUT pin output status

L output

HiZ (initial value)

The TO1 to TO4 bits set the TEMPn pin output status.

TOn

0

1

TEMPn pin output status

L output (initial value)

HOutput

24. RSVD Register (Adrs = 17H to 1FH)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

—

R

0

2

—

R

0

1

—

R

0

—

R

0

Bit

name

R/W

Initial

value

The RSVD register is a reserved register.

The data write is disabled, and the read data is 00H.

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25. VCELLnL Register (Adrs = even addresses from 20H to 3FH)

7

VAD7

R

6

VAD6

R

5

VAD5

R

4

VAD4

R

3

VAD3

R

2

VAD2

R

1

0

VAD0

R

Bit

name

R/W

Initial

value

VAD1

R

0

The VCELLnL register (n = 1 to 16) stores the lower byte data of the A/D conversion result and

open/short detection measurement result of the cell voltages.

26. VCELLnH Register (Adrs = odd addresses from 20H to 3FH)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

2

1

VAD9

R

0

VAD8

R

Bit

name

R/W

Initial

value

VAD11 VAD10

R

0

R

0

The VCELLnH register (n = 1 to 16) stores the high-order 4-bit data of the A/D conversion result and

open/short detection measurement result of the cell voltages.

27. TEMPnL Register (Adrs = even addresses from 40H to 47H)

7

TAD7

R

6

TAD6

R

5

TAD5

R

4

TAD4

R

3

TAD3

R

2

TAD2

R

1

TAD1

R

0

TAD0

R

Bit

name

R/W

Initial

value

0

The TEMPnL register (n = 1 to 4) stores the lower byte data of the A/D conversion result of the

TEMP1 to TEMP4 pins.

28. TEMPnH Register (Adrs = odd addresses from 40H to 47H)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

2

1

TAD9

R

0

TAD8

R

Bit

name

R/W

Initial

value

TAD11 TAD10

R

0

R

0

The TEMPnH register (n = 1 to 4) stores the high-order 4-bit data of the A/D conversion result of the

TEMP1 to TEMP4 pins.

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29. VREGL Register (Adrs = 48H)

7

RAD7

R

6

RAD6

R

5

RAD5

R

4

RAD4

R

3

RAD3

R

2

RAD2

R

1

0

RAD0

R

Bit

name

R/W

Initial

value

RAD1

R

0

The VREGL register stores the lower byte data of the A/D conversion result of VREG×1/2 voltage.

30. VREGH Register (Adrs = 49H)

7

—

R

0

6

—

R

0

5

—

R

0

4

—

R

0

3

2

1

RAD9

R

0

RAD8

R

Bit

name

R/W

Initial

value

RAD11 RAD10

R

0

R

0

The VREGH register stores the high-order 4-bit data of the A/D conversion result of VREG×1/2

voltage.

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⚫ Operation Mode

This IC has the following operation modes.

Normal operation

mode

All the functions operate.

Power-down

mode

All the circuits other than power-up are stopped to reduce the current

consumption.

The transition conditions to each mode are shown in the following figure.

PUPI signal "H" pulse input

Power-down

mode

Normal

mode

Turn on sequence

Power-down transition

instruction (PDWN = 1 write*)

or

WDT overflow

or

VREG reduction

* To write 1 to PDWN, PDACP is required to enable writing in advance.

Transition from power-down mode to normal mode needs time for internal circuits to stabilize after

inputting "H" pulse to PUPI pin. The waiting time before preparing for SPI communication is as follows:

SPI instruction

Waiting time

Other than voltage measurement

(various settings, etc.)

t_PDPO×number of multi-stage stages

Voltage measurement (cell, temperature t_PUW+t_PDPO×(number of multi-stage stages - 1)

sensor, VREG)

If the voltage measurement is performed during power-up stabilization (t_PUWinterval), the measurement

error cannot be guaranteed.

For multi-stage connection, ID assignment to each IC is needed after transition to the normal mode.

Power-up operation (starting SPI communication) timing diagram

V_IHP(For the lowest IC. For upper ICs, PUPO of the lower IC is input)

PUPI

t_PUP

t_PDPO

/PUPO

PUPO

5.3V

VREG

0V

4.7V

VREF

0V

t_PUW

Initial setting

Command

Any

Command

SPI

Communication

enabled

Voltage measurement

enabled

State

Waiting power-up stabilization

Power-down

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⚫ ID Automatic Setting Function

ML5239 has a function to assign each IC with ID automatically at multi-stage connection.

After internal circuit stabilization wait time at power-on, the ID automatic setting register IDREG of all ICs

in multi-stage connection has an initial value 0x00. Write 0x5A to the ID automatic setting code acceptor

IDACP with ID = WR_ALL using SPI communication to enable writing to the ID automatic setting register

IDREG.

Then, write "number of multi-stage stages -1" to the ID automatic setting register IDREG with ID =

WR_ALL to automatically set IDs in turns from the 2nd lowest IC, as shown in the following table.

Multi-stage

ID3 ID2 ID1 ID0

connection order

0

1

0

1

0

Lowest IC

2nd lowest IC

3rd lowest IC

:

1

0

1

0

1

14th lowest IC

15th lowest IC

16th lowest IC

The ID automatic setting takes about 170μs per stage of multi-stage connection after writing any value to

IDREG. Do not execute any SPI communication from MCU during ID automatic setting. For automatic ID

setting, each higher ML5239 ID are set by the lowest ML5239, sequentially. And the MCU clock is not

used but the SCKO from the lowest ML5239 is used.

The interrupt signal can be output to the external MCU on the /INTO pin on completion of the ID automatic

setting. To output the interrupt signal, specify ID=”0” and the EID bit of the INT_EN register needs to be

used to enable ID automatic setting completion interrupt before ID automatic setting. For details, refer to

the INT_EN and INT_REQ registers of the control register.

⚫ Watchdog Timer Function

ML5239 has a watchdog timer function which detects failure when an SPI communication is not performed

for certain period of time.

To clear the counter of WDT (for IC to recognize the SPI communication operation), 16CLK of SCK clock

should be input with /CS="L" state.

⚫ Power-on/Power-off Sequence

Battery cells can be connected in any order, but we recommend that you connect the GND and VDD pins

first, then connect from lower cells.

Note that the initial state is the power-down mode after power-on. Write "H" pulse to the PUPI pin to power

up. For details, please refer to "Operation Mode".

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⚫ Cell Voltage Measurement

There are two modes of the cell voltage measurement method. The select measurement measures the

voltage of one selected cell, and the scan measurement continuously measures the voltages of selected

multiple cells.

The MEAS_VCELL register is used to select the cell voltage measurement mode and set the measurement.

For details, see the MEAS_VCELL register section.

The following timing diagrams show the cell voltage measurement operation for both measurement modes.

Select measurement mode operation timing diagram (measuring the lowest cell 1 and the cell 16)

MEAS_VCELL

INT_REQ

MEAS_VCELL

SPI

MEAS_VCELL

MVC bit

STAT_MVL/H

VC1 bit

VC16 bit

VCELL1L/H

VCELL16L/H

/INTO

Hi-Z

Standby

Cell 16

measurement

Cell 1

measurement

Measurement

circuit state

Standby

Cell voltage measurement completion

interrupt enabled

Cell voltage measurement completion

interrupt cleared

Scan measurement mode operation timing diagram (cells 1 and 2 measured)

MEAS_VCELL

INT_REQ

MEAS_VCELL

SPI

MEAS_VCELL

MVC bit

STAT_MVH

VC1 bit

VC2-bit

VCELL1L/H

VCELL2L/H

/INTO

Hi-Z

Standby

Cell 2

measure-

ment

Cell 1

measurement

Measurement

circuit state

Cell

measure-

ment

Cell voltage measurement completion

interrupt enabled

Cell voltage measurement

completion

interrupt cleared

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⚫ Temperature Sensor Input Voltage Measurement

There are two modes of the temperature sensor input voltage measurement method. The select measurement

mode measures the voltage of one selected temperature sensor input, and the scan measurement mode

continuously measures the voltages of multiple temperature sensor inputs.

The MEAS_TEMP register is used to select the temperature sensor measurement mode and set the

measurement.

For temperature sensor measurement, output 0V to the TDRV pin, and wait until the TEMP1 to TEMP4 pin

input voltages stabilize before starting the measurement. For details, refer to the SETOUT and

MEAS_TEMP registers. After the temperature sensor measurement completes, we recommend that you set

the TDRV pin to the Hi-Z state for reduced current consumption and minimized VREG output voltage

drop.

The following timing diagrams show the temperature sensor input voltage measurement operation for both

measurement modes.

Select measurement mode operation timing diagram (TEMP1 pin input measured)

SETOUT

MEAS_TEMP

SETOUT

INT_REQ

SPI

SETOUT

TDRV bit =

MEAS_TEMP

MT bit

VREG

TDRV pin

0V

TEMP1 pin

TEMP1L/H

/INTO

Hi-Z

Standby

Stabilization

time

Measurement

circuit state

TEMP1

measurem

ent

TDRV pin

=Hi-Z output

Temperature sensor

measurement completion

interrupt enabled

TDRV pin

=0V output

Temperature sensor

measurement completion

interrupt cleared

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Scan measurement mode operation timing diagram (TEMP1 and TEMP2 measured)

SETOUT

MEAS_TEMP

INT_REQ

SETOUT

SPI

SETOUT

TDRV bit =

MEAS_TEMP

MT bit

VREG

TDRV pin

0V

TEMP1 and

TEMP2 pins

TEMP1L/H

TEMP2L/H

/INTO

Hi-Z

Measurement

circuit state

Standby

Stabilization

time

TEMP1

measurem

ent

TEMP2

measurem

ent

TDRV pin

=Hi-Z output

Temperature sensor

measurement completion

interrupt enabled

TDRV pin

=0V output

Temperature sensor measurement completion

interrupt cleared

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⚫ VREG Voltage Measurement

The VREG voltage measurement is performed using the MEAS_VREG register. For details, see the

MEAS_VREG register section.

The following timing diagram shows the VREG voltage measurement operation.

VREG voltage measurement operation timing diagram

MEAS_VREG

INT_REQ

SPI

MEAS_VREG

MVR bit

VREGL/H

/INTO

Hi-Z

Standby

VREG

measurem

ent

Measurement

circuit state

VREG voltage measurement completion

interrupt enabled

VREG voltage measurement

completion

interrupt cleared

⚫ Cell Balancing

Use an external Nch-FET to configure the cell balancing circuit shown in the following figure.

For cell balancing, a 100k (typ) resistor is connected between the CBn and Vn pins by setting the SWn bit

of the CBALL and CBALH registers to "1". If the SWn bit is "0", 100k (typ) resistor is connected

between CBn pin and Vn-1 pin.

ML5239

R_CEL

C_CEL

Vn

SWn

R_d

50k

CBn

R_CB

50k

R_CEL

Vn-1

C_CEL

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⚫ Interrupt Signal Output

This function outputs interrupt signals from the /INTO pin to notify the external MCU of measurement

completion and error occurrence.

The INT_EN register is used to enable various interrupts, and the INT_REQ register is read/written to

check and clear generated interrupts.

The following table shows interrupt sources, generation conditions, and states after generation.

Interrupt source

Cell voltage

measurement

completion

Interrupt generation condition

The MVC bit of the MEAS_VCELL

register is set to "1", then the cell voltage

measurement is completed.

State after interrupt

The measurement result

is stored in the

VCELLnL/H register.

Temperature

sensor input

Measurement

completed

The MT bit of the MEAS_TEMP register is

set to "1", then the temperature sensor

measurement is completed.

The measurement result

is stored in the TEMPnL/H

register.

VREG voltage

measurement

completed

The MVR bit of the MEAS_VREG register

is set to "1", then the VREG voltage

measurement is completed.

The measurement result

is stored in the VREGL/H

register.

The received SPI

communication data is

disabled.

The received CRC code does not match

the calculation result.

CRC error

All ICs enter the Standby

(instruction acceptable)

state.

ID automatic

setting completed

ID automatic setting is completed.

VREG output

voltage

dropping

detection

It is detected that the VREG pin output

voltage is equal to or less than 4.3V (typ).

Various measurement

results are not valid.

It is detected that the VREG pin output

voltage is equal to or more than 4.85V

(typ).

An interrupt does not occur during VREG

output rising at power-up.

VREG output

voltage

return detection

Various measurements

can be performed

successfully.

WDT

An overflow occurs.

IC powers down.

* When VREG is less than the recommended operation range, an interrupt occurs. In addition, when it

drops nearly to a level where internal IC circuits cannot operate normally, it enters the power-down.

⚫ Cell Connection Method

We recommend the following connections when the number of connected cells is 15 or less.

Conne

V1 to V5

pins

cted

cells

15

14

13

12

11

10

9

8

7

6

5

V16 pin

V15 pin

V14 pin

V13 pin

V12 pin

V11 pin

V10 pin

V9 pin

V8 pin

V7 pin

V6 pin

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

Cell

V_TOP

* V_TOP: Same potential as highest connected battery V pin of the IC

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⚫ Multi-stage Connection Method

ML5239 allows up to 16 ICs to be used in multi-stage connection.

In multi-stage connection, ICs should be connected as shown in the following figure. Refer to an

application circuit example for more connection details.

Set the ID pin of the lowest IC to "L" level. Set the ID pin of all the higher ICs to "H" level.

For the SDOI pin and SDI pin of the higher ICs, the I/O mode automatically switches according to

read/write operation.

Use an actual application to check the SPI communication speed, which is limited by IC-IC wiring parasitic

capacitance, etc.

GNDU

VDD

VREGU

/CSO

Open

：

PUPO

/PUPO

SCKO

SDOI

/INTI

VREG4

VREG

/CS

VREG4

ID

SCK

SDI

/PUPI

PUPI

GND

SDO

/INTO

GNDU

VDD

VREGU

/CSO

PUPO

/PUPO

SCKO

SDOI

/INTI

VREG3

VREG

/CS

VREG3

ID

SCK

SDI

/PUPI

PUPI

GND

SDO

/INTO

GNDU

VDD

VREGU

/CSO

PUPO

/PUPO

SCKO

SDOI

/INTI

VREG2

VREG

/CS

VREG2

ID

SCK

SDI

/PUPI

PUPI

GND

SDO

/INTO

GNDU

VDD

VREGU

/CSO

PUPO

/PUPO

SCKO

SDOI

/INTI

VREG

/CS

ID

SCK

SDI

SCK

SOUT

SIN

/PUPI

PUPI

GND

SDO

/INTO

/INT

Power-Up

GND

41/47

FEDL5239-05

ML5239

⚫ Unused Pins Treatment

The following table shows how to handle unused pins.

Unused pins

V6 to V16

Recommended treatment

Same potential as highest connected battery V

pin of the IC

CB1 to CB16

TDRV

Open

Left open or connected to the GND pin

TEMP1 to TEMP4 Connected to the GND pin

/INTO

PUPO

/PUPO

/INTI

SDOI

SCKO

/CSO

Left open or connected to the GND pin

Open

42/47

FEDL5239-05

ML5239

Unconnected pins are open.

Refer on page 11 about PUPI input.

◼ Application circuit example (16 cells with two-stage connection)

R_VDD

R_CEL

C_VDD

C_CEL

PACK(+)

C_HV

R_CB

C_C

C_REF

C_REG

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CB13

V12

CB12

V11

CB11

V10

CB10

V9

TEST2

TEST1

VREGU

/CSO

SCKO

SDOI

3

4

5

6

7

/INTI

8

GNDU

VREF

9

ML5239

CB9

V8

10

11

12

13

14

15

16

VREG

CB8

V7

TEMP4

TEMP3

TEMP2

TEMP1

TDRV

GPOUT

CB7

V6

CB6

V5

R_PUP

R_VDD

R_CEL

R_CB

C_VDD

C_CEL

R_GNDU

R_VREGU

R_SPI

C_HV

C_C

C_REF

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CB13

V12

CB12

V11

CB11

V10

CB10

V9

TEST2

TEST1

VREGU

/CSO

SCKO

SDOI

3

4

5

6

C_REGU

7

/INTI

8

GNDU

VREF

9

ML5239

CB9

V8

10

11

12

13

14

15

16

VREG

CB8

V7

TEMP4

TEMP3

TEMP2

TEMP1

TDRV

GPOUT

CB7

V6

CB6

V5

C_REG

Power supply

MCU

GND

PACK(-)

43/47

FEDL5239-05

ML5239

◼ Application circuit example (12 cells without multi-stage connection) _{Unconnected pins are open.}

Refer on page 11 about PUPI input.

R_VDD

C_VDD

PACK(+)

C_HV

C_C

C_REF

R_CEL

R_CB

C_CEL

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CB13

V12

CB12

V11

CB11

V10

CB10

V9

TEST2

TEST1

VREGU

/CSO

SCKO

SDOI

3

4

5

6

7

/INTI

8

GNDU

VREF

9

ML5239

CB9

V8

10

11

12

13

14

15

16

VREG

CB8

V7

TEMP4

TEMP3

TEMP2

TEMP1

TDRV

GPOUT

CB7

V6

CB6

V5

C_REG

Power supply

MCU

GND

PACK(-)

⚫ Recommended Values for Externally Connected Components

Recommended value

Component

Withstanding

pressure[V]

Min

Typ

Max

R_VDD

C_VDD

R_CEL

C_CEL

R_CB

—

100

—

100

1.0F

100

0.1F

1k

—

10nF

100

500

330

—

1k

—

1.0F

330

1k

100

—

10

—

C_C

C_HV

0.22F

1.0F

0.1F

—

C_REF

C_REG

C_REGU

R_VREGU

R_GNDU

R_SPI

—

R_PUP

(Note) Required tolerance are ΔR±1%, ΔC±20%.

These circuit examples and recommended values of external parts do not guarantee the operation under

all operation conditions. The product should be evaluated using the actual application to select an

optimal circuit configuration and part constants.

44/47

FEDL5239-05

ML5239

◼ Package Dimensions

Remarks for surface mount type package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in

storage. Therefore, before you perform reflow mounting, contact ROHM sales representative for the product

name, package name, pin number, package code and desired mounting conditions (reflow method, temperature

and times).

45/47

FEDL5239-05

ML5239

◼ Revision History

Document No.

Issue date

Pages

Revision description

Initial release

Before

After

FEDL5239-01

FEDL5239-02

March 12, 2015

March 29, 2019

-

9

-

9

Change AC Characteristics

35

Add automatic ID setting description.

Change

Recommended

values

for

44

6

44

6

externally connected components.

Change Absolute maximum ratings of

PUPI, /PUPI input voltage

FEDL5239-03

FEDL5239-04

FEDL5239-05

August 8, 2019

March 23, 2020

Dec. 1, 2020

Change Electrical Characteristics of VHV

L-limit 3.8V to 3.3V

Changed Company name

7

-

47

Changed “Notes”

46/47

FEDL5239-05

ML5239

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,

application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating

conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any

malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products

outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such

usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.

Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS

Technology Products, please take safety at your own risk measures such as complying with the derating

characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe

procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate

the standard operation of semiconductor products and application examples. You are fully responsible for the

incorporation or any other use of the circuits, software, and information in the design of your product or system.

And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS

Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising

from the use of these circuits, software, and other related information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS

Technology or any third party with respect to LAPIS Technology Products or the information contained in this

document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application

examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute,

concerning such rights owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer

systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our

Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a

LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,

trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all

liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not

intended by us. Do not use our Products in applications requiring extremely high reliability, such as aerospace

equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document.

However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall

have no responsibility for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS

Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance

with any applicable laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by

the procedures and provisions stipulated in all applicable export laws and regulations, including without

limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this

document or LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

47/47


型号：	ML5239
厂家：	ROHM
描述：	电池电压和温度测量多级连接MCU接口：SPI电池均衡开关驱动引脚电池开关驱动
文件：	总47页 (文件大小：2179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML5239 [ROHM]

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