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K3N3V1000D-GC100 [SAMSUNG]

MASK ROM, 256KX16, 100ns, CMOS, PDSO40, 0.525 INCH, SOP-40;
K3N3V1000D-GC100
型号： K3N3V1000D-GC100
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 256KX16, 100ns, CMOS, PDSO40, 0.525 INCH, SOP-40

有原始数据的样本ROM 光电二极管 内存集成电路
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K3N3V(U)1000D-D(G)C  
CMOS MASK ROM  
4M-Bit (512Kx8 /256Kx16) CMOS MASK ROM  
GENERAL DESCRIPTION  
FEATURES  
· Switchable orginization  
524,288 x 8(byte mode)  
262,144 x 16(word mode)  
· Fast access time  
3.3V Operation : 100ns(Max.)  
3.0V Operation : 120ns(Max.)  
· Supply voltage : single +3.0V/ single +3.3V  
· Current consumption  
The K3N3V(U)1000D-D(G)C is a fully static mask programma-  
ble ROM fabricated using silicon gate CMOS process technol-  
ogy, and is organized either as 524,288 x 8bit(byte mode) or as  
262,144  
x 16bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
Operating : 25mA(Max.)  
Standby : 30mA(Max.)  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
-. K3N3V(U)1000D-DC : 40-DIP-600  
-. K3N3V(U)1000D-GC : 40-SOP-525  
The K3N3V(U)1000D-DC is packaged in a 40-DIP and the  
K3N3V(U)1000D-GC is a 40-SOP.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A17  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
(262,144x16/  
524,288x8)  
A8  
A9  
A17  
A7  
40  
39  
38  
1
DECODER  
2
A6  
A10  
3
4
A5  
A11  
A12  
A13  
37  
36  
35  
34  
Y
A4  
SENSE AMP.  
5
BUFFERS  
AND  
A3  
6
DATA OUT  
BUFFERS  
A2  
7
A14  
DECODER  
A0  
A1  
8
33 A15  
A0  
A16  
32  
9
A-1  
CE  
VSS  
BHE  
VSS  
10  
11  
31  
30  
29  
28  
27  
26  
DIP  
&
SOP  
. . .  
Q15/A-1  
Q7  
OE 12  
CE  
Q0  
Q8  
13  
14  
15  
16  
17  
18  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
Q14  
OE  
Q1  
Q6  
BHE  
Q9  
25 Q13  
24 Q5  
Q2  
Q10  
Q12  
Q4  
23  
22  
21  
Pin Name  
A0 - A17  
Pin Function  
Q3 19  
Q11  
Address Inputs  
Data Outputs  
20  
VCC  
Q0 - Q14  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
K3N3V(U)1000D-D(G)C  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
OE  
VCC  
VSS  
Ground  
K3N3V(U)1000D-D(G)C  
CMOS MASK ROM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
VIN  
Rating  
Unit  
Voltage on Any Pin Relative to VSS  
Temperature Under Bias  
Storage Temperature  
-0.3 to +4.5  
-10 to +85  
-55 to +150  
V
TBIAS  
TSTG  
°C  
°C  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be\ restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)  
Item  
Min  
2.7/3.0  
0
Symbol  
Typ  
3.0/3.3  
0
Max  
3.3/3.6  
0
Unit  
V
Supply Voltage  
VCC  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
25  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
V
VCC=3.3±0.3V  
VCC=3.0±0.3V  
-
Cycle=5MHz, all outputs open, CE=OE=VIL,  
VIN=0.45V to 2.4V (AC Test Condition)  
Operating Current  
ICC  
-
20  
Standby Current(TTL)  
ISB1  
ISB2  
ILI  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
VIN=0 to VCC  
-
-
500  
30  
Standby Current(CMOS)  
Input Leakage Current  
-
10  
Output Leakage Current  
Input High Voltage, All Inputs  
Input Low Voltage, All Inputs  
Output High Voltage Level  
Output Low Voltage Level  
ILO  
VOUT=0 to VCC  
-
10  
VIH  
VIL  
2.0  
-0.3  
2.4  
-
VCC+0.3  
0.6  
V
VOH  
VOL  
IOH=-400mA  
-
V
IOL=2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
OE  
BHE  
X
Q15/A-1  
Mode  
Data  
High-Z  
Power  
Standby  
Active  
H
X
X
X
Standby  
Operating  
Operating  
L
H
X
High-Z  
H
Output  
Q0~Q15 : Dout  
Active  
L
L
Q0~Q7 : Dout  
Q8~Q14 : Hi-Z  
L
Input  
Operating  
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Output Capacitance  
Input Capacitance  
Symbol  
Test Conditions  
VOUT=0V  
Min  
Max  
10  
Unit  
pF  
COUT  
CIN  
-
-
VIN=0V  
10  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
K3N3V(U)1000D-D(G)C  
CMOS MASK ROM  
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
0.45V to 2.4V  
10ns  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output timing Levels  
Output Loads  
1.5V  
1 TTL Gate and CL=100pF  
READ CYCLE  
Item  
VCC=3.3V±0.3V  
VCC=3.0V±0.3V  
Symbol  
Unit  
Min  
100  
Max  
Min  
120  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
100  
100  
50  
120  
120  
60  
tOE  
Output or Chip Disable to  
Output High-Z  
tDF  
tOH  
20  
20  
ns  
ns  
Output Hold from Address Change  
0
0
TIMING DIAGRAM  
READ  
ADD  
ADD2  
ADD1  
A0~A17  
A-1(*1)  
tRC  
tDF(*3)  
tACE  
CE  
OE  
tOE  
tAA  
tOH  
DOUT  
VALID DATA  
VALID DATA  
D0~D7  
D8~D15(*2)  
NOTES :  
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)  
*2. Word Mode only.(BHE = VIH)  
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.  

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