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K3N6U1000D-YE [SAMSUNG]

MASK ROM, 2MX16, 100ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48;
K3N6U1000D-YE
型号： K3N6U1000D-YE
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 2MX16, 100ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48

有原始数据的样本ROM 光电二极管 内存集成电路
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K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
CMOS MASK ROM  
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
4,194,304x8(byte mode)  
2,097,152x16(word mode)  
· Fast access time  
The K3N6V(U)1000D-YC(E) and K3N6S1000D-YC(E) are fully  
static mask programmable ROM fabricated using silicon gate  
CMOS process technology, and is organized either as  
4,194,304 x8 bit(byte mode) or as 2,097,152x16 bit(word  
mode) depending on BHE voltage level.(See mode selection  
table)  
Random Access Time  
3.3V/3.0V Operation : 100ns(Max.)  
2.5V Operation : 150ns(Max.)  
· Supply voltage  
K3N6V(U)1000D-YC(E) : single +3.0V/ single +3.3V  
K3N6S1000D-YC(E) : single +2.5V  
· Current consumption  
This device operates with low power supply, and all inputs and  
outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
Operating : 40mA(Max.)  
Standby : 30mA(Max.)  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N6V(U)1000D-YC(E) and K3N6S1000D-YC(E) are  
packaged in a 48-TSOP1.  
· Package  
-. K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
: 48-TSOP1-1218  
FUNCTIONAL BLOCK DIAGRAM  
Pin Name  
A0 - A20  
Pin Function  
Address Inputs  
A20  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
(2,097,152x16/  
4,194,304x8)  
Q0 - Q14  
Data Outputs  
DECODER  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
Y
SENSE AMP.  
BUFFERS  
AND  
DATA OUT  
BUFFERS  
OE  
DECODER  
A0  
VCC  
VSS  
A-1  
.
.
.
Ground  
CE  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE  
BHE  
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
CMOS MASK ROM  
PRODUCT INFORMATION  
Operating  
Temp Range  
VCC Range  
(Typical)  
Speed  
(ns)  
Product  
K3N6V(U)1000D-YC  
3.3V/3.0V  
2.5V  
100  
150  
100  
150  
0°C ~ 70°C  
K3N6S1000D-YC  
K3N6V(U)1000D-YE  
-20°C ~ 85°C  
K3N6S1000D-YE  
3.3V/3.0V  
2.5V  
PIN CONFIGURATION  
BHE  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VSS  
VSS  
Q15/A-1  
Q7  
Q14  
Q6  
Q13  
Q5  
3
4
5
6
7
8
9
Q12  
Q4  
A8  
A19  
VSS  
10  
11  
12  
VCC  
VCC  
VSS  
Q11  
Q3  
TSOP I  
A20 13  
A18 14  
A17 15  
A7 16  
A6 17  
A5  
A4  
A3  
A2 21  
A1 22  
A0 23  
CE 24  
Q10  
Q2  
18  
19  
20  
Q9  
Q1  
Q8  
Q0  
OE  
VSS  
VSS  
K3N6V(U)1000D-YC(E)  
K3N6S1000D-YC(E)  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
Rating  
Unit  
Remark  
Voltage on Any Pin Relative to  
VIN  
-0.3 to +4.5  
-10 to +85  
-55 to +150  
V
-
-
-
Temperature Under Bias  
Storage Temperature  
TBIAS  
TSTG  
°C  
°C  
K3N6V(U)1000D-YC  
K3N6S1000D-YC  
0 to +70  
°C  
°C  
Operating Temperature  
TA  
K3N6V(U)1000D-YE  
K3N6S1000D-YE  
-20 to +85  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
CMOS MASK ROM  
RECOMMENDED OPERATING CONDITIONS (Voltage reference to VSS)  
Item  
Min  
2.7/3.0  
2.3  
Symbol  
Typ  
3.0/3.3  
2.5  
Max  
3.3/3.6  
2.7  
Unit  
V
Supply Voltage  
VCC  
V
Supply Voltage  
VSS  
0
0
0
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
40  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
VCC=3.3V±0.3V  
-
CE=OE=VIL,  
all outputs open  
Operating Current  
ICC  
VCC=3.0V±0.3V  
VCC=2.5V±0.2V  
-
35  
-
30  
K3N6V(U)1000D-YC(E)  
K3N6S1000D-YC(E)  
K3N6V(U)1000D-YC(E)  
K3N6S1000D-YC(E)  
ILI  
-
500  
100  
30  
Standby Current(TTL)  
ISB1  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
-
-
Standby Current(CMOS)  
ISB2  
-
5
Input Leakage Current  
VIN=0 to VCC  
-
10  
Output Leakage Current  
Input High Voltage, All Inputs  
ILO  
VOUT=0 to VCC  
-
10  
VIH  
2.0  
-0.3  
-0.3  
2.4  
2.0  
-
VCC+0.3  
K3N6V(U)1000D-YC(E)  
K3N6S1000D-YC(E)  
0.6  
0.4  
-
V
Input Low Voltage, All Inputs  
VIL  
V
K3N6V(U)1000D-YC(E) IOH=-400mA  
K3N6S1000D-YC(E) IOH=-400mA  
V
Output High Voltage Level  
Output Low Voltage Level  
VOH  
-
V
VOL  
IOL=2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
H
OE  
X
BHE  
X
Q15/A-1  
Mode  
Data  
High-Z  
Power  
X
X
Standby  
Operating  
Operating  
Standby  
Active  
L
H
X
High-Z  
H
Output  
Q0~Q15 : Dout  
Active  
L
L
Q0~Q7 : Dout  
Q8~Q14 : Hi-Z  
L
Input  
Operating  
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Output Capacitance  
Input Capacitance  
Symbol  
Test Conditions  
VOUT=0V  
Min  
Max  
12  
Unit  
pF  
COUT  
CIN  
-
-
VIN=0V  
12  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
CMOS MASK ROM  
AC CHARACTERISTICS(VCC=3.3V/3.0V±0.3V, VCC=2.5V±0.2V, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
0.45V to 2.4V(at VCC=3.3V/3.0V)  
0.4V to 2.2V (at VCC=2.5V)  
10ns  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output timing Levels  
Output Loads  
1.5V (at VCC=3.3V/3.0V)  
1.1V (at VCC=2.5V)  
1 TTL Gate and CL=100pF  
READ CYCLE  
Item  
VCC=3.3V/3.0V±0.3V  
VCC=2.5V±0.2V  
Symbol  
Unit  
Min  
Max  
Min  
150  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
100  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
100  
100  
50  
150  
150  
70  
tOE  
Output or Chip Disable to  
Output High-Z  
tDF  
20  
30  
ns  
ns  
Output Hold from Address Change  
tOH  
0
0
TIMING DIAGRAM  
READ  
ADD  
ADD2  
A0~A20  
A-1(*1)  
ADD1  
tRC  
tDF(*3)  
tACE  
CE  
OE  
tOE  
tAA  
tOH  
DOUT  
D0~D7  
VALID DATA  
VALID DATA  
D8~D15(*2)  
NOTES :  
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)  
*2. Word Mode only.(BHE = VIH)  
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.  
K3N6V(U)1000D-YC(E)/K3N6S1000D-YC(E)  
CMOS MASK ROM  
PACKAGE DIMENSIONS  
(Unit : mm/inch)  
48-TSOP1-1218  
18.00±0.20  
0.709±0.008  
#1  
#48  
12.40  
MAX  
0.488  
1.00±0.10  
0.039±0.004  
1.20  
0.05  
0.002  
#25  
#24  
MIN  
MAX  
16.40±0.10  
0.646±0.004  
0.047  
0~8°  
0.50  
0.020  
(
)
0.45~0.75  
0.018~0.030  

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