K3P5C1000F-GC10 [SAMSUNG]
MASK ROM, 1MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44;
| 型号： | K3P5C1000F-GC10 |
| 厂家： | 
SAMSUNG |
| 描述： | MASK ROM, 1MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44 有原始数据的样本ROM 输入元件 光电二极管 输出元件 内存集成电路 |
| 文件： | 总4页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K3P5C1000F-D(G)C
CMOS MASK ROM
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
2,097,152 x 8(byte mode)
1,048,576 x 16(word mode)
· Fast access time
Random Access : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
The K3P5C1000F-D(G)C is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 2,097,152 x 8 bit(byte mode) or as
1,048,576 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 words (or 8 bytes) of data to read fast in the same
page, CE and A3 ~ A19 should not be changed.
Page Access
: 30ns(Max.)@CL=50pF
40ns(Max.)@CL=100pF
4 Words / 8 Bytes page access
· Supply voltage : single +5V
· Current consumption
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Operating : 150mA(Max.)
Standby : 50mA(Max.)
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
· Package
-. K3P5C1000F-DC : 42-DIP-600
-. K3P5C1000F-GC : 44-SOP-600
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P5C1000F-DC is packaged in a 42-DIP and the
K3P5C1000F-GC in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A19
X
MEMORY CELL
MATRIX
(1,048,576x16/
2,097,152x8)
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
1
2
42
41
40
A18
A19
A8
N.C
A18
N.C
A19
A8
1
2
44
43
42
41
40
39
A17
A7
3
A9
A17
A7
3
4
A6
A5
39 A10
4
A9
5
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A11
A12
A6
A5
A4
A3
A10
A11
5
Y
SENSE AMP.
6
A4
6
BUFFERS
AND
DECODER
7
A3
A13
A14
7
38 A12
37 A13
DATA OUT
BUFFERS
8
A2
8
A2
9
A1
A15
A16
A14
36
A2
A1
9
10
11
12
13
14
15
16
A0
A15
35
10
11
A0~A1
A-1
CE
VSS
OE
Q0
Q8
Q1
BHE
VSS
. . .
A0
A16
34
DIP
SOP
CE 12
33
BHE
Q15/A-1
CE
VSS
13
32 VSS
Q7
Q0/Q8
Q7/Q15
CONTROL
LOGIC
OE 14
Q15/A-1
31
30
OE
Q14
Q6
Q7
Q0
15
BHE
Q8
Q1
Q9
16
29 Q14
28 Q6
Q9 17
Q13
Q5
17
18
18
Q2
Q13
Q5
27
26
25
24
19
Q10
Pin Name
A0 - A1
Pin Function
Page Address Inputs
Q12
Q4
Q2 19
20
21
Q3
Q10 20
Q12
Q4
Q11
VCC
Q3
21
22
A2 - A19
Q0 - Q14
Address Inputs
Q11
23 VCC
Data Outputs
K3P5C1000F-DC
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
K3P5C1000F-GC
BHE
CE
Word/Byte selection
Chip Enable
Output Enable
Power ( +5V)
Ground
OE
VCC
VSS
N.C
No Connection
K3P5C1000F-D(G)C
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +7.0
-10 to +85
-55 to +150
V
TBIAS
TStg
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Min
4.5
0
Symbol
Typ
5.0
0
Max
5.5
0
Unit
V
Supply Voltage
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Unit
Operating Current
ICC
-
150
mA
Standby Current(TTL)
mA
mA
mA
mA
V
ISB1
ISB2
ILI
-
-
1
Standby Current(CMOS)
Input Leakage Current
50
10
10
-
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
-
V
VOH
VOL
IOH = -400mA
V
IOL = 2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
H
L
X
H
X
X
Standby
Operating
Operating
Standby
Active
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P5C1000F-D(G)C
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
K3P5C1000F-D(G)C10 K3P5C1000F-D(G)C12 K3P5C1000F-D(G)C15
(CL=50pF)
(CL=100pF)
(CL=100pF)
Item
Symbol
Unit
Min
100
Max
Min
120
Max
Min
150
Max
Read Cycle Time
tRC
tACE
tAA
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
40
150
150
50
Page Address Access Time
Output Enable Access Time
tPA
tOE
30
40
50
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
NOTE : Page Address is determined as below.
Word mode(BHE=VIH) ; A0, A1
Byte mode(BHE=VIL) ; A-1, A0, A1
K3P5C1000F-D(G)C
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A19
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
VALID DATA
D0~D7
VALID DATA
D8~D15(*2)
PAGE READ
CE
tDF(*3)
OE
ADD
A2~A19
ADD
A0,A1
3 rd
1 st
2 nd
A-1(*1)
tAA
tPA
DOUT
D0~D7
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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