K4D551638H-LC500 [SAMSUNG]
DDR DRAM, 16MX16, 0.65ns, CMOS, PDSO66, ROHS COMPLIANT, TSOP2-66;
| 型号： | K4D551638H-LC500 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 16MX16, 0.65ns, CMOS, PDSO66, ROHS COMPLIANT, TSOP2-66 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4D551638H
256M GDDR SDRAM
256Mbit GDDR SDRAM
Revision 1.3
April 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
Revision History
Revision
Month
Year
2005
2005
History
- Target Spec
- Defined Target Specification
0.0
July
0.1
September
- Preliminary Spec
- Changed CL from 4clk to 3clk of -LC40
- Added current spec
0.2
November
2005
- Added IBIS data
- Final Spec
- Deleted -LC33/36/60 spec.
1.0
1.1
1.2
1.3
January
April
2006
2006
2006
2007
- Deleted CL4 option in MRS table according to deleting high frequency bin(-LC33/36).
- Added CL2.5 option(-LC50 can support 166MHz@CL 2.5)
- Changed VDD(min) spec from 2.5V to 2.35V.
April
April
- Corrected typo on page 14.
- 2 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
1.0 FEATURES
• 2.35V ~ 2.7V power supply for device operation
• 2.35V ~ 2.7V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• 2 DQS’s (1DQS / Byte)
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• MRS cycle with address key programs
-. Read latency 2.5, 3 (clock)
-. Burst length (2, 4 and 8)
• Auto & Self refresh
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going
edge of the system clock
• 64ms refresh period (8K cycle)
• 66pin TSOP-II lead free package(RoHS Compliant)
• Maximum clock frequency up to250MHz
• Maximum data rate up to 500Mbps/pin
• Differential clock input
• No Write-Interrupted by Read Function
(WIR function can be supported only for 200/166MHz)
2.0 ORDERING INFORMATION
Part NO.
K4D551638H-LC40
K4D551638H-LC50
Max Freq.
250MHz
200MHz
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
VDD & VDDQ
Package
2.35V ~
2.7V
SSTL_2
66pin TSOP-II
3.0 GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank GDDR SDRAM
The K4D551638H is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fab-
ricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system
applications.
- 3 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
4.0 PIN CONFIGURATION (Top View)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
1
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
VSSQ
UDQS
NC
VDDQ
LDQS
NC
VREF
VSS
VDD
NC
UDM
CK
LDM
WE
CK
CAS
RAS
CS
22
23
CKE
NC
24
25
26
27
28
29
30
31
32
33
A12
NC
A11
BA0
BA1
AP/A10
A0
A9
A8
A7
A6
A1
A5
A2
A4
A3
VSS
VDD
PIN DESCRIPTION
CK,CK
CKE
CS
Differential Clock Input
BA0, BA1
A0 ~A12
Bank Select Address
Address Input
Data Input/Output
Power
Clock Enable
Chip Select
DQ0 ~ DQ15
RAS
Row Address Strobe
V
V
V
V
DD
CAS
Column Address Strobe
Write Enable
Ground
SS
WE
Power for DQ’s
Ground for DQ’s
DDQ
SSQ
L(U)DQS
Data Strobe
L(U)DM
RFU
Data Mask
NC
No Connection
Reserved for Future Use
VREF
Reference voltage
- 4 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
*1
Input
CK, CK
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.CKE is synchronous
for Power down entry and exit, and for Self refresh entry. CKE is asynchronous for Self
refresh exit, and for output disable. CKE must be maintained high through Read and Write
accesses. Input buffers, excluding CK, CK and CKE are disbled during Power down. Input
buffers, excluding CKE are disabled during Self refresh. CKE is an SSTL_2 input, but will
detect a LVCMOS low level after Vdd is applied upon 1st power up. After Vref has become
stable during the power on and intialization sequence, it must be maintained for proper oper-
ation of the CKE receiver. For proper Self refresh entry and exit, Vref must be maintained to
this input.
CKE
Input
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
CS
Input
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
RAS
CAS
WE
Input
Input
Input
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
LDQS,UDQS
LDM,UDM
Input/Output
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
DQ0 ~ DQ15
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
A0 ~ A12
Input
V
/V
Power Supply
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
DD SS
V
/V
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
DDQ SSQ
V
REF
No connection/
Reserved for future use
NC/RFU
This pin is recommended to be left "No connection" on the device
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V to CK pin.
REF
- 5 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
6.0 BLOCK DIAGRAM (4Mbit x 16I/O x 4 Bank)
16
Intput Buffer
LWE
CK, CK
Data Input Register
Serial to parallel
LDMi
Bank Select
4Mx16
4Mx16
4Mx16
4Mx16
32
16
x16
DQi
CK,CK
ADDR
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
DLL
LCKE
LRAS LCBR
LWE
LCAS
CK,CK
LDMi
Timing Register
UDM
CK,CK
CKE
CS
RAS
CAS
WE
LDM
- 6 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
7.0 FUNCTIONAL DESCRIPTION
7.1 Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply V before V
.
DD
DDQ
- Apply V
before V
& V
REF TT
DDQ
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16 17
18
19
CK,CK
tRP
2 Clock min.
tRFC
tRFC
2 Clock min.
tRP
2 Clock min.
Command
precharge
ALL Banks
MRS
DLL Reset
precharge
ALL Banks
1st Auto
Refresh
2nd Auto
Refresh
Mode
Register Set
Any
Command
EMRS
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
7.2 MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing
mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-
cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper
operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with
CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS,
RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in
the mode register. The mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length
uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various
burst length, addressing modes and CAS latencies.
BA1
BA0
0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
*1
*1
DLL
TM
CAS Latency
Burst Length
Mode Register
RFU
RFU
Burst Type
DLL
Test Mode
A3
0
Type
A8
0
DLL Reset
No
A7
0
mode
Sequential
Interleave
Normal
Test
1
1
Yes
1
CAS Latency
Burst Length
BA0
An ~ A0
MRS
A6
0
A5
0
A4
0
Latency
Reserved
Reserved
Reserved
3
Burst Type
A2
A1
A0
0
1
Sequential
Interleave
Reserve
2
EMRS
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
0
1
0
0
1
1
4
4
* 1 : RFU(Reserved for future use)
should stay "0" during MRS cycle.
1
0
0
Reserved
Reserved
2.5
8
8
1
0
1
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
1
1
0
1
1
1
Reserved
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Precharge
All Banks
Any
Command
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
tMRD=2 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
7.3 EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the
extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL.
The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12 and
BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting
driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended
mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as
long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
Address Bus
BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Extended
Mode Register
*1
*1
1
D.I.C DLL
RFU
RFU
BA0
An ~ A0
MRS
A1
0
Output Driver Impedence Control
A0
0
DLL Enable
Enable
0
1
Full
100%
60%
EMRS
1
Weak
1
Disable
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
- 9 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
7.4 WRITE INTERRUPTED BY A READ & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to
avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be
written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=3 >
0
1
2
3
4
5
6
7
8
CK
CK
Command
NOP
WRITE
NOP
DQSSmax
NOP
NOP
CDLR
READ
NOP
NOP
NOP
t
t
DQS
5
t
WPRES*
CAS Latency=3
Din 7
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6
CDLR
Dout 0 Dou
DQ
′s
tDQSSmin
t
DQS
5
CAS Latency=3
t
WPRES*
Din 6
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5
Din 7
DQ
′s
Dout 0 Dou
DM
The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
is 1 clock cycle is disallowed
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting
Read operation and the input data word which immediately follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow
the buses to turn around before the GDDR drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the GDDR.
* This function is only supported in 200/166MHz.
8.0 ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
2.0
Unit
V
V
VDDQ
TSTG
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
- 10 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
9.0 AC & DC OPERATING CONDITIONS
9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
Symbol
Min
2.35
2.35
Typ
2.6
2.6
-
Max
2.7
Unit
V
Note
V
1
DD
V
2.7
V
1
DDQ
V
0.49*V
0.51*V
DDQ
V
2
REF
DDQ
Termination voltage
Vtt
V (DC)
V
-0.04
V
V
+0.04
V
3
REF
REF
REF
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
V
+0.15
-
V
+0.30
-0.15
V
4
IH
REF
DDQ
V (DC)
-0.30
-
-
-
-
-
V
V
5
IL
REF
V
Vtt+0.76
-
V
I
=-15.2mA
OH
OH
V
I
-
Vtt-0.76
V
I
=+15.2mA
OL
OL
IL
-5
-5
5
5
uA
uA
6
6
I
OL
Note :
1. Under all conditions V
must be less than or equal to V
.
DD
DDQ
2. V
is expected to equal 0.50*V
of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V
REF
D
D
Q
R
E
F
may not exceed + 2% of the DC value. Thus, from 0.50*V
, V
is allowed + 25mV for DC error and an additional + 25mV for AC noise.
DDQ
REF
3. V of the transmitting device must track V
of the receiving device.
REF
tt
4. V (max.)= V
+1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
IH
DDQ
5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
IL
6. For any pin under test input of 0V < V < V is acceptable. For all other pins that are not under test V =0V.
IN
DD
IN
9.2 DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, (TA=0 to 65°C)
Version
-40
Parameter
Operating Current
Symbol
Test Condition
Unit
Note
-50
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
ICC1
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
160
140
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
(One Bank Active)
Precharge Standby Current
in Power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
5
Precharge Standby Current
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
80
65
80
70
55
70
Active Standby Current
power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
Active Standby Current in
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Operating Current
(Burst Mode)
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
Page Burst, All Banks activated.
265
180
220
160
Refresh Current
ICC5
ICC6
tRC ≥ tRFC(min)
CKE ≤ 0.2V
mA
mA
1, 2,3
1, 2
Self Refresh Current
5
Burst Length=4, tRC ≥ tRFC(min)
IOL=0mA, tCC = tCC(min)
Operating Current
(4Bank Interleaving)
ICC7
300
260
mA
1, 2
Note :
1. Measured with output open.
2. Current meassured at V (max).
DD
3. Refresh period is 64ms.
- 11 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
9.3 AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, V /V
=2.35V ~ 2.7V,TA=0 to 65°C)
DD DDQ
Parameter
Symbol
Min
+0.35
REF
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
V
V
-
-
V
IH
Input Low (Logic 0) Voltage; DQ
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
Note :
V
-
-
-
-
V
-0.35
REF
V
V
V
IL
ID
IX
V
V
0.7
V
+0.6
1
2
DDQ
0.5*
-0.2
0.5*V
+0.2
VDDQ
DDQ
1. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
2. The value of V is expected to equal 0.5*V
IX
of the transmitting device and must track variations in the DC level of the same.
DDQ
(V =2.35V ~ 2.7V, TA= 0 to 65°C)
9.4 AC OPERATING TEST
DD
Parameter
Value
0.50*V
Unit
Note
Input reference voltage for CK(for single ended)
V
1
DDQ
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(VIH/VIL)
1.5
1.0
V
V/ns
V
V
+0.35/V
-0.35
REF
REF
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
V
V
REF
V
tt
See Fig.1
Note 1 : In case of differential clocks(CK and CK), input reference voltage for clock is a CK and CK’s crossing point.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
- 12 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
(V =2.6V, TA= 25°C, f=1MHz)
9.5 CAPACITANCE
DD
Parameter
Symbol
CIN1
Min
1.0
1.0
1.0
1.0
1.0
Max
5.0
4.0
4.0
6.5
6.5
Unit
pF
Input capacitance( CK, CK )
Input capacitance(A0~A12, BA0~BA1)
Input capacitance( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ0~DQ15)
Input capacitance(DM0 ~ DM3)
CIN2
pF
CIN3
pF
COUT
CIN4
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between V and V
CDC1
0.1 + 0.01
0.1 + 0.01
uF
uF
DD
SS
Decoupling Capacitance between V
and V
CDC2
DDQ
SSQ
Note :
1. V and V
pins are separated each other. All V pins are connected in chip. All V
pins are connected in chip.
pins are connected in chip.
DD
DDQ
DD
DDQ
2. V and V
pins are separated each other. All V pins are connected in chip. All V
SS
SS
SSQ
SSQ
9.6 AC CHARACTERISTICS(I)
-40
-50
Symbol
Unit
Note
Parameter
Min
4.0
-
Max
Min
5.0
Max
CL=3
10
-
10
10
0.55
0.55
0.55
0.65
0.4
1.1
0.6
1.28
-
ns
CK cycle time
CL=2.5
tCK
6.0
CK high level width
tCH
tCL
0.45
0.45
-0.6
-0.6
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.45
0.45
-0.55
-0.65
-
tCK
tCK
ns
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
ns
1
0.9
0.4
0.85
0
0.9
tCK
tCK
tCK
ns
Read postamble
0.4
CK to valid DQS-in
0.72
0
DQS-In setup time
DQS-in hold time
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
-
0.25
0.4
-
tCK
tCK
tCK
tCK
ns
DQS write postamble
0.6
0.6
0.6
-
0.6
-
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
0.35
0.35
0.6
-
-
tIH
-
0.6
-
ns
tDS
-
0.4
-
ns
tDH
-
0.4
-
ns
tCLmin
or
tCHmin
tCLmin
or
tCHmin
Clock half period
tHP
tQH
-
-
-
-
ns
ns
1
1
Data output hold time from DQS
Note 1 :
tHP-0.4
tHP-0.5
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with
that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then
the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
- 13 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
AC CHARACTERISTICS (I)
-40
-50
Parameter
Symbol
Unit
Note
Min
13
15
9
Max
Min
12
14
8
Max
Row cycle time
tRC
tRFC
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Refresh row cycle time
-
-
Row active time
tRAS
100K
100K
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
tRCDRD
tRCDWR
tRP
4
-
-
-
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
-
2
2
4
4
Row active to Row active
tRRD
tWR
3
2
Last data in to Row precharge @Normal Precharge
Last data in to Row precharge @Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Precharge
Exit self refresh to read command
3
3
1
1
1
tWR_A
tCDLR
tCCD
tMRD
tDAL
3
3
2
2
1
1
2
2
7
7
tXSR
200
200
3tCK
+tIS
1tCK
+tIS
Power down exit time
Refresh interval time
tPDEX
tREF
-
-
ns
us
-
7.8
-
7.8
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
AC CHARACTERISTICS (II)
(Unit : Number of Clock)
K4D551638H-LC40
Unit
tCK
tCK
Frequency
250MHz ( 4.0ns )
200MHz ( 5.0ns )
Cas Latency
tRC
13
12
tRFC
15
14
tRAS
9
8
tRCDRD tRCDWR
tRP
4
4
tRRD
3
3
tDAL
7
7
3
3
4
4
2
2
K4D551638H-LC50
Frequency
200MHz ( 5.0ns )
166MHz ( 6.0ns )
Unit
tCK
tCK
Cas Latency
tRC
12
10
tRFC
14
12
tRAS
8
7
tRCDRD tRCDWR
tRP
4
3
tRRD
2
2
tDAL
7
6
3
2.5
4
3
2
2
- 14 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to
avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be
written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=3 >
0
1
2
3
4
5
6
7
8
CK
CK
Command
NOP
WRITE
NOP
DQSSmax
NOP
NOP
CDLR
READ
NOP
NOP
NOP
t
t
DQS
5
t
WPRES*
CAS Latency=3
Din 7
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6
CDLR
Dout 0 Dou
DQ
′s
tDQSSmin
t
DQS
5
CAS Latency=3
t
WPRES*
Din 6
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5
Din 7
DQ
′s
Dout 0 Dou
DM
The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
is 1 clock cycle is disallowed.
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting
Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow
the buses to turn around before the GDDR drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the GDDR.
* This function is only supported in 200/166MHz.
- 15 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
10.0 IBIS : I/V Characteristics for Input and Output Buffers
(1) Full Strength Driver Characteristics
Pulldown Current (mA)
Voltage
Pullup Current (mA)
Maximum
Minimum
Maximum
Minimum
(V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
0
0
0
0
4.8
10.0
-4.8
-10.4
9.6
18.9
-9.6
-20.8
14.4
19.1
23.9
28.8
33.5
38.3
41.2
44.3
46.6
48.0
49.0
49.3
49.6
49.9
50.3
50.9
51.1
51.4
51.6
51.8
51.9
52.0
52.2
52.4
52.5
27.0
-14.4
-19.1
-23.9
-28.8
-33.5
-37.4
-39.7
-40.2
-40.6
-40.6
-41.0
-41.2
-41.5
-41.7
-41.8
-41.9
-42.0
-42.1
-42.2
-42.3
-42.4
-42.5
-42.6
-42.7
-42.8
-31.0
35.3
-40.4
43.5
-48.7
51.4
-56.6
59.1
-64.3
65.7
-72.3
72.7
-80.4
79.4
-88.6
85.8
-96.7
91.8
-104.6
-112.4
-120.1
-127.9
-135.6
-142.2
-150.0
-156.5
-163.2
-169.7
-176.4
-183.0
-188.6
-195.1
-200.6
-206.1
97.6
103.1
108.0
112.7
116.6
120.5
124.4
128.2
131.6
134.7
137.7
140.4
142.8
144.8
146.4
- 16 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
10.0 IBIS : I/V Characteristics for Input and Output Buffers
(2) Weak Strength Driver Characteristics
Pulldown Current (mA)
Voltage
Pullup Current (mA)
Maximum
Minimum
Maximum
Minimum
(V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
0
0
0
0
2.7
5.2
-2.7
-5.2
5.4
10.3
15.2
20.0
24.5
29.1
33.5
37.2
41.1
44.9
48.6
52.0
55.2
58.3
61.0
63.9
66.0
68.2
70.4
72.6
74.5
76.2
77.9
79.5
80.8
82.0
82.9
-5.4
-10.3
-15.2
-20.0
-24.5
-29.1
-33.5
-37.2
-41.1
-44.9
-48.6
-52.0
-55.2
-58.3
-61.0
-63.9
-66.0
-68.2
-70.4
-72.6
-74.5
-76.2
-77.9
-79.5
-80.8
-82.0
-82.9
8.1
-8.1
10.8
13.5
16.3
18.9
21.6
23.3
25.1
26.4
27.2
27.7
27.9
28.1
28.3
28.5
28.8
28.9
29.1
29.2
29.3
29.4
29.4
29.5
29.6
29.7
-10.8
-13.5
-16.3
-18.9
-21.2
-22.5
-22.8
-23.0
-23.1
-23.2
-23.3
-23.5
-23.6
-23.6
-23.7
-23.8
-23.8
-23.9
-24.0
-24.1
-24.1
-24.1
-24.2
-24.2
- 17 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
11.0 PACKAGE DIMENSIONS (66pin TSOP-II)
Units : Millimeters
#66
#34
(10×)
(10×)
#1
#33
+0.075
-0.035
0.125
(1.50)
22.22±0.10
(10×)
(10×)
0.10 MAX
0.25TYP
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
[
]
0.075 MAX
NOTE
1. (
0×~8×
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
- 18 -
Rev. 1.3 April 2007
相关型号：
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