K4N56163QF-GC33 [SAMSUNG]
DDR DRAM, 16MX16, 0.47ns, CMOS, PBGA84, FBGA-84;
| 型号： | K4N56163QF-GC33 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 16MX16, 0.47ns, CMOS, PBGA84, FBGA-84 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总19页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256M gDDR2 SDRAM
K4N56163QF-GC
256Mbit gDDR2 SDRAM
Revision 1.8
May 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.8 May 2005
- 1 -
256M gDDR2 SDRAM
K4N56163QF-GC
Revision History
Revision
Month
Year
History
- Target Spec
- Defined Target Specification
0.0
April
2004
- DC spec defined.
1.0
1.1
1.2
October
December
December
2004
2004
2004
- Changed VDD&VDDQ of K4N56163QF-GC20/22 from 1.8V+0.1V to 2.0V+0.1V
- Changed ICC2P and ICC6 to 10mA
- Changed the DC characteristics table
- Added 50 ohm at the EMRS(1) programming table.
1.3
1.4
1.5
1.6
1.7
January
February
March
April
2005
2005
2005
2005
2005
- Typo corrected
- Added Lead-Free part number in the datasheet.
- Removed K4N56163QF-GC20/22 from the datasheet.
- Modified Power-up and Initialization Sequence on page 22.
- Corrected typo.
April
- Changed speed bin organization.
(K4N56163QF-GC2A/K4N56163QF-GC33/K4N56163QF-GC36)
- 533 Speed bin changed into 550 speed bin.
- 600 speed bin is added.
1.8
May
2005
- 667 speed bin changed into 700 speed bin.
- Seperated device operation and timing diagram
- Corrected typo.
Rev. 1.8 May 2005
- 2 -
256M gDDR2 SDRAM
K4N56163QF-GC
4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.0 FEATURES
• 1.8V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• 4 Banks operation
• Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
• Off-chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Posted CAS
• Programmable CAS Letency : 4,5,6 and 7
• Programmable Additive Latency : 0, 1, 2, 3. 4 and 5
• Write Latency (WL) = Read Latency (RL) -1
• Burst Legth : 4 and 8 (Interleave/nibble sequential)
• Programmable Sequential/ Interleave Burst Mode
• Refresh and Self Refresh
Average Refesh Period 7.8us at lower then TCASE 85×C,
3.9us at 85×C < TCASE < 95 ×C
• 84 ball FBGA
2.0 ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
Interface
Package
K4N56163QF-GC25
K4N56163QF-GC2A*
K4N56163QF-GC33
K4N56163QF-GC36*
400MHz
350MHz
300MHz
275MHz
SSTL
84 Ball FBGA
* K4N56163QF-GC2A/36 can fully cover previous K4N56163QF-GC30/37(667/533Mbps) product.
** K4N56163QF-ZC is the Lead-Free part number.
3.0 GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM
The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is designed to comply with the follow-
ing key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a
source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 256Mb(x16) device receive 13/9/2 addressing. The 256Mb gDDR2 devices operate with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb gDDR2 devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Rev. 1.8 May 2005
- 3 -
256M gDDR2 SDRAM
K4N56163QF-GC
4.0 PIN CONFIGURATION
Normal Package (Top View)
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
UDQS
VSSQ
VDDQ
VDD
NC
VSS
UDM
UDQ6
VSSQ
UDQ1
B
C
UDQ7
VDDQ
VDDQ
UDQ3
VSS
VDDQ
UDQ4
VDD
UDQ0
D
E
F
VSSQ
LDQS
VSSQ
UDQ5
VDDQ
VSSQ
NC
LDQ6
VSSQ
LDQ1
LDM
LDQS
VDDQ
LDQ2
LDQ7
VDDQ
LDQ4
VDDQ
LDQ3
LDQ0
VSSQ
CK
VDDQ
G
H
J
VSSQ
VREF
CKE
LDQ5
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
K
CK
NC
L
BA0
A10
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
M
N
P
VDD
VSS
VSS
A5
A6
A7
A9
A11
R
VDD
A12
NC
NC
NC
Note : VDDL and VSSDL are power and ground for the DLL. lt is recommended that
they are isolated on the device from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Rev. 1.8 May 2005
- 4 -
256M gDDR2 SDRAM
K4N56163QF-GC
5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
11.00 ± 0.10
# A1 INDEX MARK (OPTIONAL)
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
M
J
K
N
L
P
R
3.20
(6.15)
(0.90)
(1.80)
84-∅0.45±0.05
∅0.2 M
A B
11.00 ± 0.10
#A1
0.35±0.05
MAX.1.20
Unit : mm
Rev. 1.8 May 2005
- 5 -
256M gDDR2 SDRAM
K4N56163QF-GC
6.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi-
CK, CK
Input tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry
and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
CKE
Input
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selec-
tion on systems with multiple banks. CS is considered part of the command code.
CS
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
ODT
Input
grammed to disable ODT.
RAS, CAS, WE
(L)UDM
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
Input HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Actove, Read, Write or Precharge command
Input is being applied. BA0 also determines if the mode register or extended mode register is to be accessed dur-
ing a MRS or EMRS cycle.
BA0 - BA1
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank.
Input A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during Mode Register Set commands.
A0 - A12
DQ
Input/
Data Input/ Output: Bi-directional data bus.
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data
Input/
LDQS,(LDQS)
UDQS,(UDQS)
strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary sig-
Output
nals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. An
EMRS(1) control bit enables or disables all complementary data strobe signals.
No Connect: No internal electrical connection is present.
Supply DQ Power Supply: 1.8V ± 0.1V
NC/RFU
VDDQ
VSSQ
VDDL
VSSL
VDD
Supply DQ Ground
Supply DLL Power Supply: 1.8V ± 0.1V
Supply DLL Ground
Supply Power Supply: 1.8V ± 0.1V
Supply Ground
VSS
VREF
Supply Reference voltage
Rev. 1.8 May 2005
- 6 -
256M gDDR2 SDRAM
K4N56163QF-GC
7.0 ABSOLUTE MAXIMUM DC RATINGS
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Rating
Units
Notes
VDD
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
V
V
V
V
1
1
1
1
VDDQ
VDDL
VIN, VOUT
TSTG
Storage Temperature
-55 to +100
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-
2 standard.
8.0 AC & DC OPERATING CONDITIONS
8.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or
equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about
0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
8.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Note
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
8.3 Input DC & AC Logic Level
Input DC Logic Level
Symbol
IH(DC)
Parameter
Min.
Max.
Units
Note
Note
V
VREF + 0.125
VDDQ - 0.3
VDDQ + 0.3
VREF - 0.125
DC input logic high
DC input logic low
V
V
VIL(DC)
Input AC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(AC)
VIL(AC)
AC input logic high
-
V
VREF + 0.250
-
AC input logic low
VREF - 0.250
V
Rev. 1.8 May 2005
- 7 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.4 AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Note
VREF
0.5 * VDDQ
V
1
VSWING(MAX)
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
SLEW
Note :
V/ns
2, 3
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
max for falling edges as shown in the below figure.
(AC) level applied to the device under test.
IH/IL
to V (AC) min for rising edges and the range from V
to V (AC)
IL
REF
IH
REF
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
VDDQ
VIH(AC) min
VIH(DC) min
VSWING(MAX)
VREF
VIL(DC) max
VIL(AC) max
VSS
delta TF
V
delta TR
Rising Slew =
REF - VIL(AC) max
delta TF
VIH(AC) min - VREF
delta TR
Falling Slew =
< AC Input Test Signal Waveform >
8.5 Differential input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID(AC)
AC differential input voltage
VDDQ + 0.6
V
1
0.5
VIX(AC)
AC differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Note :
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or
UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ .
VIX(AC) indicates the voltage at which differential input signals must cross.
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
8.6 Differential AC output parameters
Symbol
Parameter
Min.
Max.
0.5 * VDDQ + 0.125
Units
Note
VOX(AC)
AC differential cross point voltage
0.5 * VDDQ - 0.125
V
1
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ .
VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 1.8 May 2005
- 8 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.7 OCD default characteristics
Description
Output impedance
Parameter
Min
Nom
Max
Unit
Note
12.6
18
23.4
ohms
1,2
Output impedance step size for
OCD calibration
0
1.5
ohms
6
Pull-up and pull-down mismatch
Output slew rate
0
4
5
ohms
V/ns
1,2,3
Sout
1.5
1,4,5,6,7,8
Notes:
1. Absolute Specifications (0°C ≤ T
≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
CASE
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V (AC) to V (AC).
IL
IH
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and
1000Mbps/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS
specification.
8.8 DC characteristics
(Recommended operating conditions unless otherwise noted, 0°C ≤ Tc ≤85°C )
Version
Parameter
Symbol
Test Condition
Unit
-25
-2A
-33
-36
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle. Address
and control inputs changing once per clock cycle
Operating Current
(One Bank Active)
ICC1
150
130
125
120
mA
Precharge Standby Current
in Power-down mode
ICC2P
ICC2N
ICC3P
CKE ≤ VIL(max), tCC= tCC(min)
10
mA
mA
mA
Precharge Standby Current
in Non Power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)
Address and control inputs changing once per clock cycle
45
50
45
50
40
45
40
45
Active Standby Current
power-down mode
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) DQ,DM,DQS
inputs changing twice per clock cycle. Address and control
inputs changing once per clock cycle
Active Standby Current in
in Non Power-down mode
ICC3N
ICC4
85
85
80
80
mA
mA
IOL=0mA ,tCC= tCC(min),
Operating Current
( Burst Mode)
Page Burst, All Banks activated. DQ,DM,DQS inputs chang-
ing twice per clock cycle. Address and control inputs changing
once per clock.
300
190
290
180
270
170
260
160
Refresh Current
ICC5
ICC6
tRC≥ tRFC
CKE ≤ 0.2V
mA
mA
Self Refresh Current
10
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle. Address
and control inputs changing once per clock cycle
Operating Current
(4Bank interleaving)
ICC7
430
410
370
350
mA
Note :
1. Measured with outputs open and ODT off
2. Refresh period is 32ms
Rev. 1.8 May 2005
- 9 -
256M gDDR2 SDRAM
K4N56163QF-GC
8.9 Input/Output capacitance
- 2A
- 25
- 36
-33
Parameter
Symbol
Units
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Input capacitance, CK and CK
CCK
CDCK
CI
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
0.25
2.0
0.25
2.0
0.25
2.0
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
0.25
4.0
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
2.5
x
CDIO
0.5
0.5
0.5
9.0 Electrical Characteristics & AC Timing for - 25/2A/33/36
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
CASE
DDQ DD
9.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
75
Units
ns
Refresh to active/Refresh command time
tRFC
0 °C ≤ TCASE ≤ 85°C
7.8
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
µs
9.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS
SPEED
Bin (CL-tRCD-tRP)
Parameter
CAS LATENCY
tCK
- 25
6-6-6
min
6
- 2A
5-5-5
min
5
-33
5-5-5
min
5
- 36
Units
4-5-5
min
4
tCK
ns
2.5
6
2.86
5
3.3
5
3.6
5
tRCD
tCK
tCK
tCK
tCK
tRP
6
5
5
5
tRC
22
18
18
16
11
tRAS
16
13
13
Rev. 1.8 May 2005
- 10 -
256M gDDR2 SDRAM
K4N56163QF-GC
9.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
- 25
max
-400 +400
-350 +350 -400 +400 -420 +420
- 2A
min max
-450 +450 -470 +470
- 33
- 36
min max
Parameter
Symbol
Units Notes
min
min max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-500 +500
-450 +450
ps
ps
tDQSCK
tCH
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
CK low-level width
tCL
min
(tCL,
tCH)
min
(tCL,
tCH)
min
(tCL,
tCH)
min
(tCL,
tCH)
CK half period
tHP
x
x
x
x
ps
20,21
24
Clock cycle time, CL= x
tCK
tDH
2.5
8.0
x
2.86
8.0
x
3.3
8.0
x
3.6
8.0
x
ns
ps
15,16,
17
DQ and DM input hold time
175
175
195
225
15,16,
17
DQ and DM input setup time
tDS
50
0.6
0.35
x
x
x
x
50
0.6
0.35
x
x
x
x
70
0.6
0.35
x
x
x
x
100
0.6
0.35
x
x
x
x
ps
tCK
tCK
ps
Control & Address input pulse width for
each input
tIPW
tDIPW
tHZ
DQ and DM input pulse width for each
input
Data-out high-impedance time from CK/
CK
tAC
max
tAC
max
tAC
max
tAC
max
tLZ
(DQS)
tAC
min
tAC
max
tAC
min
tAC
max
tAC
min
tAC
max
tAC
min
tAC
max
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
ps
27
27
2*tAC tAC 2*tAC tAC 2*tAC tAC 2* tAC tAC
min
tLZ(DQ)
ps
max
280
380
x
min
max
310
410
x
min
max
320
420
x
min
max
340
440
x
DQS-DQ skew for DQS and associated
DQ signals
tDQSQ
tQHS
tQH
x
x
x
x
ps
ps
ps
22
21
DQ hold skew factor
x
x
x
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
Write command to first DQS latching tran-
sition
WL
WL
WL
WL
WL
WL
WL
WL
tDQSS
tCK
-0.25 +0.25 -0.25 +0.25 -0.25 +0.25 -0.25 +0.25
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
x
x
x
x
tDSH
x
x
x
x
tMRD
x
x
x
x
tWPST
tWPRE
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
19
Write preamble
14,16,
18
Address and control input hold time
Address and control input setup time
tIH
tIS
250
175
x
x
325
200
x
x
345
220
x
x
375
250
x
x
ps
ps
14,16,
18
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
28
28
Active to active command period for 1KB
page size products
tRRD
tRRD
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
12
12
Active to active command period for 2KB
page size products
Rev. 1.8 May 2005
- 11 -
256M gDDR2 SDRAM
K4N56163QF-GC
- 25
max
- 2A
-33
- 36
max
Parameter
Symbol
tFAW
Units Notes
min
min
max
min
max
min
Four Activate Window for 1KB page size
products
37.5
37.5
50
37.5
37.5
ns
ns
Four Activate Window for 2KB page size
products
tFAW
50
50
50
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
6
2
5
2
5
2
4
tCK
tCK
x
x
x
x
x
x
x
x
Auto precharge write recovery + precharge
time
tWR
+tRP
tWR
+tRP
tWR
+tRP
tWR
+tRP
tDAL
x
x
tCK
23
11
Internal write to read command delay
tWTR
3
3
x
3
3
3
3
2
2
x
tCK
tCK
Internal read to precharge command delaytRTP
tRFC +
10
tRFC +
10
tRFC +
10
tRFC +
10
Exit self refresh to a non-read command tXSNR
ns
Exit self refresh to a read command
tXSRD
tXP
200
200
200
200
tCK
tCK
tCK
tCK
Exit precharge power down to any non-
read command
2
x
x
2
x
x
2
x
x
2
x
Exit active power down to read command tXARD
2
2
2
2
x
9
Exit active power down to read command
tXARDS
6 - AL
6 - AL
6 - AL
6 - AL
9, 10
(Slow exit, Lower power)
CKE minimum pulse width
tCKE
3
3
3
2
3
2
3
2
tCK
tCK
(high and low pulse width)
ODT turn-on delay
tAOND
tAON
3
2
2
2
tAC
(max)+
0.7
tAC
(max)+
0.7
tAC
(max)+
0.7
tAC
(max)+
1
tAC
(min)
tAC
(min)
tAC
(min)
tAC
(min)
ODT turn-on
ns
13, 25
2tCK+
tAC(ma
x)+1
2tCK+
tAC(ma
x)+1
2tCK+
tAC(ma
x)+1
2tCK+t
AC(ma
x)+1
tAC
(min)+2
tAC
(min)+2
tAC
(min)+2
tAC
(min)+2
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
ns
tCK
ns
3.5
3.5
2.5
2.5
2.5
2.5
2.5
2.5
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(max)+
0.6
tAC
(min)
tAC
(min)
tAC
(min)
tAC
(min)
ODT turn-off
26
2.5tCK
+
n)+2 tAC(ma
x)+1
2.5tCK
+tAC(m
ax)+1
2.5tCK
+tAC(m
ax)+1
2.5tCK
+tAC(m
ax)+1
tAC(mi
n)+2
tAC(mi
n)+2
tAC(mi
n)+2
tAC(mi
ODT turn-off (Power-Down mode)
tAOFPD
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
3
8
tCK
tCK
ns
12
12
12
0
12
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tIS+tC
K +tIH
tIS+tC
K +tIH
tIS+tC
K +tIH
tIS+tC
K +tIH
tDelay
ns
24
Note : General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from
VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK =
-250 mV to CK - CK = +500 mV (250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
Rev. 1.8 May 2005
- 12 -
256M gDDR2 SDRAM
K4N56163QF-GC
2. gDDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
V
= V
/2
TT
DDQ
Timing
reference
point
25Ω
<AC Timing Reference Load>
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. gDDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
Output
DQS, DQS
V
= V
/2
TT
DDQ
25Ω
<Slew Rate Test Load>
Test point
4. Differential data strobe
gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
VIH(dc)
VIL(dc)
VIH(ac)
DQ
DM
D
D
D
D
t
VIL(ac)
t
t
DH
DH
VIH(dc)
DS
t
DS
VIH(ac)
DMin
DMin
DMin
DMin
VIL(ac)
VIL(dc)
<Data input (write) timing>
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
QH
t
QH
<Data output (read) timing>
Rev. 1.8 May 2005
- 13 -
256M gDDR2 SDRAM
K4N56163QF-GC
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
: Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied.
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or
tester correlation.
15. Timings are guaranteed with data, mask, and (DQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns
in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH (data setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the V (AC) level for a rising signal and V (AC) for a falling signal applied to
IH
IL
the device under test.
2) Input waveform timing is referenced from the input signal crossing at the V (DC) level for a rising signal and V (DC) for a falling signal applied to
IH
IL
the device under test.
∆tDS, ∆tDH Derating Values (ALL units in ‘ps’, Note 1 applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
125
45
125
83
0
45
21
0
-
95
12
1
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
83
21
-
-
-
-
0
0
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
-
-
-
-
-
-
-
-
-
DQ
Slew
rate
-11
-14
-11
-25
-
-14
-31
-
25
11
-7
-31
-74
-
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-13
-31
-
23
5
17
-6
-35
-77
-
-
-
-
-
-
-18
-47
-89
-
17
-7
-50
6
-
-
V/ns
-
-
-
-
-19
-62
-23
-65
5
-11
-53
-
-
-
-
-
-
-38
-
-
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the
delta tDS and delta tDH derating value respectively. Example : tDS (total setup time) = tDS(base) + delta tDS.
Rev. 1.8 May 2005
- 14 -
256M gDDR2 SDRAM
K4N56163QF-GC
18. tIS and tIH (input setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the V (AC) level for a rising signal and V (AC) for a falling signal applied to
IH
IL
the device under test.
2) Input waveform timing is referenced from the input signal crossing at the V (DC) level for a rising signal and V (DC) for a falling signal applied to
IH
IL
the device under test.
tIS, tIH Derating Values for DDR2 550
CK,CK Differential Slew Rate
1.5 V/ns
Units
Notes
2.0 V/ns
1.0 V/ns
∆tIS
+187
+179
+167
+150
+125
+83
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+60
0.9
-11
-14
+19
+49
+46
Command
/Adress Slew
rate(V/ns)
0.8
0.7
-25
-31
+5
+35
+29
-43
-54
-13
-24
+17
+6
0.6
-67
-83
-37
-53
-7
-23
0.5
-110
-175
-285
-350
-525
-800
-125
-188
-292
-375
-500
-708
-80
-95
-50
-65
0.4
-145
-255
-320
-495
-770
-158
-262
-345
-470
-678
-115
-225
-290
-465
-740
-128
-232
-315
-440
-648
0.3
0.25
0.2
0.15
∆tIS and ∆tIH Derating Values for DDR2-600 DDR2-700, DDR2-800
CK,CK Differential Slew Rate
Units
Notes
2.0 V/ns
1.5 V/ns
1.0 V/ns
∆tIS
+150
+143
+133
+120
+100
+67
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
∆tIH
+124
+119
+113
+105
+75
∆tIS
+210
+203
+193
+180
+160
+127
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
+60
-5
-14
+16
+55
+46
Command
/Adress Slew
rate(V/ns)
-13
-31
-1
+47
29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
Rev. 1.8 May 2005
- 15 -
256M gDDR2 SDRAM
K4N56163QF-GC
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = (nWR) + ( tRP/tCK) :
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the
tWR parameter stored in the MRS.
Example: For gDDR550 at t CK = 3.6 ns with tWR programmed to 4 clocks. tDAL = 4 + (18 ns / 3.6 ns) clocks =4 +(5)clocks=9clocks.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in gDDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Following figure shows a method to calculate the point when
device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consis-
tent. These notes are referenced to the “Timing parameters by speed grade” tables for gDDR2-550/700 and gDDR2-800.
VTT + 2x mV
VTT + x mV
VOH + x mV
VOH + 2x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VTT - x mV
VOL + 2x mV
VOL + x mV
T1
T2
T2
T1
VTT - 2x mV
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
<Test method for tLZ, tHZ, tRPRE and tRPST>
Rev. 1.8 May 2005
- 16 -
256M gDDR2 SDRAM
K4N56163QF-GC
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differ-
IH(ac)
ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
falling signal applied to the device under test.
level to the differential data strobe crosspoint for a
IL(ac)
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
level to the differ-
IH(dc)
ential data strobe crosspoint for a rising signal and V
test.
to the differential data strobe crosspoint for a falling signal applied to the device under
IL(dc)
Differential Input waveform timing
DQS
DQS
tDS
tDS
tDH
tDH
V
V
V
V
DDQ
(AC) min
IH
(DC) min
IH
REF
V (DC) max
IL
V (AC) max
IL
V
SS
<Data setup/hold timing>
31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test.
32. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test.
CK
CK
tIS
tIS
tIH
tIH
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
REF
V (DC) max
IL
V (AC) max
IL
V
SS
<Input setup/hold timing>
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period
of tIS + 2*tCK + tIH.
Rev. 1.8 May 2005
- 17 -
256M gDDR2 SDRAM
K4N56163QF-GC
10.0 Command Truth Table.
CKE
BA0
BA1
Function
CS
RAS
CAS
WE
A11
A10
A9 - A0 Note
Previous Current
Cycle
Cycle
(Extended) Mode Register Set
Refresh (REF)
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
1,2
X
X
X
X
X
X
1
Self Refresh Entry
L
L
X
1,8
X
H
L
X
H
H
H
H
L
Self Refresh Exit
L
H
X
X
X
X
1,7
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BA
X
X
X
L
X
X
1,2
1
L
L
H
L
H
L
BA
BA
BA
BA
BA
X
Row Address
1,2
Write
H
H
H
H
H
X
X
H
X
H
Column
Column
Column
Column
X
L
H
L
Column 1,2,3
Column 1,2,3
Column 1,2,3
Column 1,2,3
Write with Auto Precharge
Read
L
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
H
X
X
H
X
H
X
X
1
1
Device Deselect
X
X
Power Down Entry
H
L
L
X
X
X
X
X
X
X
X
1,4
1,4
Power Down Exit
Note :
H
1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write"
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
8. VREF must be maintained during Self Refresh operation.
Rev. 1.8 May 2005
- 18 -
256M gDDR2 SDRAM
K4N56163QF-GC
11.0 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
Command (N) 3
Current State 2
Action (N) 3
Note
Previous Cycle 1 Current Cycle 1
RAS, CAS, WE, CS
(N-1)
(N)
L
L
X
Maintain Power-Down
Power Down Exit
11, 13, 15
4, 8, 11,13
11, 15
Power Down
L
H
L
DESELECT or NOP
X
L
Maintain Self Refresh
Self Refresh Exit
Self Refresh
Bank(s) Active
All Banks Idle
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
4, 5,9
H
Active Power Down Entry
Precharge Power Down Entry
Self Refresh Entry
4,8,10,11,13
4, 8, 10,11,13
6, 9, 11,13
7
H
L
H
L
H
H
Refer to the Command Truth Table
Note :
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
period. Read commands may be
XSNR
issued only after t
(200 clocks) is satisfied.
XSRD
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations
are in progress. See section "Power Down" and "Self Refresh Command" for a detailed list of restrictions.
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if
the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
16. V
must be maintained during Self Refresh operation.
REF
11.1 DM Truth Table
Name (Functional)
DM
DQs
Note
-
Valid
1
Write enable
H
X
1
Write inhibit
Note :
1. Used to mask write data, provided coincident with the corresponding data
Rev. 1.8 May 2005
- 19 -
相关型号：
©2020 ICPDF网 联系我们和版权申明