K4T51083QM-GLD4 [SAMSUNG]
DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60, FBGA-60;
| 型号： | K4T51083QM-GLD4 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60, FBGA-60 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总80页 (文件大小：1416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512Mb M-die DDR2 SDRAM
Preliminary
512Mb M-die DDR2 SDRAM Specification
Version 0.92
Rev. 0.92 (Jun. 2003)
Page 1 of 80
512Mb M-die DDR2 SDRAM
Contents
Preliminary
1. Key Feature
2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pintout & Mechnical Dimension
2.2 Input/Output Function Description
2.3 Addressing
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up and Initialization
3.2.2 Programming the Mode Register
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.2.3 OCD Impedance Adjustment-Protocol
3.2.2.4 ODT (On-die termination)
3.2.3 Bank Activate Command
3.2.4 Read and write Access Modes
3.2.4.1 Posted CAS
3.2.4.2 4 bit or 8 bit Burst Mode operation
3.2.4.3 Burst Read opeartion
3.2.4.4 Burst write operation
3.2.4.5 Write data mask
3.2.5 Precharge operation
3.2.6 Auto-Precharge operation
3.2.7 Refresh
3.2.8 Self Refresh
3.2.9 Power Down mode
4. Command Truth Table
5. Absolute Maximum Rating
6. AC & DC Operating Conditions & Specifications
Rev. 0.92 (Jun. 2003)
Page 2 of 80
512Mb M-die DDR2 SDRAM
Revision History
Preliminary
Version 0.0 (Feb, 2002)
- Initial Release
Version 0.1 (Mar, 2002)
- Corrected the typo
- Add FBGA package dimension
- Delete SS800 AC parameter table
- Changed the CAS Latency & Additive Latency
CAS Latency : removed CL=2(Optional) and changed CL=5(Optional) to CL=5 & Added CL=6(Optional)
Additive Latency : Changed AL=4(Optional) to AL=4 & Added AL=5
- Delete tHZ min
- tIH/tIS for DDR2-533 : min 500ps(from TBD)
- tRRD : differentiate 1KB & 2KB page size as 7.5ns & 10ns each
- tWTR : Changed to analog value(400Mbps : 10ns, 533Mbps + : 7.5ns)
Version 0.11 (April, 2002)
- Corrected typo
- Changed Additive Latency definition as below
Old : AL=0(Default), 1,2,3,4 and 5
New : AL=0,1,2,3 and 4
- Added Comment of Max. Package dimension
Maximum Package Height : 21mm
Maximum Package Center to Center spacing : 12.8mm
Version 0.12 (May 2002)
- BL = 8 and corresponding modification
- Added reads interupted by a read and writes interrupted by a write section
Version 0.13 (September, 2002)
- tRTP concept and example timing diagrams are added
- Power down mode session is updated to describe CKE function more clearly
- Command and CKE truth table formats have been changed. No function change
- Self refresh session is updated. Instead of tXP, tXSNR and tXSRD are used. Improvement from previous
version.
- A12 of EMRS(1), Qff function is added as an optional feature.
Version 0.14 (October, 2002)
- Corrected typos
- Added VDLL(Voltage for DLL) in absolute maximum ratings.
- Removed DDR2-667, ss800 AC parameter table.
Version 0.8 (November, 2002)
- Added a description about OCD default mode.
- tRRD is changed from number of clock to “ns”, 7.5ns for 1KB page, 10ns for 2KB page size products repec-
tively.
- Added speed bin table and corresponding tRCD, tRP and tRC
- Added differential signal spec (definition and basic timing diagram, VID, VIX, VOX)
- Power up and initialization sequence is more clearly described.
- Added ODT timing at power down mode.
- Added IDD Specification Parameters and Test Conditions.
Rev. 0.92 (Jun. 2003)
Page 3 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Version 0.9 (January, 2003)
- Added additioinal notes on AC spec table
- Changed nomenclator : from DDR-II to DDR2
Version 0.91 (March 2003)
- Re-worded power-up and initialization sequence
- Added clock frequency change procedure during precharge power down in section 3.2.9 power down mode
- Added CKE Asynchronous Event in section 3.2.9
- Added full strength driver I/V characteristics
- Added overshoot/undershoo specification
- Added AC parameters: tCCD, tRAS(max), tOIT, tDelay
- Changed tWTR spec from 2*tCK to analog value
- Reordered pages and corrected typos
Version 0.92 (Jun. 2003)
- Corrected typo: from 2(optional) to reserved in CAS latency of page18
- Changed package thickness from 0.95 +0.05 to MAX. 1.20.
Rev. 0.92 (Jun. 2003)
Page 4 of 80
512Mb M-die DDR2 SDRAM
Part Number Information
Preliminary
Organization
DDR2-400 4-4-4**
K4T51043QM-GCD4
K4T51043QM-GLD4
K4T51083QM-GCD4
K4T51083QM-GLD4
K4T51163QM-GCD4
K4T51163QM-GLD4
DDR2-533 5-4-4**
K4T51043QM-GCE5
K4T51043QM-GLE5
K4T51083QM-GCE5
K4T51083QM-GLE5
K4T51163QM-GCE5
K4T51163QM-GLE5
*DDR2-533 4-4-4**
K4T51043QM-GCD5
K4T51043QM-GLD5
K4T51083QM-GCD5
K4T51083QM-GLD5
K4T51163QM-GCD5
K4T51163QM-GLD5
128Mx4
64Mx8
32Mx16
Note:
* DDR2-400 3-3-3 speed bin is covered by DDR2-533 4-4-4 speed bin
** Speed bin is in order of CL-tRCD-tRP
1
2
3
4
5
6
7
8
9
10
11
K 4 T XX XX X X X - X X XX
Memory
DRAM
Speed
Temperature & Power
Small Classification
Density and Refresh
Package
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
T : DDR2 SDRAM
8. Version
M : 1st Generation
A : 2nd Generation
B : 3rd Generation
C : 4th Generation
D : 5th Generation
E : 6th Generation
4. Density & Refresh
51 : 512M 8K/64ms
9. Package
G : BGA
10. Temperature & Power
C : (Commercial, Normal)
L : (Commercial, Low)
5. Organization
04 : x4
08 : x8
16 : x16
11. Speed
D4 : DDR2-400 4-4-4
D5 : DDR2-533 4-4-4
E5 : DDR2-533 5-4-4
6. Bank
3 : 4 Bank
4 : 8 Bank
7. Interface (VDD & VDDQ)
Q: SSTL-18(1.8V, 1.8V)
Rev. 0.92 (Jun. 2003)
Page 5 of 80
512Mb M-die DDR2 SDRAM
1.Key Features
Preliminary
Speed
DDR2-533
DDR2-533
DDR2-400
Units
4 - 4 - 4
5 - 4- 4
4 - 4 - 4
CAS Latency
tRCD(min)
tRP(min)
4
5
4
tCK
ns
15
15
60
15
15
60
20
20
65
ns
tRC(min)
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin & 267MHz fCK for 533Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Refresh and Self Refresh
Refesh Period 7.8us (8192 refresh cycles/64ms)
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA - 32Mx16
Rev. 0.92 (Jun. 2003)
Page 6 of 80
512Mb M-die DDR2 SDRAM
Description
Preliminary
The 512Mb DDR2 SDRAM chip is organized as either 32Mbit x 4 I/O x 4 banks or 16Mbit x 8 I/O x 4banks or
8Mbit x 16I/O x 4 banks device. This synchronous device achieve high speed double-data-rate transfer rates
of up to 533Mb/sec/pin (DDR2-533) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive
latency, (2) write latency = read latency -1, (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Ter-
mination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A fourteen bit address
bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 512Mb(x4) device receive 14/11/2 addressing.
The 512Mb DDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 devices are available in 60ball FBGAs(x4/8) and in 84ball FBGAs(x16). Refresh and Self
Refresh operations of 8192 refresh cycles per 64ms are supported. (Refresh Period 7.8us)
Note: The functionality described and the timing specifications included in this data sheet are for the DLL
Enabled mode of operation.
Rev. 0.92 (Jun. 2003)
Page 7 of 80
512Mb M-die DDR2 SDRAM
Preliminary
2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pinout
x4 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
VDDQ
VDD
NC
NC
VSS
A
B
C
D
E
F
DQS
VSSQ
DQS VSSQ
VSSQ DM
NC
VDDQ
DQ3
VDDQ DQ0 VDDQ
VDDQ DQ1
VSSQ
NC
DQ2
VSSQ
CK
CK
CS
NC
VDDL
VREF
VSSDL
VSS
WE
VDD
ODT
CKE
BA0
RAS
CAS
A2
NC
BA1
G
H
J
A10
A3
A1
A5
A0
VDD
VSS
VSS
A6
A4
A7
A9
K
L
A11
NC
A8
VDD
A12
NC
A13
Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x4)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
G
H
J
+
+
+
K
L
+
+
Rev. 0.92 (Jun. 2003)
Page 8 of 80
512Mb M-die DDR2 SDRAM
Preliminary
x8 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
NU/
VSSQ
DQS
VDDQ DQ0
DQ2
VSSDL CK
VDD
DQ6
VSS
DQS VDDQ
A
RDQS
DM/
VSSQ
DQ1
VSSQ
DQ7
B
C
RDQS
VDDQ
DQ4
VDDQ
DQ3
VDDQ
VSSQ
VREF
VSSQ
DQ5
D
VDDL
VSS
E
F
VDD
ODT
CK
CKE
BA0
A10
A3
WE
BA1
A1
RAS
CAS
A2
NC
CS
A0
A4
A8
G
H
J
VDD
VSS
VSS
A5
A6
A7
A9
K
A11
VDD
A12
NC
NC
A13
L
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x8)
: Populated Ball
: Depopulated Ball
+
Top View (See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+
+
+
G
H
J
+
+
+
K
L
Rev. 0.92 (Jun. 2003)
Page 9 of 80
512Mb M-die DDR2 SDRAM
Preliminary
x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
B
C
VSSQ UDQS VDDQ
VDD
NC
VSS
UDM
VDDQ
UDQ3
VSS
VSSQ
UDQ0
UDQ6 VSSQ
VDDQ UDQ1
UDQS
VDDQ
UDQ2
UDQ7
VDDQ
UDQ4
VSSQ
D
E
F
VSSQ UDQ5
VDD
NC
VSSQ LDQS VDDQ
VSSQ
LDQ6
VDDQ
LDQ4
VDDL
VSSQ LDM
LDQS
LDQ7
LDQ1
VDDQ
LDQ3
VSS
WE
VDDQ LDQ0 VDDQ
G
H
J
LDQ2
VSSQ
VREF
CKE
BA0
A10
A3
VSSQ LDQ5
VSSDL CK
VDD
ODT
K
L
CK
RAS
CAS
A2
NC
BA1
A1
CS
A0
A4
A8
NC
M
N
P
R
VDD
VSS
VSS
A5
A6
A7
A9
A11
NC
VDD
A12
NC
Notes:
VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations (x16)
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Rev. 0.92 (Jun. 2003)
Page 10 of 80
512Mb M-die DDR2 SDRAM
Preliminary
FBGA Package Dimension(x4/x8)
12.30 ± 0.10
6.40
# A1 INDEX MARK (OPTIONAL)
0.80
1.60
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
3.20
(1.00)
(2.00)
(6.15)
60-∅0.45±0.05
∅0.2 M
A B
12.30 ± 0.10
#A1
0.35±0.05
MAX.1.20
Rev. 0.92 (Jun. 2003)
Page 11 of 80
512Mb M-die DDR2 SDRAM
Preliminary
FBGA Package Dimension(x16)
12.30 ± 0.10
# A1 INDEX MARK (OPTIONAL)
6.40
0.80
1.60
4
9
8
7
6
5
3
2
1
A
B
C
D
E
F
G
H
M
J
K
N
L
P
R
3.20
(1.00)
(2.00)
(6.15)
84-∅0.45±0.05
∅0.2 M
A B
12.30 ± 0.10
#A1
0.35±0.05
MAX.1.20
Rev. 0.92 (Jun. 2003)
Page 12 of 80
512Mb M-die DDR2 SDRAM
Preliminary
2.2 Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE,
are disabled during self refresh.
CKE
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on systems with multiple Ranks. CS is considered part of the command code.
CS
Input
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM
signal for x4x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS,
LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register
(EMRS) is programmed to disable ODT.
ODT
RAS, CAS, WE
DM
Input
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also determines if the
mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
BA0 - BA2
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during
Mode Register Set commands.
A0 - A15
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in
write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to
simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to
provide differential pair signaling to the system during both reads and writes. An EMRS(1) control
bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
Input/Output
NC
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8V +/- 0.1V
DQ Ground
V
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DDQ
V
SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
DDL
V
SSDL
V
Power Supply: 1.8V +/- 0.1V
Ground
DD
V
SS
V
Reference voltage
REF
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS
if EMRS(1) [A11] = 0
if EMRS(1) [A11] = 1
x8 DQS, RDQS,
x16 LDQS and UDQS
Rev. 0.92 (Jun. 2003)
Page 13 of 80
512Mb M-die DDR2 SDRAM
Preliminary
2.3 512Mb Addressing
Configuration
# of Bank
128Mb x4
64Mb x 8
32Mb x16
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
Column Address
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration
# of Bank
64Mb x4
32Mb x 8
16Mb x16
4
4
4
Bank Address
Auto precharge
Row Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
A0 ~ A12
A0 ~ A9,A11
Column Address
1Gb
Configuration
# of Bank
256Mb x4
128Mb x 8
64Mb x16
8
8
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9,A11
A0 ~ A13
A0 ~ A9
A0 ~ A12
A0 ~ A9
Column Address
2Gb
Configuration
# of Bank
512Mb x4
256Mb x 8
128Mb x16
8
8
8
Bank Address
Auto precharge
Row Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9,A11
A0 ~ A14
A0 ~ A9
A0 ~ A13
A0 ~ A9
Column Address
4Gb
Configuration
1 Gb x4
512Mb x 8
256Mb x16
# of Bank
8
BA0 ~ BA2
A10/AP
tbd
8
BA0 ~ BA2
A10/AP
tbd
8
BA0 ~ BA2
A10/AP
tbd
Bank Address
Auto precharge
Row Address
Column Address/page size
tbd
tbd
tbd
Rev. 0.92 (Jun. 2003)
Page 14 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3. Functional Description
3.1 Simplified State Diagram
Initialization
Sequence
CKEL
OCD
calibration
Self
Refreshing
SRF
CKEH
PR
Idle
Setting
MRS
EMRS
MRS
REF
All banks
precharged
Refreshing
CKEL
CKEH
ACT
CKEL
Precharge
Power
Down
CKEL
Activating
CKEL
CKEL
Automatic Sequence
Command Sequence
Active
Power
Down
CKEH
CKEL
Bank
Active
Read
Write
Write
Read
WRA
RDA
Read
Reading
Writing
RDA
WRA
RDA
PR, PRA
Writing
with
Autoprecharge
Reading
with
Autoprecharge
PR, PRA
PR, PRA
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
Precharging
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
3.2 Basic Functionality
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of
an Active command, which is then followed by a Read or Write command. The address bits registered coinci-
dent with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank;
A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to
select the starting column location for the burst access and to determine if the auto precharge command is to
be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
3.2.1 Power up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs
may be undefined.)
- VDD, VDDL and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
or
- Apply VDD before or at the same time as VDDL.
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200µs after stable power and clock(CK, CK), then apply NOP or deselect & take CKE
high.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns
period.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and
"Low" to BA1 and A12.)
8. Issue a Mode Register Set command for “DLL reset”.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.
12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).
If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of
EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Initialization Sequence after Power Up
tCHtCL
CK
/CK
tIS
CKE
ODT
ANY
CMD
PRE
ALL
PRE
ALL
NOP
EMRS
MRS
REF
MRS
EMRS
REF
Command
EMRS
OCD
tRFC
tRP
tMRD
tRFC
tMRD
tMRD
400ns
tRP
Follow OCD
Flowchart
tOIT
min. 200 Cycle
DLL
RESET
DLL
ENABLE
OCD
Default
CAL. MODE
EXIT
3.2.2 Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR)
are user defined variables and must be programmed with a Mode Register Set (MRS) command. Addition-
ally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended
strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be pro-
grammed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or
Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the
user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when
the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be
executed any time after power-up without affecting array contents.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
3.2.2.1 DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to
make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined,
therefore the mode register must be written after power-up for proper operation. The mode register is written
by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15.
The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode reg-
ister. The mode register set command cycle time (tMRD) is required to complete the write operation to the
mode register. The mode register contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. The mode register is
divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and
8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type
is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn’t support half clock latency mode. A7
is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recov-
ery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
1
15*1~A13
A12
A
BA2*
A
BA1
BA0
Address Field
11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*1
0*1
Mode Register
0
0
PD
WR
Burst Length
DLL TM
CAS Latency
BT
Burst Length
A3
0
Burst Type
Sequential
Interleave
A8
0
DLL Reset
No
A7
0
mode
A2 A1 A0 BL
Normal
Test
1
0
0
1
1
0
1
4
8
1
Yes
1
Write recovery for autoprecharge
CAS Latency
Active power
down exit time
A12
A11 A10 A9 WR(cycles)
A6
0
A5
0
A4
Latency
*2
0
1
Fast exit(use tXARD)
Slow exit(use tXARDS)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
2
0
0
3
0
1
BA1 BA0
MRS mode
MRS
4
0
1
0
0
1
1
0
1
0
1
5
1
0
4
EMRS(1)
6
1
0
5
EMRS(2): Reserved
EMRS(3): Reserved
Reserved
Reserved
1
1
Reserved
Reserved
1
1
*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.
BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future
usage.
*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to
the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is
also used with tRP to determine tDAL.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
3.2.2.2 DDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT
value selection and additive latency. The default value of the extended mode register is not defined, therefore
the extended mode register must be written after power-up for proper operation. The extended mode register
is written by asserting low on CS, RAS, CAS, WE and high on BA0, while controlling the states of address
pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to com-
plete the write operation to the extended mode register. Mode register contents can be changed using the
same command and clock cycle requirements during normal operation as long as all banks are in the pre-
charge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver.
A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for
OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time
the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn-
chronization to occur may result in a violation of the tAC or tDQSCK parameters.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
EMRS(1) Programming
1
1
Address Field
BA1
BA0
A
15*
~A
13
A
12
A
11
A
10
A9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
BA
2*
1
Extended Mode Register
0
0
1
0*
Qoff RDQS DQS
OCD program
Rtt
Additive latency
D.I.C DLL
Rtt
BA1 BA0
MRS mode
A6 A2 Rtt (NOMINAL)
0
0
1
1
0
1
0
1
MRS
0
0
1
1
0
1
0
1
ODT Disabled
75 ohm
A0
0
DLL Enable
Enable
EMRS(1)
EMRS(2): Reserved
EMRS(3): Reserved
150 ohm
1
Disable
Reserved
A9 A8 A7 OCD Calibration Program
A5 A4 A3 Additive Latency
0
0
0
1
0
0
1
0
0
1
0
0
OCD Calibration mode exit; maintain setting
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Drive(1)
Drive(0)
1
2
Adjust modea
3
4
OCD Calibration default b
1
1
1
Reserved
Reserved
Reserved
a: When Adjust mode is issued, AL from previously set value must be applied.
b: After setting to default, OCD mode needs to be exited by setting A9-A7 to
000. Refer to the following 3.2.2.3 section for detailed information
Qoff (Optional)a
A12
Output Driver
Impedence Control
Driver
Size
A1
0
1
Output buffer enabled
Output buffer disabled
0
1
Normal
100%
60%
a. Outputs disabled - DQs, DQSs, DQSs,
Weak
RDQS, RDQS. This feature is used in
conjunction with dimm IDD meaurements when
IDDQ is not desired to be included.
A10
0
DQS
Enable
Disable
1
Strobe Function Matrix
A11
A10
(DQS Enable)
A11
0
RDQS Enable
Disable
(RDQS Enable)
RDQS/DM
DM
RDQS
Hi-z
DQS
DQS
DQS
DQS
DQS
DQS
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
DQS
Hi-z
1
Enable
DM
Hi-z
* If RDQS is enabled, the
DM function is disabled. RDQS
is active for reads and don’t
care for writes.
RDQS
RDQS
RDQS
Hi-z
DQS
Hi-z
*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.
BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future
usage.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
EMRS(2) Programming: Reserved 1
*
2
2
Address Field
BA
2
*
BA
1
1
A
12
BA
0
0
A15
*
~
A
13
A
11
A
10
A9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
2
2
Extended Mode Register(2)
1
0 *
0 *
0*
*1 : EMRS(2) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting
the mode register during initialization.
*2 : BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future
usage.
EMRS(3) Programming: Reserved 1
*
2
2
Address Field
BA2
*
BA1
A12
BA
0
A
15
*
~
A
13
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
2
2
1
Extended Mode Register(3)
1
0
0 *
0 *
0*
*1 : EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting
the mode register during initialization.
*2 : BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb DDR2 SDRAMs. A15 is reserved for future
usage.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
3.2.2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every
calibration mode command should be followed by “OCD calibration mode exit” before any other command
being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termian-
tion) should be carefully controlled depending on system environment.
MRS shoud be set before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
EMRS: Drive(0)
DQ & DQS High; DQS Low
DQ & DQS Low; DQS High
ALL OK
ALL OK
Test
Test
Need Calibration
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS :
EMRS :
Enter Adjust Mode
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs
are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMRS bit enabling RDQS operation. In
Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS signals are driven low. In
drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS signals are driven high. In adjust
mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver charac-
teristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions.
Output driver characteristics for OCD calibration default are specified in section 6. OCD applies only to nor-
mal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver
characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver
characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,
subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in
order to maintain the default or calibrated value.
Off- Chip-Driver program
A9
0
A8
0
A7
0
Operation
OCD calibration mode exit
Drive(1) DQ, DQS, (RDQS) high and DQS low
Drive(0) DQ, DQS, (RDQS) low and DQS high
Adjust mode
0
0
1
0
1
0
1
0
0
1
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit
burst code to DDR2 SDRAM as in the folowing table. For this operation, Burst Length has to be set to BL = 4
via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same
time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver out-
put impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a
given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjust-
ment is 16 and when the limit is reached, further increment or decrement code has no effect. The default set-
ting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set
value must be applied
Off- Chip-Driver Program
4bit burst code inputs to all DQs
Operation
Pull-down driver strength
DT0
0
DT1
0
DT2
0
DT3
0
Pull-up driver strength
NOP (No operation)
Increase by 1 step
Decrease by 1 step
NOP
NOP (No operation)
NOP
0
0
0
1
0
0
1
0
NOP
0
1
0
0
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
1
0
0
0
NOP
0
1
0
1
Increase by 1 step
Decrease by 1 step
0
1
1
0
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
1
1
0
0
0
1
1
0
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the fol-
lowing timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by
MRS addressing mode (ie. sequential or interleave).
OCD adjust mode
CMD
OCD calibration mode exit
NOP
EMRS
NOP
EMRS
NOP
NOP
NOP
NOP
CK
CK
WL
WR
DQS
DQS_in
tDS
tDH
DQ_in
DM
DT0
DT2
DT3
DT1
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance.
In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are
turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
OCD calibration mode exit
Enter Drive mode
CMD
EMRS
NOP
NOP
NOP
EMRS
CK
CK
Hi-Z
Hi-Z
DQS
DQS
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
DQs high for Drive(1)
DQs low for Drive(0)
DQ
tOIT
tOIT
Rev. 0.92 (Jun. 2003)
Page 24 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.2.4 ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ,
DQS/DQS, RDQS/RDQS, and DM signal for x4/x8 configurations via the ODT control pin. For x16 configu-
ration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control
pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM
controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF
REFRESH mode.
Functional Representation of ODT
VDDQ
VDDQ
sw1
sw2
Rval2
Rval2
Rval1
Rval1
DRAM
Input
Buffer
Input
Pin
sw1
Q
sw2
Q
VSS
VSS
Switch sw1 or sw2 is enabled by ODT pin.
Selection between sw1 or sw2 is determined by “
Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.
Target tt ohm) (Rval1) / 2 or (Rval2) / 2
Rtt (nominal)” in EMRS
R
(
=
ODT DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Nom
Max
Units
Notes
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt mismatch tolerance between any pull-up/pull-down pair
Rtt1(eff)
Rtt2(eff)
Rtt(mis)
60
120
-3.75
75
150
90
180
+3.75
ohm
ohm
%
1
1
1
Note 1: Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(
VIL (ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.
2 x Vm
- 1
x 100%
delta VM =
VDDQ
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
ODT Timing for Active/Standby Mode
T0
T1
T2
T3
T4
T5
T6
CK
CK
CKE
ODT
t
IS
t
IS
t
AOFD
t
AOND
Internal
Term Res.
RTT
t
t
AOF,min
AON,min
t
t
AOF,max
AON,max
ODT Timing for Powerdown Mode
T0
T1
T2
T3
T4
T5
T6
CK
CK
CKE
ODT
t
IS
t
IS
t
AOFPD,max
t
AOFPD,min
Internal
Term Res.
RTT
t
AONPD,min
AONPD,max
t
Rev. 0.92 (Jun. 2003)
Page 26 of 80
512Mb M-die DDR2 SDRAM
Preliminary
ODT timing mode switch at entering power down mode
T-5
T-4
T-3
T-2
T-1
T0
T1
T2
T3
T4
CK
CK
t
ANPD
t
IS
CKE
Entering Slow Exit Active Power Down Mode
or Precharge Power Down Mode.
t
IS
ODT
Active & Standby
mode timings to
be applied.
t
AOFD
Internal
Term Res.
RTT
t
IS
ODT
Power Down
mode timings to
be applied.
t
AOFPDmax
Internal
Term Res.
RTT
t
IS
ODT
t
AOND
Active & Standby
mode timings to
be applied.
Internal
Term Res.
RTT
t
IS
ODT
Power Down
mode timings to
be applied.
t
AONPDmax
Internal
Term Res.
RTT
Rev. 0.92 (Jun. 2003)
Page 27 of 80
512Mb M-die DDR2 SDRAM
Preliminary
ODT timing mode switch at exiting power down mode
T0
T1
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
t
IS
t
AXPD
CKE
Exiting from Slow Active Power Down Mode
or Precharge Power Down Mode.
t
IS
ODT
Active & Standby
t
AOFD
mode timings to
be applied.
Internal
Term Res.
RTT
t
IS
ODT
Power Down
mode timings to
t
AOFPDmax
be applied.
Internal
RTT
Term Res.
t
IS
Active & Standby
mode timings to
be applied.
ODT
t
AOND
Internal
RTT
Term Res.
t
IS
ODT
Power Down
mode timings to
be applied.
t
AONPDmax
Internal
RTT
Term Res.
Rev. 0.92 (Jun. 2003)
Page 28 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.3 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0
through A13 is used to determine which row to activate in the selected bank. The Bank Activate command
must be applied before any Read or Write operation can be executed. Immediately after the bank active
command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W
command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay when the R/W command is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4 are sup-
ported. Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-
tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate
commands is tRRD
.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
. . . . . . . . . .
CK / CK
Internal RAS-CAS delay (>= tRCDmin
)
Bank B
Col. Addr.
Bank A
Col. Addr.
Bank A
Row Addr.
Bank A
Row Addr.
Bank B
Row Addr.
Bank A
Addr.
Bank B
Addr.
. . . . . .
ADDRESS
CAS-CAS delay time (tCCD
)
)
RCD =1
additive latency delay (AL
Read Begins
RAS - RAS delay time (>= tRRD
)
Post CAS
Read B
Post CAS
Read A
Bank B
Activate
Bank A
Activate
Bank B
Precharge
Bank A
Active
Bank A
Precharge
. . . . . .
COMMAND
Bank Active (>= tRAS
)
Bank Precharge time (>= tRP
)
: “H” or “L”
RAS Cycle time (>= tRC
)
Rev. 0.92 (Jun. 2003)
Page 29 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a write operation (WE low).
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted
to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of
2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addres-
sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-
bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column
address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and
fourth access will also occur within this group segment, however, the burst order is a function of the starting
address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However,
in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by
a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to
CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
3.2.4.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued
immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD,
period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device.
The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses
to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1). The
Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of
additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to
semaless operation timing diagram examples in Read burst and Wirte burst section)
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CK/CK
CMD
Write
A-Bank
Active
A-Bank
Read
A-Bank
WL = RL -1 = 4
CL = 3
AL = 2
DQS/DQS
DQ
> = tRCD
RL = AL + CL = 5
Dout2
Dout3
Din0
Din1
Din2
Din3
Dout0
Dout1
> = tRAC
Example 2 Read followed by a write to the same bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CK/CK
CMD
AL = 0
Read
A-Bank
Write
A-Bank
Active
A-Bank
CL = 3
WL = RL -1 = 2
DQS/DQS
DQ
> = tRCD
RL = AL + CL = 3
Dout2
Dout3
Din0
Din1
Din2
Din3
Dout0
Dout1
> = tRAC
Rev. 0.92 (Jun. 2003)
Page 31 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.4.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst
sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for
ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write
operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode
operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is lim-
ited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop com-
mand is not supported on DDR2 SDRAM devices.
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
0, 1, 2, 3
Interleave Addressing (decimal)
0, 1, 2, 3
0 0 0
0 0 1
0 1 0
0 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1, 2, 3, 0
1, 0, 3, 2
4
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
Note: Page length is a function of I/O organization and column addressing
Rev. 0.92 (Jun. 2003)
Page 32 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.4.3 Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the
start of the command to when the data from the first cell appears on the outputs is equal to the value of the
read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven
onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each
subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register
Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register
Set (1)(EMRS(1)).
DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on
the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in sys-
tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-
plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 Kohm resis-tor to insure proper operation.
t
t
CL
CH
CK
CK
CK
DQS
DQS
DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
QH
t
QH
Data output (read) timing
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< tDQSCK
AL = 2
CL =3
RL = 5
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Rev. 0.92 (Jun. 2003)
Page 33 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< tDQSCK
CL =3
RL = 3
DQs
DOUT A0
DOUT A4
DOUT A1
DOUT A2
DOUT A3
DOUT A5
DOUT A6
DOUT A7
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
CK/CK
CMD
DQS
Post CAS
READ A
Post CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRTW (Read to Write turn around time)
RL =5
WL = RL - 1 = 4
DQ’s
DOUT A0
DIN A0
DOUT A1
DOUT A2
DOUT A3
DIN A1
DIN A2
DIN A3
The minimum time from the burst read command to the burst write command is defined by a read-to-write-
turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Rev. 0.92 (Jun. 2003)
Page 34 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Post CAS
READ A4
Post CAS
READ A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CL =3
AL = 2
RL = 5
DQs
DOUT A0
DOUT A4
DOUT A1
DOUT A2
DOUT A3
DOUT A5
DOUT A6
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4
operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
Rev. 0.92 (Jun. 2003)
Page 35 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Reads Intrrupted by a Read
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt
is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
Read B
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst
interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length
set in the mode register and not the actual burst (which is shorter because of interrupt).
Rev. 0.92 (Jun. 2003)
Page 36 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.4.4 Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined
by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven
low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins
at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is
completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins
will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the com-
pletion of the burst write to bank precharge is the write recovery time (WR).
DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the
setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-
plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS
t
t
WPST
WPRE
DQ
DM
D
D
D
D
t
t
t
DH
DH
DS
t
DS
DMin
DMin
DMin
DMin
Data input (write) timing
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
T0
CK/CK
T1
T2
T3
T4
T5
T6
T7
Tn
CMD Posted CAS
NOP
NOP
NOP
NOP
< = tDQSS
NOP
NOP
NOP
Precharge
WRITE A
Completion of
the Burst Write
DQS
DQs
WL = RL - 1 = 4
> = WR
DIN A0
DIN A1
DIN A2
DIN A3
Rev. 0.92 (Jun. 2003)
Page 37 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CAS
WRITE A
NOP
NOP
< = tDQSS
NOP
NOP
NOP
Precharge
NOP
Bank A
Activate
CMD
DQS
DQs
Completion of
the Burst Write
WL = RL - 1 = 2
> = tRP
> = WR
DIN A0
DIN A1
DIN A2
DIN A3
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK/CK
CMD
Write to Read = CL - 1 + BL/2 + tWTR
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
CL = 3
AL = 2
WL = RL - 1 = 4
RL =5
> = tWTR
DQ
DOUT A0
DIN
DOUT A1
DOUT A2
DOUT A3
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +
tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from
the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
Rev. 0.92 (Jun. 2003)
Page 38 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Seamless Burst Write Operation: RL = 5, WL = 4, BL=8
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
Post CAS
WRITE A1
Post CAS
WRITE A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = RL - 1 = 4
DQ’s
DIN A4
DIN A5
DIN A6
DIN A7
DIN A0
DIN A1
DIN A2
DIN A3
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4
operation, every four clocks for BL = 8 operation. . This operation is allowed regardless of same or different
banks as long as the banks are activated
Rev. 0.92 (Jun. 2003)
Page 39 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Writes intrrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt
is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
CMD
NOP
DQS/DQS
DQs
A2
B2
B3
B4
B5
B6
B7
A0
A1
A3
B0
B1
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with
the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Rev. 0.92 (Jun. 2003)
Page 40 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.4.5 Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with
the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though
used in a uni-directional manner, is intermally loaded identically to data bits to insure matched system timing.
DM of x4 and x16 bit organization is not used during read cycles. However DM of x8 bit organization can be
used as RDQS during read cycles by EMRS(1) settng.
Data Mask Timing
DQS
DQ
DM
tDS tDH
tDS tDH
Data Mask Function, WL=3, AL=0 shown
Case 1 : min tDQSS
CK
CK
Write
COMMAND
tWR
tDQSS
DQS
DQ
DM
Case 2 : max tDQSS
tDQSS
DQS
DQ
DM
Rev. 0.92 (Jun. 2003)
Page 41 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.5 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued.
Bank Selection for Precharge by Address Bits
A10
LOW
LOW
LOW
LOW
HIGH
BA0
LOW
BA1
LOW
Precharged Bank(s)
Bank 0 only
LOW
HIGH
Bank 1 only
HIGH
LOW
Bank 2 only
HIGH
HIGH
Bank 3 only
DON’T CARE
DON’T CARE
All Banks 0 ~ 3
Burst Read Operation Followed by Precharge
Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks
For the earliest possible precharge, the precharge command may be issued on the rising edge which is
“Additive latency(AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to
the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is sat-
isfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock
egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to
Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge com-
mand. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
Rev. 0.92 (Jun. 2003)
Page 42 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Example 1: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, t
<= 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Active
Post CAS
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
NOP
AL + BL/2 clks
> = tRP
CL = 3
AL = 1
RL =4
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
> = tRAS
> = tRTP
CL =3
Example 2: Burst Read Operation Followed by Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, t
<= 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
AL + BL/2 clks
CL = 3
AL = 1
RL =4
DQ’s
DOUT A4
DOUT A0
DOUT A5
DOUT A6
DOUT A8
DOUT A1
DOUT A2
DOUT A3
> = tRTP
second 4-bit prefetch
first 4-bit prefetch
Rev. 0.92 (Jun. 2003)
Page 43 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Example 3: Burst Read Operation Followed by Precharge:
RL = 5, AL = 2, CL = 3, BL = 4, t
<= 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Posted CAS
READ A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
AL + BL/2 clks
> = tRP
AL = 2
CL =3
RL =5
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
> = tRAS
CL =3
> = tRTP
Example 4: Burst Read Operation Followed by Precharge:
RL = 6, AL = 2, CL = 4, BL = 4, t
<= 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
READ A
Precharge A
NOP
NOP
NOP
NOP
NOP
NOP
AL + BL/2 Clks
> = tRP
AL = 2
CL =4
RL = 6
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
> = tRAS
CL =4
> = tRTP
Rev. 0.92 (Jun. 2003)
Page 44 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Example 5: Burst Read Operation Followed by Precharge:
RL = 4, AL = 0, CL = 4, BL = 8, t
> 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
AL + 2 Clks + max{tRTP;2 tCK}*
> = tRP
CL =4
RL = 4
AL = 0
DQ’s
DOUT A0
DOUT A4
DOUT A1
DOUT A2
DOUT A3
DOUT A5
DOUT A6
DOUT A8
> = tRAS
> = tRTP
second 4-bit prefetch
first 4-bit prefetch
* : rounded to next interger
Rev. 0.92 (Jun. 2003)
Page 45 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Burst Write followed by Precharge
Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge
Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion
of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.
Example 1: Burst Write followed by Precharge: WL = (RL-1) =3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
DQs
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
Completion of the Burst Write
> = tWR
WL = 3
DIN A0
DIN A1
DIN A2
DIN A3
Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T 9
CK/CK
CMD
DQS
DQs
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
Completion of the Burst Write
> = tWR
WL = 4
DIN A0
DIN A1
DIN A2
DIN A3
Rev. 0.92 (Jun. 2003)
Page 46 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.6 Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2
SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-
matically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low
when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and
the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Com-
mand is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will
execute as normal with the exception that the active bank will begin to precharge on the rising edge which is
CAS latency (CL) clock cycles before the end of the read burst.
Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto
precharge command will not begin until the last data of the burst write sequence is properly stored in the
memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles
(dependent upon CAS latency) thus improving system performance for random data access. The RAS lock-
out circuit internally delays the Precharge operation until the array restore operation has been completed
(tRAS satisfied) so that the auto precharge command may be issued with any read or write command.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than
the read with AP command if tRAS(min) and tRTP are satisfied.
If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRAS(min) is satisfied.
If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge
happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to
the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP
to the next Activate is AL + 2 + (tRTP + tRP)*, where “*” means: “rouded up to the next integer”. In any event
internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied
simultaneously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Rev. 0.92 (Jun. 2003)
Page 47 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Example 1: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 8, t
<= 2 clocks
RTP
T3
T0
T1
T2
T4
T5
T6
T7
T 8
CK/CK
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
Autoprecharge
AL + BL/2 clks
> = tRP
DQS
DQ’s
CL = 3
AL = 1
RL =4
DOUT A4
DOUT A0
DOUT A5
DOUT A6
DOUT A8
DOUT A1
DOUT A2
DOUT A3
> = tRTP
second 4-bit prefetch
first 4-bit prefetch
tRTP
Precharge begins here
Example 2: Burst Read Operation with Auto Precharge:
RL = 4, AL = 1, CL = 3, BL = 4, t
> 2 clocks
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T 8
CK/CK
CMD
DQS
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Autoprecharge
> = AL + tRTP + tRP
CL = 3
AL = 1
RL =4
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
4-bit prefetch
tRP
tRTP
Precharge begins here
Rev. 0.92 (Jun. 2003)
Page 48 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Example 3: Burst Read with Auto Precharge Followed by an activation to the Same
Bank(tRC Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t
<= 2 clocks)
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
A10 = 1
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
> = tRas(min)
Auto Precharge Begins
> = tRP
AL = 2
CL =3
RL = 5
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CL =3
> = tRC
Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same
Bank(tRP Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, t
<= 2 clocks)
RTP
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
DQS
A10 = 1
Bank A
Activate
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
> = tRas(min)
Auto Precharge Begins
> = tRP
AL = 2
CL =3
RL = 5
DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CL =3
> = tRC
Rev. 0.92 (Jun. 2003)
Page 49 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The
DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write
recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be
reactivated if the following two conditions are satisfied.
(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, tRP=3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CK/CK
A10 = 1
Bank A
Active
Post CAS
NOP
NOP
NOP
NOP
NOP
CMDWRA BankA
NOP
Auto Precharge Begins
NOP
Completion of the Burst Write
DQS/DQS
DQs
> = tRP
> = WR
WL =RL - 1 = 2
DIN A0
DIN A1
DIN A2
DIN A3
> = tRC
Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, tRP=3, BL=4
T0
T3
T4
T5
T6
T7
T8
T9
T12
CK/CK
A10 = 1
Bank A
Active
Post CAS
NOP
NOP
NOP
NOP
NOP
CMDWRA Bank A
DQS/DQS
DQs
NOP
Auto Precharge Begins
NOP
Completion of the Burst Write
> = WR
WL =RL - 1 = 4
> = tRP
DIN A0
DIN A1
DIN A2
DIN A3
> = tRC
Rev. 0.92 (Jun. 2003)
Page 50 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.7 Refresh Command
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the
Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Pre-
charge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the
device, supplies the bank address during the refresh cycle. No control of the external address bus is required
once this cycle has started.
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A
delay between the Refresh command (REF) and the next Activate command or subsequent Refresh com-
mand must be greater than or equal to the Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2
SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh
command is 9 * tREFI.
T0
T1
T2
T3
T15
T7
T8
CK/CK
High
> = tRP
> = tRFC
> = tRFC
CKE
Precharge
NOP
CBR
CBR
NOP
ANY
NOP
CMD
Rev. 0.92 (Jun. 2003)
Page 51 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.8 Self Refresh Operation
The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh
Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS
command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are “don’t
care”. The clock is internally disabled during Self Refresh Operation to save power. The user may change the
external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the device can exit Self Refresh operation. Once Self Refresh
Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a
valid command can be issued to the device. CKE must remain high for the entire Self Refresh exit period
tXSRD for proper operation. NOP or deselect commands must be registered on each positive clock edge dur-
ing the Self Refresh exit interval. ODT should also be turned off during tXSRD.
T3
T4
T5
T6
T0
T1
T2
Tm
Tn
tCK
tCH tCL
CK
CK
> = tXSNR
> = tXSRD
tRP*
CKE
ODT
tIS
tIS
tAOFD
tIS
tIH
tIS
Self
Refresh
Valid
NOP
NOP
NOP
CMD
- Device must be in the “All banks idle” state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again
when tXSRD timing is satisfied.
- tXSRD is applied for a Read or a Read with autoprecharge command
- tXSNR is applied for any command except a Read or a Read with autoprecharge command.
Rev. 0.92 (Jun. 2003)
Page 52 of 80
512Mb M-die DDR2 SDRAM
Preliminary
3.2.9 Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE
is not allowed to go low while mode register or extended mode register command time, or read or write operation
is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-
precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those opera-
tions. Timing diagrams are shown in the following pages with details for entry into power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation.
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down
occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon
entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit
active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of
the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must
be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect com-
mand). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied
with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined
at AC spec table of this data sheet.
Basic Power Down Entry and Exit timing diagram
CK/CK
t
t
t
IH
t
t
IS
t
t
t
IH
t
IH
IS
IH
IH
IS
IS
CKE
VALID
VALID
VALID
NOP
VALID
NOP
Command
t
t
t
t
XP, XARD,
CKE
t
CKE
XARDS
t
CKE
Enter Power-Down mode
Don’t Care
Exit Power-Down mode
Rev. 0.92 (Jun. 2003)
Page 53 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Read to power down entry
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CK
CK
Read operation starts with a read command and
CKE should be kept high until the end of burst operation.
CMD
CKE
DQ
RD
BL=4
AL + CL
Q
Q
Q
Q
DQS
DQS
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CMD
CKE
RD
BL=8
CKE should be kept high until the end of burst operation.
AL + CL
DQ
Q
Q
Q
Q
Q
Q
Q
Q
DQS
DQS
Read with Autoprecharge to power down entry
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
CK
CK
CMD
RDA
PRE
BL=4
AL + BL/2
with tRTP = 7.5ns
& tRAS min satisfied
CKE should be kept high
until the end of burst operation.
CKE
DQ
AL + CL
Q
Q
Q
Q
DQS
DQS
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6 Tx+7
Tx+8
Tx+9
Start internal precharge
CMD
RDA
PRE
AL + BL/2
BL=8
with tRTP = 7.5ns
CKE should be kept high
& tRAS min satisfied
until the end of burst operation.
CKE
DQ
AL + CL
Q
Q
Q
Q
Q
Q
Q
Q
DQS
DQS
Rev. 0.92 (Jun. 2003)
Page 54 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Write to power down entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
CK
CK
CMD
WR
BL=4
CKE
WL
D
D
D
D
DQ
DQS
DQS
tWTR
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2
Tx+3
Tx+4
CMD
CKE
DQ
WR
BL=8
WL
D
D
D
D
D
D
D
D
tWTR
DQS
DQS
Write with Autoprecharge to power down entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tx
Tx+1
Tx+2
Tx+3 Tx+4
Tx+5
Tx+6
CK
CK
CMD
WRA
PRE
BL=4
CKE
DQ
WL
D
D
D
D
WR*1
DQS
DQS
T0
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
Tx+1 Tx+2
Tx+3
Tx+4
CK
CK
CMD
WRA
PRE
BL=8
CKE
DQ
WL
D
D
D
D
D
D
D
D
WR*1
DQS
DQS
* 1: WR is programmed through MRS
Rev. 0.92 (Jun. 2003)
Page 55 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Refresh command to power down entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
REF
CKE can go to low one clock after an Auto-refresh command
CKE
Active command to power down entry
CMD
CKE
ACT
CKE can go to low one clock after an Active command
Precharge/Precharge all command to power down entry
PR or
PRA
CMD
CKE can go to low one clock after a Precharge or Precharge all command
CKE
MRS/EMRS command to power down entry
MRS or
EMRS
CMD
CKE
tMRD
Rev. 0.92 (Jun. 2003)
Page 56 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asyn-
chronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array. If
this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks.
Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initial-
ized (steps 4 thru 13) as described in initializaliation sequence. DRAM is ready for normal operation after the ini-
tialization sequence. See AC timing parametric table for tDelay specification
Stable clocks
tCK
CK#
CK
tDelay
CKE
CKE asynchronously drops low
Clocks can be turned
off after this point
Rev. 0.92 (Jun. 2003)
Page 57 of 80
512Mb M-die DDR2 SDRAM
Preliminary
Input Clock Frequency Change during Precharge Power Down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level.
A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input
clock frequency is allowed to change only within minimum and maximum operating frequency specified for the
particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power
down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new
clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During
DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
Clock Frequency Change in Precharge Power Down Mode
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2 Ty+3 Ty+4
Tz
CK
CK
DLL
RESET
NOP
NOP
NOP
NOP
NOP
Valid
CMD
CKE
Frequency Change
Occurs here
200 Clocks
ODT
tRP
tAOFD
tXP
ODT is off during
DLL RESET
Stable new clock
before power down exit
Minmum 2 clocks
required before
changing frequency
Rev. 0.92 (Jun. 2003)
Page 58 of 80
512Mb M-die DDR2 SDRAM
Preliminary
No Operation Command
The No Operation Command should be used in cases when the DDR2 SDRAM is in an idle or a wait state.
The purpose of the No Operation Command (NOP) is to prevent the DDR2 SDRAM from registering any
unwanted commands between operations. A No Operation Command is registered when CS is low with RAS,
CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previ-
ous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command
occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t
cares.
Rev. 0.92 (Jun. 2003)
Page 59 of 80
512Mb M-die DDR2 SDRAM
Preliminary
4. Command Truth Table.
4.1 Command truth table.
CKE
BA0
Function
CS
RAS
CAS
WE BA1 A15-A11 A10 A9 - A0 Notes
BA2
Previous
Cycle
Current
Cycle
(Extended) Mode Register Set
Refresh (REF)
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
1,2
1
X
X
X
X
X
X
Self Refresh Entry
L
L
X
1
X
H
L
X
H
H
H
H
L
Self Refresh Exit
L
H
X
X
X
X
1,7
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BA
X
X
X
L
H
X
X
1,2
1
L
L
L
H
L
BA
Row Address
1,2
Write
H
H
H
H
H
X
X
H
X
H
BA Column
BA Column
BA Column
BA Column
L
H
L
Column 1,2,3,
Column 1,2,3,
Column 1,2,3
Column 1,2,3
Write with Auto Precharge
Read
L
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
H
X
X
H
X
H
X
X
X
X
X
X
1
1
Device Deselect
Power Down Entry
Power Down Exit
H
L
L
X
X
X
X
X
X
X
X
1,4
1,4
H
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-
rupted by a Write" in section 2.2.4 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements outlined in section 2.2.7.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 2.2.2.4.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
Rev. 0.92 (Jun. 2003)
Page 60 of 80
512Mb M-die DDR2 SDRAM
Preliminary
4.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
1
3
Command (N)
2
3
Notes
Current State
Power Down
Action (N)
1
Previous Cycle
(N-1)
Current Cycle
RAS, CAS, WE, CS
X
(N)
L
L
L
Maintain Power-Down
Power Down Exit
11, 13, 15
4, 8, 11,13
11, 15
H
L
DESELECT or NOP
X
L
Maintain Self Refresh
Self Refresh Exit
Self Refresh
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
4, 5,9
Bank(s) Active
All Banks Idle
H
H
H
H
Active Power Down Entry
Precharge Power Down Entry
Self Refresh Entry
4,8,10,11,13
4, 8, 10,11,13
6, 9, 11,13
7
L
L
H
Refer to the Command Truth Table
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
period.
XSNR
Read commands may be issued only after t
(200 clocks) is satisfied.
XSRD
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or
Precharge operations are in progress. See section 2.2.9 "Power Down" and 3.2.8 "Self Refresh Command" for a detailed list of
restrictions.
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 2.2.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh
requirements outlined in section 2.2.7.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or
low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
4.3 DM Truth Table
Name (Functional)
Write enable
Write inhibit
DM
-
DQs
Note
1
Valid
H
X
1
1. Used to mask write data, provided coinsident with the corresponding data
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
5. Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
V
Notes
1
- 1.0 V ~ 2.3 V
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
1
1
VIN VOUT
,
V
TSTG
°C
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
6. AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
V
V
Supply Voltage
1.7
1.8
1.8
1.9
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1.2
3
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Input DC Logic Level
Symbol
IH(dc)
Parameter
dc input logic high
dc input logic low
Min.
Max.
Units
V
Notes
V
VREF + 0.125
VDDQ + 0.3
VIL(dc)
- 0.3
VREF - 0.125
V
Input AC Logic Level
Symbol
VIH (ac)
Parameter
Min.
Max.
-
Units
V
Notes
VREF + 0.250
ac input logic high
ac input logic low
VIL (ac)
-
VREF - 0.250
V
AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Notes
V
V
0.5 * V
1.0
V
V
1
1
REF
DDQ
Input signal maximum peak to peak swing
Input signal minimum slew rate
SWING(MAX)
SLEW
Notes:
1.0
V/ns
2, 3
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
level applied to the device under test.
REF
max to V
min for rising edges and the
IL(dc)
IH(ac)
range from V
min to V
max for falling edges as shown in the below figure.
IL(ac)
IH(dc)
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
Start of Rising Edge Input Timing
Start of Falling Edge Input Timing
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
min
min
V
SWING(MAX)
max
max
IL(dc)
IL(ac)
SS
delta TF
VIH
delta TR
Rising Slew =
V
min - V
max
min - VIL
max
IH(ac)
IL(dc)
(dc)
(ac)
Falling Slew =
delta TR
delta TF
< AC Input Test Signal Waveform >
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Differential input AC logic Level
Symbol
VID (ac)
Parameter
Min.
0.5
Max.
Units
V
Notes
VDDQ + 0.6
1
2
ac differential input voltage
ac differential cross point voltage
VIX (ac)
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
V
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
V
DDQ
V
TR
Crossing point
V
ID
V
V
IX or OX
V
CP
V
SSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,
LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)
- V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Differential AC output parameters
Symbol
VOX (ac)
Parameter
Min.
Max.
Units
V
Notes
1
0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125
ac differential cross point voltage
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Input Signal Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS,
CAS, WE, CKE, ODT
Parameter
Specification
DDR2-400
0.9V
DDR2-533 DDR2-667
Maximum peak amplitude allowed for overshoot area (See Figure 1):
Maximum peak amplitude allowed for undershoot area (See Figure 1):
Maximum overshoot area above VDD (See Figure1).
0.9V
0.9V
0.9V
0.9V
0.9V
0.75 V-ns
0.75 V-ns
0.56 V-ns
0.56 V-ns
0.45 V-ns
0.45 V-ns
Maximum undershoot area below VSS (See Figure 1).
Maximum Amplitude
Overshoot Area
VDD
Volts
(V)
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Address and Control Pins
AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK,
CK
Parameter
Specification
DDR2-533
0.9V
DDR2-400
0.9V
DDR2-667
0.9V
Maximum peak amplitude allowed for overshoot area (See Figure 2):
Maximum peak amplitude allowed for undershoot area (See Figure 2):
Maximum overshoot area above VDDQ (See Figure 2).
0.9V
0.9V
0.9V
0.38 V-ns
0.38 V-ns
0.28 V-ns
0.28 V-ns
0.23 V-ns
0.23 V-ns
Maximum undershoot area below VSSQ (See Figure 2).
Maximum Amplitude
Overshoot Area
VDDQ
Volts
(V)
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Power and ground clamps are implemented on the following input only pins:
1. BA0-BA2
2. A0-A15
3. RAS
4. CAS
5. WE
6. CS
7. ODT
8. CKE
V-I Characteristics for input only pins with clamps
Minimum Ground
Clamp Current (mA)
0
Voltage across
clamp(V)
Minimum Power
Clamp Current (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Output Buffer Levels
Output AC Test Conditions
Symbol
VOH
Parameter
SSTL_18 Class II
Units
V
Notes
Minimum Required Output Pull-up under AC Test Load
Maximum Required Output Pull-down under AC Test Load
Output Timing Measurement Reference Level
V
+ 0.603
- 0.603
TT
VOL
V
V
TT
VOTR
0.5 * V
V
1
DDQ
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTl_18 Class II
- 13.4
Units
mA
Notes
1, 3, 4
2, 3, 4
13.4
mA
1.
2.
V
= 1.7 V; V
= 1420 mV. (V
- V
)/I must be less than 21 ohm for values of V
between V
and V
- 280
DDQ
DDQ
OUT
OUT
DDQ OH
OUT
DDQ
mV.
V
= 1.7 V; V
= 280 mV. V
/I must be less than 21 ohm for values of V
between 0 V and 280 mV.
DDQ
OUT
OUT OL
OUT
3. The dc value of V
applied to the receiving device is set to V
TT
REF
4. The values of I
and I
are based on the conditions given in Notes 1 and 2. They are used to test device drive current
OH(dc)
OL(dc)
capability to ensure V min plus a noise margin and V max minus a noise margin are delivered to an SSTL_18 receiver. The
IH
IL
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
OCD defalut characteristics
Description
Parameter
Min
12.6
Nom
18
Max
23.4
Unit
Notes
Output impedance
ohms 1,2
ohms 1,2,3
V/ns 1,4,5
Pull-up and pull-
down mismatch
0
4
Output slew rate
tbd
tbd
Note 1: Absolute Specifications (0°C ≤ TCASE ≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol
must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and
voltage.
Note 4: Slew rate measured from vil(ac) to vih(ac).
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew
rate as measured from AC to AC. This is guaranteed by design and characterization.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Table 1. Full Strength Default Pulldown Driver Characteristics
Pulldow n Current (mA)
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Voltage (V) Minimum (23.4 Ohms)
Maximum (12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
8.5
11.3
16.5
21.2
25.0
28.3
30.9
33.0
34.5
35.5
36.1
36.6
36.9
37.1
37.4
37.6
37.7
37.9
11.8
16.8
22.1
27.6
32.4
36.9
40.9
44.6
47.7
50.4
52.6
54.2
55.9
57.1
58.4
59.6
60.9
15.9
23.8
31.8
39.7
47.7
55.0
62.3
69.4
75.3
80.5
84.6
87.7
90.8
92.9
94.9
97.0
99.1
101.1
12.1
14.7
16.4
17.8
18.6
19.0
19.3
19.7
19.9
20.0
20.1
20.2
20.3
20.4
20.6
Figure 1. DDR2 Default Pulldown Characteristics for Full Strength Driver
120
100
80
60
40
20
0
Maximum
Nominal
Default
High
Nominal
Default
Low
Minimum
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
VOUT to VSSQ (V)
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Table 2. Full Strength Default Pullup Driver Characteristics
Pullup Current (mA)
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Voltage (V) Minimum (23.4 Ohms)
Maximum (12.6 Ohms)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-8.5
-11.1
-16.0
-20.3
-24.0
-27.2
-29.8
-31.9
-33.4
-34.6
-35.5
-36.2
-36.8
-37.2
-37.7
-38.0
-38.4
-38.6
-11.8
-17.0
-22.2
-27.5
-32.4
-36.9
-40.8
-44.5
-47.7
-50.4
-52.5
-54.2
-55.9
-57.1
-58.4
-59.6
-60.8
-15.9
-23.8
-31.8
-39.7
-47.7
-55.0
-62.3
-69.4
-75.3
-80.5
-84.6
-87.7
-90.8
-92.9
-94.9
-97.0
-99.1
-101.1
-12.1
-14.7
-16.4
-17.8
-18.6
-19.0
-19.3
-19.7
-19.9
-20.0
-20.1
-20.2
-20.3
-20.4
-20.6
Figure 2. DDR2 Default Pullup Characteristics for Full Strength Output Driver
0
-20
-40
Minimum
Nominal
Default
Low
-60
Nominal
Default
High
-80
-100
-120
Maximum
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VDDQ to VOUT (V)
Rev. 0.92 (Jun. 2003)
Page 69 of 80
512Mb M-die DDR2 SDRAM
Preliminary
DDR2 SDRAM Default Output Driver V–I Characteristics
DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by
the EMRS1 bits A7-A9 = ‘111’. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and
2 show the same data in tabular format suitable for input into simulation tools. The driver characteristics
evaluation conditions are:
Nominal Default 25 oC (T case), VDDQ = 1.8 V, typical process
Minimum TBD oC (T case), VDDQ = 1.7 V, slow–slow process
Maximum 0 oC (T case), VDDQ = 1.9 V, fast–fast process
Default Output Driver Characteristic Curves Notes:
1) The full variation in driver current from minimum to maximum process, temperature, and voltage will
lie within the outer bounding lines of the V–I curve of figures 1 and 2.
2) It is recommended that the ”typical” IBIS V–I curve lie within the inner bounding lines of the V–I curves
of figures 1 and 2.
Table 3. Full Strength Calibrated Pulldown Driver Characteristics
Calibrated Pulldow n Current (mA)
Nominal Minimum Nominal Low (18.75
Nominal High (17.25 Nominal Maximum (15
Voltage (V)
Nominal (18 ohms)
(21 ohms)
ohms)
ohms)
ohms)
0.2
0.3
0.4
9.5
10.7
16.0
21.0
11.5
16.6
21.6
11.8
17.4
23.0
13.3
20.0
27.0
14.3
18.7
Table 4. Full Strength Calibrated Pullup Driver Characteristics
Calibrated Pullup Current (mA)
Nominal Minimum Nominal Low (18.75
Nominal High (17.25Nominal Maximum (15
Voltage (V)
Nominal (18 ohms)
(21 ohms)
ohms)
ohms)
ohms)
0.2
0.3
0.4
-9.5
-14.3
-18.7
-10.7
-16.0
-21.0
-11.4
-16.5
-21.2
-11.8
-17.4
-23.0
-13.3
-20.0
-27.0
DDR2 SDRAM Calibrated Output Driver V–I Characteristics
DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by
the procedure outlined in section 2.2.2.3, Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4
show the data in tabular format suitable for input into simulation tools. The nominal points represent a
device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be
achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only
(i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system
calibration error needs to be added to these values. It must be understood that these V-I curves as repre-
sented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system cali-
bration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the
calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the cali
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
bration procedure is used, it is possible to cause the device to operate outside the bounds of the default
device characteristics tables and figures. In such a situation, the timing parameters in the specification can-
not be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the
minimum and maximum default values at all times. If this can’t be guaranteed by the system calibration pro-
cedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the
default values be used. The nominal maximum and minimum values represent the change in impedance
from nominal low and high as a result of voltage and temperature change from the nominal condition to the
maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as
much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evalu-
ation conditions are:
Nominal 25 oC (T case), VDDQ = 1.8 V, typical process
Nominal Low and Nominal High 25 oC (T case), VDDQ = 1.8 V, any process
Nominal Minimum TBD oC (T case), VDDQ = 1.7 V, any process
Nominal Maximum 0 oC (T case), VDDQ = 1.9 V, any process
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Sym-
bol
Proposed Conditions
DDR2-
400
DDR2-
533
DDR2-
533
Units
Notes
(CL=4)
(CL=4)
(CL=5)
IDD0
Operating one bank active-precharge current;
TBD
TBD
TBD
mA
t
t
t
t
t
t
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA;
TBD
TBD
TBD
mA
BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
t
RCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
IDD2P
IDD2Q
IDD2N
IDD3P
Precharge power-down current;
All banks idle;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
t
t
CK = CK(IDD);
CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby current;
All banks idle;
t
t
CK = CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle;
t
t
CK = CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
Fast PDN Exit
MRS(12) = 0mA
t
t
CK = CK(IDD);
CKE is LOW;
Other control and address bus inputs are STA-
BLE;
Slow PDN Exit
MRS(12) = 1mA
Data bus inputs are FLOATING
IDD3N
Active standby current;
All banks open;
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
IDD4W
Operating burst write current;
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
t
t
t
t
t
t
CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
IDD5B
Burst auto refresh current;
mA
t
t
CK = CK(IDD);
t
Refresh command at every RFC(IDD) interval;
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD6
Self refresh current;
CK and CK\ at 0V;
CKE ≤ 0.2V;
Other control and address bus inputs are
FLOATING;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Normal
Low Power
Data bus inputs are FLOATING
IDD7
Operating bank interleave read current;
mA
All bank interleaving reads, IOUT = 0mA;
t
t
BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD);
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD =
t
1* CK(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
- Refer to the following page for detailed timing conditions
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi-
nations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
For purposes of IDD testing, the following parameters are to be utilized
DDR2-533
4-4-4
DDR2-400
Parameter
5-4-4
5
4-4-4
4
Units
CL(IDD)
4
tCK
t
15
15
20
RCD(IDD)
ns
ns
t
60
60
7.5
10
65
7.5
10
5
RC(IDD)
t
ns
ns
RRD(IDD)-x4/x8
7.5
t
RRD(IDD)-x16
10
t
3.75
3.75
45
CK(IDD)
RASmin(IDD)
ns
ns
t
45
15
45
20
105
t
15
ns
ns
RP(IDD)
RFC(IDD)-512Mb
t
105
105
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-533 5/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
Timing Patterns for 8 bank devices x4/x8
-DDR2-400 and DDR2-533 all bins
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Input/Output Capacitance
Parameter
Symbol
CCK
CDCK
CI
Min
1.5
x
Max
2.5
Units
pf
Input capacitance, CK and CK
Input capacitance delta, CK and CK
0.25
2.5
pF
pf
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.5
x
CDI
0.25
4.0
pF
pF
pF
CIO
3.0
x
CDIO
0.5
Electrical Characteristics & AC Timing for DDR2-400/DDR2-533
(0 °C < TCASE < TBD °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
75
512Mb
105
1Gb
127.5
7.8
2Gb
195
7.8
4Gb
tbd
Units
ns
Auto refresh to active/auto refresh command time
Average periodic refresh interval
tRFC
tREFI
7.8
7.8
7.8
µs
Speed Bins and CL, tRCD, tRP and tRC for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-533(D5)
DDR2-533(E5)
DDR2-400(D4)
Units
4 - 4 - 4
5 - 4- 4
4 - 4 - 4
min
max
min
max
min
max
5
3.75
-
8
8
-
-
5
-
-
-
8
-
ns
ns
ns
ns
ns
ns
8
8
5
3.75
15
15
60
-
15
15
60
20
20
65
tRP
tRC
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Symbol
Unit
s
Notes
Parameter
DDR2-400
DDR2-533
min
max
min
max
DQ output access time from
CK/CK
tAC
-600
+600
-500
+500
ps
ps
DQS output access time from
CK/CK
tDQSCK
-500
+500
-450
+450
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
CK high-level width
CK low-level width
tCH
tCL
tHP
tCK
tDH
0.45
0.45
0.55
0.55
x
0.45
0.45
0.55
0.55
x
tCK
tCK
CK half period
min(tCL,tCH)
5000
min(tCL,tCH)
3750
ps
ps
ps
19,20
23
Clock cycle time, CL=x
DQ and DM input hold time
8000
x
8000
x
400
350
14,15,
16
DQ and DM input setup time
tDS
400
0.6
x
350
0.6
x
ps
tCK
tCK
ps
14,15,
16
Control & Address input pulse
width for each input
tIPW
tDIPW
tHZ
x
x
DQ and DM input pulse width for
each input
0.35
x
x
0.35
x
x
Data-out high-impedance time
from CK/CK
tAC max
tAC max
350
tAC max
tAC max
300
Data-out low-impedance time from
CK/CK
tLZ
tAC min
x
tAC min
x
ps
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
ps
21
20
DQ hold skew factor
tQHS
tQH
x
450
x
x
400
x
ps
ps
DQ/DQS output hold time from
DQS
tHP - tQHS
tHP - tQHS
Write command to first DQS
latching transition
tDQSS
WL - 0.25
WL + 0.25
WL - 0.25
WL + 0.25
tCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
x
x
x
0.35
0.35
0.2
0.2
2
x
x
x
x
x
tCK
tCK
tCK
tCK
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
tDSH
Mode register set command cycle
time
tMRD
Write preamble setup time
Write postamble
tWPRES
tWPST
tWPRE
tIH
0
x
0.6
x
0
x
0.6
x
ps
tCK
tCK
ps
0.4
0.4
600
0.4
0.4
500
18
Write preamble
Address and control input hold
time
x
x
13,15,
17
Address and control input setup
time
tIS
600
x
500
x
ps
13,15,
17
Read preamble
tRPRE
tRPST
tRAS
0.9
0.4
45
1.1
0.6
0.9
0.4
45
1.1
0.6
tCK
tCK
ns
Read postamble
Active to precharge command
70000
70000
11
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Preliminary
Active to active command period
for 1KB page size products
tRRD
7.5
10
x
7.5
10
x
ns
12
Active to active command period
for 2KB page size products
tRRD
x
x
ns
12
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
15
2
15
tCK
ns
x
x
Auto precharge write recovery +
precharge time
tDAL
tWR+tRP*
x
tWR+tRP*
x
tCK
22
11
Internal write to read command
delay
tWTR
tRTP
10
x
7.5
x
ns
ns
Internal read to precharge
command delay
7.5
7.5
Exit self refresh to a non-read
command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read
command
200
2
200
2
tCK
tCK
tCK
tCK
Exit precharge power down to any
non-read command
x
x
x
Exit active power down to read
command
tXARD
tXARDS
2
2
x
9
Exit active power down to read
command
6 - AL
6 - AL
9, 10
(Slow exit, Lower power)
t
CKE minimum pulse width
(high and low pulse width)
3
3
tCK
CKE
t
ODT turn-on delay
2
2
2
2
tCK
ns
AOND
t
ODT turn-on
tAC(min)
tAC(min)+2
tAC(max)+1
tAC(min)
tAC(min)+2
tAC(max)+1
24
25
AON
t
ODT turn-on(Power-Down mode)
2tCK+tAC(m
ax)+1
2tCK+tAC(
max)+1
ns
AONPD
t
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
AOFD
t
tAC(max)+ 0.6
tAC(min)
tAC(max)+
0.6
tAC(min)
AOF
t
ODT turn-off (Power-Down mode)
tAC(min)+2
2.5tCK+tAC(
max)+1
tAC(min)+2
2.5tCK+tAC
(max)+1
ns
AOFPD
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
3
tCK
tCK
ns
8
8
0
12
0
12
Minimum time clocks remains ON
after CKE asynchronously drops
LOW
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
23
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
Rev. 0.92 (Jun. 2003)
Page 77 of 80
512Mb M-die DDR2 SDRAM
Preliminary
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK - CK = +500 mV
(250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
between DQS and DQS for differential strobe.
2. DDR2 SDRAM AC timing reference load
Figure AA represents the timing reference load used in defining the relevant timing parameters of the part.
It is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to cor-
relate the timing reference load to a system environment. Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS
Output
DUT
V
= V
/2
TT
DDQ
RDQS
RDQS
Timing
reference
point
25Ω
Figure AA : AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure.
VDDQ
DUT
DQ
Output
DQS, DQS
V
= V
/2
TT
DDQ
RDQS, RDQS
25Ω
Test point
Slew Rate Test Load
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm
Rev. 0.92 (Jun. 2003)
Page 78 of 80
512Mb M-die DDR2 SDRAM
Preliminary
resisor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS/
DQS
DQS
t
t
WPST
WPRE
DQ
DM
D
D
D
D
t
t
t
DH
DH
DS
t
DS
DMin
DMin
DMin
DMin
Figure XX -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
QH
t
QH
Figure YY-- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full volt-
age range specified.
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
Rev. 0.92 (Jun. 2003)
Page 79 of 80
512Mb M-die DDR2 SDRAM
Preliminary
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for
other slew rate values.
14. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0
V/ns. See System Derating for other slew rate values.
15. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS
signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single
ended mode. See System Derating for other slew rate values.
16. tDS and tDH (data setup and hold) derating
tbd
17. tIS and tIH (input setup and hold) derating
tbd
18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
19. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as pro-
vided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For
example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and
less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.
20. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers for any given cycle.
22. t DAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the
application clock period. nWR refers to the t WR parameter stored in the MRS.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)
clocks =4 +(4)clocks=8clocks.
23. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In
case of clock frequency change during precharge power-down, a specific procedure is required as described
in section 3.2.9.
24. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
25. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Rev. 0.92 (Jun. 2003)
Page 80 of 80
相关型号：
K4T51083QQ-BCF70
DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60
SAMSUNG
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