K6E0808C1E-TL12T [SAMSUNG]
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28;型号: | K6E0808C1E-TL12T |
厂家: | SAMSUNG |
描述: | Standard SRAM, 32KX8, 12ns, CMOS, PDSO28 静态存储器 光电二极管 |
文件: | 总9页 (文件大小:181K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
Document Title
32Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
History
Remark
Preliminary
Final
Draft Data
Aug. 1. 1998
Nov. 2. 1998
Feb. 25. 1999
Initial release with Preliminary.
Release to Final Data Sheet.
2.1. Add Low Power Version.
2.2. Add data retention charactoristic.
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 2.0
Feburary 1999
- 1 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10, 12, 15ns(Max.)
• Low Power Dissipation
The K6E0808C1E is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
K6E0808C1E uses 8 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG¢s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6E0808C1E is packaged
in a 300mil 28-pin plastic SOJ or TSOP1 forward.
Standby (TTL)
(CMOS) : 2mA(Max.)
0.6mA(Max.) L-ver. Only
: 20mA(Max.)
Operating K6E0808C1E-10 : 80mA(Max.)
K6E0808C1E-12 : 80mA(Max.)
K6E0808C1E-15 : 80mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention : L-Ver. only
• Standard Pin Configuration
PIN CONFIGURATION(Top View)
OE
A11
A9
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A8
K6E0808C1E-J : 28-SOJ-300
K6E0808C1E-T : 28-TSOP1-0813. 4F
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
5
6
7
8
TSOP1
9
ORDERING INFORMATION
10
11
12
13
14
K6E0808C1E-C10/C12/C15
K6E0808C1E-I10/I12/I15
Commercial Temp.
Industrial Temp.
A1
A2
FUNCTIONAL BLOCK DIAGRAM
A14
1
2
3
4
5
6
7
8
9
28 Vcc
27 WE
26 A13
25 A8
A12
A7
A6
A5
A4
A3
A2
A1
Clk Gen.
Pre-Charge-Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
24 A9
23 A11
22 OE
21 A10
20 CS
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
Memory Array
512 Rows
64x8 Columns
SOJ
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O8
CLK
Gen.
PIN FUNCTION
A9
A10 A11 A12 A13 A14
Pin Name
A0 - A14
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CS
WE
OE
CS
OE
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
I/O1 ~ I/O8
VCC
VSS
Revision 2.0
Feburary 1999
- 2 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
TA
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Commercial
Industrial
TA
-40 to 85
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Supply Voltage
Symbol
Min
4.5
Typ
Max
Unit
V
VCC
5.0
5.5
Ground
VSS
0
0
-
0
V
V
Input High Voltage
Input Low Voltage
VIH
2.2
VCC+0.5***
0.8
V
VIL
-0.5**
-
*
The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0(Pulse Width£7ns) for I£20mA.
*** VIH(Max) = VCC+2.0V(Pulse Width£7ns) for I£20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)
Min
Max
Parameter
Input Leakage Current
Output Leakage Current
Symbol
ILI
Test Conditions
VIN = VSS to VCC
Unit
mA
-2
2
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL,
IOUT=0mA
10ns
12ns
15ns
-
80
80
80
20
2
mA
-
-
Standby Current
ISB
Min. Cycle, CS=VIH
-
mA
mA
ISB1
f=0MHz, CS³ VCC-0.2V,
VIN³ VCC-0.2V or VIN£0.2V
Normal
L-Ver
-
-
-
0.6
0.4
-
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
V
V
V
IOH=-4mA
IOH1=0.1mA
2.4
-
VOH1**
3.95
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
VI/O=0V
MIN
Max
8
Unit
Input/Output Capacitance
Input Capacitance
CI/O
-
-
pF
pF
VIN=0V
CIN
7
* Capacitance is sampled and not 100% tested.
Revision 2.0
Feburary 1999
- 3 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5V
+5.0V
480W
480W
DOUT
DOUT
255W
255W
30pF*
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
K6E0808C1E-10
K6E0808C1E-12
K6E0808C1E-15
Unit
Symbol
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
-
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
-
3
-
3
-
3
-
tOLZ
tHZ
0
-
0
-
0
-
0
5
0
6
0
7
tOHZ
tOH
tPU
tPD
0
5
0
6
0
7
3
-
3
-
3
-
0
-
0
-
0
-
-
10
-
12
-
15
* The above parameters are also guaranteed at industrial temperature range.
Revision 2.0
Feburary 1999
- 4 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
WRITE CYCLE*
Parameter
Write Cycle Time
K6E0808C1E-10
K6E0808C1E-12
K6E0808C1E-15
Unit
Symbol
Min
10
8
Max
Min
12
9
Max
Min
15
10
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
Chip Select to End of Write
Address Setup Time
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
8
9
10
10
15
0
8
9
10
0
12
0
Write to Output High-Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
6
7
0
0
0
tOW
0
0
0
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
Valid Data
Data Out
Previous Valid Data
Revision 2.0
Feburary 1999
- 5 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
CS
tAA
tCO
tHZ(3,4,5)
tOHZ
tOE
OE
tOLZ
tLZ(4,5)
tOH
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
OE
tWR(5)
tAW
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Valid Data
Data in
tOHZ(6)
High-Z(8)
Data out
Revision 2.0
Feburary 1999
- 6 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
CS
tWR(5)
tAW
tCW(3)
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Valid Data
Data in
Data out
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
tWP(2)
CS
tAS(4)
WE
tDH
tDW
High-Z
High-Z
Data in
Data out
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end
of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Revision 2.0
Feburary 1999
- 7 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
VCC for Data Retention
Data Retention Current
Symbol
VDR
Test Condition
CS³ VCC-0.2V
Min.
2.0
-
Typ.
Max.
5.5
Unit
V
-
-
IDR
VCC=3.0V, CS³ VCC-0.2V
VIN³ VCC-0.2V or VIN£0.2V
0.5
mA
Data Retention Set-Up Time
Recovery Time
tSDR
tRDR
See Data Retention
Wave form(below)
0
5
-
-
-
-
ns
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-Ver only.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
VIH
VDR
CS³ VCC - 0.2V
CS
GND
Revision 2.0
Feburary 1999
- 8 -
For Cisco
CMOS SRAM
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
Units:millimeters/Inches
PACKAGE DIMENSIONS
28-SOJ-300
#28
#15
6.86 ±0.25
0.270 ±0.010
8.51 ±0.12
0.335 ±0.005
+0.10
-0.05
0.20
+0.004
0.008-0.002
#1
#14
0.69
0.027
MIN
18.82
MAX
0.741
18.41 ±0.12
0.725 ±0.005
1.30
0.051
(
)
0.10
0.004
3.76
0.148
MAX
MAX
(
)
0.051
+0.10
-0.05
+0.004
-0.002
+0.10
-0.05
+0.004
-0.002
0.71
0.43
0.95
0.0375
1.27
0.050
(
)
0.017
0.028
28-TSOP1-0813.4F
13.40 ±0.20
0.528 ±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
0.425
0.017
(
)
#1
#28
0.55
0.0217
#14
#15
1.00 ±0.10
0.039 ±0.004
0.25
TYP
11.80 ±0.10
0.465 ±0.004
0.05
0.002
0.010
+0.10
-0.05
+0.004
-0.002
MIN
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 2.0
Feburary 1999
- 9 -
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