K6F2008V2M-TI85 [SAMSUNG]

Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;


型号：	K6F2008V2M-TI85
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32 静态存储器光电二极管
文件：	总9页 (文件大小：138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

Document Title

256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

0.1

Initial draft

October 2, 1996

Advance

Revise

December 1, 1996

Preliminary

- Remove sTSOP1 from product

- Rename high power product to low power.

ISB1=10.0mA(Max)

- Add super low power version with special handling

ISB1=1.0mA(Max)

- Remove 70ns and add 85ns part on KM68F2000 Family

1.0

2.0

Finalize

April 11, 1997

March 5, 1998

Final

Revise

- Change datasheet format

- Remove reverse type package from product

- Remove reseved speed bin(100ns)

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

• Process Technology: Full CMOS

• Organization: 256Kx8

The K6F2008V2M, K6F2008S2M and K6F2008R2M families

are fabricated by SAMSUNG¢s advanced Full CMOS process

technology. The families support various operating temperature

ranges and have various package types for user flexibility of

system design. The families also supports low data retention

voltage for battery back-up operation with low data retention

current.

• Power Supply Voltage

K6F2008V2M Family: 3.0 ~ 3.6V

K6F2008S2M Family: 2.3 ~ 3.3V

K6F2008R2M Family: 1.8 ~ 2.7V

• Low Data Retention Voltage: 1.5V(Min)

• Three state output and TTL Compatible

• Package Type: 32-TSOP1-0820F

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature Vcc Range

Speed(ns)

PKG Type

Standby

Operating

(ISB1, Max) (ICC2, Max)

70¹⁾/85@VCC=3.3±0.3V

85@VCC=3.0±0.3V

K6F2008V2M-C

K6F2008S2M-C

3.0~3.6V

2.3~3.3V

60mA

55mA

30mA

Commercial(0~70°C)

Industrial(-40~85°C)

120¹⁾/150@VCC=2.5±0.2V

300¹⁾@VCC=2.0±0.2V

K6F2008R2M-C

K6F2008V2M-I

1.8~2.7V

3.0~3.6V

15mA

10mA²⁾

32-TSOP1-F

70¹⁾/85@VCC=3.3±0.3V

85@VCC=3.0±0.3V

60mA

55mA

30mA

15mA

K6F2008S2M-I

2.3~3.3V

1.8~2.7V

120¹⁾/150@VCC=2.5±0.2V

300¹⁾@VCC=2.0±0.2V

K6F2008R2M-I

1. The parameter is measured with 30pF test load.

2. 2mA for super low power version with special handling.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

A11

Clk gen.

Precharge circuit.

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

CS2

A15

VCC

A17

A16

A14

A12

A14

A12

32-TSOP

Type I - Forward

Memory array

1024 rows

256¥8 columns

Row

select

Name

Function

Name

Function

CS1,CS2 Chip Select Input

I/O1~I/O8 Data Inputs/Outputs

I/O Circuit

Data

cont

I/O1

I/O8

Column select

Output Enable

Vcc

Vss

Power

Write Enable Input

Ground

Data

cont

A0~A17 Address Inputs

N.C.

No Connection

A9 A11 A10 A15 A13 A8 A16 A17

CS1

Control

logic

CS2

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

K6F2008V2M-TC70

K6F2008V2M-TC85

32-TSOP F, 70ns, 3.3V, LL

32-TSOP F, 85ns, 3.3V, LL

K6F2008V2M-TI70

K6F2008V2M-TI85

32-TSOP F, 70ns, 3.3V, LL

32-TSOP F, 85ns, 3.3V, LL

K6F2008S2M-TC12

K6F2008S2M-TC15

32-TSOP F, 120/85ns, 2.5/3.0V, LL

32-TSOP F, 150/85ns, 2.5/3.0V, LL

K6F2008S2M-TI12

K6F2008S2M-TI15

32-TSOP F, 120/85ns, 2.5/3.0V, LL

32-TSOP F, 150/85ns, 2.5/3.0V, LL

K6F2008R2M-TC30

32-TSOP F, 300ns, 2.0/2.5V, LL

K6F2008R2M-TI30

32-TSOP F, 300ns, 2.0/2.5V, LL

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Power

Standby

Active

X¹⁾

High-Z

Dout

Deselected

Output Disable

Read

X¹⁾

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOU

VCC

Ratings

Unit

Remark

-0.2 to 3.6V²⁾

-0.2 to 4.0V³⁾

1.0

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Storage temperature

TSTG

-55 to 150

0 to 70

°C

°C K6F2008V2M-C, K6F2008S2M-C, K6F2008R2M-C

Operating Temperature

-40 to 85

°C

K6F2008V2M-I, K6F2008S2M-I, K6F2008R2M-I

Soldering temperature and time

TSOLDER 260°C, 5sec (Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VIN/VOUT=-0.2 to 3.9V for K6F2008V2M Family.

3. Maximum VCC=-0.2 to 4.6V for K6F2008V2M Family.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Typ²⁾

Item

Symbol

Product

Min

Max

Unit

K6F2008V2M Family

K6F2008S2M Family

K6F2008R2M Family

3.0

2.3

1.8

3.3

2.5/3.0

2.0/2.5

3.6

3.3

2.7

Supply voltage

Vcc

Ground

Vss

All Family

K6F2008V2M Family

Vcc=3.3±0.3V

2.2

2.0

1.6

Vcc=3.0±0.3V

Vcc=2.5±0.2V

Vcc=2.0±0.2V

K6F2008S2M Family

Vcc+0.2²⁾

Input high voltage

VIH

K6F2008R2M Family

-0.2³⁾

Input low voltage

Note

VIL

All Family

0.4

1. Commercial Product : TA=0 to 70°C, unless otherwise specified

Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : Vcc + 1.0V in case of pulse width£20ns

3. Undershoot : -1.0V in case of pulse width£20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read

-1

ICC

55¹⁾

0.4

Read

Write

Cycle time=1ms, 100% duty, IIO=0mA, CS1£0.2V,

CS2³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

Average operating current

Vcc=3.3V@70ns

Vcc=2.7V@120ns

Vcc=2.2V@300ns

Cycle time=Min, 100% duty, IIO=0mA,

CS1=VIL, CS2=VIH, VIN=VIL or VIH

2.1mA at Vcc=3.0/3.3V

Output low voltage

Output high voltage

VOL

VOH

IOL

IOH

0.5mA at Vcc=2.5V

0.33mA at Vcc=2.0V

-1.0mA at Vcc=3.0/3.3V

-0.5mA at Vcc=2.5V

-0.44mA at Vcc=2.0V

2.4

2.0

1.6

Standby Current(TTL)

ISB

CS1=VIH or CS2=VIL, Other inputs=VIL or VIH

0.3

10²⁾

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc

Standby Current(CMOS)

ISB1

1.The value is measured at Vcc=3.0±0.3V

- ICC2=60mA with 70ns at Vcc=3.3±0.3V, but this value is not 100% tested but obtained statistically.

2. Super low power product = 2mA with special handling.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

VTM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V

0.4 to 1.8V for Vcc=2.0V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V for Vcc=3.3V, 3.0V

1.1V for Vcc=2.5V

1. Including scope and jig capacitance

2. R1=3070W, R2=3150W

3. VTM =2.8V for VCC=3.0/3.3V

=2.3V for VCC=2.5V

0.9V for Vcc=2.0V

Output load (See right):CL=100pF+1TTL

CL=30pF+1TTL

=1.8V for VCC=2.0V

AC CHARACTERISTICS(Commercial product:TA=0 to 70°C, Industrial product: TA=-40 to 85°C

K6F2008V2M Family: Vcc=3.0~3.6V, K6F2008S2M Family: Vcc=2.3~3.3V,

K6F2008R2M Family: Vcc=1.8~2.7V)

Speed Bins

Parameter List

Symbol

Units

70ns

85ns

120ns

150ns

300ns

Min Max Min Max Min Max Min Max Min Max

Read cycle time

tRC

tAA

120

150

300

Address access time

120

150

300

Chip select to output

tCO1, tCO2

tOE

120

150

300

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

150

Read

tLZ1, tLZ2

tOLZ

tHZ1, tHZ2

tOHZ

tOH

120

100

150

120

300

tWC

Chip select to end of write

Address set-up time

tCW

tAS

Address valid to end of write

Write pulse width

tAW

100

120

100

300

200

tWP

Write

Write recovery time

tWR

Write to output high-Z

tWHZ

tDW

Data to write time overlap

Data hold from write time

End write to output low-Z

120

tDH

tOW

DATA RETENTION CHARACTERISTICS

Item

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

Symbol

VDR

Test Condition

CS1³ Vcc-0.2V¹⁾

Vcc=3.0V, CS1³ Vcc-0.2V¹⁾

Min

Typ

Max

Unit

1.5

3.6

10²⁾

IDR

tSDR

See data retention waveform

tRDR

tRC

1. CS

³ Vcc-0.2V, CS

³ Vcc-0.2V(CS

controlled) or CS

£0.2V(CS controlled)

2. Super low power product = 2mA with special handling.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Out

Data Valid

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)

tWC

Address

tAS(3)

tCW(2)

tWR(4)

CS1

tAW

CS2

tWP(2)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)

applied in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7/2.3/1.8V

2.2V

VDR

CS³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

3.0/2.7/2.3/1.8V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 2.0

March 1998

K6F2008V2M, K6F2008S2M, K6F2008R2M Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

+0.004

20.00±0.20

0.787±0.008

0.20

0.008

-0.002

#32

0.25

(

)

0.010

8.40

0.331

MAX

0.50

0.0197

#17

#16

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 2.0

March 1998

K6F2008V2M-TI85 [SAMSUNG]

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